##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Update DMA : split IP DMA and Reg AHB.
pellion -
r124:f7d30b8fef72 JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -33,8 +33,9 USE esa.memoryctrl.ALL;
33 USE esa.pcicomp.ALL;
33 USE esa.pcicomp.ALL;
34 USE work.config.ALL;
34 USE work.config.ALL;
35 LIBRARY lpp;
35 LIBRARY lpp;
36 USE lpp.lpp_bootloader_pkg.ALL;
36 USE lpp.lpp_dma_pkg.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
37 use lpp.lpp_memory.all;
38 USE lpp.lpp_memory.ALL;
38
39
39 ENTITY leon3mp IS
40 ENTITY leon3mp IS
40 GENERIC (
41 GENERIC (
@@ -55,24 +56,24 ENTITY leon3mp IS
55 address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
56 address : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
56 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
57 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
57
58
58 dsutx : OUT STD_ULOGIC; -- DSU tx data
59 dsutx : OUT STD_ULOGIC; -- DSU tx data
59 dsurx : IN STD_ULOGIC; -- DSU rx data
60 dsurx : IN STD_ULOGIC; -- DSU rx data
60 dsuen : IN STD_ULOGIC;
61 dsuen : IN STD_ULOGIC;
61 dsubre : IN STD_ULOGIC;
62 dsubre : IN STD_ULOGIC;
62 dsuact : OUT STD_ULOGIC;
63 dsuact : OUT STD_ULOGIC;
63 txd1 : OUT STD_ULOGIC; -- UART1 tx data
64 txd1 : OUT STD_ULOGIC; -- UART1 tx data
64 rxd1 : IN STD_ULOGIC; -- UART1 rx data
65 rxd1 : IN STD_ULOGIC; -- UART1 rx data
65 txd2 : OUT STD_ULOGIC; -- UART2 tx data
66 txd2 : OUT STD_ULOGIC; -- UART2 tx data
66 rxd2 : IN STD_ULOGIC; -- UART2 rx data
67 rxd2 : IN STD_ULOGIC; -- UART2 rx data
67 ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
68 ramsn : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
68 ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
69 ramoen : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
69 rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
70 rwen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
70 oen : OUT STD_ULOGIC;
71 oen : OUT STD_ULOGIC;
71 writen : OUT STD_ULOGIC;
72 writen : OUT STD_ULOGIC;
72 read : OUT STD_ULOGIC;
73 read : OUT STD_ULOGIC;
73 iosn : OUT STD_ULOGIC;
74 iosn : OUT STD_ULOGIC;
74 romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
75 romsn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
75 gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port
76 gpio : INOUT STD_LOGIC_VECTOR(CFG_GRGPIO_WIDTH-1 DOWNTO 0); -- I/O port
76
77
77 emddis : OUT STD_LOGIC;
78 emddis : OUT STD_LOGIC;
78 epwrdwn : OUT STD_ULOGIC;
79 epwrdwn : OUT STD_ULOGIC;
@@ -101,35 +102,35 ENTITY leon3mp IS
101 pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3);
102 pci_arb_req : IN STD_LOGIC_VECTOR(0 TO 3);
102 pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3);
103 pci_arb_gnt : OUT STD_LOGIC_VECTOR(0 TO 3);
103
104
104 spw_clk : IN STD_ULOGIC;
105 spw_clk : IN STD_ULOGIC;
105 spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2);
106 spw_rxd : IN STD_LOGIC_VECTOR(0 TO 2);
106 spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2);
107 spw_rxdn : IN STD_LOGIC_VECTOR(0 TO 2);
107 spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2);
108 spw_rxs : IN STD_LOGIC_VECTOR(0 TO 2);
108 spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2);
109 spw_rxsn : IN STD_LOGIC_VECTOR(0 TO 2);
109 spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2);
110 spw_txd : OUT STD_LOGIC_VECTOR(0 TO 2);
110 spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2);
111 spw_txdn : OUT STD_LOGIC_VECTOR(0 TO 2);
111 spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2);
112 spw_txs : OUT STD_LOGIC_VECTOR(0 TO 2);
112 spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2);
113 spw_txsn : OUT STD_LOGIC_VECTOR(0 TO 2);
113
114
114 ramclk : OUT STD_LOGIC;
115 ramclk : OUT STD_LOGIC;
115
116
116 nBWa : out std_logic;
117 nBWa : OUT STD_LOGIC;
117 nBWb : out std_logic;
118 nBWb : OUT STD_LOGIC;
118 nBWc : out std_logic;
119 nBWc : OUT STD_LOGIC;
119 nBWd : out std_logic;
120 nBWd : OUT STD_LOGIC;
120 nBWE : out std_logic;
121 nBWE : OUT STD_LOGIC;
121 nADSC : out std_logic;
122 nADSC : OUT STD_LOGIC;
122 nADSP : out std_logic;
123 nADSP : OUT STD_LOGIC;
123 nADV : out std_logic;
124 nADV : OUT STD_LOGIC;
124 nGW : out std_logic;
125 nGW : OUT STD_LOGIC;
125 nCE1 : out std_logic;
126 nCE1 : OUT STD_LOGIC;
126 CE2 : out std_logic;
127 CE2 : OUT STD_LOGIC;
127 nCE3 : out std_logic;
128 nCE3 : OUT STD_LOGIC;
128 nOE : out std_logic;
129 nOE : OUT STD_LOGIC;
129 MODE : out std_logic;
130 MODE : OUT STD_LOGIC;
130 SSRAM_CLK : out std_logic;
131 SSRAM_CLK : OUT STD_LOGIC;
131 ZZ : out std_logic;
132 ZZ : OUT STD_LOGIC;
132
133
133 tck, tms, tdi : IN STD_ULOGIC;
134 tck, tms, tdi : IN STD_ULOGIC;
134 tdo : OUT STD_ULOGIC
135 tdo : OUT STD_ULOGIC
135 );
136 );
@@ -206,20 +207,20 ARCHITECTURE rtl OF leon3mp IS
206
207
207 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
208
209
209 SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 SIGNAL fifo_empty : STD_LOGIC;
211 SIGNAL fifo_empty : STD_LOGIC;
211 SIGNAL fifo_ren : STD_LOGIC;
212 SIGNAL fifo_ren : STD_LOGIC;
212 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL dma_empty : STD_LOGIC;
214 SIGNAL dma_empty : STD_LOGIC;
214 SIGNAL dma_ren : STD_LOGIC;
215 SIGNAL dma_ren : STD_LOGIC;
215 SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL header_val : STD_LOGIC;
217 SIGNAL header_val : STD_LOGIC;
217 SIGNAL header_ack : STD_LOGIC;
218 SIGNAL header_ack : STD_LOGIC;
218
219
219 signal lclk2x : std_ulogic;
220 SIGNAL lclk2x : STD_ULOGIC;
220 signal clk2x : std_ulogic;
221 SIGNAL clk2x : STD_ULOGIC;
221
222
222 constant boardfreq : integer := 50000;
223 CONSTANT boardfreq : INTEGER := 50000;
223
224
224 BEGIN
225 BEGIN
225
226
@@ -232,30 +233,24 BEGIN
232 cgi.pllctrl <= "00";
233 cgi.pllctrl <= "00";
233 cgi.pllrst <= rstraw;
234 cgi.pllrst <= rstraw;
234
235
235 pllref_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (pllref, cgi.pllref);
236 pllref_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (pllref, cgi.pllref);
237
238 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk2x);
236
239
237 -- clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
240 PROCESS(lclk2x)
238 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk2x);
239
240 process(lclk2x)
241 BEGIN
241 BEGIN
242 if lclk2x'event and lclk2x = '1' then
242 IF lclk2x'EVENT AND lclk2x = '1' THEN
243 lclk <= not lclk;
243 lclk <= NOT lclk;
244 end if;
244 END IF;
245 end process;
245 END PROCESS;
246
246
247 pci_clk_pad : clkpad GENERIC MAP (tech => padtech, level => pci33) PORT MAP (pci_clk, pci_lclk);
247 pci_clk_pad : clkpad GENERIC MAP (tech => padtech, level => pci33) PORT MAP (pci_clk, pci_lclk);
248
248
249 --clkgen0 : clkgen -- clock generator
249 clkgen0 : clkgen -- clock generator
250 -- GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
250 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
251 -- CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK)
251 PORT MAP (lclk, lclk, clkm, OPEN, clk2x, sdclkl, pciclk, cgi, cgo);
252 -- PORT MAP (lclk, pci_lclk, clkm, OPEN, OPEN, sdclkl, pciclk, cgi, cgo);
253
252
254 clkgen0 : clkgen -- clock generator
253 ramclk <= clkm;
255 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
256 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
257
258 ramclk <= clkm;
259
254
260 rst0 : rstgen -- reset generator
255 rst0 : rstgen -- reset generator
261 PORT MAP (resetn, clkm, cgo.clklock, rstn, rstraw);
256 PORT MAP (resetn, clkm, cgo.clklock, rstn, rstraw);
@@ -322,91 +317,49 BEGIN
322 ----------------------------------------------------------------------
317 ----------------------------------------------------------------------
323 --- Memory controllers ----------------------------------------------
318 --- Memory controllers ----------------------------------------------
324 ----------------------------------------------------------------------
319 ----------------------------------------------------------------------
325
320 -- LEON2 memory controller
326 --src : IF CFG_SRCTRL = 1 GENERATE -- 32-bit PROM/SRAM controller
321 sr1 : mctrl
327 -- sr0 : srctrl GENERIC MAP (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
322 GENERIC MAP (
328 -- romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
323 hindex => 0,
329 -- prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
324 pindex => 0,
330 -- PORT MAP (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
325 romaddr => 16#000#,
331 -- apbo(0) <= apb_none;
326 rommask => 16#E00#,
332 --END GENERATE;
327 ioaddr => 16#200#,
333
328 iomask => 16#E00#,
334 --sdc : IF CFG_SDCTRL = 1 GENERATE
329 ramaddr => 16#400#,
335 -- sdc : sdctrl GENERIC MAP (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
330 rammask => 16#C00#,
336 -- ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
331 paddr => 0,
337 -- sdbits => 32 + 32*CFG_SDCTRL_SD64, pageburst => CFG_SDCTRL_PAGE)
332 pmask => 16#fff#,
338 -- PORT MAP (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
333 wprot => 0,
339 -- sa_pad : outpadv GENERIC MAP (width => 15, tech => padtech)
334 invclk => 0,
340 -- PORT MAP (sa, sdo2.address);
335 fast => 0,
341 -- sd_pad : iopadv GENERIC MAP (width => 32, tech => padtech)
336 romasel => 28,
342 -- PORT MAP (sd(31 DOWNTO 0), sdo2.data(31 DOWNTO 0), sdo2.bdrive, sdi.data(31 DOWNTO 0));
337 sdrasel => 29,
343 -- sd2 : IF CFG_SDCTRL_SD64 = 1 GENERATE
338 srbanks => 4,
344 -- sd_pad2 : iopadv GENERIC MAP (width => 32)
339 ram8 => 0,
345 -- PORT MAP (sd(63 DOWNTO 32), sdo2.data, sdo2.bdrive, sdi.data(63 DOWNTO 32));
340 ram16 => 0,
346 -- END GENERATE;
341 sden => 0,
347 -- sdcke_pad : outpadv GENERIC MAP (width => 2, tech => padtech)
342 sepbus => 0,
348 -- PORT MAP (sdcke, sdo2.sdcke);
343 sdbits => 32,
349 -- sdwen_pad : outpad GENERIC MAP (tech => padtech)
344 sdlsb => 2, -- set to 12 for the GE-HPE board
350 -- PORT MAP (sdwen, sdo2.sdwen);
345 oepol => 0,
351 -- sdcsn_pad : outpadv GENERIC MAP (width => 2, tech => padtech)
346 syncrst => 0,
352 -- PORT MAP (sdcsn, sdo2.sdcsn);
347 pageburst => 0,
353 -- sdras_pad : outpad GENERIC MAP (tech => padtech)
348 scantest => 0,
354 -- PORT MAP (sdrasn, sdo2.rasn);
349 mobile => 0
355 -- sdcas_pad : outpad GENERIC MAP (tech => padtech)
350 )
356 -- PORT MAP (sdcasn, sdo2.casn);
351 PORT MAP (
357 -- sddqm_pad : outpadv GENERIC MAP (width => 8, tech => padtech)
352 rst => rstn,
358 -- PORT MAP (sddqm, sdo2.dqm(7 DOWNTO 0));
353 clk => clkm,
359 --END GENERATE;
354 memi => memi,
360
355 memo => memo,
361 -- mg2 : IF CFG_MCTRL_LEON2 = 1 GENERATE -- LEON2 memory controller
356 ahbsi => ahbsi,
362 sr1 : mctrl GENERIC MAP ( hindex => 0,
357 ahbso => ahbso(0),
363 pindex => 0,
358 apbi => apbi,
364 paddr => 0--,
359 apbo => apbo(0),
365 --srbanks => 4+CFG_MCTRL_5CS,
360 wpo => wpo,
366 --sden => CFG_MCTRL_SDEN,
361 sdo => sdo
367 --ram8 => CFG_MCTRL_RAM8BIT,
362 );
368 --ram16 => CFG_MCTRL_RAM16BIT,
369 --invclk => CFG_MCTRL_INVCLK,
370 --sepbus => CFG_MCTRL_SEPBUS,
371 --sdbits => 32 + 32*CFG_MCTRL_SD64,
372 --pageburst => CFG_MCTRL_PAGE
373 )
374 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
375 --sdpads : IF CFG_MCTRL_SDEN = 1 GENERATE -- SDRAM controller
376 -- sd2 : IF CFG_MCTRL_SEPBUS = 1 GENERATE
377 -- sa_pad : outpadv GENERIC MAP (width => 15) PORT MAP (sa, memo.sa);
378 -- bdr : FOR i IN 0 TO 3 GENERATE
379 -- sd_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
380 -- PORT MAP (sd(31-i*8 DOWNTO 24-i*8), memo.data(31-i*8 DOWNTO 24-i*8),
381 -- memo.bdrive(i), memi.sd(31-i*8 DOWNTO 24-i*8));
382 -- sd2 : IF CFG_MCTRL_SD64 = 1 GENERATE
383 -- sd_pad2 : iopadv GENERIC MAP (tech => padtech, width => 8)
384 -- PORT MAP (sd(31-i*8+32 DOWNTO 24-i*8+32), memo.data(31-i*8 DOWNTO 24-i*8),
385 -- memo.bdrive(i), memi.sd(31-i*8+32 DOWNTO 24-i*8+32));
386 -- END GENERATE;
387 -- END GENERATE;
388 -- END GENERATE;
389 -- sdwen_pad : outpad GENERIC MAP (tech => padtech)
390 -- PORT MAP (sdwen, sdo.sdwen);
391 -- sdras_pad : outpad GENERIC MAP (tech => padtech)
392 -- PORT MAP (sdrasn, sdo.rasn);
393 -- sdcas_pad : outpad GENERIC MAP (tech => padtech)
394 -- PORT MAP (sdcasn, sdo.casn);
395 -- sddqm_pad : outpadv GENERIC MAP (width => 8, tech => padtech)
396 -- PORT MAP (sddqm, sdo.dqm);
397 -- sdcke_pad : outpadv GENERIC MAP (width => 2, tech => padtech)
398 -- PORT MAP (sdcke, sdo.sdcke);
399 -- sdcsn_pad : outpadv GENERIC MAP (width => 2, tech => padtech)
400 -- PORT MAP (sdcsn, sdo.sdcsn);
401 --END GENERATE;
402 -- END GENERATE;
403
404 --nosd0 : IF (CFG_MCTRL_SDEN = 0) AND (CFG_SDCTRL = 0) GENERATE -- no SDRAM controller
405 -- sdcke_pad : outpadv GENERIC MAP (width => 2, tech => padtech)
406 -- PORT MAP (sdcke, sdo3.sdcke);
407 -- sdcsn_pad : outpadv GENERIC MAP (width => 2, tech => padtech)
408 -- PORT MAP (sdcsn, sdo3.sdcsn);
409 --END GENERATE;
410
363
411
364
412 memi.brdyn <= '1'; memi.bexcn <= '1';
365 memi.brdyn <= '1'; memi.bexcn <= '1';
@@ -414,14 +367,14 BEGIN
414
367
415 mgpads : IF (CFG_SRCTRL = 1) OR (CFG_MCTRL_LEON2 = 1) GENERATE -- prom/sram pads
368 mgpads : IF (CFG_SRCTRL = 1) OR (CFG_MCTRL_LEON2 = 1) GENERATE -- prom/sram pads
416 addr_pad : outpadv GENERIC MAP (width => 28, tech => padtech) PORT MAP (address, memo.address(27 DOWNTO 0));
369 addr_pad : outpadv GENERIC MAP (width => 28, tech => padtech) PORT MAP (address, memo.address(27 DOWNTO 0));
417 rams_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramsn, memo.ramsn(4 DOWNTO 0));
370 rams_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramsn, memo.ramsn(4 DOWNTO 0));
418 roms_pad : outpadv GENERIC MAP (width => 2, tech => padtech) PORT MAP (romsn, memo.romsn(1 DOWNTO 0));
371 roms_pad : outpadv GENERIC MAP (width => 2, tech => padtech) PORT MAP (romsn, memo.romsn(1 DOWNTO 0));
419 oen_pad : outpad GENERIC MAP ( tech => padtech) PORT MAP (oen, memo.oen);
372 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (oen, memo.oen);
420 rwen_pad : outpadv GENERIC MAP (width => 4, tech => padtech) PORT MAP (rwen, memo.wrn);
373 rwen_pad : outpadv GENERIC MAP (width => 4, tech => padtech) PORT MAP (rwen, memo.wrn);
421 roen_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramoen, memo.ramoen(4 DOWNTO 0));
374 roen_pad : outpadv GENERIC MAP (width => 5, tech => padtech) PORT MAP (ramoen, memo.ramoen(4 DOWNTO 0));
422 wri_pad : outpad GENERIC MAP ( tech => padtech) PORT MAP (writen, memo.writen);
375 wri_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (writen, memo.writen);
423 read_pad : outpad GENERIC MAP ( tech => padtech) PORT MAP (read, memo.read);
376 read_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (read, memo.read);
424 iosn_pad : outpad GENERIC MAP ( tech => padtech) PORT MAP (iosn, memo.iosn);
377 iosn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (iosn, memo.iosn);
425
378
426 bdr : FOR i IN 0 TO 3 GENERATE
379 bdr : FOR i IN 0 TO 3 GENERATE
427 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
380 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
@@ -431,22 +384,12 BEGIN
431
384
432 END GENERATE;
385 END GENERATE;
433
386
434 SSRAM_0: ssram_plugin
387 SSRAM_0 : ssram_plugin
435 generic map (tech => padtech)
388 GENERIC MAP (tech => padtech)
436 port map (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
389 PORT MAP (lclk2x, memo, SSRAM_CLK,
437
390 nBWa, nBWb, nBWc, nBWd, nBWE, nADSC, nADSP, nADV, nGW, nCE1, CE2, nCE3, nOE, MODE, ZZ);
438 ----------------------------------------------------------------------
439 --- APB Bridge and various periherals -------------------------------
440 ----------------------------------------------------------------------
441
391
442 bpromgen : IF CFG_AHBROMEN /= 0 GENERATE
392
443 brom : ENTITY work.ahbrom
444 GENERIC MAP (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
445 PORT MAP (rstn, clkm, ahbsi, ahbso(5));
446 END GENERATE;
447 nobpromgen : IF CFG_AHBROMEN = 0 GENERATE
448 ahbso(5) <= ahbs_none;
449 END GENERATE;
450
393
451 ----------------------------------------------------------------------
394 ----------------------------------------------------------------------
452 --- APB Bridge and various periherals -------------------------------
395 --- APB Bridge and various periherals -------------------------------
@@ -572,7 +515,7 BEGIN
572 noarb : IF CFG_PCI_ARB = 0 GENERATE apbo(10) <= apb_none; END GENERATE;
515 noarb : IF CFG_PCI_ARB = 0 GENERATE apbo(10) <= apb_none; END GENERATE;
573
516
574
517
575 ahbso(6) <= ahbs_none;
518 -- ahbso(6) <= ahbs_none;
576
519
577 -----------------------------------------------------------------------
520 -----------------------------------------------------------------------
578 --- AHB RAM ----------------------------------------------------------
521 --- AHB RAM ----------------------------------------------------------
@@ -614,11 +557,35 BEGIN
614 END GENERATE;
557 END GENERATE;
615 END GENERATE;
558 END GENERATE;
616
559
560
561
562 -------------------------------------------------------------------------------
563 -- BOOT MEMORY AND REGISTER
564 -------------------------------------------------------------------------------
565
566 lpp_bootloader_1: lpp_bootloader
567 GENERIC MAP (
568 pindex => 13,
569 paddr => 13,
570 pmask => 16#fff#,
571
572 hindex => 6,
573 haddr => 16#900#,
574 hmask => 16#F00#)
575 PORT MAP (
576 HCLK => clkm,
577 HRESETn => resetn,
578 apbi => apbi,
579 apbo => apbo(13),
580 ahbsi => ahbsi,
581 ahbso => ahbso(6));
582
583
617 -------------------------------------------------------------------------------
584 -------------------------------------------------------------------------------
618 -- AHB DMA
585 -- AHB DMA
619 -------------------------------------------------------------------------------
586 -------------------------------------------------------------------------------
620
587
621 lpp_dma_1: lpp_dma
588 lpp_dma_1 : lpp_dma
622 GENERIC MAP (
589 GENERIC MAP (
623 tech => fabtech,
590 tech => fabtech,
624 hindex => 2,
591 hindex => 2,
@@ -633,24 +600,24 BEGIN
633 apbo => apbo(14),
600 apbo => apbo(14),
634 AHB_Master_In => ahbmi,
601 AHB_Master_In => ahbmi,
635 AHB_Master_Out => ahbmo(2),
602 AHB_Master_Out => ahbmo(2),
636 fifo_data => dma_data,
603 fifo_data => fifo_data, --dma_data,
637 fifo_empty => dma_empty,
604 fifo_empty => fifo_empty, --dma_empty,
638 fifo_ren => dma_ren,
605 fifo_ren => fifo_ren, --dma_ren,
639 header => header,
606 header => header,
640 header_val => header_val,
607 header_val => header_val,
641 header_ack => header_ack);
608 header_ack => header_ack);
642
609
643 fifo_latency_correction_1: fifo_latency_correction
610 --fifo_latency_correction_1 : fifo_latency_correction
644 PORT MAP (
611 -- PORT MAP (
645 HCLK => clkm,
612 -- HCLK => clkm,
646 HRESETn => resetn,
613 -- HRESETn => resetn,
647 fifo_data => fifo_data,
614 -- fifo_data => fifo_data,
648 fifo_empty => fifo_empty,
615 -- fifo_empty => fifo_empty,
649 fifo_ren => fifo_ren,
616 -- fifo_ren => fifo_ren,
650 dma_data => dma_data,
617 -- dma_data => dma_data,
651 dma_empty => dma_empty,
618 -- dma_empty => dma_empty,
652 dma_ren => dma_ren);
619 -- dma_ren => dma_ren);
653
620
654 fifo_test_dma_1 : fifo_test_dma
621 fifo_test_dma_1 : fifo_test_dma
655 GENERIC MAP (
622 GENERIC MAP (
656 tech => fabtech,
623 tech => fabtech,
@@ -658,16 +625,16 BEGIN
658 paddr => 15,
625 paddr => 15,
659 pmask => 16#fff#)
626 pmask => 16#fff#)
660 PORT MAP (
627 PORT MAP (
661 HCLK => clkm,
628 HCLK => clkm,
662 HRESETn => resetn,
629 HRESETn => resetn,
663 apbi => apbi,
630 apbi => apbi,
664 apbo => apbo(15),
631 apbo => apbo(15),
665 fifo_data => fifo_data,
632 fifo_data => fifo_data,
666 fifo_empty => fifo_empty,
633 fifo_empty => fifo_empty,
667 fifo_ren => fifo_ren,
634 fifo_ren => fifo_ren,
668 header => header,
635 header => header,
669 header_val => header_val,
636 header_val => header_val,
670 header_ack => header_ack);
637 header_ack => header_ack);
671
638
672 -----------------------------------------------------------------------
639 -----------------------------------------------------------------------
673 --- Boot message ----------------------------------------------------
640 --- Boot message ----------------------------------------------------
Show file before | Show file after | Hide comments
@@ -4,6 +4,7 vcom -quiet -93 -work lpp ../../lib/lp
4 vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_apbreg.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_apbreg.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_ip.vhd
7 ##vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_fsm.vhd
8 ##vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma_fsm.vhd
8 vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma.vhd
9 vcom -quiet -93 -work lpp ../../lib/lpp/./lpp_dma/lpp_dma.vhd
9
10
@@ -13,12 +14,21 vcom -quiet -93 -work lpp ../../lib/lp
13 vcom -quiet -93 -work work CY7C1360C/package_utility.vhd
14 vcom -quiet -93 -work work CY7C1360C/package_utility.vhd
14 vcom -quiet -93 -work work CY7C1360C/CY7C1360C.vhd
15 vcom -quiet -93 -work work CY7C1360C/CY7C1360C.vhd
15
16
17 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/./bootrom.vhd
18 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/./lpp_bootloader_pkg.vhd
19 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/./lpp_bootloader.vhd
20
16 vcom -quiet -93 -work work config.vhd
21 vcom -quiet -93 -work work config.vhd
17 vcom -quiet -93 -work work ahbrom.vhd
22 vcom -quiet -93 -work work ahbrom.vhd
18 vcom -quiet -93 -work work leon3mp.vhd
23 vcom -quiet -93 -work work leon3mp.vhd
19 vcom -quiet -93 -work work testbench.vhd
24 vcom -quiet -93 -work work testbench.vhd
20
25
21 vsim work.testbench
26 vsim work.testbench
27
22 log -r *
28 log -r *
23 do wave_dma.do
29 do wave_bootloader.do
24 ##run -all No newline at end of file
30 run 20 us
31 force -freeze sim:/testbench/d3/lpp_bootloader_1/reg.addr_start_execution 00000000000000000000000000000000 0
32 run 60 ns
33 force -freeze sim:/testbench/d3/lpp_bootloader_1/reg.config_start_execution 1 0
34 run -all No newline at end of file
Show file before | Show file after | Hide comments
@@ -19,7 +19,10
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
24 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -------------------------------------------------------------------------------
23 LIBRARY ieee;
26 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
27 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
28 USE ieee.numeric_std.ALL;
@@ -28,7 +31,7 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
31 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
32 USE grlib.devices.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
31
34 --USE GRLIB.DMA2AHB_TestPackage.ALL;
32 LIBRARY lpp;
35 LIBRARY lpp;
33 USE lpp.lpp_amba.ALL;
36 USE lpp.lpp_amba.ALL;
34 USE lpp.apb_devices_list.ALL;
37 USE lpp.apb_devices_list.ALL;
@@ -72,11 +75,6 ENTITY lpp_dma IS
72 END;
75 END;
73
76
74 ARCHITECTURE Behavioral OF lpp_dma IS
77 ARCHITECTURE Behavioral OF lpp_dma IS
75 -----------------------------------------------------------------------------
76 SIGNAL DMAIn : DMA_In_Type;
77 SIGNAL header_dmai : DMA_In_Type;
78 SIGNAL component_dmai : DMA_In_Type;
79 SIGNAL DMAOut : DMA_OUt_Type;
80
78
81 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
79 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
82 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
80 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
@@ -85,6 +83,8 ARCHITECTURE Behavioral OF lpp_dma IS
85 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
83 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
86 SIGNAL error_bad_component_error : STD_LOGIC;
84 SIGNAL error_bad_component_error : STD_LOGIC;
87
85
86 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
87
88 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
88 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
89 SIGNAL config_active_interruption_onError : STD_LOGIC;
89 SIGNAL config_active_interruption_onError : STD_LOGIC;
90 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
90 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
@@ -97,258 +97,61 ARCHITECTURE Behavioral OF lpp_dma IS
97 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 -----------------------------------------------------------------------------
101
102 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
104 TYPE state_DMAWriteBurst IS (IDLE,
105 TRASH_FIFO,
106 WAIT_HEADER_ACK,
107 SEND_DATA,
108 WAIT_DATA_ACK,
109 CHECK_LENGTH
110 );
111 SIGNAL state : state_DMAWriteBurst := IDLE;
112
113 SIGNAL nbSend : INTEGER;
114 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL header_check_ok : STD_LOGIC;
118 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL send_matrix : STD_LOGIC;
120 SIGNAL request : STD_LOGIC;
121 SIGNAL remaining_data_request : INTEGER;
122 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
123 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 SIGNAL header_select : STD_LOGIC;
126
127 SIGNAL header_send : STD_LOGIC;
128 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL header_send_ok : STD_LOGIC;
130 SIGNAL header_send_ko : STD_LOGIC;
131
132 SIGNAL component_send : STD_LOGIC;
133 SIGNAL component_send_ok : STD_LOGIC;
134 SIGNAL component_send_ko : STD_LOGIC;
135 -----------------------------------------------------------------------------
136 SIGNAL fifo_ren_trash : STD_LOGIC;
137 SIGNAL component_fifo_ren : STD_LOGIC;
138
139 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140
100
141 BEGIN
101 BEGIN
142
102
143 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
144 -- DMA to AHB interface
104 -- LPP DMA IP
145 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
146
147 DMA2AHB_1 : DMA2AHB
148 GENERIC MAP (
149 hindex => hindex,
150 vendorid => VENDOR_LPP,
151 deviceid => 0,
152 version => 0,
153 syncrst => 1,
154 boundary => 1) -- set TO TEST
155 PORT MAP (
156 HCLK => HCLK,
157 HRESETn => HRESETn,
158 DMAIn => DMAIn,
159 DMAOut => DMAOut,
160 AHBIn => AHB_Master_In,
161 AHBOut => AHB_Master_Out);
162
163
164 debug_info: PROCESS (HCLK, HRESETn)
165 BEGIN -- PROCESS debug_info
166 IF HRESETn = '0' THEN -- asynchronous reset (active low)
167 debug_reg <= (OTHERS => '0');
168 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
169 debug_reg(0) <= debug_reg(0) OR (DMAOut.Retry );
170 debug_reg(1) <= debug_reg(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
171 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
172 debug_reg(3) <= debug_reg(3) OR (header_send_ko);
173 debug_reg(4) <= debug_reg(4) OR (header_send_ok);
174 debug_reg(5) <= debug_reg(5) OR (component_send_ko);
175 debug_reg(6) <= debug_reg(6) OR (component_send_ok);
176
177 debug_reg(31 DOWNTO 7) <= (OTHERS => '1');
178 END IF;
179 END PROCESS debug_info;
180
181
182 matrix_type <= header(1 DOWNTO 0);
183 component_type <= header(5 DOWNTO 2);
184
185 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
186 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
187 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
188 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
189 '0';
190
191 header_check_ok <= '0' WHEN component_type = "1111" ELSE
192 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
193 '1' WHEN component_type = component_type_pre + "0001" ELSE
194 '0';
195
196 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
197 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
198 addr_matrix_f1 WHEN matrix_type = "10" ELSE
199 addr_matrix_f2 WHEN matrix_type = "11" ELSE
200 (OTHERS => '0');
201
202 -----------------------------------------------------------------------------
203 -- DMA control
204 -----------------------------------------------------------------------------
205 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
206 BEGIN -- PROCESS DMAWriteBurst_p
207 IF HRESETn = '0' THEN -- asynchronous reset (active low)
208 state <= IDLE;
209 header_ack <= '0';
210 ready_matrix_f0_0 <= '0';
211 ready_matrix_f0_1 <= '0';
212 ready_matrix_f1 <= '0';
213 ready_matrix_f2 <= '0';
214 error_anticipating_empty_fifo <= '0';
215 error_bad_component_error <= '0';
216 component_type_pre <= "1110";
217 fifo_ren_trash <= '1';
218 component_send <= '0';
219 address <= (OTHERS => '0');
220 header_select <= '0';
221 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
222
106
223 CASE state IS
107 lpp_dma_ip_1: ENTITY work.lpp_dma_ip
224 WHEN IDLE =>
108 GENERIC MAP (
225 ready_matrix_f0_0 <= '0';
109 tech => tech,
226 ready_matrix_f0_1 <= '0';
110 hindex => hindex,
227 ready_matrix_f1 <= '0';
111 pindex => pindex,
228 ready_matrix_f2 <= '0';
112 paddr => paddr,
229 error_bad_component_error <= '0';
113 pmask => pmask,
230 header_select <= '1';
114 pirq => pirq)
231 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
115 PORT MAP (
232 IF header_check_ok = '1' THEN
116 HCLK => HCLK,
233 header_data <= header;
117 HRESETn => HRESETn,
234 component_type_pre <= header(5 DOWNTO 2);
118 AHB_Master_In => AHB_Master_In,
235 header_ack <= '1';
119 AHB_Master_Out => AHB_Master_Out,
236 --
120 fifo_data => fifo_data,
237 header_send <= '1';
121 fifo_empty => fifo_empty,
238 IF component_type = "0000" THEN
122 fifo_ren => fifo_ren,
239 address <= address_matrix;
123 header => header,
240 END IF;
124 header_val => header_val,
241 header_data <= header;
125 header_ack => header_ack,
242 --
126 -------------------------------------------------------------------------
243 state <= WAIT_HEADER_ACK;
127 -- REG
244 ELSE
128 ready_matrix_f0_0 => ready_matrix_f0_0,
245 error_bad_component_error <= '1';
129 ready_matrix_f0_1 => ready_matrix_f0_1,
246 component_type_pre <= "1110";
130 ready_matrix_f1 => ready_matrix_f1,
247 header_ack <= '1';
131 ready_matrix_f2 => ready_matrix_f2,
248 state <= TRASH_FIFO;
132 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
249 END IF;
133 error_bad_component_error => error_bad_component_error,
250 END IF;
251
252 WHEN TRASH_FIFO =>
253 error_bad_component_error <= '0';
254 error_anticipating_empty_fifo <= '0';
255 IF fifo_empty = '1' THEN
256 state <= IDLE;
257 fifo_ren_trash <= '1';
258 ELSE
259 fifo_ren_trash <= '0';
260 END IF;
261
262 WHEN WAIT_HEADER_ACK =>
263 header_send <= '0';
264 IF header_send_ko = '1' THEN
265 state <= TRASH_FIFO;
266 error_anticipating_empty_fifo <= '1';
267 -- TODO : error sending header
268 ELSIF header_send_ok = '1' THEN
269 header_select <= '0';
270 state <= SEND_DATA;
271 address <= address + 4;
272 END IF;
273
134
274 WHEN SEND_DATA =>
135 debug_reg => debug_reg,
275 IF fifo_empty = '1' THEN
276 state <= IDLE;
277 IF component_type = "1110" THEN
278 CASE matrix_type IS
279 WHEN "00" => ready_matrix_f0_0 <= '1';
280 WHEN "01" => ready_matrix_f0_1 <= '1';
281 WHEN "10" => ready_matrix_f1 <= '1';
282 WHEN "11" => ready_matrix_f2 <= '1';
283 WHEN OTHERS => NULL;
284 END CASE;
285 END IF;
286 ELSE
287 component_send <= '1';
288 address <= address;
289 state <= WAIT_DATA_ACK;
290 END IF;
291
292 WHEN WAIT_DATA_ACK =>
293 component_send <= '0';
294 IF component_send_ok = '1' THEN
295 address <= address + 64;
296 state <= SEND_DATA;
297 ELSIF component_send_ko = '1' THEN
298 error_anticipating_empty_fifo <= '0';
299 state <= TRASH_FIFO;
300 END IF;
301
302 WHEN CHECK_LENGTH =>
303 state <= IDLE;
304 WHEN OTHERS => NULL;
305 END CASE;
306
307 END IF;
308 END PROCESS DMAWriteFSM_p;
309
136
310 -----------------------------------------------------------------------------
137 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
311 -- SEND 1 word by DMA
138 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
312 -----------------------------------------------------------------------------
139 status_ready_matrix_f1 => status_ready_matrix_f1,
313 lpp_dma_send_1word_1 : lpp_dma_send_1word
140 status_ready_matrix_f2 => status_ready_matrix_f2,
314 PORT MAP (
141 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
315 HCLK => HCLK,
142 status_error_bad_component_error => status_error_bad_component_error,
316 HRESETn => HRESETn,
143 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
317 DMAIn => header_dmai,
144 config_active_interruption_onError => config_active_interruption_onError,
318 DMAOut => DMAOut,
145 addr_matrix_f0_0 => addr_matrix_f0_0,
319
146 addr_matrix_f0_1 => addr_matrix_f0_1,
320 send => header_send,
147 addr_matrix_f1 => addr_matrix_f1,
321 address => address,
148 addr_matrix_f2 => addr_matrix_f2);
322 data => header_data,
149
323 send_ok => header_send_ok,
324 send_ko => header_send_ko
325 );
326
327 -----------------------------------------------------------------------------
328 -- SEND 16 word by DMA (in burst mode)
329 -----------------------------------------------------------------------------
330 lpp_dma_send_16word_1 : lpp_dma_send_16word
331 PORT MAP (
332 HCLK => HCLK,
333 HRESETn => HRESETn,
334 DMAIn => component_dmai,
335 DMAOut => DMAOut,
336 send => component_send,
337 address => address,
338 data => fifo_data,
339 ren => component_fifo_ren,
340 send_ok => component_send_ok,
341 send_ko => component_send_ko);
342
343 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
344 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
345
346
347 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
348 -- APB REGISTER
151 -- APB REGISTER
349 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
350
153
351 lpp_dma_apbreg_2 : lpp_dma_apbreg
154 lpp_dma_apbreg_1 : lpp_dma_apbreg
352 GENERIC MAP (
155 GENERIC MAP (
353 pindex => pindex,
156 pindex => pindex,
354 paddr => paddr,
157 paddr => paddr,
Show file before | Show file after | Hide comments
@@ -160,5 +160,45 PACKAGE lpp_dma_pkg IS
160 dma_empty : OUT STD_LOGIC;
160 dma_empty : OUT STD_LOGIC;
161 dma_ren : IN STD_LOGIC);
161 dma_ren : IN STD_LOGIC);
162 END COMPONENT;
162 END COMPONENT;
163
164 COMPONENT lpp_dma_ip
165 GENERIC (
166 tech : INTEGER;
167 hindex : INTEGER;
168 pindex : INTEGER;
169 paddr : INTEGER;
170 pmask : INTEGER;
171 pirq : INTEGER);
172 PORT (
173 HCLK : IN STD_ULOGIC;
174 HRESETn : IN STD_ULOGIC;
175 AHB_Master_In : IN AHB_Mst_In_Type;
176 AHB_Master_Out : OUT AHB_Mst_Out_Type;
177 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
178 fifo_empty : IN STD_LOGIC;
179 fifo_ren : OUT STD_LOGIC;
180 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
181 header_val : IN STD_LOGIC;
182 header_ack : OUT STD_LOGIC;
183 ready_matrix_f0_0 : OUT STD_LOGIC;
184 ready_matrix_f0_1 : OUT STD_LOGIC;
185 ready_matrix_f1 : OUT STD_LOGIC;
186 ready_matrix_f2 : OUT STD_LOGIC;
187 error_anticipating_empty_fifo : OUT STD_LOGIC;
188 error_bad_component_error : OUT STD_LOGIC;
189 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
190 status_ready_matrix_f0_0 : IN STD_LOGIC;
191 status_ready_matrix_f0_1 : IN STD_LOGIC;
192 status_ready_matrix_f1 : IN STD_LOGIC;
193 status_ready_matrix_f2 : IN STD_LOGIC;
194 status_error_anticipating_empty_fifo : IN STD_LOGIC;
195 status_error_bad_component_error : IN STD_LOGIC;
196 config_active_interruption_onNewMatrix : IN STD_LOGIC;
197 config_active_interruption_onError : IN STD_LOGIC;
198 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
199 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
200 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
201 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
202 END COMPONENT;
163
203
164 END;
204 END;
Show file before | Show file after | Hide comments
@@ -1,7 +1,8
1 lpp_dma_pkg.vhd
1 fifo_test_dma.vhd
2 fifo_test_dma.vhd
2 fifo_latency_correction.vhd
3 fifo_latency_correction.vhd
3 lpp_dma_send_1word.vhd
4 lpp_dma_send_1word.vhd
4 lpp_dma_send_16word.vhd
5 lpp_dma_send_16word.vhd
5 lpp_dma_apbreg.vhd
6 lpp_dma_apbreg.vhd
7 lpp_dma_ip.vhd
6 lpp_dma.vhd
8 lpp_dma.vhd
7 lpp_dma_pkg.vhd
General Comments 0
You need to be logged in to leave comments. Login now