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Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards...
Alexis Jeandet -
r662:f19abbf47ea7 SOLO_LFR_01-5B (LFR-EM) default draft
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1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname N18 -fixed yes -DIRECTION Inout
4
5 set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
24 set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
25
26 set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
27 set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
28 set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
29 set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
30 set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
31 set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
32 set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
33 set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
34 set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
35 set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
37 set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
38 set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
39 set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
40 set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
41 set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
42 set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
44 set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
45 set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
46 set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
47 set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
48 set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
49 set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
50 set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
51 set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
52 set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
53 set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
54 set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
55 set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
56 set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
57 set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
58
59 set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
60 set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
61 set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
62 set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
63 set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
64 set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
65 set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
66
67 set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76
77 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
78 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
79 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
80
81 #set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
82 set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
83 set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout
84 set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
85 #set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout
86 #set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
88 set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
89 #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
90
91 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
92
93 set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
98 set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
99 set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
100 set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
101
102 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
103
104 set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
105 set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout
106 set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout
107 set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout
108
109 set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
118 set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
119 set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
120 set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
121 set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
122 set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout
123
124 set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout
125 set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout
126 set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout
127 set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { SPW1_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y }
26
27 create_clock -name { SPW0_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50
51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
73 address[7] address[8] address[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
77 address[7] address[8] address[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }]
82
83
84 ######## Delay Constraints ########
85
86 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
87
88 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
89
90
91 ######## Delay Constraints ########
92
93
94
95 ######## Multicycle Constraints ########
96
97
98
99 ######## False Path Constraints ########
100
101
102
103 ######## Output load Constraints ########
104
105
106
107 ######## Disable Timing Constraints #########
108
109
110
111 ######## Clock Uncertainty Constraints #########
112
113
114
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1 SOLO\_LFR\_LFR-EM is the implementation of Solar Orbiter LFR analyser for the board LFR-EM.
2
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@@ -1,18 +1,19
1 TECHNOLOGY=PROASIC3
2 1 PACKAGE=\"\"
3 2 SPEED=Std
4 3 SYNFREQ=50
5 4
6 PART=A3PE3000L
5 TECHNOLOGY=ProASIC3E
6 LIBERO_DIE=IT14X14M4
7 PART=A3PE3000
8
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
7 11 DESIGNER_PACKAGE=FBGA
8 12 DESIGNER_PINS=324
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11 13
12 14 MANUFACTURER=Actel
15 MGCTECHNOLOGY=Proasic3
13 16 MGCPART=$(PART)
14 MGCTECHNOLOGY=PROASIC3
15 17 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
16 LIBERO_DIE=IT14X14M4LDP
17 18 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
18 19
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@@ -1,490 +1,488
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY LFR_em IS
49 49
50 50 PORT (
51 51 clk100MHz : IN STD_ULOGIC;
52 52 clk49_152MHz : IN STD_ULOGIC;
53 53 reset : IN STD_ULOGIC;
54 54
55 55 -- TAG --------------------------------------------------------------------
56 56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 58 -- UART APB ---------------------------------------------------------------
59 59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 61 -- RAM --------------------------------------------------------------------
62 62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 nSRAM_BE0 : OUT STD_LOGIC;
65 65 nSRAM_BE1 : OUT STD_LOGIC;
66 66 nSRAM_BE2 : OUT STD_LOGIC;
67 67 nSRAM_BE3 : OUT STD_LOGIC;
68 68 nSRAM_WE : OUT STD_LOGIC;
69 69 nSRAM_CE : OUT STD_LOGIC;
70 70 nSRAM_OE : OUT STD_LOGIC;
71 71 -- SPW --------------------------------------------------------------------
72 72 spw1_din : IN STD_LOGIC;
73 73 spw1_sin : IN STD_LOGIC;
74 74 spw1_dout : OUT STD_LOGIC;
75 75 spw1_sout : OUT STD_LOGIC;
76 76 spw2_din : IN STD_LOGIC;
77 77 spw2_sin : IN STD_LOGIC;
78 78 spw2_dout : OUT STD_LOGIC;
79 79 spw2_sout : OUT STD_LOGIC;
80 80 -- ADC --------------------------------------------------------------------
81 81 bias_fail_sw : OUT STD_LOGIC;
82 82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 83 ADC_smpclk : OUT STD_LOGIC;
84 84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 85 -- DAC --------------------------------------------------------------------
86 86 DAC_SDO : OUT STD_LOGIC;
87 87 DAC_SCK : OUT STD_LOGIC;
88 88 DAC_SYNC : OUT STD_LOGIC;
89 89 DAC_CAL_EN : OUT STD_LOGIC;
90 90 -- HK ---------------------------------------------------------------------
91 91 HK_smpclk : OUT STD_LOGIC;
92 92 ADC_OEB_bar_HK : OUT STD_LOGIC;
93 93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
94 94 ---------------------------------------------------------------------------
95 95 TAG8 : OUT STD_LOGIC;
96 96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
97 97 );
98 98
99 99 END LFR_em;
100 100
101 101
102 102 ARCHITECTURE beh OF LFR_em IS
103 103
104 104 --==========================================================================
105 105 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
106 106 -- when enabled, chip enable polarity should be reversed and bank size also
107 107 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
108 108 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
109 109 --==========================================================================
110 110 CONSTANT USE_IAP_MEMCTRL : integer := 1;
111 111 --==========================================================================
112 112
113 113 SIGNAL clk_50_s : STD_LOGIC := '0';
114 114 SIGNAL clk_25 : STD_LOGIC := '0';
115 115 SIGNAL clk_24 : STD_LOGIC := '0';
116 116 -----------------------------------------------------------------------------
117 117 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
118 118 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 119
120 120 -- CONSTANTS
121 121 CONSTANT CFG_PADTECH : INTEGER := inferred;
122 122 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
123 123 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
124 124 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
125 125
126 126 SIGNAL apbi_ext : apb_slv_in_type;
127 127 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
128 128 SIGNAL ahbi_s_ext : ahb_slv_in_type;
129 129 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
130 130 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
131 131 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
132 132
133 133 -- Spacewire signals
134 134 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 135 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
136 136 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
137 137 SIGNAL spw_rxtxclk : STD_ULOGIC;
138 138 SIGNAL spw_rxclkn : STD_ULOGIC;
139 139 SIGNAL spw_clk : STD_LOGIC;
140 140 SIGNAL swni : grspw_in_type;
141 141 SIGNAL swno : grspw_out_type;
142 142
143 143 --GPIO
144 144 SIGNAL gpioi : gpio_in_type;
145 145 SIGNAL gpioo : gpio_out_type;
146 146
147 147 -- AD Converter ADS7886
148 148 SIGNAL sample : Samples14v(8 DOWNTO 0);
149 149 SIGNAL sample_s : Samples(8 DOWNTO 0);
150 150 SIGNAL sample_val : STD_LOGIC;
151 151 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
152 152
153 153 -----------------------------------------------------------------------------
154 154 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 155
156 156 -----------------------------------------------------------------------------
157 157 SIGNAL rstn_25 : STD_LOGIC;
158 158 SIGNAL rstn_24 : STD_LOGIC;
159 159
160 160 SIGNAL LFR_soft_rstn : STD_LOGIC;
161 161 SIGNAL LFR_rstn : STD_LOGIC;
162 162
163 163 SIGNAL ADC_smpclk_s : STD_LOGIC;
164 164 ----------------------------------------------------------------------------
165 165 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 166 SIGNAL nSRAM_READY : STD_LOGIC;
167 167 SIGNAL SRAM_MBE : STD_LOGIC;
168 168
169 169 BEGIN -- beh
170 170
171 171 -----------------------------------------------------------------------------
172 172 -- CLK
173 173 -----------------------------------------------------------------------------
174 174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
175 175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
176 176
177 177 PROCESS(clk100MHz)
178 178 BEGIN
179 179 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
180 180 clk_50_s <= NOT clk_50_s;
181 181 END IF;
182 182 END PROCESS;
183 183
184 184 PROCESS(clk_50_s)
185 185 BEGIN
186 186 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
187 187 clk_25 <= NOT clk_25;
188 188 END IF;
189 189 END PROCESS;
190 190
191 191 PROCESS(clk49_152MHz)
192 192 BEGIN
193 193 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
194 194 clk_24 <= NOT clk_24;
195 195 END IF;
196 196 END PROCESS;
197 197
198 198 -----------------------------------------------------------------------------
199 199
200 200 PROCESS (clk_25, rstn_25)
201 201 BEGIN -- PROCESS
202 202 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
203 203 led(0) <= '0';
204 204 led(1) <= '0';
205 205 led(2) <= '0';
206 206 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
207 207 led(0) <= '0';
208 208 led(1) <= '1';
209 209 led(2) <= '1';
210 210 END IF;
211 211 END PROCESS;
212 212
213 213 --
214 214 leon3_soc_1 : leon3_soc
215 215 GENERIC MAP (
216 216 fabtech => apa3e,
217 217 memtech => apa3e,
218 218 padtech => inferred,
219 219 clktech => inferred,
220 220 disas => 0,
221 221 dbguart => 0,
222 222 pclow => 2,
223 223 clk_freq => 25000,
224 224 IS_RADHARD => 0,
225 225 NB_CPU => 1,
226 226 ENABLE_FPU => 1,
227 227 FPU_NETLIST => 0,
228 228 ENABLE_DSU => 1,
229 229 ENABLE_AHB_UART => 0,
230 230 ENABLE_APB_UART => 1,
231 231 ENABLE_IRQMP => 1,
232 232 ENABLE_GPT => 1,
233 233 NB_AHB_MASTER => NB_AHB_MASTER,
234 234 NB_AHB_SLAVE => NB_AHB_SLAVE,
235 235 NB_APB_SLAVE => NB_APB_SLAVE,
236 236 ADDRESS_SIZE => 20,
237 237 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
238 238 USES_MBE_PIN => 0,
239 239 BYPASS_EDAC_MEMCTRLR => '0',
240 240 SRBANKSZ => 9)
241 241 PORT MAP (
242 242 clk => clk_25,
243 243 reset => rstn_25,
244 244 errorn => OPEN,
245 245
246 246 ahbrxd => TAG1,
247 247 ahbtxd => TAG3,
248 248 urxd1 => TAG2,
249 249 utxd1 => TAG4,
250 250
251 251 address => address,
252 252 data => data,
253 253 nSRAM_BE0 => nSRAM_BE0,
254 254 nSRAM_BE1 => nSRAM_BE1,
255 255 nSRAM_BE2 => nSRAM_BE2,
256 256 nSRAM_BE3 => nSRAM_BE3,
257 257 nSRAM_WE => nSRAM_WE,
258 258 nSRAM_CE => nSRAM_CE_s,
259 259 nSRAM_OE => nSRAM_OE,
260 260 nSRAM_READY => nSRAM_READY,
261 261 SRAM_MBE => SRAM_MBE,
262 262
263 263 apbi_ext => apbi_ext,
264 264 apbo_ext => apbo_ext,
265 265 ahbi_s_ext => ahbi_s_ext,
266 266 ahbo_s_ext => ahbo_s_ext,
267 267 ahbi_m_ext => ahbi_m_ext,
268 268 ahbo_m_ext => ahbo_m_ext);
269 269
270 270 PROCESS (clk_25, rstn_25)
271 271 BEGIN -- PROCESS
272 272 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
273 273 nSRAM_READY <= '1';
274 274 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
275 275 nSRAM_READY <= '1';
276 276 END IF;
277 277 END PROCESS;
278 278
279 279 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
280 280 nSRAM_CE <= not nSRAM_CE_s(0);
281 281 END GENERATE;
282 282
283 283 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
284 284 nSRAM_CE <= nSRAM_CE_s(0);
285 285 END GENERATE;
286 286
287 287 -------------------------------------------------------------------------------
288 288 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
289 289 -------------------------------------------------------------------------------
290 290 apb_lfr_management_1 : apb_lfr_management
291 291 GENERIC MAP (
292 292 tech => apa3e,
293 293 pindex => 6,
294 294 paddr => 6,
295 295 pmask => 16#fff#,
296 296 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
297 297 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
298 298 PORT MAP (
299 299 clk25MHz => clk_25,
300 300 resetn_25MHz => rstn_25, -- TODO
301 301 -- clk24_576MHz => clk_24, -- 49.152MHz/2
302 302 -- resetn_24_576MHz => rstn_24, -- TODO
303 303
304 304 grspw_tick => swno.tickout,
305 305 apbi => apbi_ext,
306 306 apbo => apbo_ext(6),
307 307
308 308 HK_sample => sample_s(8),
309 309 HK_val => sample_val,
310 310 HK_sel => HK_SEL,
311 311
312 312 DAC_SDO => DAC_SDO,
313 313 DAC_SCK => DAC_SCK,
314 314 DAC_SYNC => DAC_SYNC,
315 315 DAC_CAL_EN => DAC_CAL_EN,
316 316
317 317 coarse_time => coarse_time,
318 318 fine_time => fine_time,
319 319 LFR_soft_rstn => LFR_soft_rstn
320 320 );
321 321
322 322 -----------------------------------------------------------------------
323 323 --- SpaceWire --------------------------------------------------------
324 324 -----------------------------------------------------------------------
325 325
326 326 -- SPW_EN <= '1';
327 327
328 328 spw_clk <= clk_50_s;
329 329 spw_rxtxclk <= spw_clk;
330 330 spw_rxclkn <= NOT spw_rxtxclk;
331 331
332 332 -- PADS for SPW1
333 333 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
334 334 PORT MAP (spw1_din, dtmp(0));
335 335 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
336 336 PORT MAP (spw1_sin, stmp(0));
337 337 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
338 338 PORT MAP (spw1_dout, swno.d(0));
339 339 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
340 340 PORT MAP (spw1_sout, swno.s(0));
341 341 -- PADS FOR SPW2
342 342 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
343 343 PORT MAP (spw2_din, dtmp(1));
344 344 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 345 PORT MAP (spw2_sin, stmp(1));
346 346 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
347 347 PORT MAP (spw2_dout, swno.d(1));
348 348 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
349 349 PORT MAP (spw2_sout, swno.s(1));
350 350
351 351 -- GRSPW PHY
352 352 --spw1_input: if CFG_SPW_GRSPW = 1 generate
353 353 spw_inputloop : FOR j IN 0 TO 1 GENERATE
354 354 spw_phy0 : grspw_phy
355 355 GENERIC MAP(
356 356 tech => apa3e,
357 357 rxclkbuftype => 1,
358 358 scantest => 0)
359 359 PORT MAP(
360 360 rxrst => swno.rxrst,
361 361 di => dtmp(j),
362 362 si => stmp(j),
363 363 rxclko => spw_rxclk(j),
364 364 do => swni.d(j),
365 365 ndo => swni.nd(j*5+4 DOWNTO j*5),
366 366 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
367 367 END GENERATE spw_inputloop;
368 368
369 369 -- SPW core
370 370 sw0 : grspwm GENERIC MAP(
371 371 tech => apa3e,
372 372 hindex => 1,
373 373 pindex => 5,
374 374 paddr => 5,
375 375 pirq => 11,
376 376 sysfreq => 25000, -- CPU_FREQ
377 377 rmap => 1,
378 378 rmapcrc => 1,
379 379 fifosize1 => 16,
380 380 fifosize2 => 16,
381 381 rxclkbuftype => 1,
382 382 rxunaligned => 0,
383 383 rmapbufs => 4,
384 384 ft => 0,
385 385 netlist => 0,
386 386 ports => 2,
387 387 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
388 388 memtech => apa3e,
389 389 destkey => 2,
390 390 spwcore => 1
391 391 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
392 392 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
393 393 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
394 394 )
395 395 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
396 396 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
397 397 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
398 398 swni, swno);
399 399
400 400 swni.tickin <= '0';
401 401 swni.rmapen <= '1';
402 402 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
403 403 swni.tickinraw <= '0';
404 404 swni.timein <= (OTHERS => '0');
405 405 swni.dcrstval <= (OTHERS => '0');
406 406 swni.timerrstval <= (OTHERS => '0');
407 407
408 408 -------------------------------------------------------------------------------
409 409 -- LFR ------------------------------------------------------------------------
410 410 -------------------------------------------------------------------------------
411 411 LFR_rstn <= LFR_soft_rstn AND rstn_25;
412 412
413 413 lpp_lfr_1 : lpp_lfr
414 414 GENERIC MAP (
415 415 Mem_use => use_RAM,
416 416 tech => inferred,
417 417 nb_data_by_buffer_size => 32,
418 418 --nb_word_by_buffer_size => 30,
419 419 nb_snapshot_param_size => 32,
420 420 delta_vector_size => 32,
421 421 delta_vector_size_f0_2 => 7, -- log2(96)
422 422 pindex => 15,
423 423 paddr => 15,
424 424 pmask => 16#fff#,
425 425 pirq_ms => 6,
426 426 pirq_wfp => 14,
427 427 hindex => 2,
428 top_lfr_version => X"010153", -- aa.bb.cc version
429 -- AA : BOARD NUMBER
430 -- 0 => MINI_LFR
431 -- 1 => EM
432 DEBUG_FORCE_DATA_DMA => 0)
428 top_lfr_version => LPP_LFR_BOARD_LFR_EM & X"015B",
429 DEBUG_FORCE_DATA_DMA => 0,
430 DATA_SHAPING_SATURATION => 1 )
433 431 PORT MAP (
434 432 clk => clk_25,
435 433 rstn => LFR_rstn,
436 434 sample_B => sample_s(2 DOWNTO 0),
437 435 sample_E => sample_s(7 DOWNTO 3),
438 436 sample_val => sample_val,
439 437 apbi => apbi_ext,
440 438 apbo => apbo_ext(15),
441 439 ahbi => ahbi_m_ext,
442 440 ahbo => ahbo_m_ext(2),
443 441 coarse_time => coarse_time,
444 442 fine_time => fine_time,
445 443 data_shaping_BW => bias_fail_sw,
446 444 debug_vector => OPEN,
447 445 debug_vector_ms => OPEN); --,
448 446 --observation_vector_0 => OPEN,
449 447 --observation_vector_1 => OPEN,
450 448 --observation_reg => observation_reg);
451 449
452 450
453 451 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
454 452 sample_s(I) <= sample(I) & '0' & '0';
455 453 END GENERATE all_sample;
456 454 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
457 455
458 456 -----------------------------------------------------------------------------
459 457 --
460 458 -----------------------------------------------------------------------------
461 459 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
462 460 GENERIC MAP (
463 461 ChanelCount => 9,
464 462 ncycle_cnv_high => 12,
465 463 ncycle_cnv => 25,
466 464 FILTER_ENABLED => 16#FF#)
467 465 PORT MAP (
468 466 cnv_clk => clk_24,
469 467 cnv_rstn => rstn_24,
470 468 cnv => ADC_smpclk_s,
471 469 clk => clk_25,
472 470 rstn => rstn_25,
473 471 ADC_data => ADC_data,
474 472 ADC_nOE => ADC_OEB_bar_CH_s,
475 473 sample => sample,
476 474 sample_val => sample_val);
477 475
478 476 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
479 477
480 478 ADC_smpclk <= ADC_smpclk_s;
481 479 HK_smpclk <= ADC_smpclk_s;
482 480
483 481 TAG8 <= ADC_smpclk_s;
484 482
485 483 -----------------------------------------------------------------------------
486 484 -- HK
487 485 -----------------------------------------------------------------------------
488 486 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
489 487
490 488 END beh;
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@@ -1,53 +1,53
1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=LFR_em
5 BOARD=em-LeonLPP-A3PE3kL-v3-core1
5 BOARD=LFR-EM
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 9 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 10 EFFORT=high
11 11 XSTOPT=
12 12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 13 VHDLSYNFILES=LFR-em.vhd
14 14 VHDLSIMFILES=testbench.vhd
15 15
16 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc
16 PDC=$(VHDLIB)/boards/$(BOARD)/LFR-EM.pdc
17 17
18 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
18 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
19 19 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
20 20
21 21 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
22 22 CLEAN=soft-clean
23 23
24 24 TECHLIBS = proasic3e
25 25
26 26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 27 tmtc openchip hynix ihp gleichmann micron usbhc opencores can greth
28 28
29 29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 31 ./amba_lcd_16x2_ctrlr \
32 32 ./general_purpose/lpp_AMR \
33 33 ./general_purpose/lpp_balise \
34 34 ./general_purpose/lpp_delay \
35 35 ./lpp_bootloader \
36 36 ./dsp/lpp_fft_rtax \
37 37 ./lpp_uart \
38 38 ./lpp_usb \
39 39 ./lpp_sim/CY7C1061DV33 \
40 40
41 41 FILESKIP = i2cmst.vhd \
42 42 APB_MULTI_DIODE.vhd \
43 43 APB_MULTI_DIODE.vhd \
44 44 Top_MatrixSpec.vhd \
45 45 APB_FFT.vhd\
46 46 CoreFFT_simu.vhd \
47 47 lpp_lfr_apbreg_simu.vhd
48 48
49 49 include $(GRLIB)/bin/Makefile
50 50 include $(GRLIB)/software/leon3/Makefile
51 51
52 52 ################## project specific targets ##########################
53 53
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