# HG changeset patch # User Alexis Jeandet # Date 2016-12-07 14:03:57 # Node ID f19abbf47ea7e81b3566763ec7538a2773d36404 # Parent 70d63ed48614dffdb8a656030bbc3a509d983615 Renamed em-LeonLPP-A3PE3kL-v3-core1 boards in LFR-EM boards Renamed LFR-em-WFP_MS designs in SOLO_LFR_LFR-EM designs Updated LFR-EM boards constraints => PDC file => SDC file for the place and route Updated SOLO_LFR_LFR-EM designs => added DATA_SHAPING_SATURATION in LPP_FILTER => changed boards number : LPP_LFR_BOARD_LFR_EM & X"015B" diff --git a/boards/LFR-EM/LFR-172200-EM-RTAX.pdc b/boards/LFR-EM/LFR-172200-EM-RTAX.pdc deleted file mode 100644 --- a/boards/LFR-EM/LFR-172200-EM-RTAX.pdc +++ /dev/null @@ -1,684 +0,0 @@ -# Actel Physical design constraints file -# Generated file - -# Version: 9.1 SP3 9.1.3.4 -# Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA -# Date generated: Tue Oct 18 08:21:45 2011 - - -# -# IO banks setting -# - - -# -# I/O constraints -# - -set_io clk_50 \ - -pinname 318 \ - -fixed yes \ - -DIRECTION Inout - -set_io clk_49 \ - -pinname 314 \ - -fixed yes \ - -DIRECTION Inout - -set_io reset \ - -pinname 212 \ - -fixed yes \ - -DIRECTION Inout -#==================================================================== -# BPs -#==================================================================== -set_io BP0 \ - -pinname 211 \ - -fixed yes \ - -DIRECTION Inout - -set_io BP1 \ - -pinname 208 \ - -fixed yes \ - -DIRECTION Inout - -#==================================================================== -# LEDs -#==================================================================== - -set_io LED0 \ - -pinname 217 \ - -fixed yes \ - -DIRECTION Inout - -set_io LED1 \ - -pinname 214 \ - -fixed yes \ - -DIRECTION Inout - -set_io LED2 \ - -pinname 213 \ - -fixed yes \ - -DIRECTION Inout - -#==================================================================== -# TAG CONNECTOR -#==================================================================== - -set_io TAG1 \ - -pinname 195 \ - -fixed yes \ - -DIRECTION Inout - -set_io TAG2 \ - -pinname 189 \ - -fixed yes \ - -DIRECTION Inout - -set_io TAG3 \ - -pinname 188 \ - -fixed yes \ - -DIRECTION Inout - -set_io TAG4 \ - -pinname 187 \ - -fixed yes \ - -DIRECTION Inout - -set_io TAG5 \ - -pinname 184 \ - -fixed yes \ - -DIRECTION Inout - -set_io TAG6 \ - -pinname 183 \ - -fixed yes \ - -DIRECTION Inout - -set_io TAG7 \ - -pinname 94 \ - -fixed yes \ - -DIRECTION Inout - -set_io TAG8 \ - -pinname 93 \ - -fixed yes \ - -DIRECTION Inout - -set_io TAG9 \ - -pinname 92 \ - -fixed yes \ - -DIRECTION Inout - -#==================================================================== -# SPACE WIRE -#==================================================================== - #================================ - # NOMINAL LINK - #================================ - -set_io SPW_NOM_DIN \ - -pinname 331 \ - -fixed yes \ - -DIRECTION Inout - -set_io SPW_NOM_SIN \ - -pinname 332 \ - -fixed yes \ - -DIRECTION Inout - -set_io SPW_NOM_DOUT \ - -pinname 303 \ - -fixed yes \ - -DIRECTION Inout - -set_io SPW_NOM_SOUT \ - -pinname 317 \ - -fixed yes \ - -DIRECTION Inout - - #================================ - # REDUNDANT LINK - #================================ - -set_io SPW_RED_DIN \ - -pinname 313 \ - -fixed yes \ - -DIRECTION Inout - -set_io SPW_RED_SIN \ - -pinname 304 \ - -fixed yes \ - -DIRECTION Inout - -set_io SPW_RED_DOUT \ - -pinname 335 \ - -fixed yes \ - -DIRECTION Inout - -set_io SPW_RED_SOUT \ - -pinname 330 \ - -fixed yes \ - -DIRECTION Inout - - -#==================================================================== -# SCM CALIBRATION -#==================================================================== - -set_io SCM_CAL_EN \ - -pinname 336 \ - -fixed yes \ - -DIRECTION Inout - -set_io SCM_CAL_DIN \ - -pinname 341 \ - -fixed yes \ - -DIRECTION Inout - -set_io SCM_CAL_SCLK \ - -pinname 338 \ - -fixed yes \ - -DIRECTION Inout - -set_io SCM_CAL_nSYNC \ - -pinname 337 \ - -fixed yes \ - -DIRECTION Inout - -#==================================================================== -# HOUSEKEEPING -#==================================================================== - -set_io HK_SEL0 \ - -pinname 6 \ - -fixed yes \ - -DIRECTION Inout - -set_io HK_SEL1 \ - -pinname 343 \ - -fixed yes \ - -DIRECTION Inout - -set_io HK_SMPCLK \ - -pinname 172 \ - -fixed yes \ - -DIRECTION Inout - -set_io HK_nOEB \ - -pinname 299 \ - -fixed yes \ - -DIRECTION Inout - -#==================================================================== -# LFR ADC INPUTS -#==================================================================== - -set_io BIAS_FAIL \ - -pinname 342 \ - -fixed yes \ - -DIRECTION Inout - -set_io SMP_CLK \ - -pinname 279 \ - -fixed yes \ - -DIRECTION Inout - - #================================ - # ADC OEB - #================================ - -set_io nOEB\[0\] \ - -pinname 282 \ - -fixed yes \ - -DIRECTION Inout - -set_io nOEB\[1\] \ - -pinname 280 \ - -fixed yes \ - -DIRECTION Inout - -set_io nOEB\[2\] \ - -pinname 288 \ - -fixed yes \ - -DIRECTION Inout - -set_io nOEB\[3\] \ - -pinname 287 \ - -fixed yes \ - -DIRECTION Inout - -set_io nOEB\[4\] \ - -pinname 281 \ - -fixed yes \ - -DIRECTION Inout - -set_io nOEB\[5\] \ - -pinname 300 \ - -fixed yes \ - -DIRECTION Inout - -set_io nOEB\[6\] \ - -pinname 286 \ - -fixed yes \ - -DIRECTION Inout - -set_io nOEB\[7\] \ - -pinname 285 \ - -fixed yes \ - -DIRECTION Inout - - #================================ - # ADC DATA - #================================ - -set_io ADC_D\[0\] \ - -pinname 276 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[1\] \ - -pinname 275 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[2\] \ - -pinname 274 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[3\] \ - -pinname 273 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[4\] \ - -pinname 270 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[5\] \ - -pinname 269 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[6\] \ - -pinname 260 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[7\] \ - -pinname 259 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[8\] \ - -pinname 258 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[9\] \ - -pinname 257 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[10\] \ - -pinname 254 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[11\] \ - -pinname 253 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[12\] \ - -pinname 252 \ - -fixed yes \ - -DIRECTION Inout - -set_io ADC_D\[13\] \ - -pinname 251 \ - -fixed yes \ - -DIRECTION Inout - - -#==================================================================== -# SRAM -#==================================================================== - - #================================ - # SRAM CTRL - #================================ - -set_io SRAM_nWE \ - -pinname 233 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_CE \ - -pinname 64 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_nOE \ - -pinname 142 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_nBE\[0\] \ - -pinname 153 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_nBE\[1\] \ - -pinname 218 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_nBE\[2\] \ - -pinname 190 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_nBE\[3\] \ - -pinname 229 \ - -fixed yes \ - -DIRECTION Inout - - - #================================ - # SRAM ADDRESS - #================================ - -set_io SRAM_A\[0\] \ - -pinname 240 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[1\] \ - -pinname 239 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[2\] \ - -pinname 236 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[3\] \ - -pinname 235 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[4\] \ - -pinname 234 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[5\] \ - -pinname 123 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[6\] \ - -pinname 124 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[7\] \ - -pinname 127 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[8\] \ - -pinname 137 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[9\] \ - -pinname 141 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[10\] \ - -pinname 154 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[11\] \ - -pinname 155 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[12\] \ - -pinname 159 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[13\] \ - -pinname 160 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[14\] \ - -pinname 161 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[15\] \ - -pinname 76 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[16\] \ - -pinname 71 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[17\] \ - -pinname 70 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[18\] \ - -pinname 66 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_A\[19\] \ - -pinname 65 \ - -fixed yes \ - -DIRECTION Inout - - - #================================ - # SRAM DATA - #================================ - -set_io SRAM_DQ\[0\] \ - -pinname 207 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[1\] \ - -pinname 206 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[2\] \ - -pinname 205 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[3\] \ - -pinname 201 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[4\] \ - -pinname 171 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[5\] \ - -pinname 167 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[6\] \ - -pinname 166 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[7\] \ - -pinname 165 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[8\] \ - -pinname 77 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[9\] \ - -pinname 78 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[10\] \ - -pinname 79 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[11\] \ - -pinname 82 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[12\] \ - -pinname 61 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[13\] \ - -pinname 52 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[14\] \ - -pinname 49 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[15\] \ - -pinname 48 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[16\] \ - -pinname 241 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[17\] \ - -pinname 242 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[18\] \ - -pinname 245 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[19\] \ - -pinname 246 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[20\] \ - -pinname 156 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[21\] \ - -pinname 162 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[22\] \ - -pinname 181 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[23\] \ - -pinname 182 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[24\] \ - -pinname 196 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[25\] \ - -pinname 199 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[26\] \ - -pinname 200 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[27\] \ - -pinname 202 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[28\] \ - -pinname 224 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[29\] \ - -pinname 223 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[30\] \ - -pinname 227 \ - -fixed yes \ - -DIRECTION Inout - -set_io SRAM_DQ\[31\] \ - -pinname 228 \ - -fixed yes \ - -DIRECTION Inout - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/boards/LFR-EM/LFR-EM.pdc b/boards/LFR-EM/LFR-EM.pdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EM/LFR-EM.pdc @@ -0,0 +1,127 @@ +set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout +set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout +set_io reset -pinname N18 -fixed yes -DIRECTION Inout + +set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout +set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout +set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout +set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout +set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout +set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout +set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout +set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout +set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout +set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout +set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout +set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout +set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout +set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout +set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout +set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout +set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout +set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout +set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout +set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout + +set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout +set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout +set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout +set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout +set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout +set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout +set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout +set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout +set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout +set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout +set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout +set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout +set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout +set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout +set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout +set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout +set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout +set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout +set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout +set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout +set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout +set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout +set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout +set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout +set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout +set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout +set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout +set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout +set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout +set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout +set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout +set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout + +set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout +set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout +set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout +set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout +set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout +set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout +set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout + +set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout +set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout +set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout +set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout + +set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout +set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout +set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout +set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout + +set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout +set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout +set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout + +#set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout +set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout +set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout +set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout +#set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout +#set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout +#set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout +set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout +#set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout + +set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout + +set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout + +set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout + +set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout +set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout +set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout +set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout + +set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout +set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout +set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout +set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout +set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout +set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout +set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout +set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout +set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout +set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout +set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout +set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout +set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout +set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout + +set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout +set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout +set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout +set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout diff --git a/boards/LFR-EM/LFR_EM_place_and_route.sdc b/boards/LFR-EM/LFR_EM_place_and_route.sdc new file mode 100644 --- /dev/null +++ b/boards/LFR-EM/LFR_EM_place_and_route.sdc @@ -0,0 +1,114 @@ +################################################################################ +# SDC WRITER VERSION "3.1"; +# DESIGN "LFR_EQM"; +# Timing constraints scenario: "Primary"; +# DATE "Fri Apr 24 16:02:16 2015"; +# VENDOR "Actel"; +# PROGRAM "Actel Designer Software Release v9.1 SP5"; +# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. +################################################################################ + + +set sdc_version 1.7 + + +######## Clock Constraints ######## + +create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz } + +create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } + +create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } + +create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } + +create_clock -name { SPW1_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y } + +create_clock -name { SPW0_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y } + + + +######## Generated Clock Constraints ######## + + + +######## Clock Source Latency Constraints ######### + + + +######## Input Delay Constraints ######## + +set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] +set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ +data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ +data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ +data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] + +#set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] +#set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] +#set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] + + + +######## Output Delay Constraints ######## + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ +data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ +data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ +data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ +address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ +address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \ +address[7] address[8] address[9] }] + +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }] + + +######## Delay Constraints ######## + +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}] + +set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}] + + +######## Delay Constraints ######## + + + +######## Multicycle Constraints ######## + + + +######## False Path Constraints ######## + + + +######## Output load Constraints ######## + + + +######## Disable Timing Constraints ######### + + + +######## Clock Uncertainty Constraints ######### + + + diff --git a/boards/LFR-EM/Makefile.inc b/boards/LFR-EM/Makefile.inc --- a/boards/LFR-EM/Makefile.inc +++ b/boards/LFR-EM/Makefile.inc @@ -1,18 +1,19 @@ -TECHNOLOGY=PROASIC3 PACKAGE=\"\" SPEED=Std SYNFREQ=50 -PART=A3PE3000L +TECHNOLOGY=ProASIC3E +LIBERO_DIE=IT14X14M4 +PART=A3PE3000 + +DESIGNER_VOLTAGE=COM +DESIGNER_TEMP=COM DESIGNER_PACKAGE=FBGA DESIGNER_PINS=324 -DESIGNER_VOLTAGE=COM -DESIGNER_TEMP=COM MANUFACTURER=Actel +MGCTECHNOLOGY=Proasic3 MGCPART=$(PART) -MGCTECHNOLOGY=PROASIC3 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} -LIBERO_DIE=IT14X14M4LDP LIBERO_PACKAGE=fg$(DESIGNER_PINS) diff --git a/boards/LFR-EM/default.sdc b/boards/LFR-EM/default.sdc deleted file mode 100644 --- a/boards/LFR-EM/default.sdc +++ /dev/null @@ -1,59 +0,0 @@ -# Synplicity, Inc. constraint file -# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc -# Written on Wed Aug 1 19:29:24 2007 -# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor - -# -# Collections -# - -# -# Clocks -# -define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# -define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} -define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} - - -# -# Registers -# - -# -# Multicycle Path -# - -# -# False Path -# - -# -# Path Delay -# - -# -# Attributes -# -define_global_attribute syn_useioff {1} -define_global_attribute -disable syn_netlist_hierarchy {0} -define_attribute {etx_clk} syn_noclockbuf {1} - -# -# I/O standards -# - -# -# Compile Points -# - -# -# Other Constraints -# diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR-em_1.1.85.pdc b/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR-em_1.1.85.pdc deleted file mode 100644 --- a/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR-em_1.1.85.pdc +++ /dev/null @@ -1,127 +0,0 @@ -set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout -set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout -set_io reset -pinname N18 -fixed yes -DIRECTION Inout - -set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout -set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout -set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout -set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout -set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout -set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout -set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout -set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout -set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout -set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout -set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout -set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout -set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout -set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout -set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout -set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout -set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout -set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout -set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout -set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout - -set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout -set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout -set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout -set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout -set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout -set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout -set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout -set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout -set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout -set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout -set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout -set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout -set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout -set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout -set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout -set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout -set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout -set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout -set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout -set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout -set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout -set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout -set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout -set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout -set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout -set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout -set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout -set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout -set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout -set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout -set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout -set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout - -set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout -set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout -set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout -set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout -set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout -set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout -set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout - -set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout -set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout -set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout -set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout - -set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout -set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout -set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout -set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout - -set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout -set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout -set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout - -#set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout -set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout -#set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout -set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout -#set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout -#set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout -#set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout -set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout -#set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout - -set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout - -set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout -set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout - -set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout - -set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout -set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout -set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout -set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout - -set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout -set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout -set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout -set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout -set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout -set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout -set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout -set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout -set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout -set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout -set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout -set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout -set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout -set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout - -set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout -set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout -set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout -set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR-em_1.1.85.sdc b/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR-em_1.1.85.sdc deleted file mode 100644 --- a/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR-em_1.1.85.sdc +++ /dev/null @@ -1,114 +0,0 @@ -################################################################################ -# SDC WRITER VERSION "3.1"; -# DESIGN "LFR_EQM"; -# Timing constraints scenario: "Primary"; -# DATE "Fri Apr 24 16:02:16 2015"; -# VENDOR "Actel"; -# PROGRAM "Actel Designer Software Release v9.1 SP5"; -# VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. -################################################################################ - - -set sdc_version 1.7 - - -######## Clock Constraints ######## - -create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz } - -create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } - -create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } - -create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } - -create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } - -create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } - - - -######## Generated Clock Constraints ######## - - - -######## Clock Source Latency Constraints ######### - - - -######## Input Delay Constraints ######## - -set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] -set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ -data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ -data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ -data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] - -#set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] -#set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] -#set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] - - - -######## Output Delay Constraints ######## - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ -data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ -data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ -data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ -address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ -address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \ -address[7] address[8] address[9] }] - -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }] - - -######## Delay Constraints ######## - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}] - -set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}] - - -######## Delay Constraints ######## - - - -######## Multicycle Constraints ######## - - - -######## False Path Constraints ######## - - - -######## Output load Constraints ######## - - - -######## Disable Timing Constraints ######### - - - -######## Clock Uncertainty Constraints ######### - - - diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_place_and_route.sdc b/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_place_and_route.sdc deleted file mode 100644 --- a/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_place_and_route.sdc +++ /dev/null @@ -1,31 +0,0 @@ -# Top Level Design Parameters - -# Clocks - -create_clock -period 10.000000 -waveform {0.000000 5.000000} clk100MHz -create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz -create_clock -period 20.000000 -waveform {0.000000 10.000000} clk_50_s:Q -create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q -create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q -create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} - - -# False Paths Between Clocks - - -# False Path Constraints - - -# Maximum Delay Constraints - - -# Multicycle Constraints - - -# Virtual Clocks -# Output Load Constraints -# Driving Cell Constraints -# Wire Loads -# set_wire_load_mode top - -# Other Constraints diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_synthesis.sdc b/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_synthesis.sdc deleted file mode 100644 --- a/boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_synthesis.sdc +++ /dev/null @@ -1,61 +0,0 @@ -# Synplicity, Inc. constraint file -# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc -# Written on Wed Aug 1 19:29:24 2007 -# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor - -# -# Collections -# - -# -# Clocks -# - -define_clock -name {clk100MHz} -freq 100 -clockgroup default_clkgroup_50 -route 5 -define_clock -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_49 -route 5 - -# -# Clock to Clock -# - -# -# Inputs/Outputs -# - - -# -# Registers -# - -# -# Multicycle Path -# - -# -# False Path -# - -set_false_path -from reset - -# -# Path Delay -# - -# -# Attributes -# - -define_global_attribute syn_useioff {1} -define_global_attribute -disable syn_netlist_hierarchy {0} - -# -# I/O standards -# - -# -# Compile Points -# - -# -# Other Constraints -# diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/Makefile.inc b/boards/em-LeonLPP-A3PE3kL-v3-core1/Makefile.inc deleted file mode 100644 --- a/boards/em-LeonLPP-A3PE3kL-v3-core1/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -PACKAGE=\"\" -SPEED=Std -SYNFREQ=50 - -TECHNOLOGY=ProASIC3E -LIBERO_DIE=IT14X14M4 -PART=A3PE3000 - -DESIGNER_VOLTAGE=COM -DESIGNER_TEMP=COM -DESIGNER_PACKAGE=FBGA -DESIGNER_PINS=324 - -MANUFACTURER=Actel -MGCTECHNOLOGY=Proasic3 -MGCPART=$(PART) -MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} -LIBERO_PACKAGE=fg$(DESIGNER_PINS) - diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/data/em-LeonLPP-A3PE3kL.pdc.ce b/boards/em-LeonLPP-A3PE3kL-v3-core1/data/em-LeonLPP-A3PE3kL.pdc.ce deleted file mode 100644 index 85dbcbf26f6540f534dc69937df1526dcfa0dc5a..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 GIT binary patch literal 0 Hc$@ 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"010153", -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - DEBUG_FORCE_DATA_DMA => 0) + top_lfr_version => LPP_LFR_BOARD_LFR_EM & X"015B", + DEBUG_FORCE_DATA_DMA => 0, + DATA_SHAPING_SATURATION => 1 ) PORT MAP ( clk => clk_25, rstn => LFR_rstn, diff --git a/designs/LFR-em-WFP_MS/Makefile b/designs/SOLO_LFR_LFR-EM/Makefile rename from designs/LFR-em-WFP_MS/Makefile rename to designs/SOLO_LFR_LFR-EM/Makefile --- a/designs/LFR-em-WFP_MS/Makefile +++ b/designs/SOLO_LFR_LFR-EM/Makefile @@ -2,7 +2,7 @@ VHDLIB=../.. SCRIPTSDIR=$(VHDLIB)/scripts/ GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) TOP=LFR_em -BOARD=em-LeonLPP-A3PE3kL-v3-core1 +BOARD=LFR-EM include $(VHDLIB)/boards/$(BOARD)/Makefile.inc DEVICE=$(PART)-$(PACKAGE)$(SPEED) UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf @@ -13,9 +13,9 @@ SYNPOPT="set_option -pipe 0; set_option VHDLSYNFILES=LFR-em.vhd VHDLSIMFILES=testbench.vhd -PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc +PDC=$(VHDLIB)/boards/$(BOARD)/LFR-EM.pdc -SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc +SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut diff --git a/designs/SOLO_LFR_LFR-EM/README.md b/designs/SOLO_LFR_LFR-EM/README.md new file mode 100644 --- /dev/null +++ b/designs/SOLO_LFR_LFR-EM/README.md @@ -0,0 +1,2 @@ +SOLO\_LFR\_LFR-EM is the implementation of Solar Orbiter LFR analyser for the board LFR-EM. +