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LPP DMA v1.0.1...
pellion@stage-ps1.lab-lpp.local -
r102:ecadbe9f5050 JC
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@@ -27,7 +27,7 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 USE grlib.devices.ALL;
29 29 USE GRLIB.DMA2AHB_Package.ALL;
30 --USE GRLIB.DMA2AHB_TestPackage.ALL;
30
31 31 LIBRARY lpp;
32 32 USE lpp.lpp_amba.ALL;
33 33 USE lpp.apb_devices_list.ALL;
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@@ -28,7 +28,7 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 USE GRLIB.DMA2AHB_Package.ALL;
31 --USE GRLIB.DMA2AHB_TestPackage.ALL;
31
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_amba.ALL;
34 34 USE lpp.apb_devices_list.ALL;
@@ -136,6 +136,8 ARCHITECTURE Behavioral OF lpp_dma IS
136 136 SIGNAL fifo_ren_trash : STD_LOGIC;
137 137 SIGNAL component_fifo_ren : STD_LOGIC;
138 138
139 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140
139 141 BEGIN
140 142
141 143 -----------------------------------------------------------------------------
@@ -149,7 +151,7 BEGIN
149 151 deviceid => 0,
150 152 version => 0,
151 153 syncrst => 1,
152 boundary => 0)
154 boundary => 1) -- set TO TEST
153 155 PORT MAP (
154 156 HCLK => HCLK,
155 157 HRESETn => HRESETn,
@@ -158,6 +160,25 BEGIN
158 160 AHBIn => AHB_Master_In,
159 161 AHBOut => AHB_Master_Out);
160 162
163
164 debug_info: PROCESS (HCLK, HRESETn)
165 BEGIN -- PROCESS debug_info
166 IF HRESETn = '0' THEN -- asynchronous reset (active low)
167 debug_reg <= (OTHERS => '0');
168 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
169 debug_reg(0) <= debug_reg(0) OR (DMAOut.Retry );
170 debug_reg(1) <= debug_reg(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
171 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
172 debug_reg(3) <= debug_reg(3) OR (header_send_ko);
173 debug_reg(4) <= debug_reg(4) OR (header_send_ok);
174 debug_reg(5) <= debug_reg(5) OR (component_send_ko);
175 debug_reg(6) <= debug_reg(6) OR (component_send_ok);
176
177 debug_reg(31 DOWNTO 7) <= (OTHERS => '1');
178 END IF;
179 END PROCESS debug_info;
180
181
161 182 matrix_type <= header(1 DOWNTO 0);
162 183 component_type <= header(5 DOWNTO 2);
163 184
@@ -312,7 +333,6 BEGIN
312 333 HRESETn => HRESETn,
313 334 DMAIn => component_dmai,
314 335 DMAOut => DMAOut,
315
316 336 send => component_send,
317 337 address => address,
318 338 data => fifo_data,
@@ -343,9 +363,11 BEGIN
343 363 ready_matrix_f0_0 => ready_matrix_f0_0,
344 364 ready_matrix_f0_1 => ready_matrix_f0_1,
345 365 ready_matrix_f1 => ready_matrix_f1,
346 ready_matrix_f2 => ready_matrix_f2,
366 ready_matrix_f2 => ready_matrix_f2,
347 367 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
348 368 error_bad_component_error => error_bad_component_error,
369 --
370 debug_reg => debug_reg,
349 371 -- OUT
350 372 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
351 373 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
@@ -360,7 +382,6 BEGIN
360 382 addr_matrix_f1 => addr_matrix_f1,
361 383 addr_matrix_f2 => addr_matrix_f2);
362 384
363 -----------------------------------------------------------------------------
385 -----------------------------------------------------------------------------
364 386
365 387 END Behavioral;
366
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@@ -33,6 +33,7 USE lpp.apb_devices_list.ALL;
33 33 USE lpp.lpp_memory.ALL;
34 34 LIBRARY techmap;
35 35 USE techmap.gencomp.ALL;
36
36 37 ENTITY lpp_dma_apbreg IS
37 38 GENERIC (
38 39 pindex : INTEGER := 4;
@@ -55,6 +56,7 ENTITY lpp_dma_apbreg IS
55 56 ready_matrix_f2 : IN STD_LOGIC;
56 57 error_anticipating_empty_fifo : IN STD_LOGIC;
57 58 error_bad_component_error : IN STD_LOGIC;
59 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 60
59 61 -- OUT
60 62 status_ready_matrix_f0_0 : OUT STD_LOGIC;
@@ -162,32 +164,35 BEGIN -- beh
162 164 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
163 165 WHEN "000100" => prdata <= reg.addr_matrix_f1;
164 166 WHEN "000101" => prdata <= reg.addr_matrix_f2;
167 WHEN "000110" => prdata <= debug_reg;
165 168 WHEN OTHERS => NULL;
166 169 END CASE;
167 170 IF (apbi.pwrite AND apbi.penable) = '1' THEN
168 171 -- APB DMA WRITE --
169 172 CASE paddr(7 DOWNTO 2) IS
170 173 WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
171 reg.config_active_interruption_onError <= apbi.pwdata(1);
172 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
173 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
174 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
175 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
176 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
177 reg.status_error_bad_component_error <= apbi.pwdata(5);
178 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
179 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
180 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
181 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
174 reg.config_active_interruption_onError <= apbi.pwdata(1);
175 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
176 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
177 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
178 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
179 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
180 reg.status_error_bad_component_error <= apbi.pwdata(5);
181 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
182 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
183 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
184 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
182 185 WHEN OTHERS => NULL;
183 186 END CASE;
184 187 END IF;
185 188 END IF;
186 189 END IF;
187 190 END PROCESS lpp_dma_apbreg;
191
188 192 apbo.pirq <= (OTHERS => '0');
189 193 apbo.pindex <= pindex;
190 194 apbo.pconfig <= pconfig;
191 195 apbo.prdata <= prdata;
192 196
197
193 198 END beh;
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@@ -103,6 +103,7 PACKAGE lpp_dma_pkg IS
103 103 ready_matrix_f2 : IN STD_LOGIC;
104 104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 105 error_bad_component_error : IN STD_LOGIC;
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 107
107 108 -- OUT
108 109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
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@@ -1,3 +1,25
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
1 23
2 24 LIBRARY ieee;
3 25 USE ieee.std_logic_1164.ALL;
@@ -28,7 +50,7 ENTITY lpp_dma_send_16word IS
28 50 send : IN STD_LOGIC;
29 51 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
30 52 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
31 ren : OUT STD_LOGIC;
53 ren : OUT STD_LOGIC;
32 54 --
33 55 send_ok : OUT STD_LOGIC;
34 56 send_ko : OUT STD_LOGIC
@@ -37,124 +59,113 END lpp_dma_send_16word;
37 59
38 60 ARCHITECTURE beh OF lpp_dma_send_16word IS
39 61
40 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1,WAIT_LAST_READY);
62 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY);
41 63 SIGNAL state : state_fsm_send_16word;
42 64
43 SIGNAL data_counter : INTEGER;
65 SIGNAL data_counter : INTEGER;
44 66 SIGNAL grant_counter : INTEGER;
45 67
46 68 BEGIN -- beh
47 69
48 DMAIn.Beat <= HINCR16;
49 DMAIn.Size <= HSIZE32;
70 DMAIn.Beat <= HINCR16;
71 DMAIn.Size <= HSIZE32;
50 72
51 73 PROCESS (HCLK, HRESETn)
52 74 BEGIN -- PROCESS
53 IF HRESETn = '0' THEN -- asynchronous reset (active low)
54 state <= IDLE;
55 send_ok <= '0';
56 send_ko <= '0';
57
58 DMAIn.Reset <= '0';
59 DMAIn.Address <= (OTHERS => '0');
60 -- DMAIn.Data <= (others => '0');
61 DMAIn.Request <= '0';
62 DMAIn.Store <= '0';
63 DMAIn.Burst <= '1';
64 DMAIn.Lock <= '0';
65 data_counter <= 0;
75 IF HRESETn = '0' THEN -- asynchronous reset (active low)
76 state <= IDLE;
77 send_ok <= '0';
78 send_ko <= '0';
79
80 DMAIn.Reset <= '0';
81 DMAIn.Address <= (OTHERS => '0');
82 DMAIn.Request <= '0';
83 DMAIn.Store <= '0';
84 DMAIn.Burst <= '1';
85 DMAIn.Lock <= '0';
86 data_counter <= 0;
66 87 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
67 88
68 89 CASE state IS
69 90 WHEN IDLE =>
70 -- ren <= '1';
71 91 DMAIn.Store <= '1';
72 92 DMAIn.Request <= '0';
73 send_ok <= '0';
74 send_ko <= '0';
75 DMAIn.Address <= address;
76 data_counter <= 0;
77 DMAIn.Lock <= '0'; -- FIX test
93 send_ok <= '0';
94 send_ko <= '0';
95 DMAIn.Address <= address;
96 data_counter <= 0;
97 DMAIn.Lock <= '0'; -- FIX test
78 98 IF send = '1' THEN
79 state <= REQUEST_BUS;
80 DMAIn.Request <= '1';
81 DMAIn.Lock <= '1'; -- FIX test
82 DMAIn.Store <= '1';
99 state <= REQUEST_BUS;
100 DMAIn.Request <= '1';
101 DMAIn.Lock <= '1'; -- FIX test
102 DMAIn.Store <= '1';
83 103 END IF;
84 104 WHEN REQUEST_BUS =>
85 -- ren <= '1';
86 IF DMAOut.Grant='1' THEN
87 data_counter <= 1;
88 grant_counter <= 1;
89 -- ren <= '0';
90 state <= SEND_DATA;
105 IF DMAOut.Grant = '1' THEN
106 data_counter <= 1;
107 grant_counter <= 1;
108 state <= SEND_DATA;
91 109 END IF;
92 110 WHEN SEND_DATA =>
93 -- ren <= '1';
94 111
95 112 IF DMAOut.Fault = '1' THEN
96 DMAIn.Reset <= '0';
97 DMAIn.Address <= (others => '0');
98 -- DMAIn.Data <= (others => '0');
99 DMAIn.Request <= '0';
100 DMAIn.Store <= '0';
101 DMAIn.Burst <= '0';
102 state <= ERROR0;
113 DMAIn.Reset <= '0';
114 DMAIn.Address <= (OTHERS => '0');
115 DMAIn.Request <= '0';
116 DMAIn.Store <= '0';
117 DMAIn.Burst <= '0';
118 state <= ERROR0;
103 119 ELSE
104 120
105 121 IF DMAOut.Grant = '1' THEN
106 if grant_counter = 15 then
107 DMAIn.Reset <= '0';
108 DMAIn.Request <= '0';
109 DMAIn.Store <= '0';
110 DMAIn.Burst <= '0';
111 else
112 grant_counter <= grant_counter+1;
113 end if;
122 IF grant_counter = 15 THEN
123 DMAIn.Reset <= '0';
124 DMAIn.Request <= '0';
125 DMAIn.Store <= '0';
126 DMAIn.Burst <= '0';
127 ELSE
128 grant_counter <= grant_counter+1;
129 END IF;
114 130 END IF;
115 131
116 132 IF DMAOut.OKAY = '1' THEN
117 133 IF data_counter = 15 THEN
118 DMAIn.Address <= (others => '0');
119 state <= WAIT_LAST_READY;
134 DMAIn.Address <= (OTHERS => '0');
135 state <= WAIT_LAST_READY;
120 136 ELSE
121 --DMAIn.Data <= data;
122 data_counter <= data_counter + 1;
123 -- ren <= '0';
137 data_counter <= data_counter + 1;
124 138 END IF;
125 139 END IF;
126 140 END IF;
127
128
141
142
129 143 WHEN WAIT_LAST_READY =>
130 -- ren <= '1';
131 144 IF DMAOut.Ready = '1' THEN
132 145 IF grant_counter = 15 THEN
133 146 state <= IDLE;
134 147 send_ok <= '1';
135 148 send_ko <= '0';
136 149 ELSE
137 state <= ERROR0;
150 state <= ERROR0;
138 151 END IF;
139 152 END IF;
140 153
141 154 WHEN ERROR0 =>
142 -- ren <= '1';
143 155 state <= ERROR1;
144 156 WHEN ERROR1 =>
145 157 send_ok <= '0';
146 158 send_ko <= '1';
147 -- ren <= '1';
148 state <= IDLE;
159 state <= IDLE;
149 160 WHEN OTHERS => NULL;
150 161 END CASE;
151 162 END IF;
152 163 END PROCESS;
153 164
154 DMAIn.Data <= data;
165 DMAIn.Data <= data;
155 166
156 ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
157 '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
167 ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
168 '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
158 169 '1';
159 170
160 171 END beh;
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@@ -1,3 +1,25
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
1 23
2 24 LIBRARY ieee;
3 25 USE ieee.std_logic_1164.ALL;
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