# HG changeset patch # User pellion@stage-ps1.lab-lpp.local # Date 2013-01-30 14:20:57 # Node ID ecadbe9f5050643552b87c85a6c95f953deb8a14 # Parent 80568b98428c9681edbe9d41241468a7a648b96e LPP DMA v1.0.1 - Correction of bugs due to "AHB bursts and 1kB address boundary" - Add TB for DMA with a RTL model of the external RAM CYC1360C in designs/Projet-LeonLFR-AP3K-Sheldon_sim-all diff --git a/lib/lpp/lpp_dma/fifo_test_dma.vhd b/lib/lpp/lpp_dma/fifo_test_dma.vhd --- a/lib/lpp/lpp_dma/fifo_test_dma.vhd +++ b/lib/lpp/lpp_dma/fifo_test_dma.vhd @@ -27,7 +27,7 @@ USE grlib.amba.ALL; USE grlib.stdlib.ALL; USE grlib.devices.ALL; USE GRLIB.DMA2AHB_Package.ALL; ---USE GRLIB.DMA2AHB_TestPackage.ALL; + LIBRARY lpp; USE lpp.lpp_amba.ALL; USE lpp.apb_devices_list.ALL; diff --git a/lib/lpp/lpp_dma/lpp_dma.vhd b/lib/lpp/lpp_dma/lpp_dma.vhd --- a/lib/lpp/lpp_dma/lpp_dma.vhd +++ b/lib/lpp/lpp_dma/lpp_dma.vhd @@ -28,7 +28,7 @@ USE grlib.amba.ALL; USE grlib.stdlib.ALL; USE grlib.devices.ALL; USE GRLIB.DMA2AHB_Package.ALL; ---USE GRLIB.DMA2AHB_TestPackage.ALL; + LIBRARY lpp; USE lpp.lpp_amba.ALL; USE lpp.apb_devices_list.ALL; @@ -136,6 +136,8 @@ ARCHITECTURE Behavioral OF lpp_dma IS SIGNAL fifo_ren_trash : STD_LOGIC; SIGNAL component_fifo_ren : STD_LOGIC; + SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + BEGIN ----------------------------------------------------------------------------- @@ -149,7 +151,7 @@ BEGIN deviceid => 0, version => 0, syncrst => 1, - boundary => 0) + boundary => 1) -- set TO TEST PORT MAP ( HCLK => HCLK, HRESETn => HRESETn, @@ -158,6 +160,25 @@ BEGIN AHBIn => AHB_Master_In, AHBOut => AHB_Master_Out); + + debug_info: PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS debug_info + IF HRESETn = '0' THEN -- asynchronous reset (active low) + debug_reg <= (OTHERS => '0'); + ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge + debug_reg(0) <= debug_reg(0) OR (DMAOut.Retry ); + debug_reg(1) <= debug_reg(1) OR (DMAOut.Grant AND DMAOut.Retry) ; + IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF; + debug_reg(3) <= debug_reg(3) OR (header_send_ko); + debug_reg(4) <= debug_reg(4) OR (header_send_ok); + debug_reg(5) <= debug_reg(5) OR (component_send_ko); + debug_reg(6) <= debug_reg(6) OR (component_send_ok); + + debug_reg(31 DOWNTO 7) <= (OTHERS => '1'); + END IF; + END PROCESS debug_info; + + matrix_type <= header(1 DOWNTO 0); component_type <= header(5 DOWNTO 2); @@ -312,7 +333,6 @@ BEGIN HRESETn => HRESETn, DMAIn => component_dmai, DMAOut => DMAOut, - send => component_send, address => address, data => fifo_data, @@ -343,9 +363,11 @@ BEGIN ready_matrix_f0_0 => ready_matrix_f0_0, ready_matrix_f0_1 => ready_matrix_f0_1, ready_matrix_f1 => ready_matrix_f1, - ready_matrix_f2 => ready_matrix_f2, + ready_matrix_f2 => ready_matrix_f2, error_anticipating_empty_fifo => error_anticipating_empty_fifo, error_bad_component_error => error_bad_component_error, + -- + debug_reg => debug_reg, -- OUT status_ready_matrix_f0_0 => status_ready_matrix_f0_0, status_ready_matrix_f0_1 => status_ready_matrix_f0_1, @@ -360,7 +382,6 @@ BEGIN addr_matrix_f1 => addr_matrix_f1, addr_matrix_f2 => addr_matrix_f2); - ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- END Behavioral; - diff --git a/lib/lpp/lpp_dma/lpp_dma_apbreg.vhd b/lib/lpp/lpp_dma/lpp_dma_apbreg.vhd --- a/lib/lpp/lpp_dma/lpp_dma_apbreg.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_apbreg.vhd @@ -33,6 +33,7 @@ USE lpp.apb_devices_list.ALL; USE lpp.lpp_memory.ALL; LIBRARY techmap; USE techmap.gencomp.ALL; + ENTITY lpp_dma_apbreg IS GENERIC ( pindex : INTEGER := 4; @@ -55,6 +56,7 @@ ENTITY lpp_dma_apbreg IS ready_matrix_f2 : IN STD_LOGIC; error_anticipating_empty_fifo : IN STD_LOGIC; error_bad_component_error : IN STD_LOGIC; + debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- OUT status_ready_matrix_f0_0 : OUT STD_LOGIC; @@ -162,32 +164,35 @@ BEGIN -- beh WHEN "000011" => prdata <= reg.addr_matrix_f0_1; WHEN "000100" => prdata <= reg.addr_matrix_f1; WHEN "000101" => prdata <= reg.addr_matrix_f2; + WHEN "000110" => prdata <= debug_reg; WHEN OTHERS => NULL; END CASE; IF (apbi.pwrite AND apbi.penable) = '1' THEN -- APB DMA WRITE -- CASE paddr(7 DOWNTO 2) IS WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0); - reg.config_active_interruption_onError <= apbi.pwdata(1); - WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0); - reg.status_ready_matrix_f0_1 <= apbi.pwdata(1); - reg.status_ready_matrix_f1 <= apbi.pwdata(2); - reg.status_ready_matrix_f2 <= apbi.pwdata(3); - reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4); - reg.status_error_bad_component_error <= apbi.pwdata(5); - WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata; - WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata; - WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata; - WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata; + reg.config_active_interruption_onError <= apbi.pwdata(1); + WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0); + reg.status_ready_matrix_f0_1 <= apbi.pwdata(1); + reg.status_ready_matrix_f1 <= apbi.pwdata(2); + reg.status_ready_matrix_f2 <= apbi.pwdata(3); + reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4); + reg.status_error_bad_component_error <= apbi.pwdata(5); + WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata; + WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata; + WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata; + WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata; WHEN OTHERS => NULL; END CASE; END IF; END IF; END IF; END PROCESS lpp_dma_apbreg; + apbo.pirq <= (OTHERS => '0'); apbo.pindex <= pindex; apbo.pconfig <= pconfig; apbo.prdata <= prdata; + END beh; diff --git a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd --- a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd @@ -103,6 +103,7 @@ PACKAGE lpp_dma_pkg IS ready_matrix_f2 : IN STD_LOGIC; error_anticipating_empty_fifo : IN STD_LOGIC; error_bad_component_error : IN STD_LOGIC; + debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- OUT status_ready_matrix_f0_0 : OUT STD_LOGIC; diff --git a/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd b/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd --- a/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd @@ -1,3 +1,25 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; @@ -28,7 +50,7 @@ ENTITY lpp_dma_send_16word IS send : IN STD_LOGIC; address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - ren : OUT STD_LOGIC; + ren : OUT STD_LOGIC; -- send_ok : OUT STD_LOGIC; send_ko : OUT STD_LOGIC @@ -37,124 +59,113 @@ END lpp_dma_send_16word; ARCHITECTURE beh OF lpp_dma_send_16word IS - TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1,WAIT_LAST_READY); + TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY); SIGNAL state : state_fsm_send_16word; - SIGNAL data_counter : INTEGER; + SIGNAL data_counter : INTEGER; SIGNAL grant_counter : INTEGER; BEGIN -- beh - DMAIn.Beat <= HINCR16; - DMAIn.Size <= HSIZE32; + DMAIn.Beat <= HINCR16; + DMAIn.Size <= HSIZE32; PROCESS (HCLK, HRESETn) BEGIN -- PROCESS - IF HRESETn = '0' THEN -- asynchronous reset (active low) - state <= IDLE; - send_ok <= '0'; - send_ko <= '0'; - - DMAIn.Reset <= '0'; - DMAIn.Address <= (OTHERS => '0'); --- DMAIn.Data <= (others => '0'); - DMAIn.Request <= '0'; - DMAIn.Store <= '0'; - DMAIn.Burst <= '1'; - DMAIn.Lock <= '0'; - data_counter <= 0; + IF HRESETn = '0' THEN -- asynchronous reset (active low) + state <= IDLE; + send_ok <= '0'; + send_ko <= '0'; + + DMAIn.Reset <= '0'; + DMAIn.Address <= (OTHERS => '0'); + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '1'; + DMAIn.Lock <= '0'; + data_counter <= 0; ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge CASE state IS WHEN IDLE => --- ren <= '1'; DMAIn.Store <= '1'; DMAIn.Request <= '0'; - send_ok <= '0'; - send_ko <= '0'; - DMAIn.Address <= address; - data_counter <= 0; - DMAIn.Lock <= '0'; -- FIX test + send_ok <= '0'; + send_ko <= '0'; + DMAIn.Address <= address; + data_counter <= 0; + DMAIn.Lock <= '0'; -- FIX test IF send = '1' THEN - state <= REQUEST_BUS; - DMAIn.Request <= '1'; - DMAIn.Lock <= '1'; -- FIX test - DMAIn.Store <= '1'; + state <= REQUEST_BUS; + DMAIn.Request <= '1'; + DMAIn.Lock <= '1'; -- FIX test + DMAIn.Store <= '1'; END IF; WHEN REQUEST_BUS => --- ren <= '1'; - IF DMAOut.Grant='1' THEN - data_counter <= 1; - grant_counter <= 1; --- ren <= '0'; - state <= SEND_DATA; + IF DMAOut.Grant = '1' THEN + data_counter <= 1; + grant_counter <= 1; + state <= SEND_DATA; END IF; WHEN SEND_DATA => --- ren <= '1'; IF DMAOut.Fault = '1' THEN - DMAIn.Reset <= '0'; - DMAIn.Address <= (others => '0'); --- DMAIn.Data <= (others => '0'); - DMAIn.Request <= '0'; - DMAIn.Store <= '0'; - DMAIn.Burst <= '0'; - state <= ERROR0; + DMAIn.Reset <= '0'; + DMAIn.Address <= (OTHERS => '0'); + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '0'; + state <= ERROR0; ELSE IF DMAOut.Grant = '1' THEN - if grant_counter = 15 then - DMAIn.Reset <= '0'; - DMAIn.Request <= '0'; - DMAIn.Store <= '0'; - DMAIn.Burst <= '0'; - else - grant_counter <= grant_counter+1; - end if; + IF grant_counter = 15 THEN + DMAIn.Reset <= '0'; + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '0'; + ELSE + grant_counter <= grant_counter+1; + END IF; END IF; IF DMAOut.OKAY = '1' THEN IF data_counter = 15 THEN - DMAIn.Address <= (others => '0'); - state <= WAIT_LAST_READY; + DMAIn.Address <= (OTHERS => '0'); + state <= WAIT_LAST_READY; ELSE - --DMAIn.Data <= data; - data_counter <= data_counter + 1; --- ren <= '0'; + data_counter <= data_counter + 1; END IF; END IF; END IF; - - + + WHEN WAIT_LAST_READY => --- ren <= '1'; IF DMAOut.Ready = '1' THEN IF grant_counter = 15 THEN state <= IDLE; send_ok <= '1'; send_ko <= '0'; ELSE - state <= ERROR0; + state <= ERROR0; END IF; END IF; WHEN ERROR0 => --- ren <= '1'; state <= ERROR1; WHEN ERROR1 => send_ok <= '0'; send_ko <= '1'; --- ren <= '1'; - state <= IDLE; + state <= IDLE; WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; - DMAIn.Data <= data; + DMAIn.Data <= data; - ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE - '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE + ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE + '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE '1'; END beh; diff --git a/lib/lpp/lpp_dma/lpp_dma_send_1word.vhd b/lib/lpp/lpp_dma/lpp_dma_send_1word.vhd --- a/lib/lpp/lpp_dma/lpp_dma_send_1word.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_send_1word.vhd @@ -1,3 +1,25 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL;