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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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--USE GRLIB.DMA2AHB_TestPackage.ALL;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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ENTITY lpp_dma IS
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GENERIC (
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tech : INTEGER := inferred;
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hindex : INTEGER := 2;
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pindex : INTEGER := 4;
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paddr : INTEGER := 4;
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pmask : INTEGER := 16#fff#;
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pirq : INTEGER := 0);
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PORT (
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-- AMBA AHB system signals
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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-- AMBA APB Slave Interface
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apbi : IN apb_slv_in_type;
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apbo : OUT apb_slv_out_type;
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-- AMBA AHB Master Interface
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AHB_Master_In : IN AHB_Mst_In_Type;
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AHB_Master_Out : OUT AHB_Mst_Out_Type;
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-- fifo interface
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : IN STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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-- header
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header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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header_val : IN STD_LOGIC;
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header_ack : OUT STD_LOGIC
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);
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END;
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ARCHITECTURE Behavioral OF lpp_dma IS
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-----------------------------------------------------------------------------
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SIGNAL DMAIn : DMA_In_Type;
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SIGNAL header_dmai : DMA_In_Type;
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SIGNAL component_dmai : DMA_In_Type;
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SIGNAL DMAOut : DMA_OUt_Type;
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SIGNAL ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL ready_matrix_f1 : STD_LOGIC;
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SIGNAL ready_matrix_f2 : STD_LOGIC;
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SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL error_bad_component_error : STD_LOGIC;
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SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
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SIGNAL config_active_interruption_onError : STD_LOGIC;
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SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
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SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f1 : STD_LOGIC;
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SIGNAL status_ready_matrix_f2 : STD_LOGIC;
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SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
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SIGNAL status_error_bad_component_error : STD_LOGIC;
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SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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TYPE state_DMAWriteBurst IS (IDLE,
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TRASH_FIFO,
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WAIT_HEADER_ACK,
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SEND_DATA,
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WAIT_DATA_ACK,
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CHECK_LENGTH
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);
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SIGNAL state : state_DMAWriteBurst := IDLE;
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SIGNAL nbSend : INTEGER;
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SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL header_check_ok : STD_LOGIC;
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SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL send_matrix : STD_LOGIC;
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SIGNAL request : STD_LOGIC;
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SIGNAL remaining_data_request : INTEGER;
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SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL header_select : STD_LOGIC;
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SIGNAL header_send : STD_LOGIC;
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SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL header_send_ok : STD_LOGIC;
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SIGNAL header_send_ko : STD_LOGIC;
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SIGNAL component_send : STD_LOGIC;
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SIGNAL component_send_ok : STD_LOGIC;
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SIGNAL component_send_ko : STD_LOGIC;
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-----------------------------------------------------------------------------
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SIGNAL fifo_ren_trash : STD_LOGIC;
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SIGNAL component_fifo_ren : STD_LOGIC;
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BEGIN
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-----------------------------------------------------------------------------
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-- DMA to AHB interface
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-----------------------------------------------------------------------------
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DMA2AHB_1 : DMA2AHB
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GENERIC MAP (
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hindex => hindex,
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vendorid => VENDOR_LPP,
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deviceid => 0,
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version => 0,
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syncrst => 1,
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boundary => 0)
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PORT MAP (
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HCLK => HCLK,
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HRESETn => HRESETn,
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DMAIn => DMAIn,
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DMAOut => DMAOut,
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AHBIn => AHB_Master_In,
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AHBOut => AHB_Master_Out);
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matrix_type <= header(1 DOWNTO 0);
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component_type <= header(5 DOWNTO 2);
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send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
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'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
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'1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
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'1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
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'0';
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header_check_ok <= '0' WHEN component_type = "1111" ELSE
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'1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
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'1' WHEN component_type = component_type_pre + "0001" ELSE
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'0';
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address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
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addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
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addr_matrix_f1 WHEN matrix_type = "10" ELSE
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addr_matrix_f2 WHEN matrix_type = "11" ELSE
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(OTHERS => '0');
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-----------------------------------------------------------------------------
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-- DMA control
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-----------------------------------------------------------------------------
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DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
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BEGIN -- PROCESS DMAWriteBurst_p
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IF HRESETn = '0' THEN -- asynchronous reset (active low)
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state <= IDLE;
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header_ack <= '0';
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ready_matrix_f0_0 <= '0';
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ready_matrix_f0_1 <= '0';
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ready_matrix_f1 <= '0';
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ready_matrix_f2 <= '0';
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error_anticipating_empty_fifo <= '0';
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error_bad_component_error <= '0';
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component_type_pre <= "1110";
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fifo_ren_trash <= '1';
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component_send <= '0';
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address <= (OTHERS => '0');
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header_select <= '0';
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ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
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CASE state IS
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WHEN IDLE =>
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ready_matrix_f0_0 <= '0';
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ready_matrix_f0_1 <= '0';
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ready_matrix_f1 <= '0';
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ready_matrix_f2 <= '0';
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error_bad_component_error <= '0';
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header_select <= '1';
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IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
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IF header_check_ok = '1' THEN
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header_data <= header;
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component_type_pre <= header(5 DOWNTO 2);
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header_ack <= '1';
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--
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header_send <= '1';
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IF component_type = "0000" THEN
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address <= address_matrix;
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END IF;
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header_data <= header;
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--
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state <= WAIT_HEADER_ACK;
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ELSE
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error_bad_component_error <= '1';
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component_type_pre <= "1110";
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header_ack <= '1';
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state <= TRASH_FIFO;
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END IF;
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END IF;
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WHEN TRASH_FIFO =>
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error_bad_component_error <= '0';
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error_anticipating_empty_fifo <= '0';
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IF fifo_empty = '1' THEN
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state <= IDLE;
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fifo_ren_trash <= '1';
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ELSE
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fifo_ren_trash <= '0';
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END IF;
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WHEN WAIT_HEADER_ACK =>
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header_send <= '0';
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IF header_send_ko = '1' THEN
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state <= TRASH_FIFO;
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error_anticipating_empty_fifo <= '1';
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-- TODO : error sending header
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ELSIF header_send_ok = '1' THEN
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header_select <= '0';
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state <= SEND_DATA;
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address <= address + 4;
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END IF;
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WHEN SEND_DATA =>
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IF fifo_empty = '1' THEN
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state <= IDLE;
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IF component_type = "1110" THEN
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CASE matrix_type IS
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WHEN "00" => ready_matrix_f0_0 <= '1';
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WHEN "01" => ready_matrix_f0_1 <= '1';
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WHEN "10" => ready_matrix_f1 <= '1';
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WHEN "11" => ready_matrix_f2 <= '1';
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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ELSE
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component_send <= '1';
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address <= address;
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state <= WAIT_DATA_ACK;
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END IF;
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WHEN WAIT_DATA_ACK =>
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component_send <= '0';
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IF component_send_ok = '1' THEN
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address <= address + 64;
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state <= SEND_DATA;
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ELSIF component_send_ko = '1' THEN
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error_anticipating_empty_fifo <= '0';
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state <= TRASH_FIFO;
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END IF;
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WHEN CHECK_LENGTH =>
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state <= IDLE;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END PROCESS DMAWriteFSM_p;
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-----------------------------------------------------------------------------
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-- SEND 1 word by DMA
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-----------------------------------------------------------------------------
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lpp_dma_send_1word_1 : lpp_dma_send_1word
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PORT MAP (
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HCLK => HCLK,
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HRESETn => HRESETn,
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DMAIn => header_dmai,
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DMAOut => DMAOut,
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send => header_send,
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address => address,
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data => header_data,
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send_ok => header_send_ok,
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send_ko => header_send_ko
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);
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-----------------------------------------------------------------------------
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-- SEND 16 word by DMA (in burst mode)
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-----------------------------------------------------------------------------
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lpp_dma_send_16word_1 : lpp_dma_send_16word
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PORT MAP (
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HCLK => HCLK,
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HRESETn => HRESETn,
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DMAIn => component_dmai,
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DMAOut => DMAOut,
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send => component_send,
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address => address,
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data => fifo_data,
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ren => component_fifo_ren,
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send_ok => component_send_ok,
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send_ko => component_send_ko);
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DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
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fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
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-----------------------------------------------------------------------------
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-- APB REGISTER
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-----------------------------------------------------------------------------
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lpp_dma_apbreg_2 : lpp_dma_apbreg
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GENERIC MAP (
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pindex => pindex,
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paddr => paddr,
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pmask => pmask,
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pirq => pirq)
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PORT MAP (
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HCLK => HCLK,
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HRESETn => HRESETn,
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apbi => apbi,
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apbo => apbo,
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-- IN
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ready_matrix_f0_0 => ready_matrix_f0_0,
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ready_matrix_f0_1 => ready_matrix_f0_1,
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ready_matrix_f1 => ready_matrix_f1,
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ready_matrix_f2 => ready_matrix_f2,
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error_anticipating_empty_fifo => error_anticipating_empty_fifo,
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error_bad_component_error => error_bad_component_error,
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-- OUT
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status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
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status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
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status_ready_matrix_f1 => status_ready_matrix_f1,
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status_ready_matrix_f2 => status_ready_matrix_f2,
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status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
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status_error_bad_component_error => status_error_bad_component_error,
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config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, -- TODO
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config_active_interruption_onError => config_active_interruption_onError, -- TODO
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addr_matrix_f0_0 => addr_matrix_f0_0,
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addr_matrix_f0_1 => addr_matrix_f0_1,
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addr_matrix_f1 => addr_matrix_f1,
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addr_matrix_f2 => addr_matrix_f2);
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-----------------------------------------------------------------------------
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END Behavioral;
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