##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

LPP DMA v1.0.0
pellion@stage-ps1.lab-lpp.local -
r101:80568b98428c martin
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,190
1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5 LIBRARY grlib;
6 USE grlib.amba.ALL;
7 USE grlib.stdlib.ALL;
8 USE grlib.devices.ALL;
9 USE GRLIB.DMA2AHB_Package.ALL;
10 LIBRARY lpp;
11 USE lpp.lpp_amba.ALL;
12 USE lpp.apb_devices_list.ALL;
13 USE lpp.lpp_memory.ALL;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 ENTITY fifo_latency_correction IS
18
19 PORT (
20 HCLK : IN STD_ULOGIC;
21 HRESETn : IN STD_ULOGIC;
22
23 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
24 fifo_empty : IN STD_LOGIC;
25 fifo_ren : OUT STD_LOGIC;
26
27 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
28 dma_empty : OUT STD_LOGIC;
29 dma_ren : IN STD_LOGIC
30 );
31
32 END fifo_latency_correction;
33
34 ARCHITECTURE beh OF fifo_latency_correction IS
35
36 SIGNAL valid_s1 : STD_LOGIC;
37 SIGNAL valid_s2 : STD_LOGIC;
38
39 SIGNAL data_s1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
40 SIGNAL data_s2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
41 SIGNAL dma_data_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
42
43
44 SIGNAL ren_s1 : STD_LOGIC;
45 SIGNAL ren_s2 : STD_LOGIC;
46
47 SIGNAL fifo_ren_s : STD_LOGIC;
48 BEGIN -- beh
49
50
51 --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 --fifo_empty : IN STD_LOGIC;
53
54 --dma_ren : IN STD_LOGIC
55
56
57 PROCESS (HCLK, HRESETn)
58 BEGIN
59 IF HRESETn = '0' THEN
60 ren_s1 <= '1';
61 ren_s2 <= '1';
62 ELSIF HCLK'event AND HCLK = '1' THEN
63 ren_s1 <= fifo_ren_s;
64 ren_s2 <= fifo_ren_s;
65 END IF;
66 END PROCESS;
67 fifo_ren <= fifo_ren_s;
68
69 PROCESS (HCLK, HRESETn)
70 BEGIN
71 IF HRESETn = '0' THEN
72 valid_s1 <= '0';
73 --data_s1 <= (OTHERS => 'X'); -- TODO just for simulation
74 data_s1 <= (OTHERS => '0');
75 ELSIF HCLK'event AND HCLK = '1' THEN
76 IF valid_s1 = '0' THEN
77 IF valid_s2 = '1' AND ren_s2 = '0' AND dma_ren = '1' THEN
78 valid_s1 <= '1';
79 data_s1 <= fifo_data;
80 END IF;
81 ELSE
82 IF valid_s2 = '0' THEN
83 IF ren_s2 = '0' AND dma_ren = '1' THEN
84 valid_s1 <= '1';
85 data_s1 <= fifo_data;
86 ELSE
87 valid_s1 <= '0';
88 -- data_s1 <= (OTHERS => 'X'); -- TODO just for simulation
89 END IF;
90 ELSE
91 IF dma_ren = '1' THEN
92 valid_s1 <= '1';
93 data_s1 <= data_s1;
94 ELSE
95 IF ren_s2 = '0' THEN
96 valid_s1 <= '1';
97 data_s1 <= fifo_data;
98 ELSE
99 valid_s1 <= '0';
100 -- data_s1 <= (OTHERS => 'X'); -- TODO just for simulation
101 END IF;
102 END IF;
103 END IF;
104 END IF;
105 END IF;
106 END PROCESS;
107
108 PROCESS (HCLK, HRESETn)
109 BEGIN
110 IF HRESETn = '0' THEN
111 valid_s2 <= '0';
112 -- data_s2 <= (OTHERS => 'X'); -- TODO just for simulation
113 data_s2 <= (OTHERS => '0');
114 ELSIF HCLK'event AND HCLK = '1' THEN
115 IF valid_s2 = '0' THEN
116 IF dma_ren = '1' THEN
117 IF valid_s1 = '1' THEN
118 valid_s2 <= '1';
119 data_s2 <= data_s1;
120 ELSE
121 IF ren_s2 = '0' THEN
122 valid_s2 <= '1';
123 data_s2 <= fifo_data;
124 END IF;
125 END IF;
126 END IF;
127 ELSE
128 IF dma_ren = '1' THEN
129 valid_s2 <= '1';
130 data_s2 <= data_s2;
131 ELSE
132 IF valid_s1 = '1' THEN
133 valid_s2 <= '1';
134 data_s2 <= data_s1;
135 ELSE
136 IF ren_s2 = '0' THEN
137 valid_s2 <= '1';
138 data_s2 <= fifo_data;
139 ELSE
140 valid_s2 <= '0';
141 -- data_s2 <= (OTHERS => 'X'); -- TODO just for simulation
142 END IF;
143 END IF;
144 END IF;
145 END IF;
146 END IF;
147 END PROCESS;
148
149 -- PROCESS (HCLK, HRESETn)
150 -- BEGIN
151 -- IF HRESETn = '0' THEN
152 -- dma_data <= (OTHERS => 'X');
153 -- ELSIF HCLK'event AND HCLK = '1' THEN
154 -- IF valid_s2 = '1' THEN
155 -- dma_data <= data_s2;
156 -- ELSIF valid_s1 = '1' THEN
157 -- dma_data <= data_s1;
158 -- ELSIF ren_s2 = '0' THEN
159 -- dma_data <= fifo_data;
160 -- ELSE
161 -- dma_data <= (OTHERS => 'X');
162 -- END IF;
163 -- END IF;
164 -- END PROCESS;
165
166
167
168 dma_data_s <= data_s2 WHEN valid_s2 = '1' ELSE
169 data_s1 WHEN valid_s1 = '1' ELSE
170 fifo_data;
171
172 PROCESS (HCLK, HRESETn)
173 BEGIN -- PROCESS
174 IF HRESETn = '0' THEN -- asynchronous reset (active low)
175 dma_data <= (OTHERS => '0');
176 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
177 IF dma_ren = '0' THEN
178 dma_data <= dma_data_s;
179 END IF;
180 END IF;
181 END PROCESS;
182
183 fifo_ren_s <= '1' WHEN fifo_empty = '1' ELSE
184 -- '0' WHEN valid_s1 = '0' OR valid_s2 = '0' ELSE -- FIX test0
185 '0' WHEN (valid_s1 = '0' OR valid_s2 = '0') AND ren_s2 = '1' ELSE -- FIX test0
186 dma_ren;
187
188 dma_empty <= fifo_empty AND (NOT valid_s1) AND (NOT valid_s2);
189
190 END beh;
Show file before | Show file after | Hide comments
@@ -0,0 +1,168
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 USE grlib.devices.ALL;
29 USE GRLIB.DMA2AHB_Package.ALL;
30 --USE GRLIB.DMA2AHB_TestPackage.ALL;
31 LIBRARY lpp;
32 USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
37
38 ENTITY fifo_test_dma IS
39 GENERIC (
40 tech : INTEGER := apa3;
41 pindex : INTEGER := 0;
42 paddr : INTEGER := 0;
43 pmask : INTEGER := 16#fff#
44 );
45 PORT (
46 -- AMBA AHB system signals
47 HCLK : IN STD_ULOGIC;
48 HRESETn : IN STD_ULOGIC;
49
50 -- AMBA APB Slave Interface
51 apbi : IN apb_slv_in_type;
52 apbo : OUT apb_slv_out_type;
53
54 -- FIFO Read interface
55 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 fifo_empty : OUT STD_LOGIC;
57 fifo_ren : IN STD_LOGIC;
58
59 -- header
60 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
61 header_val : OUT STD_LOGIC;
62 header_ack : IN STD_LOGIC
63 );
64 END;
65
66 ARCHITECTURE Behavioral OF fifo_test_dma IS
67 CONSTANT REVISION : INTEGER := 1;
68 CONSTANT pconfig : apb_config_type := (
69 0 => ahb_device_reg (VENDOR_LPP, 0 , 0, REVISION, 0),
70 1 => apb_iobar(paddr, pmask));
71
72 TYPE lpp_test_dma_regs IS RECORD
73 tt : STD_LOGIC;
74 END RECORD;
75 SIGNAL reg : lpp_test_dma_regs;
76
77 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 -----------------------------------------------------------------------------
79 SIGNAL fifo_empty_s : STD_LOGIC;
80 SIGNAL fifo_raddr : STD_LOGIC_VECTOR(7 DOWNTO 0);
81 SIGNAL fifo_wen : STD_LOGIC;
82 SIGNAL fifo_wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 SIGNAL fifo_full : STD_LOGIC;
84 SIGNAL fifo_waddr : STD_LOGIC_VECTOR(7 DOWNTO 0);
85 -----------------------------------------------------------------------------
86 SIGNAL fifo_nb_data : STD_LOGIC_VECTOR( 7 DOWNTO 0);
87 SIGNAL fifo_nb_data_s : STD_LOGIC_VECTOR( 7 DOWNTO 0);
88 -----------------------------------------------------------------------------
89 SIGNAL header_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
90 SIGNAL header_val_s : STD_LOGIC;
91 BEGIN
92
93 lpp_fifo_i : lpp_fifo
94 GENERIC MAP (
95 tech => tech,
96 Enable_ReUse => '0',
97 DataSz => 32,
98 abits => 8)
99 PORT MAP (
100 rstn => HRESETn,
101 ReUse => '0',
102
103 rclk => HCLK,
104 ren => fifo_ren,
105 rdata => fifo_data,
106 empty => fifo_empty_s,
107 raddr => fifo_raddr,
108
109 wclk => HCLK,
110 wen => fifo_wen,
111 wdata => fifo_wdata,
112 full => fifo_full,
113 waddr => fifo_waddr); -- OUT
114
115 fifo_nb_data_s(7) <= '1' WHEN (fifo_waddr < fifo_raddr) ELSE '0';
116 fifo_nb_data_s(6 DOWNTO 0) <= (OTHERS => '0');
117 fifo_nb_data <= (fifo_waddr - fifo_raddr) + fifo_nb_data_s;
118
119 fifo_empty <= fifo_empty_s;
120 header <= header_s;
121 header_val <= header_val_s;
122 -----------------------------------------------------------------------------
123
124 apb_reg_p : PROCESS (HCLK, HRESETn)
125 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
126 BEGIN -- PROCESS lpp_dma_top
127 IF HRESETn = '0' THEN -- asynchronous reset (active low)
128 prdata <= (OTHERS => '0');
129 fifo_wdata <= (OTHERS => '0');
130 fifo_wen <= '1';
131 header_val_s <= '0';
132 header_s <= (OTHERS => '0');
133 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
134 paddr := "000000";
135 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
136 fifo_wen <= '1';
137 header_val_s <= header_val_s AND (NOT header_ack);
138 IF (apbi.psel(pindex)) = '1' THEN
139 -- APB DMA READ --
140 CASE paddr(7 DOWNTO 2) IS
141 WHEN "000000" => prdata( 7 DOWNTO 0) <= fifo_waddr;
142 prdata(15 DOWNTO 8) <= fifo_raddr;
143 prdata(23 DOWNTO 16) <= fifo_nb_data;
144 prdata(24) <= fifo_full;
145 prdata(25) <= fifo_empty_s;
146 WHEN "000001" => prdata(31 DOWNTO 0) <= header_s;
147
148 WHEN OTHERS => prdata <= (OTHERS => '0');
149 END CASE;
150 IF (apbi.pwrite AND apbi.penable) = '1' THEN
151 -- APB DMA WRITE --
152 CASE paddr(7 DOWNTO 2) IS
153 WHEN "000000" => fifo_wdata <= apbi.pwdata;
154 fifo_wen <= '0';
155 WHEN "000001" => header_s <= apbi.pwdata;
156 header_val_s <= '1';
157 WHEN OTHERS => NULL;
158 END CASE;
159 END IF;
160 END IF;
161 END IF;
162 END PROCESS apb_reg_p;
163 apbo.pirq <= (OTHERS => '0');
164 apbo.pindex <= pindex;
165 apbo.pconfig <= pconfig;
166 apbo.prdata <= prdata;
167
168 END Behavioral;
Show file before | Show file after | Hide comments
@@ -0,0 +1,366
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
31 --USE GRLIB.DMA2AHB_TestPackage.ALL;
32 LIBRARY lpp;
33 USE lpp.lpp_amba.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_dma_pkg.ALL;
37 LIBRARY techmap;
38 USE techmap.gencomp.ALL;
39
40
41 ENTITY lpp_dma IS
42 GENERIC (
43 tech : INTEGER := inferred;
44 hindex : INTEGER := 2;
45 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
48 pirq : INTEGER := 0);
49 PORT (
50 -- AMBA AHB system signals
51 HCLK : IN STD_ULOGIC;
52 HRESETn : IN STD_ULOGIC;
53
54 -- AMBA APB Slave Interface
55 apbi : IN apb_slv_in_type;
56 apbo : OUT apb_slv_out_type;
57
58 -- AMBA AHB Master Interface
59 AHB_Master_In : IN AHB_Mst_In_Type;
60 AHB_Master_Out : OUT AHB_Mst_Out_Type;
61
62 -- fifo interface
63 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 fifo_empty : IN STD_LOGIC;
65 fifo_ren : OUT STD_LOGIC;
66
67 -- header
68 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 header_val : IN STD_LOGIC;
70 header_ack : OUT STD_LOGIC
71 );
72 END;
73
74 ARCHITECTURE Behavioral OF lpp_dma IS
75 -----------------------------------------------------------------------------
76 SIGNAL DMAIn : DMA_In_Type;
77 SIGNAL header_dmai : DMA_In_Type;
78 SIGNAL component_dmai : DMA_In_Type;
79 SIGNAL DMAOut : DMA_OUt_Type;
80
81 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
82 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
83 SIGNAL ready_matrix_f1 : STD_LOGIC;
84 SIGNAL ready_matrix_f2 : STD_LOGIC;
85 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
86 SIGNAL error_bad_component_error : STD_LOGIC;
87
88 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
89 SIGNAL config_active_interruption_onError : STD_LOGIC;
90 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
91 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
92 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
93 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
94 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
95 SIGNAL status_error_bad_component_error : STD_LOGIC;
96 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 -----------------------------------------------------------------------------
101
102 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
104 TYPE state_DMAWriteBurst IS (IDLE,
105 TRASH_FIFO,
106 WAIT_HEADER_ACK,
107 SEND_DATA,
108 WAIT_DATA_ACK,
109 CHECK_LENGTH
110 );
111 SIGNAL state : state_DMAWriteBurst := IDLE;
112
113 SIGNAL nbSend : INTEGER;
114 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL header_check_ok : STD_LOGIC;
118 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL send_matrix : STD_LOGIC;
120 SIGNAL request : STD_LOGIC;
121 SIGNAL remaining_data_request : INTEGER;
122 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
123 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 SIGNAL header_select : STD_LOGIC;
126
127 SIGNAL header_send : STD_LOGIC;
128 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL header_send_ok : STD_LOGIC;
130 SIGNAL header_send_ko : STD_LOGIC;
131
132 SIGNAL component_send : STD_LOGIC;
133 SIGNAL component_send_ok : STD_LOGIC;
134 SIGNAL component_send_ko : STD_LOGIC;
135 -----------------------------------------------------------------------------
136 SIGNAL fifo_ren_trash : STD_LOGIC;
137 SIGNAL component_fifo_ren : STD_LOGIC;
138
139 BEGIN
140
141 -----------------------------------------------------------------------------
142 -- DMA to AHB interface
143 -----------------------------------------------------------------------------
144
145 DMA2AHB_1 : DMA2AHB
146 GENERIC MAP (
147 hindex => hindex,
148 vendorid => VENDOR_LPP,
149 deviceid => 0,
150 version => 0,
151 syncrst => 1,
152 boundary => 0)
153 PORT MAP (
154 HCLK => HCLK,
155 HRESETn => HRESETn,
156 DMAIn => DMAIn,
157 DMAOut => DMAOut,
158 AHBIn => AHB_Master_In,
159 AHBOut => AHB_Master_Out);
160
161 matrix_type <= header(1 DOWNTO 0);
162 component_type <= header(5 DOWNTO 2);
163
164 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
165 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
166 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
167 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
168 '0';
169
170 header_check_ok <= '0' WHEN component_type = "1111" ELSE
171 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
172 '1' WHEN component_type = component_type_pre + "0001" ELSE
173 '0';
174
175 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
176 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
177 addr_matrix_f1 WHEN matrix_type = "10" ELSE
178 addr_matrix_f2 WHEN matrix_type = "11" ELSE
179 (OTHERS => '0');
180
181 -----------------------------------------------------------------------------
182 -- DMA control
183 -----------------------------------------------------------------------------
184 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
185 BEGIN -- PROCESS DMAWriteBurst_p
186 IF HRESETn = '0' THEN -- asynchronous reset (active low)
187 state <= IDLE;
188 header_ack <= '0';
189 ready_matrix_f0_0 <= '0';
190 ready_matrix_f0_1 <= '0';
191 ready_matrix_f1 <= '0';
192 ready_matrix_f2 <= '0';
193 error_anticipating_empty_fifo <= '0';
194 error_bad_component_error <= '0';
195 component_type_pre <= "1110";
196 fifo_ren_trash <= '1';
197 component_send <= '0';
198 address <= (OTHERS => '0');
199 header_select <= '0';
200 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
201
202 CASE state IS
203 WHEN IDLE =>
204 ready_matrix_f0_0 <= '0';
205 ready_matrix_f0_1 <= '0';
206 ready_matrix_f1 <= '0';
207 ready_matrix_f2 <= '0';
208 error_bad_component_error <= '0';
209 header_select <= '1';
210 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
211 IF header_check_ok = '1' THEN
212 header_data <= header;
213 component_type_pre <= header(5 DOWNTO 2);
214 header_ack <= '1';
215 --
216 header_send <= '1';
217 IF component_type = "0000" THEN
218 address <= address_matrix;
219 END IF;
220 header_data <= header;
221 --
222 state <= WAIT_HEADER_ACK;
223 ELSE
224 error_bad_component_error <= '1';
225 component_type_pre <= "1110";
226 header_ack <= '1';
227 state <= TRASH_FIFO;
228 END IF;
229 END IF;
230
231 WHEN TRASH_FIFO =>
232 error_bad_component_error <= '0';
233 error_anticipating_empty_fifo <= '0';
234 IF fifo_empty = '1' THEN
235 state <= IDLE;
236 fifo_ren_trash <= '1';
237 ELSE
238 fifo_ren_trash <= '0';
239 END IF;
240
241 WHEN WAIT_HEADER_ACK =>
242 header_send <= '0';
243 IF header_send_ko = '1' THEN
244 state <= TRASH_FIFO;
245 error_anticipating_empty_fifo <= '1';
246 -- TODO : error sending header
247 ELSIF header_send_ok = '1' THEN
248 header_select <= '0';
249 state <= SEND_DATA;
250 address <= address + 4;
251 END IF;
252
253 WHEN SEND_DATA =>
254 IF fifo_empty = '1' THEN
255 state <= IDLE;
256 IF component_type = "1110" THEN
257 CASE matrix_type IS
258 WHEN "00" => ready_matrix_f0_0 <= '1';
259 WHEN "01" => ready_matrix_f0_1 <= '1';
260 WHEN "10" => ready_matrix_f1 <= '1';
261 WHEN "11" => ready_matrix_f2 <= '1';
262 WHEN OTHERS => NULL;
263 END CASE;
264 END IF;
265 ELSE
266 component_send <= '1';
267 address <= address;
268 state <= WAIT_DATA_ACK;
269 END IF;
270
271 WHEN WAIT_DATA_ACK =>
272 component_send <= '0';
273 IF component_send_ok = '1' THEN
274 address <= address + 64;
275 state <= SEND_DATA;
276 ELSIF component_send_ko = '1' THEN
277 error_anticipating_empty_fifo <= '0';
278 state <= TRASH_FIFO;
279 END IF;
280
281 WHEN CHECK_LENGTH =>
282 state <= IDLE;
283 WHEN OTHERS => NULL;
284 END CASE;
285
286 END IF;
287 END PROCESS DMAWriteFSM_p;
288
289 -----------------------------------------------------------------------------
290 -- SEND 1 word by DMA
291 -----------------------------------------------------------------------------
292 lpp_dma_send_1word_1 : lpp_dma_send_1word
293 PORT MAP (
294 HCLK => HCLK,
295 HRESETn => HRESETn,
296 DMAIn => header_dmai,
297 DMAOut => DMAOut,
298
299 send => header_send,
300 address => address,
301 data => header_data,
302 send_ok => header_send_ok,
303 send_ko => header_send_ko
304 );
305
306 -----------------------------------------------------------------------------
307 -- SEND 16 word by DMA (in burst mode)
308 -----------------------------------------------------------------------------
309 lpp_dma_send_16word_1 : lpp_dma_send_16word
310 PORT MAP (
311 HCLK => HCLK,
312 HRESETn => HRESETn,
313 DMAIn => component_dmai,
314 DMAOut => DMAOut,
315
316 send => component_send,
317 address => address,
318 data => fifo_data,
319 ren => component_fifo_ren,
320 send_ok => component_send_ok,
321 send_ko => component_send_ko);
322
323 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
324 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
325
326
327 -----------------------------------------------------------------------------
328 -- APB REGISTER
329 -----------------------------------------------------------------------------
330
331 lpp_dma_apbreg_2 : lpp_dma_apbreg
332 GENERIC MAP (
333 pindex => pindex,
334 paddr => paddr,
335 pmask => pmask,
336 pirq => pirq)
337 PORT MAP (
338 HCLK => HCLK,
339 HRESETn => HRESETn,
340 apbi => apbi,
341 apbo => apbo,
342 -- IN
343 ready_matrix_f0_0 => ready_matrix_f0_0,
344 ready_matrix_f0_1 => ready_matrix_f0_1,
345 ready_matrix_f1 => ready_matrix_f1,
346 ready_matrix_f2 => ready_matrix_f2,
347 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
348 error_bad_component_error => error_bad_component_error,
349 -- OUT
350 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
351 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
352 status_ready_matrix_f1 => status_ready_matrix_f1,
353 status_ready_matrix_f2 => status_ready_matrix_f2,
354 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
355 status_error_bad_component_error => status_error_bad_component_error,
356 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, -- TODO
357 config_active_interruption_onError => config_active_interruption_onError, -- TODO
358 addr_matrix_f0_0 => addr_matrix_f0_0,
359 addr_matrix_f0_1 => addr_matrix_f0_1,
360 addr_matrix_f1 => addr_matrix_f1,
361 addr_matrix_f2 => addr_matrix_f2);
362
363 -----------------------------------------------------------------------------
364
365 END Behavioral;
366
Show file before | Show file after | Hide comments
@@ -0,0 +1,193
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
36 ENTITY lpp_dma_apbreg IS
37 GENERIC (
38 pindex : INTEGER := 4;
39 paddr : INTEGER := 4;
40 pmask : INTEGER := 16#fff#;
41 pirq : INTEGER := 0);
42 PORT (
43 -- AMBA AHB system signals
44 HCLK : IN STD_ULOGIC;
45 HRESETn : IN STD_ULOGIC;
46
47 -- AMBA APB Slave Interface
48 apbi : IN apb_slv_in_type;
49 apbo : OUT apb_slv_out_type;
50
51 -- IN
52 ready_matrix_f0_0 : IN STD_LOGIC;
53 ready_matrix_f0_1 : IN STD_LOGIC;
54 ready_matrix_f1 : IN STD_LOGIC;
55 ready_matrix_f2 : IN STD_LOGIC;
56 error_anticipating_empty_fifo : IN STD_LOGIC;
57 error_bad_component_error : IN STD_LOGIC;
58
59 -- OUT
60 status_ready_matrix_f0_0 : OUT STD_LOGIC;
61 status_ready_matrix_f0_1 : OUT STD_LOGIC;
62 status_ready_matrix_f1 : OUT STD_LOGIC;
63 status_ready_matrix_f2 : OUT STD_LOGIC;
64 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
65 status_error_bad_component_error : OUT STD_LOGIC;
66
67 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
68 config_active_interruption_onError : OUT STD_LOGIC;
69 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
70 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
73 );
74
75 END lpp_dma_apbreg;
76
77 ARCHITECTURE beh OF lpp_dma_apbreg IS
78
79 CONSTANT REVISION : INTEGER := 1;
80
81 CONSTANT pconfig : apb_config_type := (
82 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
83 1 => apb_iobar(paddr, pmask));
84
85 TYPE lpp_dma_regs IS RECORD
86 config_active_interruption_onNewMatrix : STD_LOGIC;
87 config_active_interruption_onError : STD_LOGIC;
88 status_ready_matrix_f0_0 : STD_LOGIC;
89 status_ready_matrix_f0_1 : STD_LOGIC;
90 status_ready_matrix_f1 : STD_LOGIC;
91 status_ready_matrix_f2 : STD_LOGIC;
92 status_error_anticipating_empty_fifo : STD_LOGIC;
93 status_error_bad_component_error : STD_LOGIC;
94 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
95 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
96 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 END RECORD;
99
100 SIGNAL reg : lpp_dma_regs;
101
102 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
103
104 BEGIN -- beh
105
106 status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0;
107 status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1;
108 status_ready_matrix_f1 <= reg.status_ready_matrix_f1;
109 status_ready_matrix_f2 <= reg.status_ready_matrix_f2;
110 status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo;
111 status_error_bad_component_error <= reg.status_error_bad_component_error;
112
113 config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix;
114 config_active_interruption_onError <= reg.config_active_interruption_onError;
115 addr_matrix_f0_0 <= reg.addr_matrix_f0_0;
116 addr_matrix_f0_1 <= reg.addr_matrix_f0_1;
117 addr_matrix_f1 <= reg.addr_matrix_f1;
118 addr_matrix_f2 <= reg.addr_matrix_f2;
119
120 lpp_dma_apbreg : PROCESS (HCLK, HRESETn)
121 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
122 BEGIN -- PROCESS lpp_dma_top
123 IF HRESETn = '0' THEN -- asynchronous reset (active low)
124 reg.config_active_interruption_onNewMatrix <= '0';
125 reg.config_active_interruption_onError <= '0';
126 reg.status_ready_matrix_f0_0 <= '0';
127 reg.status_ready_matrix_f0_1 <= '0';
128 reg.status_ready_matrix_f1 <= '0';
129 reg.status_ready_matrix_f2 <= '0';
130 reg.status_error_anticipating_empty_fifo <= '0';
131 reg.status_error_bad_component_error <= '0';
132 reg.addr_matrix_f0_0 <= (OTHERS => '0');
133 reg.addr_matrix_f0_1 <= (OTHERS => '0');
134 reg.addr_matrix_f1 <= (OTHERS => '0');
135 reg.addr_matrix_f2 <= (OTHERS => '0');
136 prdata <= (OTHERS => '0');
137 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
138
139 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
140 reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
141 reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1;
142 reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2;
143
144 reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
145 reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error;
146
147 paddr := "000000";
148 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
149 prdata <= (OTHERS => '0');
150 IF apbi.psel(pindex) = '1' THEN
151 -- APB DMA READ --
152 CASE paddr(7 DOWNTO 2) IS
153 WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix;
154 prdata(1) <= reg.config_active_interruption_onError;
155 WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0;
156 prdata(1) <= reg.status_ready_matrix_f0_1;
157 prdata(2) <= reg.status_ready_matrix_f1;
158 prdata(3) <= reg.status_ready_matrix_f2;
159 prdata(4) <= reg.status_error_anticipating_empty_fifo;
160 prdata(5) <= reg.status_error_bad_component_error;
161 WHEN "000010" => prdata <= reg.addr_matrix_f0_0;
162 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
163 WHEN "000100" => prdata <= reg.addr_matrix_f1;
164 WHEN "000101" => prdata <= reg.addr_matrix_f2;
165 WHEN OTHERS => NULL;
166 END CASE;
167 IF (apbi.pwrite AND apbi.penable) = '1' THEN
168 -- APB DMA WRITE --
169 CASE paddr(7 DOWNTO 2) IS
170 WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
171 reg.config_active_interruption_onError <= apbi.pwdata(1);
172 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
173 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
174 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
175 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
176 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
177 reg.status_error_bad_component_error <= apbi.pwdata(5);
178 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
179 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
180 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
181 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
182 WHEN OTHERS => NULL;
183 END CASE;
184 END IF;
185 END IF;
186 END IF;
187 END PROCESS lpp_dma_apbreg;
188 apbo.pirq <= (OTHERS => '0');
189 apbo.pindex <= pindex;
190 apbo.pconfig <= pconfig;
191 apbo.prdata <= prdata;
192
193 END beh;
Show file before | Show file after | Hide comments
@@ -0,0 +1,164
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
36
37 ENTITY lpp_dma_fsm IS
38 PORT (
39 -- AMBA AHB system signals
40 HCLK : IN STD_ULOGIC;
41 HRESETn : IN STD_ULOGIC;
42
43 -- AMBA APB Slave Interface
44 apbi : IN apb_slv_in_type;
45 apbo : OUT apb_slv_out_type;
46
47 -- AMBA AHB Master Interface
48 AHB_Master_In : IN AHB_Mst_In_Type;
49 AHB_Master_Out : OUT AHB_Mst_Out_Type;
50
51 -- fifo interface
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_empty : IN STD_LOGIC;
54 fifo_ren : OUT STD_LOGIC;
55
56 -- header
57 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 header_val : IN STD_LOGIC;
59 header_ack : OUT STD_LOGIC;
60
61
62 -- OUT
63 ready_matrix_f0_0 : OUT STD_LOGIC; -- TODO
64 ready_matrix_f0_1 : OUT STD_LOGIC; -- TODO
65 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
66 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
67 error_anticipating_empty_fifo : OUT STD_LOGIC; -- TODO
68 error_bad_component_error : OUT STD_LOGIC; -- TODO
69
70 -- IN
71 status_ready_matrix_f0_0 : IN STD_LOGIC;
72 status_ready_matrix_f0_1 : IN STD_LOGIC;
73 status_ready_matrix_f1 : IN STD_LOGIC;
74 status_ready_matrix_f2 : IN STD_LOGIC;
75 status_error_anticipating_empty_fifo : IN STD_LOGIC; -- TODO
76 status_error_bad_component_error : IN STD_LOGIC; -- TODO
77
78 config_active_interruption_onNewMatrix : IN STD_LOGIC;
79 config_active_interruption_onError : IN STD_LOGIC;
80 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
84 );
85 END lpp_dma_fsm;
86
87 ARCHITECTURE beh OF lpp_dma_fsm IS
88 -----------------------------------------------------------------------------
89 -- HEADER check and update
90 -----------------------------------------------------------------------------
91 SIGNAL send_matrix_val : STD_LOGIC;
92 SIGNAL current_header : STD_LOGIC_VECTOR(31 DOWNTO 0);
93 -----------------------------------------------------------------------------
94 SIGNAL send_matrix : STD_LOGIC;
95 SIGNAL trash_matrix : STD_LOGIC;
96 SIGNAL get_new_header : STD_LOGIC;
97 -----------------------------------------------------------------------------
98 -- CONTROL SEND COMPONENT
99 -----------------------------------------------------------------------------
100 TYPE state_fsm_send_component IS (IDLE,
101 CHECK_HEADER,
102 TRASH_FIFO,
103
104 PACKET_IDLE,REQUEST_BUS,SEND_DATA_nextADDRESS,FAULT1,FAULT2);
105 BEGIN -- beh
106
107 -----------------------------------------------------------------------------
108 -- HEADER check and update
109 -----------------------------------------------------------------------------
110
111 PROCESS (HCLK, HRESETn)
112 BEGIN -- PROCESS
113 IF HRESETn = '0' THEN -- asynchronous reset (active low)
114 current_header <= (OTHERS => '0');
115 header_ack <= '0';
116 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
117 IF get_new_header = '1' AND header_val = '1' THEN
118 IF send_matrix_val = '1' THEN
119 current_header <= header;
120 header_ack <= '1';
121 send_matrix <= component_val;
122 trash_matrix <= (NOT component_val) OR (trash_matrix AND NOT (header(5 DOWNTO 2) = "0000"));
123 END IF;
124 ELSE
125 current_header <= current_header;
126 header_ack <= '0';
127 send_matrix <= '0';
128 trash_matrix <= '0';
129 END IF;
130 END IF;
131 END PROCESS;
132
133 send_matrix_val <= '1' WHEN header(1 DOWNTO 0) = "00" AND status_ready_matrix_f0_0 = '0' ELSE
134 '1' WHEN header(1 DOWNTO 0) = "01" AND status_ready_matrix_f0_1 = '0' ELSE
135 '1' WHEN header(1 DOWNTO 0) = "10" AND status_ready_matrix_f1 = '0' ELSE
136 '1' WHEN header(1 DOWNTO 0) = "11" AND status_ready_matrix_f2 = '0' ELSE
137 '0';
138
139 component_val <= '0' WHEN header(5 DOWNTO 2) = "1111" ELSE
140 '1' WHEN header(5 DOWNTO 2) = "0000" ELSE
141 '1' WHEN header(5 DOWNTO 2) = current_header(5 DOWNTO 2) + "0001" ELSE
142 '0';
143
144 --OUT
145 --send_matrix
146 --trash_matrix
147
148 --IN
149 --get_new_header
150
151 -----------------------------------------------------------------------------
152 -- CONTROL SEND COMPONENT
153 -----------------------------------------------------------------------------
154 fsm_send_component: PROCESS (HCLK, HRESETn)
155 BEGIN -- PROCESS fsm_send_component
156 IF HRESETn = '0' THEN -- asynchronous reset (active low)
157
158 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
159
160 END IF;
161 END PROCESS fsm_send_component;
162
163
164 END beh;
Show file before | Show file after | Hide comments
@@ -0,0 +1,163
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE std.textio.ALL;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
38
39 PACKAGE lpp_dma_pkg IS
40
41 COMPONENT lpp_dma
42 GENERIC (
43 tech : INTEGER;
44 hindex : INTEGER;
45 pindex : INTEGER;
46 paddr : INTEGER;
47 pmask : INTEGER;
48 pirq : INTEGER);
49 PORT (
50 HCLK : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
52 apbi : IN apb_slv_in_type;
53 apbo : OUT apb_slv_out_type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 -- fifo interface
57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 fifo_empty : IN STD_LOGIC;
59 fifo_ren : OUT STD_LOGIC;
60 -- header
61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 header_val : IN STD_LOGIC;
63 header_ack : OUT STD_LOGIC);
64 END COMPONENT;
65
66 COMPONENT fifo_test_dma
67 GENERIC (
68 tech : INTEGER;
69 pindex : INTEGER;
70 paddr : INTEGER;
71 pmask : INTEGER);
72 PORT (
73 HCLK : IN STD_ULOGIC;
74 HRESETn : IN STD_ULOGIC;
75 apbi : IN apb_slv_in_type;
76 apbo : OUT apb_slv_out_type;
77 -- fifo interface
78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fifo_empty : OUT STD_LOGIC;
80 fifo_ren : IN STD_LOGIC;
81 -- header
82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 header_val : OUT STD_LOGIC;
84 header_ack : IN STD_LOGIC
85 );
86 END COMPONENT;
87
88 COMPONENT lpp_dma_apbreg
89 GENERIC (
90 pindex : INTEGER;
91 paddr : INTEGER;
92 pmask : INTEGER;
93 pirq : INTEGER);
94 PORT (
95 HCLK : IN STD_ULOGIC;
96 HRESETn : IN STD_ULOGIC;
97 apbi : IN apb_slv_in_type;
98 apbo : OUT apb_slv_out_type;
99 -- IN
100 ready_matrix_f0_0 : IN STD_LOGIC;
101 ready_matrix_f0_1 : IN STD_LOGIC;
102 ready_matrix_f1 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
106
107 -- OUT
108 status_ready_matrix_f0_0 : OUT STD_LOGIC;
109 status_ready_matrix_f0_1 : OUT STD_LOGIC;
110 status_ready_matrix_f1 : OUT STD_LOGIC;
111 status_ready_matrix_f2 : OUT STD_LOGIC;
112 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
113 status_error_bad_component_error : OUT STD_LOGIC;
114
115 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
116 config_active_interruption_onError : OUT STD_LOGIC;
117 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
121 );
122 END COMPONENT;
123
124 COMPONENT lpp_dma_send_1word
125 PORT (
126 HCLK : IN STD_ULOGIC;
127 HRESETn : IN STD_ULOGIC;
128 DMAIn : OUT DMA_In_Type;
129 DMAOut : IN DMA_OUt_Type;
130 send : IN STD_LOGIC;
131 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 send_ok : OUT STD_LOGIC;
134 send_ko : OUT STD_LOGIC);
135 END COMPONENT;
136
137 COMPONENT lpp_dma_send_16word
138 PORT (
139 HCLK : IN STD_ULOGIC;
140 HRESETn : IN STD_ULOGIC;
141 DMAIn : OUT DMA_In_Type;
142 DMAOut : IN DMA_OUt_Type;
143 send : IN STD_LOGIC;
144 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 ren : OUT STD_LOGIC;
147 send_ok : OUT STD_LOGIC;
148 send_ko : OUT STD_LOGIC);
149 END COMPONENT;
150
151 COMPONENT fifo_latency_correction
152 PORT (
153 HCLK : IN STD_ULOGIC;
154 HRESETn : IN STD_ULOGIC;
155 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
156 fifo_empty : IN STD_LOGIC;
157 fifo_ren : OUT STD_LOGIC;
158 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
159 dma_empty : OUT STD_LOGIC;
160 dma_ren : IN STD_LOGIC);
161 END COMPONENT;
162
163 END;
Show file before | Show file after | Hide comments
@@ -0,0 +1,160
1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5 LIBRARY grlib;
6 USE grlib.amba.ALL;
7 USE grlib.stdlib.ALL;
8 USE grlib.devices.ALL;
9 USE GRLIB.DMA2AHB_Package.ALL;
10 LIBRARY lpp;
11 USE lpp.lpp_amba.ALL;
12 USE lpp.apb_devices_list.ALL;
13 USE lpp.lpp_memory.ALL;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 ENTITY lpp_dma_send_16word IS
18 PORT (
19 -- AMBA AHB system signals
20 HCLK : IN STD_ULOGIC;
21 HRESETn : IN STD_ULOGIC;
22
23 -- DMA
24 DMAIn : OUT DMA_In_Type;
25 DMAOut : IN DMA_OUt_Type;
26
27 --
28 send : IN STD_LOGIC;
29 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
30 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
31 ren : OUT STD_LOGIC;
32 --
33 send_ok : OUT STD_LOGIC;
34 send_ko : OUT STD_LOGIC
35 );
36 END lpp_dma_send_16word;
37
38 ARCHITECTURE beh OF lpp_dma_send_16word IS
39
40 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1,WAIT_LAST_READY);
41 SIGNAL state : state_fsm_send_16word;
42
43 SIGNAL data_counter : INTEGER;
44 SIGNAL grant_counter : INTEGER;
45
46 BEGIN -- beh
47
48 DMAIn.Beat <= HINCR16;
49 DMAIn.Size <= HSIZE32;
50
51 PROCESS (HCLK, HRESETn)
52 BEGIN -- PROCESS
53 IF HRESETn = '0' THEN -- asynchronous reset (active low)
54 state <= IDLE;
55 send_ok <= '0';
56 send_ko <= '0';
57
58 DMAIn.Reset <= '0';
59 DMAIn.Address <= (OTHERS => '0');
60 -- DMAIn.Data <= (others => '0');
61 DMAIn.Request <= '0';
62 DMAIn.Store <= '0';
63 DMAIn.Burst <= '1';
64 DMAIn.Lock <= '0';
65 data_counter <= 0;
66 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
67
68 CASE state IS
69 WHEN IDLE =>
70 -- ren <= '1';
71 DMAIn.Store <= '1';
72 DMAIn.Request <= '0';
73 send_ok <= '0';
74 send_ko <= '0';
75 DMAIn.Address <= address;
76 data_counter <= 0;
77 DMAIn.Lock <= '0'; -- FIX test
78 IF send = '1' THEN
79 state <= REQUEST_BUS;
80 DMAIn.Request <= '1';
81 DMAIn.Lock <= '1'; -- FIX test
82 DMAIn.Store <= '1';
83 END IF;
84 WHEN REQUEST_BUS =>
85 -- ren <= '1';
86 IF DMAOut.Grant='1' THEN
87 data_counter <= 1;
88 grant_counter <= 1;
89 -- ren <= '0';
90 state <= SEND_DATA;
91 END IF;
92 WHEN SEND_DATA =>
93 -- ren <= '1';
94
95 IF DMAOut.Fault = '1' THEN
96 DMAIn.Reset <= '0';
97 DMAIn.Address <= (others => '0');
98 -- DMAIn.Data <= (others => '0');
99 DMAIn.Request <= '0';
100 DMAIn.Store <= '0';
101 DMAIn.Burst <= '0';
102 state <= ERROR0;
103 ELSE
104
105 IF DMAOut.Grant = '1' THEN
106 if grant_counter = 15 then
107 DMAIn.Reset <= '0';
108 DMAIn.Request <= '0';
109 DMAIn.Store <= '0';
110 DMAIn.Burst <= '0';
111 else
112 grant_counter <= grant_counter+1;
113 end if;
114 END IF;
115
116 IF DMAOut.OKAY = '1' THEN
117 IF data_counter = 15 THEN
118 DMAIn.Address <= (others => '0');
119 state <= WAIT_LAST_READY;
120 ELSE
121 --DMAIn.Data <= data;
122 data_counter <= data_counter + 1;
123 -- ren <= '0';
124 END IF;
125 END IF;
126 END IF;
127
128
129 WHEN WAIT_LAST_READY =>
130 -- ren <= '1';
131 IF DMAOut.Ready = '1' THEN
132 IF grant_counter = 15 THEN
133 state <= IDLE;
134 send_ok <= '1';
135 send_ko <= '0';
136 ELSE
137 state <= ERROR0;
138 END IF;
139 END IF;
140
141 WHEN ERROR0 =>
142 -- ren <= '1';
143 state <= ERROR1;
144 WHEN ERROR1 =>
145 send_ok <= '0';
146 send_ko <= '1';
147 -- ren <= '1';
148 state <= IDLE;
149 WHEN OTHERS => NULL;
150 END CASE;
151 END IF;
152 END PROCESS;
153
154 DMAIn.Data <= data;
155
156 ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
157 '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
158 '1';
159
160 END beh;
Show file before | Show file after | Hide comments
@@ -0,0 +1,101
1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5 LIBRARY grlib;
6 USE grlib.amba.ALL;
7 USE grlib.stdlib.ALL;
8 USE grlib.devices.ALL;
9 USE GRLIB.DMA2AHB_Package.ALL;
10 LIBRARY lpp;
11 USE lpp.lpp_amba.ALL;
12 USE lpp.apb_devices_list.ALL;
13 USE lpp.lpp_memory.ALL;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 ENTITY lpp_dma_send_1word IS
18 PORT (
19 -- AMBA AHB system signals
20 HCLK : IN STD_ULOGIC;
21 HRESETn : IN STD_ULOGIC;
22
23 -- DMA
24 DMAIn : OUT DMA_In_Type;
25 DMAOut : IN DMA_OUt_Type;
26 --
27 send : IN STD_LOGIC;
28 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
29 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
30 --
31 send_ok : OUT STD_LOGIC;
32 send_ko : OUT STD_LOGIC
33 );
34 END lpp_dma_send_1word;
35
36 ARCHITECTURE beh OF lpp_dma_send_1word IS
37
38 TYPE state_fsm_send_1word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1);
39 SIGNAL state : state_fsm_send_1word;
40
41 BEGIN -- beh
42
43 DMAIn.Reset <= '0';
44 DMAIn.Address <= address;
45 DMAIn.Data <= data;
46 DMAIn.Beat <= (OTHERS => '0');
47 DMAIn.Size <= HSIZE32;
48 DMAIn.Burst <= '0';
49
50 PROCESS (HCLK, HRESETn)
51 BEGIN -- PROCESS
52 IF HRESETn = '0' THEN -- asynchronous reset (active low)
53 state <= IDLE;
54 DMAIn.Request <= '0';
55 DMAIn.Store <= '0';
56 send_ok <= '0';
57 send_ko <= '0';
58 DMAIn.Lock <= '0';
59 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
60 CASE state IS
61 WHEN IDLE =>
62 DMAIn.Store <= '1';
63 DMAIn.Request <= '0';
64 send_ok <= '0';
65 send_ko <= '0';
66 DMAIn.Lock <= '0';
67 IF send = '1' THEN
68 DMAIn.Request <= '1';
69 DMAIn.Lock <= '1';
70 state <= REQUEST_BUS;
71 END IF;
72 WHEN REQUEST_BUS =>
73 IF DMAOut.Grant = '1' THEN
74 DMAIn.Request <= '0';
75 DMAIn.Store <= '0';
76 state <= SEND_DATA;
77 END IF;
78 WHEN SEND_DATA =>
79 IF DMAOut.Fault = '1' THEN
80 DMAIn.Request <= '0';
81 DMAIn.Store <= '0';
82 state <= ERROR0;
83 ELSIF DMAOut.Ready = '1' THEN
84 DMAIn.Request <= '0';
85 DMAIn.Store <= '0';
86 send_ok <= '1';
87 send_ko <= '0';
88 state <= IDLE;
89 END IF;
90 WHEN ERROR0 =>
91 state <= ERROR1;
92 WHEN ERROR1 =>
93 send_ok <= '0';
94 send_ko <= '1';
95 state <= IDLE;
96 WHEN OTHERS => NULL;
97 END CASE;
98 END IF;
99 END PROCESS;
100
101 END beh;
Show file before | Show file after | Hide comments
@@ -0,0 +1,7
1 fifo_test_dma.vhd
2 fifo_latency_correction.vhd
3 lpp_dma_send_1word.vhd
4 lpp_dma_send_16word.vhd
5 lpp_dma_apbreg.vhd
6 lpp_dma.vhd
7 lpp_dma_pkg.vhd
Show file before | Show file after | Hide comments
@@ -61,6 +61,7 Patched-dist: Patch-GRLIB
61
61
62
62
63 doc:
63 doc:
64 mkdir -p doc/html
64 cp doc/ressources/*.jpg doc/html/
65 cp doc/ressources/*.jpg doc/html/
65 cp doc/ressources/doxygen.css doc/html/
66 cp doc/ressources/doxygen.css doc/html/
66 make -C lib/lpp doc
67 make -C lib/lpp doc
General Comments 0
You need to be logged in to leave comments. Login now