HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r108:ec95871b78ac

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r108:ec95871b78ac

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LPP_drivers/exemples/BenchFFT/main.c +36 -30

@@ -1,45 +1,51
1	#include <stdio.h>	1	#include <stdio.h>
2	#include "lpp_apb_functions.h"	2	#include "lpp_apb_functions.h"
		3	#include "apb_fifo_Driver.h"
3	#include "apb_uart_Driver.h"	4	#include "apb_uart_Driver.h"
4	#include "~~apb_fft_Driver~~.h"	5	#include "TableTest.h"
5	#include "apb_delay_Driver.h"
6		6
7		7
8	int main()	8	int main()
9	{	9	{
		10	int i=0,j=0;
		11	int data1,data2;
10	char temp[256];	12	char temp[256];
11	int i;	13
12	int Table[256];	14	int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE};
13	//Somme de 2 sinus//	15	int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD};
14	//int Tablo[256] = {0x00000000,0x0DA20000,0x1B080000,0x27F70000,0x34380000,0x3F960000,0x49E10000,0x52F10000,0x5AA10000,0x60D60000,0x657D0000,0x688C0000,0x69FE0000,0x69DB0000,0x68310000,0x65170000,0x60A90000,0x5B0D0000,0x546D0000,0x4CF90000,0x44E30000,0x3C610000,0x33AA0000,0x2AF40000,0x22750000,0x1A610000,0x12E70000,0x0C310000,0x06660000,0x01A30000,0xFE010000,0xFB8E0000,0xFA520000,0xFA4D0000,0xFB770000,0xFDBE0000,0x010A0000,0x053E0000,0x0A330000,0x0FBF0000,0x15B30000,0x1BDE0000,0x220C0000,0x28080000,0x2D9D0000,0x329B0000,0x36D20000,0x3A170000,0x3C440000,0x3D390000,0x3CDE0000,0x3B210000,0x37F90000,0x33650000,0x2D6D0000,0x26210000,0x1D990000,0x13F30000,0x09570000,0xFDF10000,0xF1F20000,0xE58F0000,0xD9030000,0xCC870000,0xC0560000,0xB4AA0000,0xA9BC0000,0x9FBF0000,0x96E40000,0x8F570000,0x893A0000,0x84AB0000,0x81BF0000,0x80830000,0x80FB0000,0x83220000,0x86EC0000,0x8C430000,0x93090000,0x9B1B0000,0xA44D0000,0xAE700000,0xB9500000,0xC4B40000,0xD0630000,0xDC240000,0xE7BD0000,0xF2F60000,0xFD9A0000,0x077A0000,0x106B0000,0x18480000,0x1EF30000,0x24570000,0x28650000,0x2B160000,0x2C6F0000,0x2C790000,0x2B470000,0x28F30000,0x259E0000,0x216E0000,0x1C8F0000,0x17310000,0x11860000,0x0BC10000,0x06170000,0x00BA0000,0xFBDD0000,0xF7AC0000,0xF44F0000,0xF1EA0000,0xF09C0000,0xF0790000,0xF1900000,0xF3E80000,0xF77E0000,0xFC4A0000,0x02370000,0x092E0000,0x110E0000,0x19AF0000,0x22E40000,0x2C7C0000,0x36420000,0x3FFF0000,0x497C0000,0x52810000,0x5AD70000,0x624B0000,0x68AD0000,0x6DD40000,0x71990000,0x73E10000,0x74950000,0x73A60000,0x71100000,0x6CD60000,0x67040000,0x5FAD0000,0x56EE0000,0x4CEA0000,0x41CD0000,0x35C50000,0x29070000,0x1BCC0000,0x0E4E0000,0x00CA0000,0xF37C0000,0xE69C0000,0xDA620000,0xCF040000,0xC4AE0000,0xBB8B0000,0xB3BC0000,0xAD5C0000,0xA87D0000,0xA5290000,0xA3630000,0xA3220000,0xA4590000,0xA6EF0000,0xAAC80000,0xAFBD0000,0xB5A40000,0xBC4F0000,0xC38B0000,0xCB220000,0xD2E00000,0xDA8E0000,0xE1F70000,0xE8EC0000,0xEF3C0000,0xF4C10000,0xF9560000,0xFCDF0000,0xFF470000,0x007F0000,0x00850000,0xFF5C0000,0xFD0B0000,0xF9A80000,0xF54B0000,0xF0170000,0xEA320000,0xE3C90000,0xDD0B0000,0xD62B0000,0xCF5F0000,0xC8DA0000,0xC2D30000,0xBD7A0000,0xB8FF0000,0xB58D0000,0xB3490000,0xB2510000,0xB2BE0000,0xB49F0000,0xB7FC0000,0xBCD60000,0xC3220000,0xCAD10000,0xD3C70000,0xDDE50000,0xE9030000,0xF4F20000,0x01800000,0x0E770000,0x1B9D0000,0x28B70000,0x35880000,0x41D70000,0x4D6C0000,0x58100000,0x61950000,0x69D00000,0x709C0000,0x75DE0000,0x79800000,0x7B750000,0x7BBB0000,0x7A570000,0x77550000,0x72CB0000,0x6CD70000,0x659E0000,0x5D490000,0x54090000,0x4A110000,0x3F980000,0x34D80000,0x2A090000,0x1F630000,0x151D0000,0x0B690000,0x02760000,0xFA6F0000,0xF3730000,0xEDA10000,0xE90B0000,0xE5BF0000,0xE3C00000,0xE30A0000,0xE38F0000,0xE53D0000,0xE7F80000,0xEB9D0000,0xF0050000,0xF5030000,0xFA680000,0x00000000,0x05980000,0x0AFD0000,0x0FFB0000,0x14630000,0x18080000};	16	int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF};
15	//1 Sinus//	17	int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C};
16	int Tablo[256] = {0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000,0xD0E10000,0xC9800000,0xC2560000,0xBB6A0000,0xB4C30000,0xAE690000,0xA8610000,0xA2B10000,0x9D600000,0x98720000,0x93ED0000,0x8FD50000,0x8C2F0000,0x88FD0000,0x86440000,0x84050000,0x82440000,0x81020000,0x80410000,0x80000000,0x80410000,0x81020000,0x82440000,0x84050000,0x86440000,0x88FD0000,0x8C2F0000,0x8FD50000,0x93ED0000,0x98720000,0x9D600000,0xA2B10000,0xA8610000,0xAE690000,0xB4C30000,0xBB6A0000,0xC2560000,0xC9800000,0xD0E10000,0xD8720000,0xE02B0000,0xE8040000,0xEFF50000,0xF7F60000,0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000,0xD0E10000,0xC9800000,0xC2560000,0xBB6A0000,0xB4C30000,0xAE690000,0xA8610000,0xA2B10000,0x9D600000,0x98720000,0x93ED0000,0x8FD50000,0x8C2F0000,0x88FD0000,0x86440000,0x84050000,0x82440000,0x81020000,0x80410000,0x80000000,0x80410000,0x81020000,0x82440000,0x84050000,0x86440000,0x88FD0000,0x8C2F0000,0x8FD50000,0x93ED0000,0x98720000,0x9D600000,0xA2B10000,0xA8610000,0xAE690000,0xB4C30000,0xBB6A0000,0xC2560000,0xC9800000,0xD0E10000,0xD8720000,0xE02B0000,0xE8040000,0xEFF50000,0xF7F60000,0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000};	18	int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E};
17	printf("Debut Main\n\n");	19
18	UART_Device* uart0 = openUART(0);	20	UART_Device* uart0 = openUART(0);
19	FFT_Device* f~~ft0~~ = openFFT(0);	21	FIFO_Device* fifotry = openFIFO(0);
20	~~DELAY~~_Device* ~~delay~~ = open~~DELAY~~(0);	22	FIFO_Device* fifoIn = openFIFO(1);
		23	FIFO_Device* fifoOut = openFIFO(2);
		24
		25	printf("\nDebut Main\n\n");
21		26
22	printf("addr_fft: %x\n",(unsigned int)fft0);	27	FillFifo(fifoIn,0,TblSinA,256);
23	printf("addr_uart: %x\n\n",(unsigned int)uart0);	28	FillFifo(fifoIn,1,TblSinAB,256);
24	printf("cfg_fft: %x\n",fft0->ConfigReg);	29	FillFifo(fifoIn,2,TblSinB,256);
25	printf("cfg_uart: %x\n\n",uart0->ConfigReg);	30	FillFifo(fifoIn,3,TblSinBC,256);
		31	FillFifo(fifoIn,4,TblSinC,256);
		32
		33	while(j<5){
		34	while((fifoOut->FIFOreg[(2*j)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN
26		35
27	while(1)	36	sprintf(temp,"FIFO %d\n\r",j);
28	{	37	uartputs(uart0,temp);
29	FftInput(Tablo,fft0,delay);	38	//while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty){ // TANT QUE empty a 0 ALORS
30	/* for (i = 0 ; i < 256 ; i++)	39	while(i < 128){
31	{	40	data1 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex;
32	sprintf(temp,"%x/in",Tablo[i]);	41	data2 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex;
33	uartputs(uart0,temp);	42	i++;
34	}*/	43	sprintf(temp,"%d\t%d\n\r",data1,data2);
35
36	FftOutput(Table,fft0);
37	for (i = 0 ; i < 128 ; i++)
38	{
39	sprintf(temp,"%x/out",Table[i]);
40	uartputs(uart0,temp);	44	uartputs(uart0,temp);
41	}	45	}
		46	i=0;
		47	j++;
42	}	48	}
		49	printf("\nFin Main\n\n");
43	return 0;	50	return 0;
44	}	51	}
45

lib/lpp/dsp/lpp_fft/Driver_FFT.vhd +45 -81

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
             entity Driver_FFT is
             generic(
-                Data_sz  : integer range 1 to 32 := 16
+                Data_sz  : integer range 1 to 32 := 16;
+                NbData : integer range 1 to 512 := 256
                 );
             port(
                 clk         : in std_logic;
                 rstn        : in std_logic;
                 Load        : in std_logic;
                 Empty       : in std_logic_vector(4 downto 0);
-                Full        : in std_logic_vector(4 downto 0);
                 DATA        : in std_logic_vector((5*Data_sz)-1 downto 0);
                 Valid       : out std_logic;
                 Read        : out std_logic_vector(4 downto 0);
                 Data_re     : out std_logic_vector(Data_sz-1 downto 0);
                 Data_im     : out std_logic_vector(Data_sz-1 downto 0)
             );
             end entity;
             architecture ar_Driver of Driver_FFT is
             type etat is (eX,e0,e1,e2);
             signal ect : etat;
-            signal FifoCpt  : integer;
+            signal DataCount : integer range 0 to 255 := 0;
-            --signal DataTmp    : std_logic_vector(Data_sz-1 downto 0);
+            signal FifoCpt  : integer range 0 to 4 := 0;
-            signal sEmpty    : std_logic;
+            signal sLoad : std_logic;
-            signal sFull    : std_logic;
-            signal sData    : std_logic_vector(Data_sz-1 downto 0);
             begin
                 process(clk,rstn)
                 begin
                     if(rstn='0')then
-                        ect <= eX;
+                        ect <= e0;
                         Read <= (others => '1');
                         Valid <= '0';
-                        FifoCpt <= 1;
                         Data_re <= (others => '0');
                         Data_im <= (others => '0');
+                        DataCount <= 0;
+                        FifoCpt <= 0;
+                        sLoad <= '0';
                     elsif(clk'event and clk='1')then
+                        sLoad <= Load;
+                        if(sLoad='1' and Load='0')then
+                            if(FifoCpt=4)then
+                                FifoCpt <= 0;
+                            else
+                                FifoCpt <= FifoCpt + 1;
+                            end if;
+                        end if;
                         case ect is
-                            when eX =>
-                                if(sFull='1')then
-                                    ect <= e0;
-                                end if;
                             when e0 =>
-                                Valid <= '0';
+                                if(Load='1' and Empty(FifoCpt)='0')then
-                                if(Load='1' and sEmpty='0')then
+                                    Read(FifoCpt) <= '0';
-                                    Read(FifoCpt-1) <= '0';
+                                    ect <= e1;
-                                    ect <= e2;
-            --                        ect <= e1;
-                                elsif(sEmpty='1')then
-                                    if(FifoCpt=6)then
-                                        FifoCpt <= 1;
-                                    else
-                                        FifoCpt <= FifoCpt+1;
-                                    end if;
-                                    ect <= eX;
                                 end if;
                             when e1 =>
-                                null;
+                                Valid <= '0';
-            --                    DataTmp <= sData;
+                                Read(FifoCpt) <= '1';
-            --                    ect <= e2;
+                                ect <= e2;
                             when e2 =>
-                                Read(FifoCpt-1) <= '1';
+                                Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz));
-                                Data_re <= sData;
                                 Data_im <= (others => '0');
-            --                    Data_re <= DataTmp;
-            --                    Data_im <= sData;
                                 Valid <= '1';
+                                if(DataCount=NbData-1)then
+                                    DataCount <= 0;
+                                    ect <= eX;
+                                else
+                                    DataCount <= DataCount + 1;
+                                    if(Load='1' and Empty(FifoCpt)='0')then
+                                        Read(FifoCpt) <= '0';
+                                        ect <= e1;
+                                    else
+                                        ect <= eX;
+                                    end if;
+                                end if;
+                            when eX =>
+                                Valid <= '0';
                                 ect <= e0;
+                            when others =>
+                                null;
                         end case;
                     end if;
                 end process;
-            with FifoCpt select
+            end architecture;
  No newline at end of file
-                sFull <=        Full(0) when 1,
-                                Full(1) when 2,
-                                Full(2) when 3,
-                                Full(3) when 4,
-                                Full(4) when 5,
-                                '1' when others;
-            with FifoCpt select
-                sEmpty <=       Empty(0) when 1,
-                                Empty(1) when 2,
-                                Empty(2) when 3,
-                                Empty(3) when 4,
-                                Empty(4) when 5,
-                                '1' when others;
-            with FifoCpt select
-                sData <=        DATA(Data_sz-1 downto 0) when 1,
-                                DATA((2*Data_sz)-1 downto Data_sz) when 2,
-                                DATA((3*Data_sz)-1 downto (2*Data_sz)) when 3,
-                                DATA((4*Data_sz)-1 downto (3*Data_sz)) when 4,
-                                DATA((5*Data_sz)-1 downto (4*Data_sz)) when 5,
-                                (others => '0') when others;
-            end architecture;

lib/lpp/dsp/lpp_fft/Linker_FFT.vhd +36 -53

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
             entity Linker_FFT is
             generic(
-                Data_sz  : integer range 1 to 32 := 8
+                Data_sz  : integer range 1 to 32 := 16;
+                NbData : integer range 1 to 512 := 256
                 );
             port(
                 clk         : in std_logic;
                 rstn        : in std_logic;
                 Ready       : in std_logic;
                 Valid       : in std_logic;
                 Full        : in std_logic_vector(4 downto 0);
                 Data_re     : in std_logic_vector(Data_sz-1 downto 0);
                 Data_im     : in std_logic_vector(Data_sz-1 downto 0);
                 Read        : out std_logic;
                 Write       : out std_logic_vector(4 downto 0);
                 ReUse       : out std_logic_vector(4 downto 0);
                 DATA        : out std_logic_vector((5*Data_sz)-1 downto 0)
             );
             end entity;
             architecture ar_Linker of Linker_FFT is
-            type etat is (eX,e0,e1,e2,e3);
+            type etat is (eX,e0,e1,e2);
             signal ect : etat;
-            signal FifoCpt  : integer;
             signal DataTmp  : std_logic_vector(Data_sz-1 downto 0);
-            signal sFull    : std_logic;
+            signal sRead   : std_logic;
-            signal sData    : std_logic_vector(Data_sz-1 downto 0);
+            signal sReady : std_logic;
-            signal sReady   : std_logic;
+            signal FifoCpt  : integer range 0 to 4 := 0;
             begin
                 process(clk,rstn)
                 begin
                     if(rstn='0')then
                         ect <= e0;
-                        Read <= '0';
+                        sRead <= '0';
+                        sReady <= '0';
                         Write <= (others => '1');
                         Reuse <= (others => '0');
-                        FifoCpt <= 1;
+                        FifoCpt <= 0;
-                        sDATA <= (others => '0');
                     elsif(clk'event and clk='1')then
                         sReady <= Ready;
+                        if(sReady='1' and Ready='0')then
+                            if(FifoCpt=4)then
+                                FifoCpt <= 0;
+                            else
+                                FifoCpt <= FifoCpt + 1;
+                            end if;
+                        elsif(Ready='1')then
+                            sRead <= not sRead;
+                        else
+                            sRead <= '0';
+                        end if;
                         case ect is
                             when e0 =>
-                                Write(FifoCpt-1) <= '1';
+                                Write(FifoCpt) <= '1';
-                                if(sReady='0' and Ready='1' and sfull='0')then
+                                if(Valid='1' and Full(FifoCpt)='0')then
-                                    Read <= '1';
+                                    DataTmp <= Data_im;
+                                    DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= Data_re;
+                                    Write(FifoCpt) <= '0';
                                     ect <= e1;
-                                end if;
+                                elsif(Full(FifoCpt)='1')then
+                                    ReUse(FifoCpt) <= '1';
-                            when e1 =>
-                                Read <= '0';
-                                if(Valid='1' and sfull='0')then
-                                    DataTmp <= Data_im;
-                                    sDATA <= Data_re;
-                                    Write(FifoCpt-1) <= '0';
-                                    ect <= e2;
-                                elsif(sfull='1')then
-                                    ReUse(FifoCpt-1) <= '1';
-                                    ect <= eX;
                                 end if;
-                             when e2 =>
+                             when e1 =>
-                                sDATA <= DataTmp;
+                                DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= DataTmp;
-                                ect <= e3;
+                                ect <= e0;
-                            when e3 =>
-                                Write(FifoCpt-1) <= '1';
-                                if(Ready='1' and sfull='0')then
-                                    Read <= '1';
-                                    ect <= e1;
-                                end if;
-                            when eX =>
+                            when others =>
-                                if(FifoCpt=5)then
+                                null;
-                                    FifoCpt <= 1;
-                                else
-                                    FifoCpt <= FifoCpt+1;
-                                end if;
-                                ect <= e0;
                         end case;
                     end if;
                 end process;
-            DATA <= sData & sData & sData & sData & sData;
+            Read <= sRead;
-            with FifoCpt select
+            end architecture;
  No newline at end of file
-                sFull <=    Full(0) when 1,
-                            Full(1) when 2,
-                            Full(2) when 3,
-                            Full(3) when 4,
-                            Full(4) when 5,
-                            '1' when others;
-            end architecture;

lib/lpp/dsp/lpp_fft/lpp_fft.vhd +4 -3

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use std.textio.all;
             library lpp;
             use lpp.lpp_amba.all;
             use lpp.lpp_memory.all;
             use work.fft_components.all;
             --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
             package lpp_fft is
             component APB_FFT is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 Data_sz      : integer := 16
                 );
               port (
                 clk     : in  std_logic;
                 rst     : in  std_logic;           --! Reset general du composant
                 apbi    : in  apb_slv_in_type;
                 apbo    : out apb_slv_out_type
                 );
             end component;
             component APB_FFT_half is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 Data_sz      : integer := 16
                 );
               port (
                 clk     : in  std_logic;           --! Horloge du composant
                 rst     : in  std_logic;           --! Reset general du composant
                 Ren     : in std_logic;
                 ready   : out std_logic;
                 valid   : out std_logic;
                 DataOut_re   : out std_logic_vector(Data_sz-1 downto 0);
                 DataOut_im   : out std_logic_vector(Data_sz-1 downto 0);
                 OUTfill : out std_logic;
                 OUTwrite : out std_logic;
                 apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
                 apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
                 );
             end component;
             component Flag_Extremum is
               port(
                 clk,raz    : in std_logic;    --! Horloge et Reset g�n�ral du composant
                 load       : in std_logic;    --! Signal en provenance de CoreFFT
                 y_rdy      : in std_logic;    --! Signal en provenance de CoreFFT
                 fill       : out std_logic;   --! Flag, Va permettre d'autoriser l'�criture (Driver C)
                 ready      : out std_logic    --! Flag, Va permettre d'autoriser la lecture (Driver C)
                 );
             end component;
             component Linker_FFT is
             generic(
-                Data_sz  : integer range 1 to 32 := 16
+                Data_sz  : integer range 1 to 32 := 16;
+                NbData : integer range 1 to 512 := 256
                 );
             port(
                 clk         : in std_logic;
                 rstn        : in std_logic;
                 Ready       : in std_logic;
                 Valid       : in std_logic;
                 Full        : in std_logic_vector(4 downto 0);
                 Data_re     : in std_logic_vector(Data_sz-1 downto 0);
                 Data_im     : in std_logic_vector(Data_sz-1 downto 0);
                 Read        : out std_logic;
                 Write       : out std_logic_vector(4 downto 0);
                 ReUse       : out std_logic_vector(4 downto 0);
                 DATA        : out std_logic_vector((5*Data_sz)-1 downto 0)
             );
             end component;
             component Driver_FFT is
             generic(
-                Data_sz  : integer range 1 to 32 := 16
+                Data_sz  : integer range 1 to 32 := 16;
+                NbData : integer range 1 to 512 := 256
                 );
             port(
                 clk         : in std_logic;
                 rstn        : in std_logic;
                 Load        : in std_logic;
                 Empty       : in std_logic_vector(4 downto 0);
-                Full        : in std_logic_vector(4 downto 0);
                 DATA        : in std_logic_vector((5*Data_sz)-1 downto 0);
                 Valid       : out std_logic;
                 Read        : out std_logic_vector(4 downto 0);
                 Data_re     : out std_logic_vector(Data_sz-1 downto 0);
                 Data_im     : out std_logic_vector(Data_sz-1 downto 0)
             );
             end component;
             component FFTamont is
             generic(
                 Data_sz  : integer range 1 to 32 := 16;
                 NbData : integer range 1 to 512 := 256
                 );
             port(
                 clk         : in std_logic;
                 rstn        : in std_logic;
                 Load        : in std_logic;
                 Empty       : in std_logic;
                 DATA        : in std_logic_vector(Data_sz-1 downto 0);
                 Valid       : out std_logic;
                 Read        : out std_logic;
                 Data_re     : out std_logic_vector(Data_sz-1 downto 0);
                 Data_im     : out std_logic_vector(Data_sz-1 downto 0)
             );
             end component;
             component FFTaval is
             generic(
                 Data_sz  : integer range 1 to 32 := 8;
                 NbData : integer range 1 to 512 := 256
                 );
             port(
                 clk         : in std_logic;
                 rstn        : in std_logic;
                 Ready       : in std_logic;
                 Valid       : in std_logic;
                 Full        : in std_logic;
                 Data_re     : in std_logic_vector(Data_sz-1 downto 0);
                 Data_im     : in std_logic_vector(Data_sz-1 downto 0);
                 Read        : out std_logic;
                 Write       : out std_logic;
                 ReUse       : out std_logic;
                 DATA        : out std_logic_vector(Data_sz-1 downto 0)
             );
             end component;
             --==============================================================|
             --================== IP VHDL de la FFT actel ===================|
             --================ non partag� dans la VHD_Lib =================|
             --==============================================================|
             component CoreFFT IS
               GENERIC (
                 LOGPTS      : integer := gLOGPTS;
                 LOGLOGPTS   : integer := gLOGLOGPTS;
                 WSIZE       : integer := gWSIZE;
                 TWIDTH      : integer := gTWIDTH;
                 DWIDTH      : integer := gDWIDTH;
                 TDWIDTH     : integer := gTDWIDTH;
                 RND_MODE    : integer := gRND_MODE;
                 SCALE_MODE  : integer := gSCALE_MODE;
                 PTS         : integer := gPTS;
                 HALFPTS     : integer := gHALFPTS;
                 inBuf_RWDLY : integer := gInBuf_RWDLY  );
               PORT (
                 clk,ifiStart,ifiNreset : IN std_logic;
                 ifiD_valid, ifiRead_y  : IN std_logic;
                 ifiD_im, ifiD_re       : IN std_logic_vector(WSIZE-1 DOWNTO 0);
                 ifoLoad, ifoPong       : OUT std_logic;
                 ifoY_im, ifoY_re       : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
                 ifoY_valid, ifoY_rdy   : OUT std_logic);
             END component;
                 component actar is
                     port( DataA : in std_logic_vector(15 downto 0); DataB : in
                         std_logic_vector(15 downto 0); Mult : out
                         std_logic_vector(31 downto 0);Clock : in std_logic) ;
                 end component;
                 component actram is
                     port( DI : in std_logic_vector(31 downto 0); DO : out
                         std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
                         WADDR : in std_logic_vector(6 downto 0); RADDR : in
                         std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
                         std_logic) ;
                 end component;
                 component switch IS
                     GENERIC ( DWIDTH  : integer := 32 );
                     PORT (
                       clk, sel, validIn       : IN std_logic;
                       inP, inQ                : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
                       outP, outQ              : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
                       validOut                : OUT std_logic);
                 END component;
                component twid_rA IS
                    GENERIC (LOGPTS    : integer := 8;
                        LOGLOGPTS : integer := 3  );
                    PORT (clk     : IN std_logic;
                        timer   : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
                        stage   : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
                        tA      : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
                END component;
                component counter IS
                    GENERIC (
                        WIDTH           : integer := 7;
                        TERMCOUNT       : integer := 127 );
                    PORT (
                        clk, nGrst, rst, cntEn : IN std_logic;
                        tc                     : OUT std_logic;
                        Q                      : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
                END component;
                component twiddle IS
                   PORT (
                       A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
                       T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
                END component;
             end;

lib/lpp/leon3mp.vhd +23 -23

             -----------------------------------------------------------------------------
             --  LEON3 Demonstration design
             --  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 2 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             library techmap;
             use techmap.gencomp.all;
             library gaisler;
             use gaisler.memctrl.all;
             use gaisler.leon3.all;
             use gaisler.uart.all;
             use gaisler.misc.all;
             library esa;
             use esa.memoryctrl.all;
             use work.config.all;
             library lpp;
             use lpp.lpp_amba.all;
             use lpp.lpp_memory.all;
             use lpp.lpp_uart.all;
             use lpp.lpp_matrix.all;
             use lpp.lpp_delay.all;
             use lpp.lpp_fft.all;
             use lpp.fft_components.all;
             use lpp.lpp_ad_conv.all;
             use lpp.iir_filter.all;
             use lpp.general_purpose.all;
             use lpp.Filtercfg.all;
             entity leon3mp is
               generic (
                 fabtech   : integer := CFG_FABTECH;
                 memtech   : integer := CFG_MEMTECH;
                 padtech   : integer := CFG_PADTECH;
                 clktech   : integer := CFG_CLKTECH;
                 disas     : integer := CFG_DISAS;	-- Enable disassembly to console
                 dbguart   : integer := CFG_DUART;	-- Print UART on console
                 pclow     : integer := CFG_PCLOW
               );
               port (
                 clk50MHz    : in  std_ulogic;
                 reset	    : in  std_ulogic;
                 ramclk 	    : out std_logic;
                 ahbrxd  : in  std_ulogic;  			-- DSU rx data
                 ahbtxd  : out std_ulogic; 			-- DSU tx data
                 dsubre  : in std_ulogic;
                 dsuact  : out std_ulogic;
                 urxd1  : in  std_ulogic;  			-- UART1 rx data
                 utxd1  : out std_ulogic; 			-- UART1 tx data
                 errorn	: out std_ulogic;
                 address : out std_logic_vector(18 downto 0);
                 data	: inout std_logic_vector(31 downto 0);
                 gpio    : inout std_logic_vector(6 downto 0); 	-- I/O port
                 nBWa        : out std_logic;
                 nBWb        : out std_logic;
                 nBWc        : out std_logic;
                 nBWd        : out std_logic;
                 nBWE        : out std_logic;
                 nADSC       : out std_logic;
                 nADSP       : out std_logic;
                 nADV        : out std_logic;
                 nGW         : out std_logic;
                 nCE1        : out std_logic;
                 CE2         : out std_logic;
                 nCE3        : out std_logic;
                 nOE         : out std_logic;
                 MODE        : out std_logic;
                 SSRAM_CLK   : out std_logic;
                 ZZ          : out std_logic;
             ---------------------------------------------------------------------
             ---  AJOUT TEST ------------------------In/Out-----------------------
             ---------------------------------------------------------------------
             -- UART
                 UART_RXD : in std_logic;
                 UART_TXD : out std_logic;
             -- ADC
             --    ADC_in  : in AD7688_in(4 downto 0);
             --    ADC_out : out AD7688_out;
             --    Bias_Fails : out std_logic;
             -- CNA
             --    DAC_SYNC : out std_logic;
             --    DAC_SCLK : out std_logic;
             --    DAC_DATA : out std_logic;
             -- Diver
                 SPW1_EN : out std_logic;
                 SPW2_EN : out std_logic;
                 TEST : out std_logic_vector(3 downto 0);
                 BP : in std_logic;
             ---------------------------------------------------------------------
                 led     : out std_logic_vector(1 downto 0)
             	);
             end;
             architecture Behavioral of leon3mp is
             constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
             	CFG_GRETH+CFG_AHB_JTAG;
             constant maxahbm : integer := maxahbmsp;
             --Clk & Rst g�n�
             signal vcc      : std_logic_vector(4 downto 0);
             signal gnd      : std_logic_vector(4 downto 0);
             signal resetnl  : std_ulogic;
             signal clk2x    : std_ulogic;
             signal lclk     : std_ulogic;
             signal lclk2x   : std_ulogic;
             signal clkm     : std_ulogic;
             signal rstn     : std_ulogic;
             signal rstraw   : std_ulogic;
             signal pciclk   : std_ulogic;
             signal sdclkl   : std_ulogic;
             signal cgi      : clkgen_in_type;
             signal cgo      : clkgen_out_type;
             --- AHB / APB
             signal apbi     : apb_slv_in_type;
             signal apbo     : apb_slv_out_vector := (others => apb_none);
             signal ahbsi    : ahb_slv_in_type;
             signal ahbso    : ahb_slv_out_vector := (others => ahbs_none);
             signal ahbmi    : ahb_mst_in_type;
             signal ahbmo    : ahb_mst_out_vector := (others => ahbm_none);
             --UART
             signal ahbuarti : uart_in_type;
             signal ahbuarto : uart_out_type;
             signal apbuarti : uart_in_type;
             signal apbuarto : uart_out_type;
             --MEM CTRLR
             signal memi     : memory_in_type;
             signal memo     : memory_out_type;
             signal wpo      : wprot_out_type;
             signal sdo      : sdram_out_type;
             --IRQ
             signal irqi     : irq_in_vector(0 to CFG_NCPU-1);
             signal irqo     : irq_out_vector(0 to CFG_NCPU-1);
             --Timer
             signal gpti     : gptimer_in_type;
             signal gpto     : gptimer_out_type;
             --GPIO
             signal gpioi    : gpio_in_type;
             signal gpioo    : gpio_out_type;
             --DSU
             signal dbgi     : l3_debug_in_vector(0 to CFG_NCPU-1);
             signal dbgo     : l3_debug_out_vector(0 to CFG_NCPU-1);
             signal dsui     : dsu_in_type;
             signal dsuo     : dsu_out_type;
             ---------------------------------------------------------------------
             ---  AJOUT TEST ------------------------Signaux----------------------
             ---------------------------------------------------------------------
             -- FIFOs
-            signal FifoIN_Full      : std_logic_vector(0 downto 0);--
+            signal FifoIN_Full      : std_logic_vector(4 downto 0);--
-            signal FifoIN_Empty     : std_logic_vector(0 downto 0);--
+            signal FifoIN_Empty     : std_logic_vector(4 downto 0);--
-            signal FifoIN_Data      : std_logic_vector(15 downto 0);--
+            signal FifoIN_Data      : std_logic_vector(79 downto 0);--
             signal FifoINT_Full     : std_logic_vector(4 downto 0);
             signal FifoINT_Data     : std_logic_vector(79 downto 0);
             signal FifoOUT_FullV    : std_logic;
-            signal FifoOUT_Full     : std_logic_vector(0 downto 0);--
+            signal FifoOUT_Full     : std_logic_vector(4 downto 0);--
             signal Matrix_WriteV    : std_logic_vector(0 downto 0);
             -- MATRICE SPECTRALE
             signal Matrix_Write     : std_logic;
             signal Matrix_Read      : std_logic_vector(1 downto 0);
             signal Matrix_Result    : std_logic_vector(31 downto 0);
             signal TopSM_Start      : std_logic;
             signal TopSM_Statu      : std_logic_vector(3 downto 0);
             signal TopSM_Read       : std_logic_vector(4 downto 0);
             signal TopSM_Data1      : std_logic_vector(15 downto 0);
             signal TopSM_Data2      : std_logic_vector(15 downto 0);
             signal Disp_FlagError   : std_logic;
             signal Disp_Pong        : std_logic;
             signal Disp_Write       : std_logic_vector(1 downto 0);
             signal Disp_Data        : std_logic_vector(63 downto 0);
             signal Dma_acq : std_logic;
             -- FFT
             signal Drive_Write      : std_logic;
-            signal Drive_Read       : std_logic_vector(0 downto 0);--
+            signal Drive_Read       : std_logic_vector(4 downto 0);--
             signal Drive_DataRE     : std_logic_vector(15 downto 0);
             signal Drive_DataIM     : std_logic_vector(15 downto 0);
             signal Start            : std_logic;
             signal RstnFFT            : std_logic;
             signal FFT_Load         : std_logic;
             signal FFT_Ready        : std_logic;
             signal FFT_Valid        : std_logic;
             signal FFT_DataRE       : std_logic_vector(15 downto 0);
             signal FFT_DataIM       : std_logic_vector(15 downto 0);
             signal Link_Read        : std_logic;
-            signal Link_Write       : std_logic_vector(0 downto 0);--
+            signal Link_Write       : std_logic_vector(4 downto 0);--
-            signal Link_ReUse       : std_logic_vector(0 downto 0);--
+            signal Link_ReUse       : std_logic_vector(4 downto 0);--
-            signal Link_Data        : std_logic_vector(15 downto 0);--
+            signal Link_Data        : std_logic_vector(79 downto 0);--
             -- ADC
             signal SmplClk          : std_logic;
             signal ADC_DataReady    : std_logic;
             signal ADC_SmplOut      : Samples_out(4 downto 0);
             signal enableADC        : std_logic;
             signal WG_Write         : std_logic_vector(4 downto 0);
             signal WG_ReUse         : std_logic_vector(4 downto 0);
             signal WG_DATA          : std_logic_vector(79 downto 0);
             signal s_out          : std_logic_vector(79 downto 0);
             signal fuller : std_logic_vector(4 downto 0);
             signal reader : std_logic_vector(4 downto 0);
             signal try : std_logic_vector(1 downto 0);
             signal TXDint : std_logic;
             -- IIR Filter
             signal sample_clk_out  :   std_logic;
             signal Rd : std_logic_vector(0 downto 0);--
-            signal Ept : std_logic_vector(0 downto 0);--
+            signal Ept : std_logic_vector(4 downto 0);--
             signal Bwr : std_logic_vector(0 downto 0);
             signal Bre : std_logic_vector(0 downto 0);
             signal DataTMP : std_logic_vector(15 downto 0);
             signal FullUp : std_logic_vector(0 downto 0);
             signal EmptyUp : std_logic_vector(0 downto 0);
             signal FullDown : std_logic_vector(0 downto 0);
             signal EmptyDown : std_logic_vector(0 downto 0);
             ---------------------------------------------------------------------
             constant IOAEN  : integer := CFG_CAN;
             constant boardfreq : integer := 50000;
             begin
             ---------------------------------------------------------------------
             ---  AJOUT TEST -------------------------------------IPs-------------
             ---------------------------------------------------------------------
             led(1 downto 0) <= gpio(1 downto 0);
             --- COM USB ---------------------------------------------------------
             --    MemIn0 : APB_FifoWrite
             --        generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
             --        port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
             --
             --    BUF0 : APB_USB
             --      generic map (6,6,DataMax => 1024)
             --      port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
             --
             --    MemOut0 : APB_FifoRead
             --        generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
             --        port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
             --
             --slrd <= usb_Read;
             --slwr <= usb_Write;
             --- CNA -------------------------------------------------------------
             --    CONV : APB_CNA
             --        generic map (5,5)
             --        port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
             --TEST(0) <= SmplClk;
             --TEST(1) <= WG_Write(0);
             --TEST(2) <= Fuller(0);
             --TEST(3) <= s_out(s_out'length-1);
             SPW1_EN <= '1';
             SPW2_EN <= '0';
             --- CAN -------------------------------------------------------------
             --    Divider : Clk_divider
             --        generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
             --        Port map(clkm,rstn,SmplClk);
             --
             --    ADC : AD7688_drvr
             --        generic map (ChanelCount => 5, clkkHz => 24_576)
             --        port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
             --
             --    WG : WriteGen_ADC
             --        port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
             --
             --enableADC <= gpio(0);
             --Bias_Fails <= '0';
             --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
             --
             --
             --    MemIn1 : APB_FIFO
             --        generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
             --        port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
             --- FFT -------------------------------------------------------------
                 MemIn : APB_FIFO
-                    generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
+                    generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
                     port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
             --    MemIn : APB_FIFO
             --        generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
             --        port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others =>'1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
             --
             Start <= '0';
-                DRIVE : FFTamont
+            --    DRIVE : FFTamont
-                    generic map(Data_sz => 16,NbData => 256)
+            --        generic map(Data_sz => 16,NbData => 256)
-                    port map(clkm,rstn,FFT_Load,FifoIN_Empty(0),FifoIN_Data,Drive_Write,Drive_Read(0),Drive_DataRE,Drive_DataIM);
+            --        port map(clkm,rstn,FFT_Load,FifoIN_Empty(0),FifoIN_Data,Drive_Write,Drive_Read(0),Drive_DataRE,Drive_DataIM);
-            --    DRIVE : Driver_FFT
+                DRIVE : Driver_FFT
-            --        generic map(Data_sz => 16)
+                    generic map(Data_sz => 16)
-            --        port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Full,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM);
+                    port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM);
             --
                 FFT : CoreFFT
                     generic map(
                     LOGPTS      => gLOGPTS,
                     LOGLOGPTS   => gLOGLOGPTS,
                     WSIZE       => gWSIZE,
                     TWIDTH      => gTWIDTH,
                     DWIDTH      => gDWIDTH,
                     TDWIDTH     => gTDWIDTH,
                     RND_MODE    => gRND_MODE,
                     SCALE_MODE  => gSCALE_MODE,
                     PTS         => gPTS,
                     HALFPTS     => gHALFPTS,
                     inBuf_RWDLY => gInBuf_RWDLY)
                     port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
             --
-            --    LINK : Linker_FFT
+                LINK : Linker_FFT
-            --        generic map(Data_sz => 16)
+                    generic map(Data_sz => 16)
-            --        port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data);--FifoOUT_Full/FifoINT_Full
+                    port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data);--FifoOUT_Full/FifoINT_Full
-                LINK : FFTaval
+            --    LINK : FFTaval
-                    generic map(Data_sz => 16,NbData => 256)
+            --        generic map(Data_sz => 16,NbData => 256)
-                    port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full(0),FFT_DataRE,FFT_DataIM,Link_Read,Link_Write(0),Link_ReUse(0),Link_Data);
+            --        port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full(0),FFT_DataRE,FFT_DataIM,Link_Read,Link_Write(0),Link_ReUse(0),Link_Data);
             --
             ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
             --
                 MemOut : APB_FIFO
-                    generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
+                    generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
                     port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9));
             --TEST(0) <= FifoOUT_Full(0);
             --TEST(1) <= Link_Write(0);
             --    MemInt : lppFIFOx5
             --        generic map(Data_sz => 16, Enable_ReUse => '1')
             --        port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open);
             --
             --Matrix_WriteV(0)    <=  not Matrix_Write;
             --FifoOUT_FullV       <=  FifoOUT_Full(0);
             --
             ----    MemInt : lppFIFOxN
             ----        generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
             ----        port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open);
             --
             --    TopSM : TopMatrix_PDR
             --        generic map (Input_SZ => 16)
             --        port map (clkm,rstn,FifoINT_Data,FifoINT_Full,Matrix_Read,Matrix_Write,TopSM_Data1,TopSM_Data2,TopSM_Start,TopSM_Read,TopSM_Statu);
             --
             --    SM : SpectralMatrix
             --        generic map (Input_SZ => 16, Result_SZ => 32)
             --        port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
             --***************************************TEST DEMI-FIFO********************************************************************************
             --    MemIn : APB_FIFO
             --        generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
             --        port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
             --
             --    Pont : Bridge
             --        port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
             --
             --    MemOut : APB_FIFO
             --        generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
             --        port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
             --*************************************************************************************************************************************
             --Dma_acq <= '1';
             --
             --    DISP : Dispatch
             --        generic map(Data_SZ => 32)
             --        port map(clkm,reset,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError);
             --
             ----- FIFO -------------------------------------------------------------
             --
             --    MemOut : APB_FIFO
             --        generic map (pindex => 15, paddr => 15, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
             --        port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(15));
             --
                 Memtest : APB_FIFO
                     generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
                     port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
             --- UART -------------------------------------------------------------
                 COM0 : APB_UART
                     generic map (pindex => 4, paddr => 4)
                     port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
             --- DELAY ------------------------------------------------------------
             --    Delay0 : APB_Delay
             --        generic map (pindex => 4, paddr => 4)
             --        port map (clkm,rstn,apbi,apbo(4));
             --- IIR Filter -------------------------------------------------------
             --Test(0) <= sample_clk_out;
             --
             --
             --    IIR1: APB_IIR_Filter
             --        generic map(
             --            tech           => CFG_MEMTECH,
             --            pindex         => 8,
             --            paddr          => 8,
             --            Sample_SZ      => Sample_SZ,
             --            ChanelsCount   => ChanelsCount,
             --            Coef_SZ        => Coef_SZ,
             --            CoefCntPerCel  => CoefCntPerCel,
             --            Cels_count     => Cels_count,
             --            virgPos        => virgPos
             --            )
             --        port map(
             --            rst             => rstn,
             --            clk             => clkm,
             --            apbi            => apbi,
             --            apbo            => apbo(8),
             --            sample_clk_out  => sample_clk_out,
             --            GOtest => Test(1),
             --            CoefsInitVal    => (others => '1')
             --            );
             ----------------------------------------------------------------------
             ----------------------------------------------------------------------
             ---  Reset and Clock generation  -------------------------------------
             ----------------------------------------------------------------------
               vcc <= (others => '1'); gnd <= (others => '0');
               cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
               rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
               clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
               clkgen0 : clkgen  		-- clock generator
                 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
             	CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
                 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
                 ramclk  <=  clkm;
             process(lclk2x)
             begin
                 if lclk2x'event and lclk2x = '1' then
                     lclk <= not lclk;
                 end if;
             end process;
             ----------------------------------------------------------------------
             ---  LEON3 processor / DSU / IRQ  ------------------------------------
             ----------------------------------------------------------------------
               l3 : if CFG_LEON3 = 1 generate
                 cpu : for i in 0 to CFG_NCPU-1 generate
                   u0 : leon3s			-- LEON3 processor
                   generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
 , CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
               	CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
               	CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
                       CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
                       CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
                   port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
                   		irqi(i), irqo(i), dbgi(i), dbgo(i));
                 end generate;
                 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
                 dsugen : if CFG_DSU = 1 generate
                   dsu0 : dsu3			-- LEON3 Debug Support Unit
                   generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
                      ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
                   port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
             --      dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
             	dsui.enable <= '1';
                   dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
                   dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
                 end generate;
               end generate;
               nodsu : if CFG_DSU = 0 generate
                 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
               end generate;
                irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
                 irqctrl0 : irqmp			-- interrupt controller
                 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
                 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
               end generate;
               irq3 : if CFG_IRQ3_ENABLE = 0 generate
                 x : for i in 0 to CFG_NCPU-1 generate
                   irqi(i).irl <= "0000";
                 end generate;
                 apbo(2) <= apb_none;
               end generate;
             ----------------------------------------------------------------------
             ---  Memory controllers  ---------------------------------------------
             ----------------------------------------------------------------------
                 memctrlr : mctrl generic map (hindex => 0,pindex   => 0, paddr    => 0)
                     port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
                 memi.brdyn <= '1'; memi.bexcn <= '1';
                 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
                 bdr : for i in 0 to 3 generate
                   data_pad : iopadv generic map (tech => padtech, width => 8)
                   port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
                 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
                 end generate;
                 addr_pad : outpadv generic map (width => 19, tech => padtech)
                 	port map (address, memo.address(20 downto 2));
                 SSRAM_0:entity ssram_plugin
                     generic map (tech => padtech)
                     port map
                     (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
             ----------------------------------------------------------------------
             ---  AHB CONTROLLER  -------------------------------------------------
             ----------------------------------------------------------------------
               ahb0 : ahbctrl 		-- AHB arbiter/multiplexer
               generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
             	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
             	ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
               port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
             ----------------------------------------------------------------------
             ---  AHB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               dcomgen : if CFG_AHB_UART = 1 generate
                 dcom0: ahbuart		-- Debug UART
                 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
                 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
                 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
                 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
             --    led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
               end generate;
               nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
             ----------------------------------------------------------------------
             ---  APB Bridge  -----------------------------------------------------
             ----------------------------------------------------------------------
               apb0 : apbctrl				-- AHB/APB bridge
               generic map (hindex => 1, haddr => CFG_APBADDR)
               port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
             ----------------------------------------------------------------------
             ---  GPT Timer  ------------------------------------------------------
             ----------------------------------------------------------------------
               gpt : if CFG_GPT_ENABLE /= 0 generate
                 timer0 : gptimer 			-- timer unit
                 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
             	sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
             	nbits => CFG_GPT_TW)
                 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
                 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
             --    led(4) <= gpto.wdog;
               end generate;
               notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
             ----------------------------------------------------------------------
             ---  APB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               ua1 : if CFG_UART1_ENABLE /= 0 generate
                 uart1 : apbuart			-- UART 1
                 generic map (pindex => 1, paddr => 1,  pirq => 2, console => dbguart,
             	fifosize => CFG_UART1_FIFO)
                 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
                 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
                 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
             --   led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
               end generate;
               noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
             ----------------------------------------------------------------------
             ---  GPIO  -----------------------------------------------------------
             ----------------------------------------------------------------------
               gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate     -- GR GPIO unit
                 grgpio0: grgpio
                   generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
                   port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
                   pio_pads : for i in 0 to 6 generate
                     pio_pad : iopad generic map (tech => padtech)
                         port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
                   end generate;
                end generate;
             end Behavioral;

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