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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity Linker_FFT is
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generic(
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Data_sz : integer range 1 to 32 := 16;
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NbData : integer range 1 to 512 := 256
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);
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port(
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clk : in std_logic;
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rstn : in std_logic;
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Ready : in std_logic;
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Valid : in std_logic;
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Full : in std_logic_vector(4 downto 0);
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Data_re : in std_logic_vector(Data_sz-1 downto 0);
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Data_im : in std_logic_vector(Data_sz-1 downto 0);
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Read : out std_logic;
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Write : out std_logic_vector(4 downto 0);
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ReUse : out std_logic_vector(4 downto 0);
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DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
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);
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end entity;
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architecture ar_Linker of Linker_FFT is
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type etat is (eX,e0,e1,e2);
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signal ect : etat;
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signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
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signal sRead : std_logic;
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signal sReady : std_logic;
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signal FifoCpt : integer range 0 to 4 := 0;
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begin
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process(clk,rstn)
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begin
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if(rstn='0')then
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ect <= e0;
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sRead <= '0';
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sReady <= '0';
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Write <= (others => '1');
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Reuse <= (others => '0');
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FifoCpt <= 0;
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elsif(clk'event and clk='1')then
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sReady <= Ready;
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if(sReady='1' and Ready='0')then
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if(FifoCpt=4)then
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FifoCpt <= 0;
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else
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FifoCpt <= FifoCpt + 1;
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end if;
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elsif(Ready='1')then
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sRead <= not sRead;
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else
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sRead <= '0';
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end if;
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case ect is
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when e0 =>
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Write(FifoCpt) <= '1';
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if(Valid='1' and Full(FifoCpt)='0')then
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DataTmp <= Data_im;
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DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= Data_re;
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Write(FifoCpt) <= '0';
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ect <= e1;
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elsif(Full(FifoCpt)='1')then
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ReUse(FifoCpt) <= '1';
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end if;
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when e1 =>
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DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= DataTmp;
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ect <= e0;
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when others =>
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null;
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end case;
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end if;
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end process;
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Read <= sRead;
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end architecture;
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