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Débug de la FIFO...
martin -
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1 -- FFTamont.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity FFTamont is
7 generic(
8 Data_sz : integer range 1 to 32 := 16
9 );
10 port(
11 clk : in std_logic;
12 rstn : in std_logic;
13 Load : in std_logic;
14 Empty : in std_logic;
15 Full : in std_logic;
16 DATA : in std_logic_vector(Data_sz-1 downto 0);
17 Valid : out std_logic;
18 Read : out std_logic;
19 Data_re : out std_logic_vector(Data_sz-1 downto 0);
20 Data_im : out std_logic_vector(Data_sz-1 downto 0)
21 );
22 end entity;
23
24
25 architecture ar_FFTamont of FFTamont is
26
27 type etat is (eX,e0,e1,e2);
28 signal ect : etat;
29
30
31 begin
32
33 process(clk,rstn)
34 begin
35 if(rstn='0')then
36 ect <= eX;
37 Read <= '1';
38 Valid <= '0';
39 Data_re <= (others => '0');
40 Data_im <= (others => '0');
41
42 elsif(clk'event and clk='1')then
43
44 case ect is
45
46 when eX =>
47 if(Full='1')then
48 ect <= e0;
49 end if;
50
51 when e0 =>
52 Valid <= '0';
53 if(Load='1' and Empty='0')then
54 Read <= '0';
55 ect <= e1;
56 elsif(Empty='1')then
57 ect <= eX;
58 end if;
59
60 when e1 =>
61 Read <= '1';
62 Data_re <= DATA;
63 Data_im <= (others => '0');
64 Valid <= '1';
65 ect <= e0;
66
67 when e2 =>
68 null;
69
70 end case;
71 end if;
72 end process;
73
74 end architecture;
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1 -- FFTaval.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity FFTaval is
7 generic(
8 Data_sz : integer range 1 to 32 := 8
9 );
10 port(
11 clk : in std_logic;
12 rstn : in std_logic;
13 Ready : in std_logic;
14 Valid : in std_logic;
15 Full : in std_logic;
16 Data_re : in std_logic_vector(Data_sz-1 downto 0);
17 Data_im : in std_logic_vector(Data_sz-1 downto 0);
18 Read : out std_logic;
19 Write : out std_logic;
20 ReUse : out std_logic;
21 DATA : out std_logic_vector(Data_sz-1 downto 0)
22 );
23 end entity;
24
25
26 architecture ar_FFTaval of FFTaval is
27
28 type etat is (eX,e0,e1,e2,e3);
29 signal ect : etat;
30
31 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
32
33 signal sReady : std_logic;
34
35 begin
36
37 process(clk,rstn)
38 begin
39 if(rstn='0')then
40 ect <= e0;
41 Read <= '0';
42 Write <= '1';
43 Reuse <= '0';
44
45 elsif(clk'event and clk='1')then
46 sReady <= Ready;
47
48 case ect is
49
50 when e0 =>
51 Write <= '1';
52 if(sReady='0' and Ready='1' and full='0')then
53 Read <= '1';
54 ect <= e1;
55 end if;
56
57 when e1 =>
58 Read <= '0';
59 if(Valid='1' and full='0')then
60 DataTmp <= Data_im;
61 DATA <= Data_re;
62 Write <= '0';
63 ect <= e2;
64 elsif(full='1')then
65 ReUse <= '1';
66 ect <= e0;
67 end if;
68
69 when e2 =>
70 DATA <= DataTmp;
71 ect <= e3;
72
73 when e3 =>
74 Write <= '1';
75 if(Ready='1' and full='0')then
76 Read <= '1';
77 ect <= e1;
78 end if;
79
80 when eX =>
81 null;
82
83 end case;
84 end if;
85 end process;
86
87
88
89 end architecture;
90
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
26
27 entity Dispatch is
28 generic(
29 Data_SZ : integer := 32);
30 port(
31 clk : in std_logic;
32 reset : in std_logic;
33 Acq : in std_logic;
34 Data : in std_logic_vector(Data_SZ-1 downto 0);
35 Write : in std_logic;
36 Full : in std_logic_vector(1 downto 0);
37 -- Empty : in std_logic_vector(1 downto 0);
38 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
39 FifoWrite : out std_logic_vector(1 downto 0);
40 -- FifoFull : out std_logic;
41 Pong : out std_logic;
42 Error : out std_logic
43
44 );
45 end entity;
46
47
48 architecture ar_Dispatch of Dispatch is
49
50 type etat is (e0,e1,e2,e3);
51 signal ect : etat;
52
53 begin
54
55 process (clk,reset)
56 begin
57 if(reset='0')then
58 Pong <= '0';
59 Error <= '0';
60
61 elsif(clk' event and clk='1')then
62
63 case ect is
64
65 when e0 =>
66 if(Full(0) = '1')then
67 pong <= '1';
68 ect <= e1;
69 end if;
70
71 when e1 =>
72 if(Acq <= '1')then
73 Error <= '0';
74 pong <= '0';
75 ect <= e2;
76 else
77 Error <= '1';
78 ect <= e1;
79 end if;
80
81 when e2 =>
82 if(Full(1) = '1')then
83 pong <= '1';
84 ect <= e3;
85 end if;
86
87 when e3 =>
88 if(Acq <= '1')then
89 Error <= '0';
90 pong <= '0';
91 ect <= e0;
92 else
93 Error <= '1';
94 ect <= e3;
95 end if;
96
97 end case;
98
99 end if;
100 end process;
101
102 FifoData <= Data & Data;
103
104 with ect select
105 FifoWrite <= '1' & not Write when e0,
106 not Write & '1' when e2,
107 "11" when others;
108
109 end architecture; No newline at end of file
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1 -- Bridge.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity Bridge is
7 generic(
8 Data_sz : integer range 1 to 32 := 16
9 );
10 port(
11 clk : in std_logic;
12 raz : in std_logic;
13 Start : in std_logic;
14 FullUp : in std_logic;
15 EmptyUp : in std_logic;
16 FullDown : in std_logic;
17 EmptyDown : in std_logic;
18 Write : out std_logic;
19 Read : out std_logic
20 );
21 end entity;
22
23
24 architecture ar_Bridge of Bridge is
25
26 type etat is (eX,e1,e2,e3);
27 signal ect : etat;
28
29 signal i : integer;
30
31 begin
32
33 process(clk,raz)
34 begin
35 if(raz='0')then
36 Write <= '1';
37 Read <= '1';
38 i <= 0;
39 ect <= eX;
40
41 elsif(clk'event and clk='1')then
42
43 case ect is
44
45 when eX =>
46 if(FullUp='1' and EmptyDown='1' and start='0')then
47 ect <= e1;
48 end if;
49
50 when e1 =>
51 Write <= '1';
52 if(EmptyUp='0')then
53 Read <= '0';
54 ect <= e2;
55 else
56 Read <= '1';
57 ect <= e3;
58 end if;
59
60 when e2 =>
61 Read <= '1';
62 if(FullDown='0')then
63 Write <= '0';
64 ect <= e1;
65 else
66 Write <= '1';
67 ect <= e3;
68 end if;
69
70 when e3 =>
71 null;
72
73 end case;
74 end if;
75 end process;
76
77
78 end architecture; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27 library techmap;
28 use techmap.gencomp.all;
29
30 entity lppFIFOx5 is
31 generic(
32 tech : integer := 0;
33 Data_sz : integer range 1 to 32 := 8;
34 Enable_ReUse : std_logic := '0'
35 );
36 port(
37 rst : in std_logic;
38 wclk : in std_logic;
39 rclk : in std_logic;
40 ReUse : in std_logic_vector(4 downto 0);
41 wen : in std_logic_vector(4 downto 0);
42 ren : in std_logic_vector(4 downto 0);
43 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
44 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
45 full : out std_logic_vector(4 downto 0);
46 empty : out std_logic_vector(4 downto 0)
47 );
48 end entity;
49
50
51 architecture ar_lppFIFOx5 of lppFIFOx5 is
52
53 begin
54
55 fifoB1 : entity work.lpp_fifo
56 generic map (tech,Enable_ReUse,Data_sz,8)
57 port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open);
58
59 fifoB2 : entity work.lpp_fifo
60 generic map (tech,Enable_ReUse,Data_sz,8)
61 port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open);
62
63 fifoB3 : entity work.lpp_fifo
64 generic map (tech,Enable_ReUse,Data_sz,8)
65 port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open);
66
67 fifoE1 : entity work.lpp_fifo
68 generic map (tech,Enable_ReUse,Data_sz,8)
69 port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open);
70
71 fifoE2 : entity work.lpp_fifo
72 generic map (tech,Enable_ReUse,Data_sz,8)
73 port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open);
74
75
76 end architecture;
77
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@@ -1,148 +1,148
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25
25
26
26
27 package FILTERcfg is
27 package FILTERcfg is
28
28
29
29
30
30
31
31
32 --===========================================================|
32 --===========================================================|
33 --========F I L T E R C O N F I G V A L U E S=============|
33 --========F I L T E R C O N F I G V A L U E S=============|
34 --===========================================================|
34 --===========================================================|
35 --____________________________
35 --____________________________
36 --Bus Width and chanels number|
36 --Bus Width and chanels number|
37 --____________________________|
37 --____________________________|
38 constant ChanelsCount : integer := 1;
38 constant ChanelsCount : integer := 1;
39 constant Sample_SZ : integer := 20;
39 constant Sample_SZ : integer := 18;
40 constant Coef_SZ : integer := 9;
40 constant Coef_SZ : integer := 9;
41 constant CoefCntPerCel: integer := 6;
41 constant CoefCntPerCel: integer := 6;
42 constant Cels_count : integer := 5;
42 constant Cels_count : integer := 5;
43 constant virgPos : integer := 7;
43 constant virgPos : integer := 7;
44 constant Mem_use : integer := 1;
44 constant Mem_use : integer := 1;
45
45
46
46
47
47
48 --============================================================
48 --============================================================
49 -- create each initial values for each coefs ============
49 -- create each initial values for each coefs ============
50 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
50 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
51 --============================================================
51 --============================================================
52 constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
52 constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
53 constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ));
53 constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ));
54 constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
54 constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
55
55
56 constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
56 constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
57 constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ));
57 constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ));
58 constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
58 constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
59
59
60 constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
60 constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
61 constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ));
61 constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ));
62 constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
62 constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
63
63
64 constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
64 constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
65 constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ));
65 constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ));
66 constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
66 constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
67
67
68 constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
68 constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
69 constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
69 constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
70 constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
70 constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
71
71
72 constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
72 constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
73 constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
73 constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
74 constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
74 constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
75
75
76 constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
76 constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
77 constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
77 constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
78 constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
78 constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
79
79
80
80
81 constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
81 constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
82 constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ));
82 constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ));
83 constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ));
83 constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ));
84
84
85 constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
85 constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
86 constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ));
86 constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ));
87 constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
87 constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
88
88
89 constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
89 constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
90 constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ));
90 constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ));
91 constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ));
91 constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ));
92
92
93 constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
93 constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
94 constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ));
94 constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ));
95 constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ));
95 constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ));
96
96
97 constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
97 constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
98 constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
98 constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
99 constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
99 constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
100
100
101 constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
101 constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
102 constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
102 constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
103 constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
103 constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
104 constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
104 constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
105 constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
105 constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
106 constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
106 constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
107
107
108 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
108 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
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111 end;
111 end;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25
25
26 entity RAM_CEL is
26 entity RAM_CEL is
27 port( WD : in std_logic_vector(35 downto 0); RD : out
27 port( WD : in std_logic_vector(15 downto 0); RD : out
28 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
28 std_logic_vector(15 downto 0);WEN, REN : in std_logic;
29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
31 ) ;
31 ) ;
32 end RAM_CEL;
32 end RAM_CEL;
33
33
34
34
35
35
36 architecture ar_RAM_CEL of RAM_CEL is
36 architecture ar_RAM_CEL of RAM_CEL is
37 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
37 type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
38 signal RAMarray : RAMarrayT:=(others => X"000000000");
38 signal RAMarray : RAMarrayT:=(others => X"0000");
39 signal RD_int : std_logic_vector(35 downto 0);
39 signal RD_int : std_logic_vector(15 downto 0);
40
40
41 begin
41 begin
42
42
43 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
43 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
44
44
45
45
46 process(RWclk,reset)
46 process(RWclk,reset)
47 begin
47 begin
48 if reset = '0' then
48 if reset = '0' then
49 RD <= (X"000000000");
49 RD <= (X"0000");
50 rst:for i in 0 to 255 loop
50 rst:for i in 0 to 255 loop
51 RAMarray(i) <= (others => '0');
51 RAMarray(i) <= (others => '0');
52 end loop;
52 end loop;
53
53
54 elsif RWclk'event and RWclk = '1' then
54 elsif RWclk'event and RWclk = '1' then
55 if REN = '0' then
55 if REN = '0' then
56 RD <= RD_int;
56 RD <= RD_int;
57 end if;
57 end if;
58
58
59 if WEN = '0' then
59 if WEN = '0' then
60 RAMarray(to_integer(unsigned(WADDR))) <= WD;
60 RAMarray(to_integer(unsigned(WADDR))) <= WD;
61 end if;
61 end if;
62
62
63 end if;
63 end if;
64 end process;
64 end process;
65 end ar_RAM_CEL;
65 end ar_RAM_CEL;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
25 library lpp;
26 use lpp.iir_filter.all;
26 use lpp.iir_filter.all;
27 use lpp.FILTERcfg.all;
27 use lpp.FILTERcfg.all;
28 use lpp.general_purpose.all;
28 use lpp.general_purpose.all;
29 library techmap;
29 library techmap;
30 use techmap.gencomp.all;
30 use techmap.gencomp.all;
31
31
32 --TODO amliorer la flexibilit de la config de la RAM.
32 --TODO amliorer la flexibilit de la config de la RAM.
33
33
34 entity RAM_CTRLR2 is
34 entity RAM_CTRLR2 is
35 generic(
35 generic(
36 tech : integer := 0;
36 tech : integer := 0;
37 Input_SZ_1 : integer := 16;
37 Input_SZ_1 : integer := 16;
38 Mem_use : integer := use_RAM
38 Mem_use : integer := use_RAM
39
39
40 );
40 );
41 port(
41 port(
42 reset : in std_logic;
42 reset : in std_logic;
43 clk : in std_logic;
43 clk : in std_logic;
44 WD_sel : in std_logic;
44 WD_sel : in std_logic;
45 Read : in std_logic;
45 Read : in std_logic;
46 WADDR_sel : in std_logic;
46 WADDR_sel : in std_logic;
47 count : in std_logic;
47 count : in std_logic;
48 SVG_ADDR : in std_logic;
48 SVG_ADDR : in std_logic;
49 Write : in std_logic;
49 Write : in std_logic;
50 GO_0 : in std_logic;
50 GO_0 : in std_logic;
51 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
51 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
52 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
52 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
53 );
53 );
54 end RAM_CTRLR2;
54 end RAM_CTRLR2;
55
55
56
56
57 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
57 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
58
58
59 signal WD : std_logic_vector(Input_SZ_1-1 downto 0);
59 signal WD : std_logic_vector(Input_SZ_1-1 downto 0);
60 signal WD_D : std_logic_vector(Input_SZ_1-1 downto 0);
60 signal WD_D : std_logic_vector(Input_SZ_1-1 downto 0);
61 signal RD : std_logic_vector(Input_SZ_1-1 downto 0);
61 signal RD : std_logic_vector(Input_SZ_1-1 downto 0);
62 signal WEN, REN : std_logic;
62 signal WEN, REN : std_logic;
63 signal WADDR_back : std_logic_vector(7 downto 0);
63 signal WADDR_back : std_logic_vector(7 downto 0);
64 signal WADDR_back_D: std_logic_vector(7 downto 0);
64 signal WADDR_back_D: std_logic_vector(7 downto 0);
65 signal RADDR : std_logic_vector(7 downto 0);
65 signal RADDR : std_logic_vector(7 downto 0);
66 signal WADDR : std_logic_vector(7 downto 0);
66 signal WADDR : std_logic_vector(7 downto 0);
67 signal WADDR_D : std_logic_vector(7 downto 0);
67 signal WADDR_D : std_logic_vector(7 downto 0);
68
68
69
69 SIGNAL WADDR_back_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
70
70
71 begin
71 begin
72
72
73 sample_out <= RD(Input_SZ_1-1 downto 0);
73 sample_out <= RD(Input_SZ_1-1 downto 0);
74
74
75
75
76 WEN <= not Write;
76 WEN <= not Write;
77 REN <= not read;
77 REN <= not read;
78
78
79
79
80 --==============================================================
80 --==============================================================
81 --=========================R A M================================
81 --=========================R A M================================
82 --==============================================================
82 --==============================================================
83 --memRAM : if (Mem_use = use_RAM or Mem_use = use_CEL)generate
83 --memRAM : if (Mem_use = use_RAM or Mem_use = use_CEL)generate
84 --RAMblk : entity work.RAM
84 --RAMblk : entity work.RAM
85 -- generic map
85 -- generic map
86 -- (
86 -- (
87 -- Input_SZ_1
87 -- Input_SZ_1
88 -- )
88 -- )
89 -- port map(
89 -- port map(
90 -- WD => WD_D,
90 -- WD => WD_D,
91 -- RD => RD,
91 -- RD => RD,
92 -- WEN => WEN,
92 -- WEN => WEN,
93 -- REN => REN,
93 -- REN => REN,
94 -- WADDR => WADDR,
94 -- WADDR => WADDR,
95 -- RADDR => RADDR,
95 -- RADDR => RADDR,
96 -- RWCLK => clk,
96 -- RWCLK => clk,
97 -- RESET => reset
97 -- RESET => reset
98 -- ) ;
98 -- ) ;
99 --end generate;
99 --end generate;
100
100
101 --memCEL : if Mem_use = use_CEL generate
101 --memCEL : if Mem_use = use_CEL generate
102 --RAMblk :RAM_CEL
102 --RAMblk :RAM_CEL
103 -- port map(
103 -- port map(
104 -- WD => WD_D,
104 -- WD => WD_D,
105 -- RD => RD,
105 -- RD => RD,
106 -- WEN => WEN,
106 -- WEN => WEN,
107 -- REN => REN,
107 -- REN => REN,
108 -- WADDR => WADDR,
108 -- WADDR => WADDR,
109 -- RADDR => RADDR,
109 -- RADDR => RADDR,
110 -- RWCLK => clk,
110 -- RWCLK => clk,
111 -- RESET => reset
111 -- RESET => reset
112 -- ) ;
112 -- ) ;
113 --end generate;
113 --end generate;
114
114
115 SRAM : syncram_2p
115 SRAM : syncram_2p
116 generic map(tech,8,Input_SZ_1)
116 generic map(tech,8,Input_SZ_1)
117 port map(clk,not REN,RADDR,RD,clk,not WEN,WADDR,WD_D);
117 port map(clk,not REN,RADDR,RD,clk,not WEN,WADDR,WD_D);
118 --==============================================================
118 --==============================================================
119 --==============================================================
119 --==============================================================
120
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121
121
122 ADDRcntr_inst : ADDRcntr
122 ADDRcntr_inst : ADDRcntr
123 port map(
123 port map(
124 clk => clk,
124 clk => clk,
125 reset => reset,
125 reset => reset,
126 count => count,
126 count => count,
127 clr => GO_0,
127 clr => GO_0,
128 Q => RADDR
128 Q => RADDR
129 );
129 );
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132
133 MUX2_inst1 :MUX2
133 MUX2_inst1 :MUX2
134 generic map(Input_SZ => Input_SZ_1)
134 generic map(Input_SZ => Input_SZ_1)
135 port map(
135 port map(
136 sel => WD_sel,
136 sel => WD_sel,
137 IN1 => sample_in,
137 IN1 => sample_in,
138 IN2 => RD(Input_SZ_1-1 downto 0),
138 IN2 => RD(Input_SZ_1-1 downto 0),
139 RES => WD(Input_SZ_1-1 downto 0)
139 RES => WD(Input_SZ_1-1 downto 0)
140 );
140 );
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142
143 MUX2_inst2 :MUX2
143 MUX2_inst2 :MUX2
144 generic map(Input_SZ => 8)
144 generic map(Input_SZ => 8)
145 port map(
145 port map(
146 sel => WADDR_sel,
146 sel => WADDR_sel,
147 IN1 => WADDR_D,
147 IN1 => WADDR_D,
148 IN2 => WADDR_back_D,
148 IN2 => WADDR_back_D,
149 RES => WADDR
149 RES => WADDR
150 );
150 );
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152
153
153 WADDR_backreg : REG
154 generic map(size => 8,initial_VALUE =>ChanelsCount*Cels_count*4-2)
155 port map(
156 reset => reset,
157 clk => clk, --SVG_ADDR,
158 D => WADDR_back_s,--RADDR,
159 Q => WADDR_back
160 );
161 WADDR_back_s <= RADDR WHEN SVG_ADDR = '1' ELSE WADDR_back;
154
162
155 WADDR_backreg :REG
163 WADDR_backreg2 :entity work.REG
156 generic map(size => 8,initial_VALUE =>ChanelsCouNT*Cels_count*4-2)
164 generic map(size => 8)
157 port map(
165 port map(
158 reset => reset,
166 reset => reset,
159 clk => SVG_ADDR,
167 clk => clk, --SVG_ADDR,
160 D => RADDR,
168 D => WADDR_back,
161 Q => WADDR_back
169 Q => WADDR_back_D
162 );
170 );
163
171
164 WADDR_backreg2 :REG
172 --WADDR_backreg :REG
165 generic map(size => 8)
173 --generic map(size => 8,initial_VALUE =>ChanelsCouNT*Cels_count*4-2)
166 port map(
174 --port map(
167 reset => reset,
175 -- reset => reset,
168 clk => SVG_ADDR,
176 -- clk => SVG_ADDR,
169 D => WADDR_back,
177 -- D => RADDR,
170 Q => WADDR_back_D
178 -- Q => WADDR_back
171 );
179 --);
180 --
181 --WADDR_backreg2 :REG
182 --generic map(size => 8)
183 --port map(
184 -- reset => reset,
185 -- clk => SVG_ADDR,
186 -- D => WADDR_back,
187 -- Q => WADDR_back_D
188 --
172
189
173 WDRreg :REG
190 WDRreg :REG
174 generic map(size => Input_SZ_1)
191 generic map(size => Input_SZ_1)
175 port map(
192 port map(
176 reset => reset,
193 reset => reset,
177 clk => clk,
194 clk => clk,
178 D => WD(Input_SZ_1-1 downto 0),
195 D => WD(Input_SZ_1-1 downto 0),
179 Q => WD_D(Input_SZ_1-1 downto 0)
196 Q => WD_D(Input_SZ_1-1 downto 0)
180 );
197 );
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185 ADDRreg :REG
202 ADDRreg :REG
186 generic map(size => 8)
203 generic map(size => 8)
187 port map(
204 port map(
188 reset => reset,
205 reset => reset,
189 clk => clk,
206 clk => clk,
190 D => RADDR,
207 D => RADDR,
191 Q => WADDR_D
208 Q => WADDR_D
192 );
209 );
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196 end ar_RAM_CTRLR2;
213 end ar_RAM_CTRLR2;
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@@ -1,74 +1,74
1 -- Top_IIR.vhd
1 -- Top_IIR.vhd
2 library IEEE;
2 library IEEE;
3 use IEEE.std_logic_1164.all;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
4 use IEEE.numeric_std.all;
5 use work.FILTERcfg.all;
5 use work.FILTERcfg.all;
6 use lpp.iir_filter.all;
6 use lpp.iir_filter.all;
7
7
8 entity Top_IIR is
8 entity Top_IIR is
9 generic(
9 generic(
10 Sample_SZ : integer := 20;
10 Sample_SZ : integer := 18;
11 ChanelsCount : integer := 1;
11 ChanelsCount : integer := 1;
12 Coef_SZ : integer := 9;
12 Coef_SZ : integer := 9;
13 CoefCntPerCel: integer := 6;
13 CoefCntPerCel: integer := 6;
14 Cels_count : integer := 5);
14 Cels_count : integer := 5);
15 port(
15 port(
16 reset : in std_logic;
16 reset : in std_logic;
17 clk : in std_logic;
17 clk : in std_logic;
18 sample_clk : in std_logic;
18 sample_clk : in std_logic;
19 -- BP : in std_logic;
19 -- BP : in std_logic;
20 BPinput : in std_logic_vector(3 downto 0);
20 -- BPinput : in std_logic_vector(3 downto 0);
21 LVLinput : in std_logic_vector(11 downto 0);
21 LVLinput : in std_logic_vector(15 downto 0);
22 INsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
22 INsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
23 OUTsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
23 OUTsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
24 );
24 );
25 end entity;
25 end entity;
26
26
27
27
28 architecture ar_Top_IIR of Top_IIR is
28 architecture ar_Top_IIR of Top_IIR is
29
29
30 signal regs_in : in_IIR_CEL_reg;
30 signal regs_in : in_IIR_CEL_reg;
31 signal regs_out : out_IIR_CEL_reg;
31 signal regs_out : out_IIR_CEL_reg;
32 signal sample_in : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
32 signal sample_in : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
33 signal sample_out : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
33 signal sample_out : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
34 signal coefs : std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0);
34 signal coefs : std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0);
35
35
36 signal sample_int : std_logic_vector(Sample_SZ-1 downto 0):=(others => '0');
36 signal sample_int : std_logic_vector(Sample_SZ-1 downto 0):=(others => '0');
37 --signal sample_temp : std_logic_vector(Sample_SZ-1 downto 0):=(others => '0');
37 --signal sample_temp : std_logic_vector(Sample_SZ-1 downto 0):=(others => '0');
38
38
39 begin
39 begin
40
40
41 ChanelLoop: for i in 0 to ChanelsCount-1 generate
41 ChanelLoop: for i in 0 to ChanelsCount-1 generate
42 SampleLoop: for j in 0 to Sample_SZ-1 generate
42 SampleLoop: for j in 0 to Sample_SZ-1 generate
43 sample_in(i,j) <= sample_int(i*20+j);
43 sample_in(i,j) <= sample_int(i*20+j);
44 end generate;
44 end generate;
45 end generate;
45 end generate;
46
46
47 --CH2loop: for k in 0 to Sample_SZ-1 generate
47 --CH2loop: for k in 0 to Sample_SZ-1 generate
48 -- sample_temp(k) <= BP;
48 -- sample_temp(k) <= BP;
49 --end generate;
49 --end generate;
50
50
51 sample_int <= BPinput(3) & BPinput(3) & BPinput(3) & BPinput(3) & BPinput & LVLinput;
51 sample_int <= LVLinput(15) & LVLinput(15) & LVLinput;
52 INsample <= sample_in;
52 INsample <= sample_in;
53 OUTsample <= sample_out;
53 OUTsample <= sample_out;
54
54
55 filter : IIR_CEL_FILTER
55 filter : IIR_CEL_FILTER
56 generic map (0,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,1)
56 generic map (0,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,1)
57 port map(
57 port map(
58 reset => reset,
58 reset => reset,
59 clk => clk,
59 clk => clk,
60 sample_clk => sample_clk,
60 sample_clk => sample_clk,
61 regs_in => regs_in,
61 regs_in => regs_in,
62 regs_out => regs_out,
62 regs_out => regs_out,
63 sample_in => sample_in,
63 sample_in => sample_in,
64 sample_out => sample_out,
64 sample_out => sample_out,
65 coefs => coefs
65 coefs => coefs
66 );
66 );
67
67
68 coefs <= CoefsInitValCst;
68 coefs <= CoefsInitValCst;
69 regs_in.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
69 regs_in.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
70 regs_in.config <= (others => '1');
70 regs_in.config <= (others => '1');
71
71
72
72
73
73
74 end architecture; No newline at end of file
74 end architecture;
Show file before | Show file after | Hide comments
@@ -1,266 +1,266
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29
29
30
30
31
31
32
32
33 package iir_filter is
33 package iir_filter is
34
34
35
35
36 --===========================================================|
36 --===========================================================|
37 --================A L U C O N T R O L======================|
37 --================A L U C O N T R O L======================|
38 --===========================================================|
38 --===========================================================|
39 constant IDLE : std_logic_vector(3 downto 0) := "0000";
39 constant IDLE : std_logic_vector(3 downto 0) := "0000";
40 constant MAC_op : std_logic_vector(3 downto 0) := "0001";
40 constant MAC_op : std_logic_vector(3 downto 0) := "0001";
41 constant MULT : std_logic_vector(3 downto 0) := "0010";
41 constant MULT : std_logic_vector(3 downto 0) := "0010";
42 constant ADD : std_logic_vector(3 downto 0) := "0011";
42 constant ADD : std_logic_vector(3 downto 0) := "0011";
43 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
43 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
44
44
45 --____
45 --____
46 --RAM |
46 --RAM |
47 --____|
47 --____|
48 constant use_RAM : integer := 1;
48 constant use_RAM : integer := 1;
49 constant use_CEL : integer := 0;
49 constant use_CEL : integer := 0;
50
50
51
51
52 --===========================================================|
52 --===========================================================|
53 --=============C O E F S ====================================|
53 --=============C O E F S ====================================|
54 --===========================================================|
54 --===========================================================|
55 -- create a specific type of data for coefs to avoid errors |
55 -- create a specific type of data for coefs to avoid errors |
56 --===========================================================|
56 --===========================================================|
57
57
58 type scaleValT is array(natural range <>) of integer;
58 type scaleValT is array(natural range <>) of integer;
59
59
60 type samplT is array(natural range <>,natural range <>) of std_logic;
60 type samplT is array(natural range <>,natural range <>) of std_logic;
61
61
62 type in_IIR_CEL_reg is record
62 type in_IIR_CEL_reg is record
63 config : std_logic_vector(31 downto 0);
63 config : std_logic_vector(31 downto 0);
64 virgPos : std_logic_vector(4 downto 0);
64 virgPos : std_logic_vector(4 downto 0);
65 end record;
65 end record;
66
66
67 type out_IIR_CEL_reg is record
67 type out_IIR_CEL_reg is record
68 config : std_logic_vector(31 downto 0);
68 config : std_logic_vector(31 downto 0);
69 status : std_logic_vector(31 downto 0);
69 status : std_logic_vector(31 downto 0);
70 end record;
70 end record;
71
71
72
72
73 component APB_IIR_CEL is
73 component APB_IIR_CEL is
74 generic (
74 generic (
75 tech : integer := 0;
75 tech : integer := 0;
76 pindex : integer := 0;
76 pindex : integer := 0;
77 paddr : integer := 0;
77 paddr : integer := 0;
78 pmask : integer := 16#fff#;
78 pmask : integer := 16#fff#;
79 pirq : integer := 0;
79 pirq : integer := 0;
80 abits : integer := 8;
80 abits : integer := 8;
81 Sample_SZ : integer := 16;
81 Sample_SZ : integer := 16;
82 ChanelsCount : integer := 6;
82 ChanelsCount : integer := 6;
83 Coef_SZ : integer := 9;
83 Coef_SZ : integer := 9;
84 CoefCntPerCel: integer := 6;
84 CoefCntPerCel: integer := 6;
85 Cels_count : integer := 5;
85 Cels_count : integer := 5;
86 virgPos : integer := 7;
86 virgPos : integer := 7;
87 Mem_use : integer := use_RAM
87 Mem_use : integer := use_RAM
88 );
88 );
89 port (
89 port (
90 rst : in std_logic;
90 rst : in std_logic;
91 clk : in std_logic;
91 clk : in std_logic;
92 apbi : in apb_slv_in_type;
92 apbi : in apb_slv_in_type;
93 apbo : out apb_slv_out_type;
93 apbo : out apb_slv_out_type;
94 sample_clk : in std_logic;
94 sample_clk : in std_logic;
95 sample_clk_out : out std_logic;
95 sample_clk_out : out std_logic;
96 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
96 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
97 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
97 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
98 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
98 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
99 );
99 );
100 end component;
100 end component;
101
101
102
102
103 component Top_IIR is
103 component Top_IIR is
104 generic(
104 generic(
105 Sample_SZ : integer := 20;
105 Sample_SZ : integer := 18;
106 ChanelsCount : integer := 1;
106 ChanelsCount : integer := 1;
107 Coef_SZ : integer := 9;
107 Coef_SZ : integer := 9;
108 CoefCntPerCel: integer := 6;
108 CoefCntPerCel: integer := 6;
109 Cels_count : integer := 5);
109 Cels_count : integer := 5);
110 port(
110 port(
111 reset : in std_logic;
111 reset : in std_logic;
112 clk : in std_logic;
112 clk : in std_logic;
113 sample_clk : in std_logic;
113 sample_clk : in std_logic;
114 -- BP : in std_logic;
114 -- BP : in std_logic;
115 BPinput : in std_logic_vector(3 downto 0);
115 -- BPinput : in std_logic_vector(3 downto 0);
116 LVLinput : in std_logic_vector(11 downto 0);
116 LVLinput : in std_logic_vector(15 downto 0);
117 INsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
117 INsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
118 OUTsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
118 OUTsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
119 );
119 );
120 end component;
120 end component;
121
121
122
122
123
123
124 --component FilterCTRLR is
124 --component FilterCTRLR is
125 --port(
125 --port(
126 -- reset : in std_logic;
126 -- reset : in std_logic;
127 -- clk : in std_logic;
127 -- clk : in std_logic;
128 -- sample_clk : in std_logic;
128 -- sample_clk : in std_logic;
129 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
129 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
130 -- sample_in : in samplT;
130 -- sample_in : in samplT;
131 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
131 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
132 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
132 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
133 --);
133 --);
134 --end component;
134 --end component;
135
135
136
136
137 --component FILTER_RAM_CTRLR is
137 --component FILTER_RAM_CTRLR is
138 --port(
138 --port(
139 -- reset : in std_logic;
139 -- reset : in std_logic;
140 -- clk : in std_logic;
140 -- clk : in std_logic;
141 -- run : in std_logic;
141 -- run : in std_logic;
142 -- GO_0 : in std_logic;
142 -- GO_0 : in std_logic;
143 -- B_A : in std_logic;
143 -- B_A : in std_logic;
144 -- writeForce : in std_logic;
144 -- writeForce : in std_logic;
145 -- next_blk : in std_logic;
145 -- next_blk : in std_logic;
146 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
146 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
147 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
147 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
148 --);
148 --);
149 --end component;
149 --end component;
150
150
151
151
152 component IIR_CEL_CTRLR is
152 component IIR_CEL_CTRLR is
153 generic(
153 generic(
154 tech : integer := 0;
154 tech : integer := 0;
155 Sample_SZ : integer := 16;
155 Sample_SZ : integer := 16;
156 ChanelsCount : integer := 1;
156 ChanelsCount : integer := 1;
157 Coef_SZ : integer := 9;
157 Coef_SZ : integer := 9;
158 CoefCntPerCel: integer := 3;
158 CoefCntPerCel: integer := 3;
159 Cels_count : integer := 5;
159 Cels_count : integer := 5;
160 Mem_use : integer := use_RAM
160 Mem_use : integer := use_RAM
161 );
161 );
162 port(
162 port(
163 reset : in std_logic;
163 reset : in std_logic;
164 clk : in std_logic;
164 clk : in std_logic;
165 sample_clk : in std_logic;
165 sample_clk : in std_logic;
166 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
166 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
167 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
167 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
168 virg_pos : in integer;
168 virg_pos : in integer;
169 GOtest : out std_logic;
169 GOtest : out std_logic;
170 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
170 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
171 );
171 );
172 end component;
172 end component;
173
173
174
174
175 component RAM is
175 component RAM is
176 generic(
176 generic(
177 Input_SZ_1 : integer := 8
177 Input_SZ_1 : integer := 8
178 );
178 );
179 port( WD : in std_logic_vector(Input_SZ_1-1 downto 0); RD : out
179 port( WD : in std_logic_vector(Input_SZ_1-1 downto 0); RD : out
180 std_logic_vector(Input_SZ_1-1 downto 0);WEN, REN : in std_logic;
180 std_logic_vector(Input_SZ_1-1 downto 0);WEN, REN : in std_logic;
181 WADDR : in std_logic_vector(7 downto 0); RADDR : in
181 WADDR : in std_logic_vector(7 downto 0); RADDR : in
182 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
182 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
183 ) ;
183 ) ;
184 end component;
184 end component;
185
185
186
186
187 component RAM_CEL is
187 component RAM_CEL is
188 port( WD : in std_logic_vector(35 downto 0); RD : out
188 port( WD : in std_logic_vector(35 downto 0); RD : out
189 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
189 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
190 WADDR : in std_logic_vector(7 downto 0); RADDR : in
190 WADDR : in std_logic_vector(7 downto 0); RADDR : in
191 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
191 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
192 ) ;
192 ) ;
193 end component;
193 end component;
194
194
195 component IIR_CEL_FILTER is
195 component IIR_CEL_FILTER is
196 generic(
196 generic(
197 tech : integer := 0;
197 tech : integer := 0;
198 Sample_SZ : integer := 16;
198 Sample_SZ : integer := 16;
199 ChanelsCount : integer := 1;
199 ChanelsCount : integer := 1;
200 Coef_SZ : integer := 9;
200 Coef_SZ : integer := 9;
201 CoefCntPerCel: integer := 3;
201 CoefCntPerCel: integer := 3;
202 Cels_count : integer := 5;
202 Cels_count : integer := 5;
203 Mem_use : integer := use_RAM);
203 Mem_use : integer := use_RAM);
204 port(
204 port(
205 reset : in std_logic;
205 reset : in std_logic;
206 clk : in std_logic;
206 clk : in std_logic;
207 sample_clk : in std_logic;
207 sample_clk : in std_logic;
208 regs_in : in in_IIR_CEL_reg;
208 regs_in : in in_IIR_CEL_reg;
209 regs_out : in out_IIR_CEL_reg;
209 regs_out : in out_IIR_CEL_reg;
210 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
210 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
211 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
211 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
212 GOtest : out std_logic;
212 GOtest : out std_logic;
213 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
213 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
214
214
215 );
215 );
216 end component;
216 end component;
217
217
218
218
219 component RAM_CTRLR2 is
219 component RAM_CTRLR2 is
220 generic(
220 generic(
221 tech : integer := 0;
221 tech : integer := 0;
222 Input_SZ_1 : integer := 16;
222 Input_SZ_1 : integer := 16;
223 Mem_use : integer := use_RAM
223 Mem_use : integer := use_RAM
224 );
224 );
225 port(
225 port(
226 reset : in std_logic;
226 reset : in std_logic;
227 clk : in std_logic;
227 clk : in std_logic;
228 WD_sel : in std_logic;
228 WD_sel : in std_logic;
229 Read : in std_logic;
229 Read : in std_logic;
230 WADDR_sel : in std_logic;
230 WADDR_sel : in std_logic;
231 count : in std_logic;
231 count : in std_logic;
232 SVG_ADDR : in std_logic;
232 SVG_ADDR : in std_logic;
233 Write : in std_logic;
233 Write : in std_logic;
234 GO_0 : in std_logic;
234 GO_0 : in std_logic;
235 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
235 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
236 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
236 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
237 );
237 );
238 end component;
238 end component;
239
239
240 component APB_IIR_Filter is
240 component APB_IIR_Filter is
241 generic (
241 generic (
242 tech : integer := 0;
242 tech : integer := 0;
243 pindex : integer := 0;
243 pindex : integer := 0;
244 paddr : integer := 0;
244 paddr : integer := 0;
245 pmask : integer := 16#fff#;
245 pmask : integer := 16#fff#;
246 pirq : integer := 0;
246 pirq : integer := 0;
247 abits : integer := 8;
247 abits : integer := 8;
248 Sample_SZ : integer := 16;
248 Sample_SZ : integer := 16;
249 ChanelsCount : integer := 1;
249 ChanelsCount : integer := 1;
250 Coef_SZ : integer := 9;
250 Coef_SZ : integer := 9;
251 CoefCntPerCel: integer := 6;
251 CoefCntPerCel: integer := 6;
252 Cels_count : integer := 5;
252 Cels_count : integer := 5;
253 virgPos : integer := 3;
253 virgPos : integer := 3;
254 Mem_use : integer := use_RAM
254 Mem_use : integer := use_RAM
255 );
255 );
256 port (
256 port (
257 rst : in std_logic;
257 rst : in std_logic;
258 clk : in std_logic;
258 clk : in std_logic;
259 apbi : in apb_slv_in_type;
259 apbi : in apb_slv_in_type;
260 apbo : out apb_slv_out_type;
260 apbo : out apb_slv_out_type;
261 sample_clk_out : out std_logic;
261 sample_clk_out : out std_logic;
262 GOtest : out std_logic;
262 GOtest : out std_logic;
263 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
263 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
264 );
264 );
265 end component;
265 end component;
266 end;
266 end;
Show file before | Show file after | Hide comments
@@ -1,155 +1,157
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25
25
26 entity Driver_FFT is
26 entity Driver_FFT is
27 generic(
27 generic(
28 Data_sz : integer range 1 to 32 := 16
28 Data_sz : integer range 1 to 32 := 16
29 );
29 );
30 port(
30 port(
31 clk : in std_logic;
31 clk : in std_logic;
32 rstn : in std_logic;
32 rstn : in std_logic;
33 Load : in std_logic;
33 Load : in std_logic;
34 Empty : in std_logic_vector(4 downto 0);
34 Empty : in std_logic_vector(4 downto 0);
35 Full : in std_logic_vector(4 downto 0);
35 Full : in std_logic_vector(4 downto 0);
36 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
36 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
37 Valid : out std_logic;
37 Valid : out std_logic;
38 Read : out std_logic_vector(4 downto 0);
38 Read : out std_logic_vector(4 downto 0);
39 Data_re : out std_logic_vector(Data_sz-1 downto 0);
39 Data_re : out std_logic_vector(Data_sz-1 downto 0);
40 Data_im : out std_logic_vector(Data_sz-1 downto 0)
40 Data_im : out std_logic_vector(Data_sz-1 downto 0)
41 );
41 );
42 end entity;
42 end entity;
43
43
44
44
45 architecture ar_Driver of Driver_FFT is
45 architecture ar_Driver of Driver_FFT is
46
46
47 type etat is (eX,e0,e1,e2);
47 type etat is (eX,e0,e1,e2);
48 signal ect : etat;
48 signal ect : etat;
49
49
50 signal FifoCpt : integer;
50 signal FifoCpt : integer;
51 --signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
51 --signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
52
52
53 signal sEmpty : std_logic;
53 signal sEmpty : std_logic;
54 signal sFull : std_logic;
54 signal sFull : std_logic;
55 signal sData : std_logic_vector(Data_sz-1 downto 0);
55 signal sData : std_logic_vector(Data_sz-1 downto 0);
56
56
57 begin
57 begin
58
58
59 process(clk,rstn)
59 process(clk,rstn)
60 begin
60 begin
61 if(rstn='0')then
61 if(rstn='0')then
62 ect <= eX;
62 ect <= eX;
63 Read <= (others => '1');
63 Read <= (others => '1');
64 Valid <= '0';
64 Valid <= '0';
65 FifoCpt <= 1;
65 FifoCpt <= 1;
66 Data_re <= (others => '0');
67 Data_im <= (others => '0');
66
68
67 elsif(clk'event and clk='1')then
69 elsif(clk'event and clk='1')then
68
70
69 case ect is
71 case ect is
70
72
71 when eX =>
73 when eX =>
72 if(sFull='1')then
74 if(sFull='1')then
73 ect <= e0;
75 ect <= e0;
74 end if;
76 end if;
75
77
76 when e0 =>
78 when e0 =>
77 Valid <= '0';
79 Valid <= '0';
78 if(Load='1' and sEmpty='0')then
80 if(Load='1' and sEmpty='0')then
79 Read(FifoCpt-1) <= '0';
81 Read(FifoCpt-1) <= '0';
80 ect <= e2;
82 ect <= e2;
81 -- ect <= e1;
83 -- ect <= e1;
82 elsif(sEmpty='1')then
84 elsif(sEmpty='1')then
83 if(FifoCpt=6)then
85 if(FifoCpt=6)then
84 FifoCpt <= 1;
86 FifoCpt <= 1;
85 else
87 else
86 FifoCpt <= FifoCpt+1;
88 FifoCpt <= FifoCpt+1;
87 end if;
89 end if;
88 ect <= eX;
90 ect <= eX;
89 end if;
91 end if;
90
92
91 when e1 =>
93 when e1 =>
92 null;
94 null;
93 -- DataTmp <= sData;
95 -- DataTmp <= sData;
94 -- ect <= e2;
96 -- ect <= e2;
95
97
96 when e2 =>
98 when e2 =>
97 Read(FifoCpt-1) <= '1';
99 Read(FifoCpt-1) <= '1';
98 Data_re <= sData;
100 Data_re <= sData;
99 Data_im <= (others => '0');
101 Data_im <= (others => '0');
100 -- Data_re <= DataTmp;
102 -- Data_re <= DataTmp;
101 -- Data_im <= sData;
103 -- Data_im <= sData;
102 Valid <= '1';
104 Valid <= '1';
103 ect <= e0;
105 ect <= e0;
104
106
105
107
106 end case;
108 end case;
107 end if;
109 end if;
108 end process;
110 end process;
109
111
110 with FifoCpt select
112 with FifoCpt select
111 sFull <= Full(0) when 1,
113 sFull <= Full(0) when 1,
112 Full(1) when 2,
114 Full(1) when 2,
113 Full(2) when 3,
115 Full(2) when 3,
114 Full(3) when 4,
116 Full(3) when 4,
115 Full(4) when 5,
117 Full(4) when 5,
116 '1' when others;
118 '1' when others;
117
119
118 with FifoCpt select
120 with FifoCpt select
119 sEmpty <= Empty(0) when 1,
121 sEmpty <= Empty(0) when 1,
120 Empty(1) when 2,
122 Empty(1) when 2,
121 Empty(2) when 3,
123 Empty(2) when 3,
122 Empty(3) when 4,
124 Empty(3) when 4,
123 Empty(4) when 5,
125 Empty(4) when 5,
124 '1' when others;
126 '1' when others;
125
127
126 with FifoCpt select
128 with FifoCpt select
127 sData <= DATA(Data_sz-1 downto 0) when 1,
129 sData <= DATA(Data_sz-1 downto 0) when 1,
128 DATA((2*Data_sz)-1 downto Data_sz) when 2,
130 DATA((2*Data_sz)-1 downto Data_sz) when 2,
129 DATA((3*Data_sz)-1 downto (2*Data_sz)) when 3,
131 DATA((3*Data_sz)-1 downto (2*Data_sz)) when 3,
130 DATA((4*Data_sz)-1 downto (3*Data_sz)) when 4,
132 DATA((4*Data_sz)-1 downto (3*Data_sz)) when 4,
131 DATA((5*Data_sz)-1 downto (4*Data_sz)) when 5,
133 DATA((5*Data_sz)-1 downto (4*Data_sz)) when 5,
132 (others => '0') when others;
134 (others => '0') when others;
133
135
134 end architecture;
136 end architecture;
135
137
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Show file before | Show file after | Hide comments
@@ -1,206 +1,242
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 use lpp.lpp_memory.all;
29 use lpp.lpp_memory.all;
30 use work.fft_components.all;
30 use work.fft_components.all;
31
31
32 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
33
33
34 package lpp_fft is
34 package lpp_fft is
35
35
36 component APB_FFT is
36 component APB_FFT is
37 generic (
37 generic (
38 pindex : integer := 0;
38 pindex : integer := 0;
39 paddr : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
41 pirq : integer := 0;
42 abits : integer := 8;
42 abits : integer := 8;
43 Data_sz : integer := 16
43 Data_sz : integer := 16
44 );
44 );
45 port (
45 port (
46 clk : in std_logic;
46 clk : in std_logic;
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type;
48 apbi : in apb_slv_in_type;
49 apbo : out apb_slv_out_type
49 apbo : out apb_slv_out_type
50 );
50 );
51 end component;
51 end component;
52
52
53
53
54 component APB_FFT_half is
54 component APB_FFT_half is
55 generic (
55 generic (
56 pindex : integer := 0;
56 pindex : integer := 0;
57 paddr : integer := 0;
57 paddr : integer := 0;
58 pmask : integer := 16#fff#;
58 pmask : integer := 16#fff#;
59 pirq : integer := 0;
59 pirq : integer := 0;
60 abits : integer := 8;
60 abits : integer := 8;
61 Data_sz : integer := 16
61 Data_sz : integer := 16
62 );
62 );
63 port (
63 port (
64 clk : in std_logic; --! Horloge du composant
64 clk : in std_logic; --! Horloge du composant
65 rst : in std_logic; --! Reset general du composant
65 rst : in std_logic; --! Reset general du composant
66 Ren : in std_logic;
66 Ren : in std_logic;
67 ready : out std_logic;
67 ready : out std_logic;
68 valid : out std_logic;
68 valid : out std_logic;
69 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
69 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
70 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
70 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
71 OUTfill : out std_logic;
71 OUTfill : out std_logic;
72 OUTwrite : out std_logic;
72 OUTwrite : out std_logic;
73 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
73 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
74 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
74 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
75 );
75 );
76 end component;
76 end component;
77
77
78
78
79 component Flag_Extremum is
79 component Flag_Extremum is
80 port(
80 port(
81 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
81 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
82 load : in std_logic; --! Signal en provenance de CoreFFT
82 load : in std_logic; --! Signal en provenance de CoreFFT
83 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
83 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
84 fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
84 fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
85 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
85 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
86 );
86 );
87 end component;
87 end component;
88
88
89
89
90 component Linker_FFT is
90 component Linker_FFT is
91 generic(
91 generic(
92 Data_sz : integer range 1 to 32 := 16
92 Data_sz : integer range 1 to 32 := 16
93 );
93 );
94 port(
94 port(
95 clk : in std_logic;
95 clk : in std_logic;
96 rstn : in std_logic;
96 rstn : in std_logic;
97 Ready : in std_logic;
97 Ready : in std_logic;
98 Valid : in std_logic;
98 Valid : in std_logic;
99 Full : in std_logic_vector(4 downto 0);
99 Full : in std_logic_vector(4 downto 0);
100 Data_re : in std_logic_vector(Data_sz-1 downto 0);
100 Data_re : in std_logic_vector(Data_sz-1 downto 0);
101 Data_im : in std_logic_vector(Data_sz-1 downto 0);
101 Data_im : in std_logic_vector(Data_sz-1 downto 0);
102 Read : out std_logic;
102 Read : out std_logic;
103 Write : out std_logic_vector(4 downto 0);
103 Write : out std_logic_vector(4 downto 0);
104 ReUse : out std_logic_vector(4 downto 0);
104 ReUse : out std_logic_vector(4 downto 0);
105 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
105 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
106 );
106 );
107 end component;
107 end component;
108
108
109
109
110 component Driver_FFT is
110 component Driver_FFT is
111 generic(
111 generic(
112 Data_sz : integer range 1 to 32 := 16
112 Data_sz : integer range 1 to 32 := 16
113 );
113 );
114 port(
114 port(
115 clk : in std_logic;
115 clk : in std_logic;
116 rstn : in std_logic;
116 rstn : in std_logic;
117 Load : in std_logic;
117 Load : in std_logic;
118 Empty : in std_logic_vector(4 downto 0);
118 Empty : in std_logic_vector(4 downto 0);
119 Full : in std_logic_vector(4 downto 0);
119 Full : in std_logic_vector(4 downto 0);
120 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
120 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
121 Valid : out std_logic;
121 Valid : out std_logic;
122 Read : out std_logic_vector(4 downto 0);
122 Read : out std_logic_vector(4 downto 0);
123 Data_re : out std_logic_vector(Data_sz-1 downto 0);
123 Data_re : out std_logic_vector(Data_sz-1 downto 0);
124 Data_im : out std_logic_vector(Data_sz-1 downto 0)
124 Data_im : out std_logic_vector(Data_sz-1 downto 0)
125 );
125 );
126 end component;
126 end component;
127
127
128 component FFTamont is
129 generic(
130 Data_sz : integer range 1 to 32 := 16
131 );
132 port(
133 clk : in std_logic;
134 rstn : in std_logic;
135 Load : in std_logic;
136 Empty : in std_logic;
137 Full : in std_logic;
138 DATA : in std_logic_vector(Data_sz-1 downto 0);
139 Valid : out std_logic;
140 Read : out std_logic;
141 Data_re : out std_logic_vector(Data_sz-1 downto 0);
142 Data_im : out std_logic_vector(Data_sz-1 downto 0)
143 );
144 end component;
145
146 component FFTaval is
147 generic(
148 Data_sz : integer range 1 to 32 := 8
149 );
150 port(
151 clk : in std_logic;
152 rstn : in std_logic;
153 Ready : in std_logic;
154 Valid : in std_logic;
155 Full : in std_logic;
156 Data_re : in std_logic_vector(Data_sz-1 downto 0);
157 Data_im : in std_logic_vector(Data_sz-1 downto 0);
158 Read : out std_logic;
159 Write : out std_logic;
160 ReUse : out std_logic;
161 DATA : out std_logic_vector(Data_sz-1 downto 0)
162 );
163 end component;
128 --==============================================================|
164 --==============================================================|
129 --================== IP VHDL de la FFT actel ===================|
165 --================== IP VHDL de la FFT actel ===================|
130 --================ non partag� dans la VHD_Lib =================|
166 --================ non partag� dans la VHD_Lib =================|
131 --==============================================================|
167 --==============================================================|
132
168
133 component CoreFFT IS
169 component CoreFFT IS
134 GENERIC (
170 GENERIC (
135 LOGPTS : integer := gLOGPTS;
171 LOGPTS : integer := gLOGPTS;
136 LOGLOGPTS : integer := gLOGLOGPTS;
172 LOGLOGPTS : integer := gLOGLOGPTS;
137 WSIZE : integer := gWSIZE;
173 WSIZE : integer := gWSIZE;
138 TWIDTH : integer := gTWIDTH;
174 TWIDTH : integer := gTWIDTH;
139 DWIDTH : integer := gDWIDTH;
175 DWIDTH : integer := gDWIDTH;
140 TDWIDTH : integer := gTDWIDTH;
176 TDWIDTH : integer := gTDWIDTH;
141 RND_MODE : integer := gRND_MODE;
177 RND_MODE : integer := gRND_MODE;
142 SCALE_MODE : integer := gSCALE_MODE;
178 SCALE_MODE : integer := gSCALE_MODE;
143 PTS : integer := gPTS;
179 PTS : integer := gPTS;
144 HALFPTS : integer := gHALFPTS;
180 HALFPTS : integer := gHALFPTS;
145 inBuf_RWDLY : integer := gInBuf_RWDLY );
181 inBuf_RWDLY : integer := gInBuf_RWDLY );
146 PORT (
182 PORT (
147 clk,ifiStart,ifiNreset : IN std_logic;
183 clk,ifiStart,ifiNreset : IN std_logic;
148 ifiD_valid, ifiRead_y : IN std_logic;
184 ifiD_valid, ifiRead_y : IN std_logic;
149 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
185 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
150 ifoLoad, ifoPong : OUT std_logic;
186 ifoLoad, ifoPong : OUT std_logic;
151 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
187 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
152 ifoY_valid, ifoY_rdy : OUT std_logic);
188 ifoY_valid, ifoY_rdy : OUT std_logic);
153 END component;
189 END component;
154
190
155
191
156 component actar is
192 component actar is
157 port( DataA : in std_logic_vector(15 downto 0); DataB : in
193 port( DataA : in std_logic_vector(15 downto 0); DataB : in
158 std_logic_vector(15 downto 0); Mult : out
194 std_logic_vector(15 downto 0); Mult : out
159 std_logic_vector(31 downto 0);Clock : in std_logic) ;
195 std_logic_vector(31 downto 0);Clock : in std_logic) ;
160 end component;
196 end component;
161
197
162 component actram is
198 component actram is
163 port( DI : in std_logic_vector(31 downto 0); DO : out
199 port( DI : in std_logic_vector(31 downto 0); DO : out
164 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
200 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
165 WADDR : in std_logic_vector(6 downto 0); RADDR : in
201 WADDR : in std_logic_vector(6 downto 0); RADDR : in
166 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
202 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
167 std_logic) ;
203 std_logic) ;
168 end component;
204 end component;
169
205
170 component switch IS
206 component switch IS
171 GENERIC ( DWIDTH : integer := 32 );
207 GENERIC ( DWIDTH : integer := 32 );
172 PORT (
208 PORT (
173 clk, sel, validIn : IN std_logic;
209 clk, sel, validIn : IN std_logic;
174 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
210 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
175 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
211 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
176 validOut : OUT std_logic);
212 validOut : OUT std_logic);
177 END component;
213 END component;
178
214
179 component twid_rA IS
215 component twid_rA IS
180 GENERIC (LOGPTS : integer := 8;
216 GENERIC (LOGPTS : integer := 8;
181 LOGLOGPTS : integer := 3 );
217 LOGLOGPTS : integer := 3 );
182 PORT (clk : IN std_logic;
218 PORT (clk : IN std_logic;
183 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
219 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
184 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
220 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
185 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
221 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
186 END component;
222 END component;
187
223
188 component counter IS
224 component counter IS
189 GENERIC (
225 GENERIC (
190 WIDTH : integer := 7;
226 WIDTH : integer := 7;
191 TERMCOUNT : integer := 127 );
227 TERMCOUNT : integer := 127 );
192 PORT (
228 PORT (
193 clk, nGrst, rst, cntEn : IN std_logic;
229 clk, nGrst, rst, cntEn : IN std_logic;
194 tc : OUT std_logic;
230 tc : OUT std_logic;
195 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
231 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
196 END component;
232 END component;
197
233
198
234
199 component twiddle IS
235 component twiddle IS
200 PORT (
236 PORT (
201 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
237 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
202 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
238 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
203 END component;
239 END component;
204
240
205
241
206 end; No newline at end of file
242 end;
Show file before | Show file after | Hide comments
@@ -1,105 +1,105
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25
25
26 entity GetResult is
26 entity GetResult is
27 generic(
27 generic(
28 Result_SZ : integer := 32);
28 Result_SZ : integer := 32);
29 port(
29 port(
30 clk : in std_logic;
30 clk : in std_logic;
31 raz : in std_logic;
31 raz : in std_logic;
32 Valid : in std_logic;
32 Valid : in std_logic;
33 Conjugate : in std_logic;
33 Conjugate : in std_logic;
34 Res : in std_logic_vector(Result_SZ-1 downto 0);
34 Res : in std_logic_vector(Result_SZ-1 downto 0);
35 Full : in std_logic;
35 -- Full : in std_logic;
36 WriteFIFO : out std_logic;
36 WriteFIFO : out std_logic;
37 Received : out std_logic;
37 Received : out std_logic;
38 Result : out std_logic_vector(Result_SZ-1 downto 0)
38 Result : out std_logic_vector(Result_SZ-1 downto 0)
39 );
39 );
40 end GetResult;
40 end GetResult;
41
41
42
42
43 architecture ar_GetResult of GetResult is
43 architecture ar_GetResult of GetResult is
44
44
45 signal Valid_reg : std_logic;
45 signal Valid_reg : std_logic;
46
46
47 type state is (st0,st1,stX,stY);
47 type state is (st0,st1,stX,stY);
48 signal ect : state;
48 signal ect : state;
49
49
50 begin
50 begin
51 process(clk,raz)
51 process(clk,raz)
52 begin
52 begin
53
53
54 if(raz='0')then
54 if(raz='0')then
55 Received <= '0';
55 Received <= '0';
56 Valid_reg <= '0';
56 Valid_reg <= '0';
57 WriteFIFO <= '0';
57 WriteFIFO <= '0';
58 ect <= st0;
58 ect <= st0;
59 Result <= (others => '0');
59 Result <= (others => '0');
60
60
61 elsif(clk'event and clk='1')then
61 elsif(clk'event and clk='1')then
62 Valid_reg <= Valid;
62 Valid_reg <= Valid;
63
63
64 case ect is
64 case ect is
65 when st0 =>
65 when st0 =>
66 if(Full='0' and Valid='1')then
66 if(Valid='1')then--if(Full='0' and Valid='1')then
67 Result <= Res;
67 Result <= Res;
68 WriteFIFO <= '1';
68 WriteFIFO <= '1';
69 Received <= '1';
69 Received <= '1';
70 ect <= stX;
70 ect <= stX;
71 end if;
71 end if;
72
72
73 when stX =>
73 when stX =>
74 WriteFIFO <= '0';
74 WriteFIFO <= '0';
75 if(Conjugate='1')then
75 if(Conjugate='1')then
76 Received <= '0';
76 Received <= '0';
77 end if;
77 end if;
78 if(Valid_reg='1' and Valid='0')then
78 if(Valid_reg='1' and Valid='0')then
79 if(Conjugate='1')then
79 if(Conjugate='1')then
80 ect <= st0;
80 ect <= st0;
81 else
81 else
82 ect <= st1;
82 ect <= st1;
83 end if;
83 end if;
84 end if;
84 end if;
85
85
86 when st1 =>
86 when st1 =>
87 if(Full='0' and Valid='1')then
87 if(Valid='1')then--if(Full='0' and Valid='1')then
88 Result <= Res;
88 Result <= Res;
89 WriteFIFO <= '1';
89 WriteFIFO <= '1';
90 Received <= '0';
90 Received <= '0';
91 ect <= stY;
91 ect <= stY;
92 end if;
92 end if;
93
93
94 when stY =>
94 when stY =>
95 WriteFIFO <= '0';
95 WriteFIFO <= '0';
96 if(Valid_reg='1' and Valid='0')then
96 if(Valid_reg='1' and Valid='0')then
97 ect <= st0;
97 ect <= st0;
98 end if;
98 end if;
99
99
100 end case;
100 end case;
101 end if;
101 end if;
102 end process;
102 end process;
103
103
104 end ar_GetResult;
104 end ar_GetResult;
105
105
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@@ -1,84 +1,84
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
25 use lpp.lpp_matrix.all;
26
26
27 entity SpectralMatrix is
27 entity SpectralMatrix is
28 generic(
28 generic(
29 Input_SZ : integer := 16;
29 Input_SZ : integer := 16;
30 Result_SZ : integer := 32);
30 Result_SZ : integer := 32);
31 port(
31 port(
32 clk : in std_logic;
32 clk : in std_logic;
33 reset : in std_logic;
33 reset : in std_logic;
34 Start : in std_logic;
34 Start : in std_logic;
35 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
35 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
36 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
36 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
37 Statu : in std_logic_vector(3 downto 0);
37 Statu : in std_logic_vector(3 downto 0);
38 FullFIFO : in std_logic;
38 -- FullFIFO : in std_logic;
39 ReadFIFO : out std_logic_vector(1 downto 0);
39 ReadFIFO : out std_logic_vector(1 downto 0);
40 WriteFIFO : out std_logic;
40 WriteFIFO : out std_logic;
41 Result : out std_logic_vector(Result_SZ-1 downto 0)
41 Result : out std_logic_vector(Result_SZ-1 downto 0)
42 );
42 );
43 end SpectralMatrix;
43 end SpectralMatrix;
44
44
45
45
46 architecture ar_SpectralMatrix of SpectralMatrix is
46 architecture ar_SpectralMatrix of SpectralMatrix is
47
47
48 signal RaZ : std_logic;
48 signal RaZ : std_logic;
49 signal Read_int : std_logic;
49 signal Read_int : std_logic;
50 signal Take_int : std_logic;
50 signal Take_int : std_logic;
51 signal Received_int : std_logic;
51 signal Received_int : std_logic;
52 signal Valid_int : std_logic;
52 signal Valid_int : std_logic;
53 signal Conjugate_int : std_logic;
53 signal Conjugate_int : std_logic;
54
54
55 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
55 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
56
56
57
57
58 begin
58 begin
59
59
60 RaZ <= reset and Start;
60 RaZ <= reset and Start;
61
61
62 IN1 : DriveInputs
62 IN1 : DriveInputs
63 port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO);
63 port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO);
64
64
65
65
66 CALC0 : Matrix
66 CALC0 : Matrix
67 generic map(Input_SZ)
67 generic map(Input_SZ)
68 port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
68 port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
69
69
70
70
71 RES0 : GetResult
71 RES0 : GetResult
72 generic map(Result_SZ)
72 generic map(Result_SZ)
73 port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,FullFIFO,WriteFIFO,Received_int,Result);
73 port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO
74
74
75
75
76 With Statu select
76 With Statu select
77 Conjugate_int <= '1' when "0001",
77 Conjugate_int <= '1' when "0001",
78 '1' when "0011",
78 '1' when "0011",
79 '1' when "0110",
79 '1' when "0110",
80 '1' when "1010",
80 '1' when "1010",
81 '1' when "1111",
81 '1' when "1111",
82 '0' when others;
82 '0' when others;
83
83
84 end ar_SpectralMatrix; No newline at end of file
84 end ar_SpectralMatrix;
Show file before | Show file after | Hide comments
@@ -1,241 +1,259
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_matrix is
32 package lpp_matrix is
33
33
34 component APB_Matrix is
34 component APB_Matrix is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 Input_SZ : integer := 16;
41 Input_SZ : integer := 16;
42 Result_SZ : integer := 32);
42 Result_SZ : integer := 32);
43 port (
43 port (
44 clk : in std_logic;
44 clk : in std_logic;
45 rst : in std_logic;
45 rst : in std_logic;
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
51 FullFIFO : in std_logic;
51 FullFIFO : in std_logic;
52 WriteFIFO : out std_logic;
52 WriteFIFO : out std_logic;
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 );
56 );
57 end component;
57 end component;
58
58
59 component Top_MatrixSpec is
59 component Top_MatrixSpec is
60 generic(
60 generic(
61 Input_SZ : integer := 16;
61 Input_SZ : integer := 16;
62 Result_SZ : integer := 32);
62 Result_SZ : integer := 32);
63 port(
63 port(
64 clk : in std_logic;
64 clk : in std_logic;
65 reset : in std_logic;
65 reset : in std_logic;
66 Statu : in std_logic_vector(3 downto 0);
66 Statu : in std_logic_vector(3 downto 0);
67 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
67 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
68 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
68 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
69 Full : in std_logic_vector(1 downto 0);
69 Full : in std_logic_vector(1 downto 0);
70 Empty : in std_logic_vector(1 downto 0);
70 Empty : in std_logic_vector(1 downto 0);
71 ReadFIFO : out std_logic_vector(1 downto 0);
71 ReadFIFO : out std_logic_vector(1 downto 0);
72 FullFIFO : in std_logic;
72 FullFIFO : in std_logic;
73 WriteFIFO : out std_logic;
73 WriteFIFO : out std_logic;
74 Result : out std_logic_vector(Result_SZ-1 downto 0)
74 Result : out std_logic_vector(Result_SZ-1 downto 0)
75 );
75 );
76 end component;
76 end component;
77
77
78 component SpectralMatrix is
78 component SpectralMatrix is
79 generic(
79 generic(
80 Input_SZ : integer := 16;
80 Input_SZ : integer := 16;
81 Result_SZ : integer := 32);
81 Result_SZ : integer := 32);
82 port(
82 port(
83 clk : in std_logic;
83 clk : in std_logic;
84 reset : in std_logic;
84 reset : in std_logic;
85 Start : in std_logic;
85 Start : in std_logic;
86 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
86 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
87 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
87 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
88 Statu : in std_logic_vector(3 downto 0);
88 Statu : in std_logic_vector(3 downto 0);
89 FullFIFO : in std_logic;
89 -- FullFIFO : in std_logic;
90 ReadFIFO : out std_logic_vector(1 downto 0);
90 ReadFIFO : out std_logic_vector(1 downto 0);
91 WriteFIFO : out std_logic;
91 WriteFIFO : out std_logic;
92 Result : out std_logic_vector(Result_SZ-1 downto 0)
92 Result : out std_logic_vector(Result_SZ-1 downto 0)
93 );
93 );
94 end component;
94 end component;
95
95
96
96
97 component Matrix is
97 component Matrix is
98 generic(
98 generic(
99 Input_SZ : integer := 16);
99 Input_SZ : integer := 16);
100 port(
100 port(
101 clk : in std_logic;
101 clk : in std_logic;
102 raz : in std_logic;
102 raz : in std_logic;
103 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
103 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
104 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
104 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
105 Take : in std_logic;
105 Take : in std_logic;
106 Received : in std_logic;
106 Received : in std_logic;
107 Conjugate : in std_logic;
107 Conjugate : in std_logic;
108 Valid : out std_logic;
108 Valid : out std_logic;
109 Read : out std_logic;
109 Read : out std_logic;
110 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
110 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
111 );
111 );
112 end component;
112 end component;
113
113
114 component GetResult is
114 component GetResult is
115 generic(
115 generic(
116 Result_SZ : integer := 32);
116 Result_SZ : integer := 32);
117 port(
117 port(
118 clk : in std_logic;
118 clk : in std_logic;
119 raz : in std_logic;
119 raz : in std_logic;
120 Valid : in std_logic;
120 Valid : in std_logic;
121 Conjugate : in std_logic;
121 Conjugate : in std_logic;
122 Res : in std_logic_vector(Result_SZ-1 downto 0);
122 Res : in std_logic_vector(Result_SZ-1 downto 0);
123 Full : in std_logic;
123 -- Full : in std_logic;
124 WriteFIFO : out std_logic;
124 WriteFIFO : out std_logic;
125 Received : out std_logic;
125 Received : out std_logic;
126 Result : out std_logic_vector(Result_SZ-1 downto 0)
126 Result : out std_logic_vector(Result_SZ-1 downto 0)
127 );
127 );
128 end component;
128 end component;
129
129
130
130
131 component TopMatrix_PDR is
131 component TopMatrix_PDR is
132 generic(
132 generic(
133 Input_SZ : integer := 16;
133 Input_SZ : integer := 16;
134 Result_SZ : integer := 32);
134 Result_SZ : integer := 32);
135 port(
135 port(
136 clk : in std_logic;
136 clk : in std_logic;
137 reset : in std_logic;
137 reset : in std_logic;
138 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
138 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
139 FULLin : in std_logic_vector(4 downto 0);
139 FULLin : in std_logic_vector(4 downto 0);
140 READin : in std_logic_vector(1 downto 0);
140 READin : in std_logic_vector(1 downto 0);
141 WRITEin : in std_logic;
141 WRITEin : in std_logic;
142 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
142 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
143 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
143 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
144 Start : out std_logic;
144 Start : out std_logic;
145 Read : out std_logic_vector(4 downto 0);
145 Read : out std_logic_vector(4 downto 0);
146 Statu : out std_logic_vector(3 downto 0)
146 Statu : out std_logic_vector(3 downto 0)
147 );
147 );
148 end component;
148 end component;
149
149
150
150
151 component Dispatch is
152 generic(
153 Data_SZ : integer := 32);
154 port(
155 clk : in std_logic;
156 reset : in std_logic;
157 Acq : in std_logic;
158 Data : in std_logic_vector(Data_SZ-1 downto 0);
159 Write : in std_logic;
160 Full : in std_logic_vector(1 downto 0);
161 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
162 FifoWrite : out std_logic_vector(1 downto 0);
163 Pong : out std_logic;
164 Error : out std_logic
165 );
166 end component;
167
168
151 component DriveInputs is
169 component DriveInputs is
152 port(
170 port(
153 clk : in std_logic;
171 clk : in std_logic;
154 raz : in std_logic;
172 raz : in std_logic;
155 Read : in std_logic;
173 Read : in std_logic;
156 Conjugate : in std_logic;
174 Conjugate : in std_logic;
157 Take : out std_logic;
175 Take : out std_logic;
158 ReadFIFO : out std_logic_vector(1 downto 0)
176 ReadFIFO : out std_logic_vector(1 downto 0)
159 );
177 );
160 end component;
178 end component;
161
179
162 component Starter is
180 component Starter is
163 port(
181 port(
164 clk : in std_logic;
182 clk : in std_logic;
165 raz : in std_logic;
183 raz : in std_logic;
166 Full : in std_logic_vector(1 downto 0);
184 Full : in std_logic_vector(1 downto 0);
167 Empty : in std_logic_vector(1 downto 0);
185 Empty : in std_logic_vector(1 downto 0);
168 Statu : in std_logic_vector(3 downto 0);
186 Statu : in std_logic_vector(3 downto 0);
169 Write : in std_logic;
187 Write : in std_logic;
170 Start : out std_logic
188 Start : out std_logic
171 );
189 );
172 end component;
190 end component;
173
191
174 component ALU_Driver is
192 component ALU_Driver is
175 generic(
193 generic(
176 Input_SZ_1 : integer := 16;
194 Input_SZ_1 : integer := 16;
177 Input_SZ_2 : integer := 16);
195 Input_SZ_2 : integer := 16);
178 port(
196 port(
179 clk : in std_logic;
197 clk : in std_logic;
180 reset : in std_logic;
198 reset : in std_logic;
181 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
199 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
182 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
200 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
183 Take : in std_logic;
201 Take : in std_logic;
184 Received : in std_logic;
202 Received : in std_logic;
185 Conjugate : in std_logic;
203 Conjugate : in std_logic;
186 Valid : out std_logic;
204 Valid : out std_logic;
187 Read : out std_logic;
205 Read : out std_logic;
188 CTRL : out std_logic_vector(4 downto 0);
206 CTRL : out std_logic_vector(4 downto 0);
189 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
207 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
190 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
208 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
191 );
209 );
192 end component;
210 end component;
193
211
194
212
195 component ALU_v2 is
213 component ALU_v2 is
196 generic(
214 generic(
197 Arith_en : integer := 1;
215 Arith_en : integer := 1;
198 Logic_en : integer := 1;
216 Logic_en : integer := 1;
199 Input_SZ_1 : integer := 16;
217 Input_SZ_1 : integer := 16;
200 Input_SZ_2 : integer := 9);
218 Input_SZ_2 : integer := 9);
201 port(
219 port(
202 clk : in std_logic;
220 clk : in std_logic;
203 reset : in std_logic;
221 reset : in std_logic;
204 ctrl : in std_logic_vector(4 downto 0);
222 ctrl : in std_logic_vector(4 downto 0);
205 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
223 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
206 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
224 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
207 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
225 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
208 );
226 );
209 end component;
227 end component;
210
228
211
229
212 component MAC_v2 is
230 component MAC_v2 is
213 generic(
231 generic(
214 Input_SZ_A : integer := 8;
232 Input_SZ_A : integer := 8;
215 Input_SZ_B : integer := 8);
233 Input_SZ_B : integer := 8);
216 port(
234 port(
217 clk : in std_logic;
235 clk : in std_logic;
218 reset : in std_logic;
236 reset : in std_logic;
219 clr_MAC : in std_logic;
237 clr_MAC : in std_logic;
220 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
238 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
221 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
239 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
222 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
240 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
223 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
241 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
224 );
242 );
225 end component;
243 end component;
226
244
227
245
228 component TwoComplementer is
246 component TwoComplementer is
229 generic(
247 generic(
230 Input_SZ : integer := 16);
248 Input_SZ : integer := 16);
231 port(
249 port(
232 clk : in std_logic;
250 clk : in std_logic;
233 reset : in std_logic;
251 reset : in std_logic;
234 clr : in std_logic;
252 clr : in std_logic;
235 TwoComp : in std_logic;
253 TwoComp : in std_logic;
236 OP : in std_logic_vector(Input_SZ-1 downto 0);
254 OP : in std_logic_vector(Input_SZ-1 downto 0);
237 RES : out std_logic_vector(Input_SZ-1 downto 0)
255 RES : out std_logic_vector(Input_SZ-1 downto 0)
238 );
256 );
239 end component;
257 end component;
240
258
241 end; No newline at end of file
259 end;
Show file before | Show file after | Hide comments
@@ -1,290 +1,263
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 -- APB_FIFO.vhd
22 -- APB_FIFO.vhd
23 library ieee;
23 library ieee;
24 use ieee.std_logic_1164.all;
24 use ieee.std_logic_1164.all;
25 use IEEE.numeric_std.all;
25 use IEEE.numeric_std.all;
26 library techmap;
26 library techmap;
27 use techmap.gencomp.all;
27 use techmap.gencomp.all;
28 library grlib;
28 library grlib;
29 use grlib.amba.all;
29 use grlib.amba.all;
30 use grlib.stdlib.all;
30 use grlib.stdlib.all;
31 use grlib.devices.all;
31 use grlib.devices.all;
32 library lpp;
32 library lpp;
33 use lpp.lpp_amba.all;
33 use lpp.lpp_amba.all;
34 use lpp.apb_devices_list.all;
34 use lpp.apb_devices_list.all;
35 use lpp.lpp_memory.all;
35 use lpp.lpp_memory.all;
36
36
37
37
38 entity APB_FIFO is
38 entity APB_FIFO is
39 generic (
39 generic (
40 tech : integer := apa3;
40 tech : integer := apa3;
41 pindex : integer := 0;
41 pindex : integer := 0;
42 paddr : integer := 0;
42 paddr : integer := 0;
43 pmask : integer := 16#fff#;
43 pmask : integer := 16#fff#;
44 pirq : integer := 0;
44 pirq : integer := 0;
45 abits : integer := 8;
45 abits : integer := 8;
46 FifoCnt : integer := 2;
46 FifoCnt : integer := 2;
47 Data_sz : integer := 16;
47 Data_sz : integer := 16;
48 Addr_sz : integer := 9;
48 Addr_sz : integer := 9;
49 Enable_ReUse : std_logic := '0';
49 Enable_ReUse : std_logic := '0';
50 R : integer := 1;
50 R : integer := 1;
51 W : integer := 1
51 W : integer := 1
52 );
52 );
53 port (
53 port (
54 clk : in std_logic; --! Horloge du composant
54 clk : in std_logic; --! Horloge du composant
55 rst : in std_logic; --! Reset general du composant
55 rst : in std_logic; --! Reset general du composant
56 rclk : in std_logic;
56 rclk : in std_logic;
57 wclk : in std_logic;
57 wclk : in std_logic;
58 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
58 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
59 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
59 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
60 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
60 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
61 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
61 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
62 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
62 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
63 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
63 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
64 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
64 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
65 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
65 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
66 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
66 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
67 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
67 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
68 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
68 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
69 );
69 );
70 end entity;
70 end entity;
71
71
72 architecture ar_APB_FIFO of APB_FIFO is
72 architecture ar_APB_FIFO of APB_FIFO is
73
73
74 constant REVISION : integer := 1;
74 constant REVISION : integer := 1;
75
75
76 constant pconfig : apb_config_type := (
76 constant pconfig : apb_config_type := (
77 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
77 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
78 1 => apb_iobar(paddr, pmask));
78 1 => apb_iobar(paddr, pmask));
79
79
80 type FIFO_ctrlr_Reg is record
80 type FIFO_ctrlr_Reg is record
81 FIFO_Ctrl : std_logic_vector(31 downto 0);
81 FIFO_Ctrl : std_logic_vector(31 downto 0);
82 FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
82 FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
83 FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
83 FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
84 end record;
84 end record;
85
85
86 type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
86 type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
87 type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0);
87 type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0);
88 type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0);
88 type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0);
89
89
90 signal Rec : FIFO_ctrlr_Reg_Vec;
90 signal Rec : FIFO_ctrlr_Reg_Vec;
91 signal PRdata : std_logic_vector(31 downto 0);
91 signal PRdata : std_logic_vector(31 downto 0);
92 signal FIFO_ID : std_logic_vector(31 downto 0);
92 signal FIFO_ID : std_logic_vector(31 downto 0);
93 signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
93 signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
94 signal sFull : std_logic_vector(FifoCnt-1 downto 0);
94 signal sFull : std_logic_vector(FifoCnt-1 downto 0);
95 signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
95 signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
96 signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
96 signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
97 signal sWen : std_logic_vector(FifoCnt-1 downto 0);
97 signal sWen : std_logic_vector(FifoCnt-1 downto 0);
98 signal sRen : std_logic_vector(FifoCnt-1 downto 0);
98 signal sRen : std_logic_vector(FifoCnt-1 downto 0);
99 signal sRclk : std_logic;
99 signal sRclk : std_logic;
100 signal sWclk : std_logic;
100 signal sWclk : std_logic;
101 signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
101 signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
102 signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
102 signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
103 signal sRDATA : fifodatabus;
103 signal sRDATA : fifodatabus;
104 signal sWDATA : fifodatabus;
104 signal sWDATA : fifodatabus;
105 signal sWADDR : fifoaddressbus;
105 signal sWADDR : fifoaddressbus;
106 signal sRADDR : fifoaddressbus;
106 signal sRADDR : fifoaddressbus;
107 signal sReUse : std_logic_vector(FifoCnt-1 downto 0); --05/06/12
107 signal sReUse : std_logic_vector(FifoCnt-1 downto 0);
108 signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0); --05/06/12
108 signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0);
109
110 signal regDataValid : std_logic_vector(FifoCnt-1 downto 0);
111 signal regData : fifodatabus;
112 signal regREN : std_logic_vector(FifoCnt-1 downto 0);
109
113
110 type state_t is (idle,Read);
114 type state_t is (idle,Read);
111 signal fiforeadfsmst : state_t;
115 signal fiforeadfsmst : state_t;
112
116
113 begin
117 begin
114
118
115 FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
119 FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
116 FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
120 FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
117 FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
121 FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
118
122
119
123
120 Write : if W /= 0 generate
124 Writeint : if W /= 0 generate
121 FIFO_ID(4) <= '1';
125 FIFO_ID(4) <= '1';
122 sWen <= sWen_APB;
126 sWen <= sWen_APB;
123 sReUse <= sReUse_APB;
127 sReUse <= sReUse_APB;
124 sWclk <= clk;
128 sWclk <= clk;
125 Wrapb: for i in 0 to FifoCnt-1 generate
129 Wrapb: for i in 0 to FifoCnt-1 generate
126 sWDATA(i) <= Rec(i).FIFO_Wdata;
130 sWDATA(i) <= Rec(i).FIFO_Wdata;
127 end generate;
131 end generate;
128 end generate;
132 end generate;
129
133
130 Writeext : if W = 0 generate
134 Writeext : if W = 0 generate
131 FIFO_ID(4) <= '0';
135 FIFO_ID(4) <= '0';
132 sWen <= WEN;
136 sWen <= WEN;
133 sReUse <= ReUse;
137 sReUse <= ReUse;
134 sWclk <= Wclk;
138 sWclk <= Wclk;
135 Wrext: for i in 0 to FifoCnt-1 generate
139 Wrext: for i in 0 to FifoCnt-1 generate
136 sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
140 sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
137 end generate;
141 end generate;
138 end generate;
142 end generate;
139
143
140 Read : if R /= 0 generate
144 Readint : if R /= 0 generate
141 FIFO_ID(5) <= '1';
145 FIFO_ID(5) <= '1';
142 sRen <= sRen_APB;
146 sRen <= sRen_APB;
143 srclk <= clk;
147 srclk <= clk;
144 Rdapb: for i in 0 to FifoCnt-1 generate
148 Rdapb: for i in 0 to FifoCnt-1 generate
145 Rec(i).FIFO_Rdata <= sRDATA(i);
149 Rec(i).FIFO_Rdata <= sRDATA(i);
146 end generate;
150 end generate;
147 end generate;
151 end generate;
148
152
149 Readext : if R = 0 generate
153 Readext : if R = 0 generate
150 FIFO_ID(5) <= '0';
154 FIFO_ID(5) <= '0';
151 sRen <= REN;
155 sRen <= REN;
152 srclk <= rclk;
156 srclk <= rclk;
153 Drext: for i in 0 to FifoCnt-1 generate
157 Drext: for i in 0 to FifoCnt-1 generate
154 RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i);
158 RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i);
155 end generate;
159 end generate;
156 end generate;
160 end generate;
157
161
158 ctrlregs: for i in 0 to FifoCnt-1 generate
162 ctrlregs: for i in 0 to FifoCnt-1 generate
159 RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
163 RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
160 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
164 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
161 Rec(i).FIFO_Ctrl(16) <= sFull(i);
165 Rec(i).FIFO_Ctrl(16) <= sFull(i);
162 --Rec(i).FIFO_Ctrl(17) <= Rec(i).FIFO_Ctrl(1); --27/01/12
166 sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1);
163 sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12
167 Rec(i).FIFO_Ctrl(3 downto 2) <= "00";
164 Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; --27/01/12
168 Rec(i).FIFO_Ctrl(19 downto 17) <= "000";
165 Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; --27/01/12
166 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
169 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
167 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i); ---|free|Waddrs|Full||free|Raddrs|empty|
170 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);
168 end generate; -- 31 17 16 15 1 0
171 end generate;
169
172
170 Empty <= sEmpty;
173 Empty <= sEmpty;
171 Full <= sFull;
174 Full <= sFull;
172
175
173
174 fifos: for i in 0 to FifoCnt-1 generate
176 fifos: for i in 0 to FifoCnt-1 generate
175 FIFO0 : lpp_fifo
177 FIFO0 : lpp_fifo
176 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
178 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
177 port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
179 port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
178 end generate;
180 end generate;
179
181
180 process(rst,clk)
182 process(rst,clk)
181 begin
183 begin
182 if(rst='0')then
184 if(rst='0')then
183 rstloop1: for i in 0 to FifoCnt-1 loop
185 rstloop1: for i in 0 to FifoCnt-1 loop
184 Rec(i).FIFO_Wdata <= (others => '0');
186 Rec(i).FIFO_Wdata <= (others => '0');
185 Rec(i).FIFO_Ctrl(1) <= '0'; --27/01/12
187 Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse
186 --Rec(i).FIFO_Ctrl(17) <= '0';
187 sWen_APB(i) <= '1';
188 sWen_APB(i) <= '1';
188 end loop;
189 end loop;
189 elsif(clk'event and clk='1')then
190 elsif(clk'event and clk='1')then
191
190 --APB Write OP
192 --APB Write OP
191 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
193 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
192 writelp: for i in 0 to FifoCnt-1 loop
194 writelp: for i in 0 to FifoCnt-1 loop
193 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
195 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
194 Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
196 Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
195 --Rec(i).FIFO_Ctrl(17) <= apbi.pwdata(17);
196 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
197 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
197 Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
198 Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
198 sWen_APB(i) <= '0';
199 sWen_APB(i) <= '0';
199 end if;
200 end if;
200 end loop;
201 end loop;
201 else
202 else
202 sWen_APB <= (others =>'1');
203 sWen_APB <= (others =>'1');
203 end if;
204 end if;
205
204 --APB Read OP
206 --APB Read OP
205 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
207 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
206 if(apbi.paddr(abits-1 downto 2)="000000") then
208 if(apbi.paddr(abits-1 downto 2)="000000") then
207 PRdata <= FIFO_ID;
209 PRdata <= FIFO_ID;
208 else
210 else
209 readlp: for i in 0 to FifoCnt-1 loop
211 readlp: for i in 0 to FifoCnt-1 loop
210 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
212 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
211 PRdata <= Rec(i).FIFO_Ctrl;
213 PRdata <= Rec(i).FIFO_Ctrl;
212 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
214 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
213 PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
215 PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
214 end if;
216 end if;
215 end loop;
217 end loop;
216 end if;
218 end if;
217 end if;
219 end if;
218 end if;
220 end if;
221
219 apbo.pconfig <= pconfig;
222 apbo.pconfig <= pconfig;
223
220 end process;
224 end process;
221 apbo.prdata <= PRdata when apbi.penable = '1';
225 apbo.prdata <= PRdata when apbi.penable = '1';
222
226
223
224
225 process(rst,clk)
227 process(rst,clk)
226 begin
228 begin
227 if(rst='0')then
229 if(rst='0')then
228 fiforeadfsmst <= idle;
230 fiforeadfsmst <= idle;
229 rstloop: for i in 0 to FifoCnt-1 loop
231 rstloop: for i in 0 to FifoCnt-1 loop
230 sRen_APB(i) <= '1';
232 sRen_APB(i) <= '1';
231 autoloaded(i) <= '1';
233 autoloaded(i) <= '1';
232 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
234 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
233 end loop;
235 end loop;
234 elsif clk'event and clk = '1' then
236 elsif clk'event and clk = '1' then
235 sEmpty_d <= sEmpty;
237 sEmpty_d <= sEmpty;
236 case fiforeadfsmst is
238 case fiforeadfsmst is
237 when idle =>
239 when idle =>
238 idlelp: for i in 0 to FifoCnt-1 loop
240 idlelp: for i in 0 to FifoCnt-1 loop
239 if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
241 if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
240 if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
242 if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
241 autoloaded(i) <= '0';
243 autoloaded(i) <= '0';
242 else
244 else
243 autoloaded(i) <= '1';
245 autoloaded(i) <= '1';
244 end if;
246 end if;
245 sRen_APB(i) <= '0';
247 sRen_APB(i) <= '0';
246 fiforeadfsmst <= read;
248 fiforeadfsmst <= read;
247 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
249 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
248 else
250 else
249 sRen_APB(i) <= '1';
251 sRen_APB(i) <= '1';
250 end if;
252 end if;
251 end loop;
253 end loop;
252 when read =>
254 when read =>
253 sRen_APB <= (others => '1');
255 sRen_APB <= (others => '1');
254 fiforeadfsmst <= idle;
256 fiforeadfsmst <= idle;
255 when others =>
257 when others =>
256 fiforeadfsmst <= idle;
258 fiforeadfsmst <= idle;
257 end case;
259 end case;
258 end if;
260 end if;
259 end process;
261 end process;
260
261
262 end ar_APB_FIFO;
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275
263 end ar_APB_FIFO; No newline at end of file
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library lpp;
25 library lpp;
26 use lpp.lpp_memory.all;
26 use lpp.lpp_memory.all;
27 use lpp.iir_filter.all;
27 library techmap;
28 library techmap;
28 use techmap.gencomp.all;
29 use techmap.gencomp.all;
29
30
30 entity lpp_fifo is
31 entity lpp_fifo is
31 generic(
32 generic(
32 tech : integer := 0;
33 tech : integer := 0;
33 Enable_ReUse : std_logic := '0';
34 Enable_ReUse : std_logic := '0';
34 DataSz : integer range 1 to 32 := 8;
35 DataSz : integer range 1 to 32 := 8;
35 abits : integer range 2 to 12 := 8
36 abits : integer range 2 to 12 := 8
36 );
37 );
37 port(
38 port(
38 rstn : in std_logic;
39 rstn : in std_logic;
39 ReUse : in std_logic; --27/01/12
40 ReUse : in std_logic;
40 rclk : in std_logic;
41 rclk : in std_logic;
41 ren : in std_logic;
42 ren : in std_logic;
42 rdata : out std_logic_vector(DataSz-1 downto 0);
43 rdata : out std_logic_vector(DataSz-1 downto 0);
43 empty : out std_logic;
44 empty : out std_logic;
44 raddr : out std_logic_vector(abits-1 downto 0);
45 raddr : out std_logic_vector(abits-1 downto 0);
45 wclk : in std_logic;
46 wclk : in std_logic;
46 wen : in std_logic;
47 wen : in std_logic;
47 wdata : in std_logic_vector(DataSz-1 downto 0);
48 wdata : in std_logic_vector(DataSz-1 downto 0);
48 full : out std_logic;
49 full : out std_logic;
49 waddr : out std_logic_vector(abits-1 downto 0)
50 waddr : out std_logic_vector(abits-1 downto 0)
50 );
51 );
51 end entity;
52 end entity;
52
53
53
54
54 architecture ar_lpp_fifo of lpp_fifo is
55 architecture ar_lpp_fifo of lpp_fifo is
55
56
56 signal sFull : std_logic:='0';
57 signal sFull : std_logic;
57 signal sEmpty : std_logic:='1';
58 signal sFull_s : std_logic;
58 signal sREN : std_logic:='0';
59 signal sEmpty_s : std_logic;
59 signal sWEN : std_logic:='0';
60
61 signal sEmpty : std_logic;
62 signal sREN : std_logic;
63 signal sWEN : std_logic;
64 signal sRE : std_logic;
65 signal sWE : std_logic;
60
66
61 signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
67 signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
62 signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
68 signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
63 signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
69 signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
64 signal Raddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
70 signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
65
71
66 begin
72 begin
67
73
74 --==================================================================================
75 -- /!\ syncram_2p Write et Read actif a l'�tat haut /!\
76 -- A l'inverse de RAM_CEL !!!
77 --==================================================================================
68 SRAM : syncram_2p
78 SRAM : syncram_2p
69 generic map(tech,abits,DataSz)
79 generic map(tech,abits,DataSz)
70 port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata);
80 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
71
81 --==================================================================================
72 --RAM0: entity work.RAM_CEL
82 --RAM0: entity work.RAM_CEL
73 -- generic map(abits, DataSz)
83 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
74 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn);
84 --==================================================================================
75
76
85
77 --=============================
86 --=============================
78 -- Read section
87 -- Read section
79 --=============================
88 --=============================
80 sREN <= not REN and not sempty;
89 sREN <= REN or sEmpty;
90 sRE <= not sREN;
91
92 sEmpty_s <= '0' when ReUse = '1' and Enable_ReUse='1' else
93 '1' when sEmpty = '1' and Wen = '1' else
94 '1' when sEmpty = '0' and (Wen = '1' and Ren = '0' and Raddr_vect_s = Waddr_vect) else
95 '0';
96
97 Raddr_vect_s <= std_logic_vector(unsigned(Raddr_vect) +1);
81
98
82 process (rclk,rstn)
99 process (rclk,rstn)
83 begin
100 begin
84 if(rstn='0')then
101 if(rstn='0')then
85 Raddr_vect <= (others =>'0');
102 Raddr_vect <= (others =>'0');
86 Raddr_vect_d <= (others =>'1');
87 sempty <= '1';
103 sempty <= '1';
88 elsif(rclk'event and rclk='1')then
104 elsif(rclk'event and rclk='1')then
89 if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
105 sEmpty <= sempty_s;
90 sempty <= '0'; --27/01/12
106
91 elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then
107 if(sREN='0' and sempty = '0')then
92 sempty <= '1';
108 Raddr_vect <= Raddr_vect_s;
93 elsif(Raddr_vect/=Waddr_vect) then
94 sempty <= '0';
95 end if;
109 end if;
96 if(sREN='1' and sempty = '0') then
110
97 Raddr_vect <= std_logic_vector(unsigned(Raddr_vect) + 1);
98 Raddr_vect_d <= Raddr_vect;
99 end if;
100
101 end if;
111 end if;
102 end process;
112 end process;
103
113
104 --=============================
114 --=============================
105 -- Write section
115 -- Write section
106 --=============================
116 --=============================
107 sWEN <= not WEN and not sfull;
117 sWEN <= WEN or sFull;
118 sWE <= not sWEN;
119
120 sFull_s <= '1' when ReUse = '1' and Enable_ReUse='1' else
121 '1' when Waddr_vect_s = Raddr_vect and REN = '1' and WEN = '0' else
122 '1' when sFull = '1' and REN = '1' else
123 '0';
124
125 Waddr_vect_s <= std_logic_vector(unsigned(Waddr_vect) +1);
108
126
109 process (wclk,rstn)
127 process (wclk,rstn)
110 begin
128 begin
111 if(rstn='0')then
129 if(rstn='0')then
112 Waddr_vect <= (others =>'0');
130 Waddr_vect <= (others =>'0');
113 Waddr_vect_d <= (others =>'1');
114 sfull <= '0';
131 sfull <= '0';
115 elsif(wclk'event and wclk='1')then
132 elsif(wclk'event and wclk='1')then
116 if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
133 sfull <= sfull_s;
117 sfull <= '1'; --27/01/12
134
118 elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then
135 if(sWEN='0' and sfull='0')then
119 sfull <= '1';
136 Waddr_vect <= Waddr_vect_s;
120 elsif(Raddr_vect/=Waddr_vect) then
121 sfull <= '0';
122 end if;
137 end if;
123 if(sWEN='1' and sfull='0') then
138
124 Waddr_vect <= std_logic_vector(unsigned(Waddr_vect) +1);
125 Waddr_vect_d <= Waddr_vect;
126 end if;
127
128
129 end if;
139 end if;
130 end process;
140 end process;
131
141
132
142
133 full <= sFull;
143 full <= sFull_s;
134 empty <= sEmpty;
144 empty <= sEmpty_s;
135 waddr <= Waddr_vect;
145 waddr <= Waddr_vect;
136 raddr <= Raddr_vect;
146 raddr <= Raddr_vect;
137
147
138 end architecture;
148 end architecture;
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@@ -1,145 +1,182
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 library gaisler;
29 library gaisler;
30 use gaisler.misc.all;
30 use gaisler.misc.all;
31 use gaisler.memctrl.all;
31 use gaisler.memctrl.all;
32 library techmap;
32 library techmap;
33 use techmap.gencomp.all;
33 use techmap.gencomp.all;
34
34
35 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
35 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
36
36
37 package lpp_memory is
37 package lpp_memory is
38
38
39 component APB_FIFO is
39 component APB_FIFO is
40 generic (
40 generic (
41 tech : integer := apa3;
41 tech : integer := apa3;
42 pindex : integer := 0;
42 pindex : integer := 0;
43 paddr : integer := 0;
43 paddr : integer := 0;
44 pmask : integer := 16#fff#;
44 pmask : integer := 16#fff#;
45 pirq : integer := 0;
45 pirq : integer := 0;
46 abits : integer := 8;
46 abits : integer := 8;
47 FifoCnt : integer := 2;
47 FifoCnt : integer := 2;
48 Data_sz : integer := 16;
48 Data_sz : integer := 16;
49 Addr_sz : integer := 9;
49 Addr_sz : integer := 9;
50 Enable_ReUse : std_logic := '0';
50 Enable_ReUse : std_logic := '0';
51 R : integer := 1;
51 R : integer := 1;
52 W : integer := 1
52 W : integer := 1
53 );
53 );
54 port (
54 port (
55 clk : in std_logic; --! Horloge du composant
55 clk : in std_logic; --! Horloge du composant
56 rst : in std_logic; --! Reset general du composant
56 rst : in std_logic; --! Reset general du composant
57 rclk : in std_logic;
57 rclk : in std_logic;
58 wclk : in std_logic;
58 wclk : in std_logic;
59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
68 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
68 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
70 );
70 );
71 end component;
71 end component;
72
72
73
73
74 component lpp_fifo is
74 component lpp_fifo is
75 generic(
75 generic(
76 tech : integer := 0;
76 tech : integer := 0;
77 Enable_ReUse : std_logic := '0';
77 Enable_ReUse : std_logic := '0';
78 DataSz : integer range 1 to 32 := 8;
78 DataSz : integer range 1 to 32 := 8;
79 abits : integer range 2 to 12 := 8
79 abits : integer range 2 to 12 := 8
80 );
80 );
81 port(
81 port(
82 rstn : in std_logic;
82 rstn : in std_logic;
83 ReUse : in std_logic; --27/01/12
83 ReUse : in std_logic; --27/01/12
84 rclk : in std_logic;
84 rclk : in std_logic;
85 ren : in std_logic;
85 ren : in std_logic;
86 rdata : out std_logic_vector(DataSz-1 downto 0);
86 rdata : out std_logic_vector(DataSz-1 downto 0);
87 empty : out std_logic;
87 empty : out std_logic;
88 raddr : out std_logic_vector(abits-1 downto 0);
88 raddr : out std_logic_vector(abits-1 downto 0);
89 wclk : in std_logic;
89 wclk : in std_logic;
90 wen : in std_logic;
90 wen : in std_logic;
91 wdata : in std_logic_vector(DataSz-1 downto 0);
91 wdata : in std_logic_vector(DataSz-1 downto 0);
92 full : out std_logic;
92 full : out std_logic;
93 waddr : out std_logic_vector(abits-1 downto 0)
93 waddr : out std_logic_vector(abits-1 downto 0)
94 );
94 );
95 end component;
95 end component;
96
96
97
97
98 component lppFIFOxN is
98 component lppFIFOxN is
99 generic(
99 generic(
100 tech : integer := 0;
100 tech : integer := 0;
101 Data_sz : integer range 1 to 32 := 8;
101 Data_sz : integer range 1 to 32 := 8;
102 FifoCnt : integer := 1;
102 FifoCnt : integer := 1;
103 Enable_ReUse : std_logic := '0'
103 Enable_ReUse : std_logic := '0'
104 );
104 );
105 port(
105 port(
106 rst : in std_logic;
106 rst : in std_logic;
107 wclk : in std_logic;
107 wclk : in std_logic;
108 rclk : in std_logic;
108 rclk : in std_logic;
109 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
109 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
110 wen : in std_logic_vector(FifoCnt-1 downto 0);
110 wen : in std_logic_vector(FifoCnt-1 downto 0);
111 ren : in std_logic_vector(FifoCnt-1 downto 0);
111 ren : in std_logic_vector(FifoCnt-1 downto 0);
112 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
112 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
113 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
113 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
114 full : out std_logic_vector(FifoCnt-1 downto 0);
114 full : out std_logic_vector(FifoCnt-1 downto 0);
115 empty : out std_logic_vector(FifoCnt-1 downto 0)
115 empty : out std_logic_vector(FifoCnt-1 downto 0)
116 );
116 );
117 end component;
117 end component;
118
118
119 component lppFIFOx5 is
120 generic(
121 tech : integer := 0;
122 Data_sz : integer range 1 to 32 := 16;
123 Addr_sz : integer range 2 to 12 := 8;
124 Enable_ReUse : std_logic := '0'
125 );
126 port(
127 rst : in std_logic;
128 wclk : in std_logic;
129 rclk : in std_logic;
130 ReUse : in std_logic_vector(4 downto 0);
131 wen : in std_logic_vector(4 downto 0);
132 ren : in std_logic_vector(4 downto 0);
133 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
134 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
135 full : out std_logic_vector(4 downto 0);
136 empty : out std_logic_vector(4 downto 0)
137 );
138 end component;
139
140 component Bridge is
141 generic(
142 Data_sz : integer range 1 to 32 := 16
143 );
144 port(
145 clk : in std_logic;
146 raz : in std_logic;
147 Start : in std_logic;
148 FullUp : in std_logic;
149 EmptyUp : in std_logic;
150 FullDown : in std_logic;
151 EmptyDown : in std_logic;
152 Write : out std_logic;
153 Read : out std_logic
154 );
155 end component;
119
156
120 component ssram_plugin is
157 component ssram_plugin is
121 generic (tech : integer := 0);
158 generic (tech : integer := 0);
122 port
159 port
123 (
160 (
124 clk : in std_logic;
161 clk : in std_logic;
125 mem_ctrlr_o : in memory_out_type;
162 mem_ctrlr_o : in memory_out_type;
126 SSRAM_CLK : out std_logic;
163 SSRAM_CLK : out std_logic;
127 nBWa : out std_logic;
164 nBWa : out std_logic;
128 nBWb : out std_logic;
165 nBWb : out std_logic;
129 nBWc : out std_logic;
166 nBWc : out std_logic;
130 nBWd : out std_logic;
167 nBWd : out std_logic;
131 nBWE : out std_logic;
168 nBWE : out std_logic;
132 nADSC : out std_logic;
169 nADSC : out std_logic;
133 nADSP : out std_logic;
170 nADSP : out std_logic;
134 nADV : out std_logic;
171 nADV : out std_logic;
135 nGW : out std_logic;
172 nGW : out std_logic;
136 nCE1 : out std_logic;
173 nCE1 : out std_logic;
137 CE2 : out std_logic;
174 CE2 : out std_logic;
138 nCE3 : out std_logic;
175 nCE3 : out std_logic;
139 nOE : out std_logic;
176 nOE : out std_logic;
140 MODE : out std_logic;
177 MODE : out std_logic;
141 ZZ : out std_logic
178 ZZ : out std_logic
142 );
179 );
143 end component;
180 end component;
144
181
145 end;
182 end;
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