# HG changeset patch
# User martin
# Date 2013-02-25 12:50:47
# Node ID e52d1f932b5edab9f893ac2bda59c8e0dbaff2b5
# Parent  fc97c34d69e38b3618df78b3cbf71b6b9645c432

Débug de la FIFO
/!\ syncram_2p, signaux d'écritue/lecture actif a l'état haut
Différent de RAM_CEL actif a l'état bas .

diff --git a/lib/lpp/dsp/iir_filter/FILTERcfg.vhd b/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
--- a/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
+++ b/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
@@ -36,7 +36,7 @@ package FILTERcfg is
 --Bus Width and chanels number|
 --____________________________|
 constant ChanelsCount :   integer :=  1;
-constant Sample_SZ    :   integer := 20;
+constant Sample_SZ    :   integer := 18;
 constant Coef_SZ    :   integer := 9;
 constant CoefCntPerCel:   integer := 6;
 constant Cels_count :   integer := 5;
diff --git a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd
--- a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd
+++ b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd
@@ -24,8 +24,8 @@ use ieee.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
 entity RAM_CEL is 
-    port( WD : in std_logic_vector(35 downto 0); RD : out 
-        std_logic_vector(35 downto 0);WEN, REN : in std_logic; 
+    port( WD : in std_logic_vector(15 downto 0); RD : out
+        std_logic_vector(15 downto 0);WEN, REN : in std_logic;
         WADDR : in std_logic_vector(7 downto 0); RADDR : in 
         std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
         ) ;
@@ -34,9 +34,9 @@ end RAM_CEL;
 
 
 architecture ar_RAM_CEL of RAM_CEL is
-type    RAMarrayT   is array (0 to 255) of std_logic_vector(35 downto 0);
-signal  RAMarray           :   RAMarrayT:=(others => X"000000000");
-signal  RD_int       :   std_logic_vector(35 downto 0);
+type    RAMarrayT   is array (0 to 255) of std_logic_vector(15 downto 0);
+signal  RAMarray           :   RAMarrayT:=(others => X"0000");
+signal  RD_int       :   std_logic_vector(15 downto 0);
 
 begin
 
@@ -46,7 +46,7 @@ RD_int  <=  RAMarray(to_integer(unsigned
 process(RWclk,reset)
 begin
 if reset = '0' then
-	RD <= (X"000000000");
+	RD <= (X"0000");
 rst:for i in 0 to 255 loop
         RAMarray(i)    <=  (others => '0');
       end loop;
diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
--- a/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
+++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
@@ -66,7 +66,7 @@ signal  RADDR       :   std_logic_vector
 signal  WADDR       :   std_logic_vector(7 downto 0);
 signal  WADDR_D     :   std_logic_vector(7 downto 0);
 
-
+SIGNAL WADDR_back_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
 begin
 
@@ -150,25 +150,42 @@ port map(
 );
 
 
-
+    WADDR_backreg : REG
+    generic map(size    => 8,initial_VALUE =>ChanelsCount*Cels_count*4-2)
+    port map(
+      reset   =>  reset,
+      clk     =>  clk,         --SVG_ADDR,
+      D       =>  WADDR_back_s,--RADDR,
+      Q       =>  WADDR_back
+    );
+  WADDR_back_s <= RADDR WHEN SVG_ADDR = '1' ELSE WADDR_back;
 
-WADDR_backreg :REG
-generic map(size    => 8,initial_VALUE =>ChanelsCouNT*Cels_count*4-2)
-port map(
-    reset   =>  reset,
-    clk     =>  SVG_ADDR,
-    D       =>  RADDR,
-    Q       =>  WADDR_back
-);
+  WADDR_backreg2 :entity work.REG
+    generic map(size    => 8)
+    port map(
+      reset   =>  reset,
+      clk     =>  clk,         --SVG_ADDR,
+      D       =>  WADDR_back,
+      Q       =>  WADDR_back_D
+      );
 
-WADDR_backreg2 :REG
-generic map(size    => 8)
-port map(
-    reset   =>  reset,
-    clk     =>  SVG_ADDR,
-    D       =>  WADDR_back,
-    Q       =>  WADDR_back_D
-);
+--WADDR_backreg :REG
+--generic map(size    => 8,initial_VALUE =>ChanelsCouNT*Cels_count*4-2)
+--port map(
+--    reset   =>  reset,
+--    clk     =>  SVG_ADDR,
+--    D       =>  RADDR,
+--    Q       =>  WADDR_back
+--);
+--
+--WADDR_backreg2 :REG
+--generic map(size    => 8)
+--port map(
+--    reset   =>  reset,
+--    clk     =>  SVG_ADDR,
+--    D       =>  WADDR_back,
+--    Q       =>  WADDR_back_D
+--
 
 WDRreg :REG
 generic map(size    => Input_SZ_1)
diff --git a/lib/lpp/dsp/iir_filter/Top_IIR.vhd b/lib/lpp/dsp/iir_filter/Top_IIR.vhd
--- a/lib/lpp/dsp/iir_filter/Top_IIR.vhd
+++ b/lib/lpp/dsp/iir_filter/Top_IIR.vhd
@@ -7,7 +7,7 @@ use lpp.iir_filter.all;
 
 entity Top_IIR is
 generic(
-        Sample_SZ : integer := 20;
+        Sample_SZ : integer := 18;
 		  ChanelsCount : integer := 1;
 		  Coef_SZ      : integer := 9;
 		  CoefCntPerCel: integer := 6;
@@ -17,8 +17,8 @@ generic(
         clk         :   in  std_logic;
         sample_clk  :   in  std_logic;
 --        BP : in std_logic;
-        BPinput       :   in std_logic_vector(3 downto 0);
-        LVLinput       :   in std_logic_vector(11 downto 0);
+--        BPinput       :   in std_logic_vector(3 downto 0);
+        LVLinput       :   in std_logic_vector(15 downto 0);
         INsample      :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
         OUTsample      :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
     ); 
@@ -48,7 +48,7 @@ end generate;
 --         sample_temp(k) <= BP;
 --end generate;
 
-sample_int <= BPinput(3) & BPinput(3) & BPinput(3) & BPinput(3) & BPinput & LVLinput;
+sample_int <= LVLinput(15) & LVLinput(15) & LVLinput;
 INsample <= sample_in;
 OUTsample <= sample_out;
 
diff --git a/lib/lpp/dsp/iir_filter/iir_filter.vhd b/lib/lpp/dsp/iir_filter/iir_filter.vhd
--- a/lib/lpp/dsp/iir_filter/iir_filter.vhd
+++ b/lib/lpp/dsp/iir_filter/iir_filter.vhd
@@ -102,7 +102,7 @@ end component;
 
 component Top_IIR is
 generic(
-        Sample_SZ : integer := 20;
+        Sample_SZ : integer := 18;
 		  ChanelsCount : integer := 1;
 		  Coef_SZ      : integer := 9;
 		  CoefCntPerCel: integer := 6;
@@ -112,8 +112,8 @@ generic(
         clk         :   in  std_logic;
         sample_clk  :   in  std_logic;
  --       BP : in std_logic;
-        BPinput       :   in std_logic_vector(3 downto 0);
-        LVLinput       :   in std_logic_vector(11 downto 0);
+ --       BPinput       :   in std_logic_vector(3 downto 0);
+        LVLinput       :   in std_logic_vector(15 downto 0);
         INsample      :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
         OUTsample      :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
     ); 
diff --git a/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd b/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd
--- a/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd
+++ b/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd
@@ -63,6 +63,8 @@ begin
             Read <= (others => '1');
             Valid <= '0';
             FifoCpt <= 1;
+            Data_re <= (others => '0');
+            Data_im <= (others => '0');
             
         elsif(clk'event and clk='1')then
 
diff --git a/lib/lpp/dsp/lpp_fft/FFTamont.vhd b/lib/lpp/dsp/lpp_fft/FFTamont.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/lpp_fft/FFTamont.vhd
@@ -0,0 +1,95 @@
+-- FFTamont.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity FFTamont is
+generic(
+    Data_sz  : integer range 1 to 32 := 16
+    );
+port(
+    clk         : in std_logic;
+    rstn        : in std_logic;
+    Load        : in std_logic;
+    Empty       : in std_logic;
+    Full        : in std_logic;
+    DATA        : in std_logic_vector(Data_sz-1 downto 0);
+    Valid       : out std_logic;
+    Read        : out std_logic;
+    Data_re     : out std_logic_vector(Data_sz-1 downto 0);
+    Data_im     : out std_logic_vector(Data_sz-1 downto 0)
+);
+end entity;
+
+
+architecture ar_FFTamont of FFTamont is
+
+type etat is (eX,e0,e1,e2);
+signal ect : etat;
+
+
+begin
+
+    process(clk,rstn)
+    begin
+        if(rstn='0')then 
+            ect <= eX;
+            Read <= '1';
+            Valid <= '0';
+            Data_re <= (others => '0');
+            Data_im <= (others => '0');
+            
+        elsif(clk'event and clk='1')then
+
+            case ect is
+
+                when eX => 
+                    if(Full='1')then
+                        ect <= e0;
+                    end if;
+
+                when e0 =>
+                    Valid <= '0';
+                    if(Load='1' and Empty='0')then
+                        Read <= '0';
+                        ect <= e1;
+                    elsif(Empty='1')then
+                        ect <= eX;                        
+                    end if;
+
+                when e1 =>
+                    Read <= '1';
+                    Data_re <= DATA;
+                    Data_im <= (others => '0');
+                    Valid <= '1';
+                    ect <= e0;  
+               
+                when e2 =>
+                    null;                                           
+
+            end case;
+        end if;
+    end process;
+
+end architecture;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/dsp/lpp_fft/FFTaval.vhd b/lib/lpp/dsp/lpp_fft/FFTaval.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/lpp_fft/FFTaval.vhd
@@ -0,0 +1,90 @@
+-- FFTaval.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity FFTaval is
+generic(
+    Data_sz  : integer range 1 to 32 := 8
+    );
+port(
+    clk         : in std_logic;
+    rstn        : in std_logic;
+    Ready       : in std_logic;
+    Valid       : in std_logic;
+    Full        : in std_logic;
+    Data_re     : in std_logic_vector(Data_sz-1 downto 0);
+    Data_im     : in std_logic_vector(Data_sz-1 downto 0);
+    Read        : out std_logic;
+    Write       : out std_logic;
+    ReUse       : out std_logic;
+    DATA        : out std_logic_vector(Data_sz-1 downto 0)
+);
+end entity;
+
+
+architecture ar_FFTaval of FFTaval is
+
+type etat is (eX,e0,e1,e2,e3);
+signal ect : etat;
+
+signal DataTmp  : std_logic_vector(Data_sz-1 downto 0);
+
+signal sReady   : std_logic;
+
+begin
+
+    process(clk,rstn)
+    begin
+        if(rstn='0')then 
+            ect <= e0;
+            Read <= '0';
+            Write <= '1';
+            Reuse <= '0';
+            
+        elsif(clk'event and clk='1')then
+            sReady <= Ready;
+
+            case ect is
+
+                when e0 =>
+                    Write <= '1';
+                    if(sReady='0' and Ready='1' and full='0')then
+                        Read <= '1';
+                        ect <= e1;
+                    end if;
+
+                when e1 =>
+                    Read <= '0';
+                    if(Valid='1' and full='0')then
+                        DataTmp <= Data_im;
+                        DATA <= Data_re;
+                        Write <= '0';
+                        ect <= e2;
+                    elsif(full='1')then
+                        ReUse <= '1';
+                        ect <= e0;
+                    end if;                    
+
+                 when e2 =>
+                    DATA <= DataTmp;
+                    ect <= e3;            
+ 
+                when e3 =>
+                    Write <= '1';
+                    if(Ready='1' and full='0')then
+                        Read <= '1';
+                        ect <= e1;
+                    end if;
+                               
+                when eX =>
+                    null;                   
+
+            end case;
+        end if;
+    end process;
+
+
+
+end architecture;
+
diff --git a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd
--- a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd
+++ b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd
@@ -125,6 +125,42 @@ port(
 );
 end component;
 
+component FFTamont is
+generic(
+    Data_sz  : integer range 1 to 32 := 16
+    );
+port(
+    clk         : in std_logic;
+    rstn        : in std_logic;
+    Load        : in std_logic;
+    Empty       : in std_logic;
+    Full        : in std_logic;
+    DATA        : in std_logic_vector(Data_sz-1 downto 0);
+    Valid       : out std_logic;
+    Read        : out std_logic;
+    Data_re     : out std_logic_vector(Data_sz-1 downto 0);
+    Data_im     : out std_logic_vector(Data_sz-1 downto 0)
+);
+end component;
+
+component FFTaval is
+generic(
+    Data_sz  : integer range 1 to 32 := 8
+    );
+port(
+    clk         : in std_logic;
+    rstn        : in std_logic;
+    Ready       : in std_logic;
+    Valid       : in std_logic;
+    Full        : in std_logic;
+    Data_re     : in std_logic_vector(Data_sz-1 downto 0);
+    Data_im     : in std_logic_vector(Data_sz-1 downto 0);
+    Read        : out std_logic;
+    Write       : out std_logic;
+    ReUse       : out std_logic;
+    DATA        : out std_logic_vector(Data_sz-1 downto 0)
+);
+end component;
 --==============================================================|
 --================== IP VHDL de la FFT actel ===================|
 --================ non partag� dans la VHD_Lib =================|
diff --git a/lib/lpp/lpp_matrix/Dispatch.vhd b/lib/lpp/lpp_matrix/Dispatch.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_matrix/Dispatch.vhd
@@ -0,0 +1,109 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Martin Morlot
+--                   Mail : martin.morlot@lpp.polytechnique.fr
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+use lpp.lpp_matrix.all;
+
+entity Dispatch is
+generic(
+    Data_SZ  : integer := 32);
+port(
+    clk         : in std_logic;
+    reset       : in std_logic;
+    Acq         : in std_logic;
+    Data        : in std_logic_vector(Data_SZ-1 downto 0);
+    Write       : in std_logic;
+    Full        : in std_logic_vector(1 downto 0);
+--    Empty       : in std_logic_vector(1 downto 0);
+    FifoData    : out std_logic_vector(2*Data_SZ-1 downto 0);
+    FifoWrite   : out std_logic_vector(1 downto 0);
+--    FifoFull    : out std_logic;
+    Pong        : out std_logic;
+    Error       : out std_logic
+
+);
+end entity;
+
+
+architecture ar_Dispatch of Dispatch is
+
+type etat is (e0,e1,e2,e3);
+signal ect : etat;
+
+begin
+
+ process (clk,reset)
+    begin
+        if(reset='0')then
+            Pong    <= '0';
+            Error   <= '0';   
+            
+        elsif(clk' event and clk='1')then
+
+            case ect is
+
+                when e0 =>
+                    if(Full(0) = '1')then
+                        pong <= '1';                        
+                        ect <= e1;
+                    end if;
+
+                when e1 =>
+                    if(Acq <= '1')then
+                        Error <= '0';
+                        pong <= '0';
+                        ect <= e2;
+                    else
+                        Error <= '1';
+                        ect <= e1;
+                    end if;
+
+                when e2 =>
+                    if(Full(1) = '1')then
+                        pong <= '1';                        
+                        ect <= e3;
+                    end if;
+
+                when e3 =>
+                    if(Acq <= '1')then
+                        Error <= '0';
+                        pong <= '0';
+                        ect <= e0;
+                    else
+                        Error <= '1';
+                        ect <= e3;
+                    end if;
+
+            end case;
+
+        end if;
+    end process;
+
+FifoData <= Data & Data;
+
+with ect select
+    FifoWrite <= '1' & not Write when e0,
+                 not Write & '1' when e2,
+                 "11" when others;
+                    
+end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_matrix/GetResult.vhd b/lib/lpp/lpp_matrix/GetResult.vhd
--- a/lib/lpp/lpp_matrix/GetResult.vhd
+++ b/lib/lpp/lpp_matrix/GetResult.vhd
@@ -32,7 +32,7 @@ port(
     Valid       : in  std_logic;
     Conjugate   : in std_logic;
     Res         : in std_logic_vector(Result_SZ-1 downto 0);
-    Full        : in std_logic;
+--    Full        : in std_logic;
     WriteFIFO   : out std_logic;
     Received    : out std_logic;    
     Result      : out std_logic_vector(Result_SZ-1 downto 0)
@@ -63,7 +63,7 @@ begin
 
             case ect is
                 when st0 =>
-                    if(Full='0' and Valid='1')then
+                    if(Valid='1')then--if(Full='0' and Valid='1')then
                         Result <= Res;
                         WriteFIFO <= '1';
                         Received <= '1';
@@ -84,7 +84,7 @@ begin
                     end if;        
                 
                 when st1 =>
-                    if(Full='0' and Valid='1')then
+                    if(Valid='1')then--if(Full='0' and Valid='1')then
                         Result <= Res;
                         WriteFIFO <= '1';
                         Received <= '0';
diff --git a/lib/lpp/lpp_matrix/SpectralMatrix.vhd b/lib/lpp/lpp_matrix/SpectralMatrix.vhd
--- a/lib/lpp/lpp_matrix/SpectralMatrix.vhd
+++ b/lib/lpp/lpp_matrix/SpectralMatrix.vhd
@@ -35,7 +35,7 @@ port(
     FIFO1      : in std_logic_vector(Input_SZ-1 downto 0);
     FIFO2      : in std_logic_vector(Input_SZ-1 downto 0);
     Statu      : in std_logic_vector(3 downto 0);
-    FullFIFO   : in std_logic;
+--    FullFIFO   : in std_logic;
     ReadFIFO   : out std_logic_vector(1 downto 0);
     WriteFIFO  : out std_logic;
     Result     : out std_logic_vector(Result_SZ-1 downto 0)
@@ -70,7 +70,7 @@ CALC0 : Matrix
 
 RES0 : GetResult
     generic map(Result_SZ)
-    port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,FullFIFO,WriteFIFO,Received_int,Result);
+    port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO
 
 
 With Statu select
diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd
--- a/lib/lpp/lpp_matrix/lpp_matrix.vhd
+++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd
@@ -86,7 +86,7 @@ port(
     FIFO1      : in std_logic_vector(Input_SZ-1 downto 0);
     FIFO2      : in std_logic_vector(Input_SZ-1 downto 0);
     Statu      : in std_logic_vector(3 downto 0);
-    FullFIFO   : in std_logic;
+--    FullFIFO   : in std_logic;
     ReadFIFO   : out std_logic_vector(1 downto 0);
     WriteFIFO  : out std_logic;
     Result     : out std_logic_vector(Result_SZ-1 downto 0)
@@ -120,7 +120,7 @@ port(
     Valid     : in  std_logic;
     Conjugate : in  std_logic;
     Res       : in std_logic_vector(Result_SZ-1 downto 0);
-    Full      : in std_logic;
+--    Full      : in std_logic;
     WriteFIFO : out std_logic;
     Received  : out std_logic;
     Result    : out std_logic_vector(Result_SZ-1 downto 0)
@@ -148,6 +148,24 @@ port(
 end component;
 
 
+component Dispatch is
+generic(
+    Data_SZ  : integer := 32);
+port(
+    clk         : in std_logic;
+    reset       : in std_logic;
+    Acq         : in std_logic;
+    Data        : in std_logic_vector(Data_SZ-1 downto 0);
+    Write       : in std_logic;
+    Full        : in std_logic_vector(1 downto 0);
+    FifoData    : out std_logic_vector(2*Data_SZ-1 downto 0);
+    FifoWrite   : out std_logic_vector(1 downto 0);
+    Pong        : out std_logic;
+    Error       : out std_logic
+);
+end component;
+
+
 component DriveInputs is
 port(
     clk     : in  std_logic;
diff --git a/lib/lpp/lpp_memory/APB_FIFO.vhd b/lib/lpp/lpp_memory/APB_FIFO.vhd
--- a/lib/lpp/lpp_memory/APB_FIFO.vhd
+++ b/lib/lpp/lpp_memory/APB_FIFO.vhd
@@ -87,37 +87,41 @@ type FIFO_ctrlr_Reg_Vec is array(FifoCnt
 type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0); 
 type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0); 
 
-signal Rec      : FIFO_ctrlr_Reg_Vec;
-signal PRdata    : std_logic_vector(31 downto 0);
-signal FIFO_ID  : std_logic_vector(31 downto 0);
-signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
-signal sFull     : std_logic_vector(FifoCnt-1 downto 0);
-signal sEmpty    : std_logic_vector(FifoCnt-1 downto 0);
-signal sEmpty_d  : std_logic_vector(FifoCnt-1 downto 0);
-signal sWen      : std_logic_vector(FifoCnt-1 downto 0);
-signal sRen      : std_logic_vector(FifoCnt-1 downto 0);
-signal sRclk     : std_logic;
-signal sWclk     : std_logic;
-signal sWen_APB  : std_logic_vector(FifoCnt-1 downto 0);
-signal sRen_APB  : std_logic_vector(FifoCnt-1 downto 0);
-signal sRDATA    : fifodatabus;   
-signal sWDATA    : fifodatabus;    
-signal sWADDR    : fifoaddressbus;   
-signal sRADDR    : fifoaddressbus;
-signal sReUse    : std_logic_vector(FifoCnt-1 downto 0);   --05/06/12
-signal sReUse_APB  : std_logic_vector(FifoCnt-1 downto 0);    --05/06/12
+signal Rec           : FIFO_ctrlr_Reg_Vec;
+signal PRdata        : std_logic_vector(31 downto 0);
+signal FIFO_ID       : std_logic_vector(31 downto 0);
+signal autoloaded    : std_logic_vector(FifoCnt-1 downto 0);
+signal sFull         : std_logic_vector(FifoCnt-1 downto 0);
+signal sEmpty        : std_logic_vector(FifoCnt-1 downto 0);
+signal sEmpty_d      : std_logic_vector(FifoCnt-1 downto 0);
+signal sWen          : std_logic_vector(FifoCnt-1 downto 0);
+signal sRen          : std_logic_vector(FifoCnt-1 downto 0);
+signal sRclk         : std_logic;
+signal sWclk         : std_logic;
+signal sWen_APB      : std_logic_vector(FifoCnt-1 downto 0);
+signal sRen_APB      : std_logic_vector(FifoCnt-1 downto 0);
+signal sRDATA        : fifodatabus;
+signal sWDATA        : fifodatabus;
+signal sWADDR        : fifoaddressbus;
+signal sRADDR        : fifoaddressbus;
+signal sReUse        : std_logic_vector(FifoCnt-1 downto 0);
+signal sReUse_APB    : std_logic_vector(FifoCnt-1 downto 0);
+
+signal regDataValid  : std_logic_vector(FifoCnt-1 downto 0);
+signal regData       : fifodatabus;
+signal regREN        : std_logic_vector(FifoCnt-1 downto 0);
 
 type state_t is (idle,Read);
 signal fiforeadfsmst : state_t;
 
 begin
 
-FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
-FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
-FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
+FIFO_ID(3 downto 0)     <= std_logic_vector(to_unsigned(FifoCnt,4));
+FIFO_ID(15 downto 8)    <= std_logic_vector(to_unsigned(Data_sz,8));
+FIFO_ID(23 downto 16)   <= std_logic_vector(to_unsigned(Addr_sz,8));
 
 
-Write : if W /= 0 generate 
+Writeint : if W /= 0 generate
     FIFO_ID(4) <= '1';
     sWen   <= sWen_APB;
     sReUse <= sReUse_APB;
@@ -137,7 +141,7 @@ Writeext : if W = 0 generate
     end generate;
 end generate;
 
-Read : if R /= 0 generate 
+Readint : if R /= 0 generate 
  FIFO_ID(5) <= '1';
  sRen   <=  sRen_APB;
  srclk  <=  clk;
@@ -159,18 +163,16 @@ ctrlregs: for i in 0 to FifoCnt-1 genera
     RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
     WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
     Rec(i).FIFO_Ctrl(16) <= sFull(i);
-    --Rec(i).FIFO_Ctrl(17) <= Rec(i).FIFO_Ctrl(1); --27/01/12
-    sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12
-    Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; --27/01/12
-    Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; --27/01/12
+    sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1);
+    Rec(i).FIFO_Ctrl(3 downto 2) <= "00";
+    Rec(i).FIFO_Ctrl(19 downto 17) <= "000";
     Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
-    Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);  ---|free|Waddrs|Full||free|Raddrs|empty|
-end generate;                                               -- 31         17  16 15          1     0
+    Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);
+end generate;
 
 Empty <= sEmpty;
 Full <= sFull;
 
-
 fifos: for i in 0 to FifoCnt-1 generate
     FIFO0 : lpp_fifo
         generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
@@ -182,17 +184,16 @@ end generate;
         if(rst='0')then
         rstloop1: for i in 0 to FifoCnt-1 loop
             Rec(i).FIFO_Wdata <=  (others => '0');
-            Rec(i).FIFO_Ctrl(1) <= '0'; --27/01/12
-            --Rec(i).FIFO_Ctrl(17) <= '0';
+            Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse
             sWen_APB(i) <= '1';
         end loop;
         elsif(clk'event and clk='1')then
+
     --APB Write OP
             if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                    writelp: for i in 0 to FifoCnt-1 loop
                         if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
                             Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
-                            --Rec(i).FIFO_Ctrl(17) <= apbi.pwdata(17);
                         elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
                             Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
                             sWen_APB(i) <= '0';
@@ -201,6 +202,7 @@ end generate;
             else
                 sWen_APB <= (others =>'1');
             end if;
+
  --APB Read OP
             if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                if(apbi.paddr(abits-1 downto 2)="000000") then
@@ -212,16 +214,16 @@ end generate;
                         elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
                             PRdata(Data_sz-1 downto 0)  <= Rec(i).FIFO_rdata;
                         end if;
-                   end loop; 
-                end if;       
+                   end loop;
+                end if;
             end if;
     end if;
+
     apbo.pconfig <= pconfig;
+
 end process;
 apbo.prdata     <=   PRdata when apbi.penable = '1';
 
-
-
 process(rst,clk)
     begin
         if(rst='0')then
@@ -256,35 +258,6 @@ process(rst,clk)
                     fiforeadfsmst <= idle;
             end case;
         end if;
-end process;
-
-
-end ar_APB_FIFO;
-
-
-
-
-
-
-
-
-
-
-
+end process; 
 
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+end ar_APB_FIFO;
\ No newline at end of file
diff --git a/lib/lpp/lpp_memory/Bridge.vhd b/lib/lpp/lpp_memory/Bridge.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_memory/Bridge.vhd
@@ -0,0 +1,78 @@
+-- Bridge.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Bridge is
+generic(
+    Data_sz  : integer range 1 to 32 := 16
+    );
+port(
+    clk         : in std_logic;
+    raz        : in std_logic;
+    Start : in std_logic;
+    FullUp : in std_logic;
+    EmptyUp : in std_logic;
+    FullDown : in std_logic;
+    EmptyDown : in std_logic;
+    Write : out std_logic;
+    Read : out std_logic
+);
+end entity;
+
+
+architecture ar_Bridge of Bridge is
+
+type etat is (eX,e1,e2,e3);
+signal ect : etat;
+
+signal i : integer;
+
+begin
+
+    process(clk,raz)
+    begin
+        if(raz='0')then 
+            Write <= '1';
+            Read <= '1';
+            i <= 0;
+            ect <= eX;
+            
+        elsif(clk'event and clk='1')then
+            
+            case ect is
+                
+                when eX =>
+                    if(FullUp='1' and EmptyDown='1' and start='0')then
+                        ect <= e1;
+                    end if;    
+
+                when e1 =>
+                    Write <= '1';
+                    if(EmptyUp='0')then
+                        Read <= '0';
+                        ect <= e2;
+                    else
+                        Read <= '1';
+                        ect <= e3;
+                    end if;
+
+                when e2 =>
+                    Read <= '1';
+                    if(FullDown='0')then
+                        Write <= '0';
+                        ect <= e1;
+                    else
+                        Write <= '1';
+                        ect <= e3;
+                    end if;
+                    
+                when e3 =>
+                     null;
+
+             end case;         
+        end if;
+    end process;
+
+
+end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_memory/lppFIFOx5.vhd b/lib/lpp/lpp_memory/lppFIFOx5.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_memory/lppFIFOx5.vhd
@@ -0,0 +1,77 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+------------------------------------------------------------------------------
+--                    Author : Martin Morlot
+--                     Mail : martin.morlot@lpp.polytechnique.fr
+------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+library lpp;
+use lpp.lpp_memory.all;
+library techmap;
+use techmap.gencomp.all;
+
+entity lppFIFOx5 is
+generic(
+    tech          :   integer := 0;
+    Data_sz       :   integer range 1 to 32 := 8;
+    Enable_ReUse  :   std_logic := '0'
+    );
+port(
+    rst     :   in std_logic;
+    wclk    :   in std_logic;    
+    rclk    :   in std_logic;
+    ReUse   :   in std_logic_vector(4 downto 0);
+    wen     :   in std_logic_vector(4 downto 0); 
+    ren     :   in std_logic_vector(4 downto 0);
+    wdata   :   in std_logic_vector((5*Data_sz)-1 downto 0);
+    rdata   :   out std_logic_vector((5*Data_sz)-1 downto 0);
+    full    :   out std_logic_vector(4 downto 0);
+    empty   :   out std_logic_vector(4 downto 0)    
+);
+end entity;
+
+
+architecture ar_lppFIFOx5 of lppFIFOx5 is
+
+begin
+
+    fifoB1 : entity work.lpp_fifo
+        generic map (tech,Enable_ReUse,Data_sz,8)
+        port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open);
+
+    fifoB2 : entity work.lpp_fifo
+        generic map (tech,Enable_ReUse,Data_sz,8)
+        port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open);
+
+    fifoB3 : entity work.lpp_fifo
+        generic map (tech,Enable_ReUse,Data_sz,8)
+        port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open);
+
+    fifoE1 : entity work.lpp_fifo
+        generic map (tech,Enable_ReUse,Data_sz,8)
+        port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open);
+
+    fifoE2 : entity work.lpp_fifo
+        generic map (tech,Enable_ReUse,Data_sz,8)
+        port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open);
+
+
+end architecture;
+
diff --git a/lib/lpp/lpp_memory/lpp_FIFO.vhd b/lib/lpp/lpp_memory/lpp_FIFO.vhd
--- a/lib/lpp/lpp_memory/lpp_FIFO.vhd
+++ b/lib/lpp/lpp_memory/lpp_FIFO.vhd
@@ -24,6 +24,7 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 library lpp;
 use lpp.lpp_memory.all;
+use lpp.iir_filter.all;
 library techmap;
 use techmap.gencomp.all;
 
@@ -36,7 +37,7 @@ generic(
     );
 port(
     rstn    :   in std_logic;
-    ReUse   :   in std_logic;   --27/01/12
+    ReUse   :   in std_logic;
     rclk    :   in std_logic;
     ren     :   in std_logic;
     rdata   :   out std_logic_vector(DataSz-1 downto 0);
@@ -53,85 +54,94 @@ end entity;
 
 architecture ar_lpp_fifo of lpp_fifo is
 
-signal sFull        : std_logic:='0';
-signal sEmpty       : std_logic:='1';
-signal sREN         : std_logic:='0';
-signal sWEN         : std_logic:='0';
+signal sFull        : std_logic;
+signal sFull_s      : std_logic;
+signal sEmpty_s     : std_logic;
+
+signal sEmpty       : std_logic;
+signal sREN         : std_logic;
+signal sWEN         : std_logic;
+signal sRE          : std_logic;
+signal sWE          : std_logic;
 
 signal Waddr_vect   : std_logic_vector(abits-1 downto 0):=(others =>'0');
 signal Raddr_vect   : std_logic_vector(abits-1 downto 0):=(others =>'0');
-signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
-signal Raddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
+signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
+signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
 
 begin
 
+--==================================================================================
+-- /!\ syncram_2p Write et Read actif a l'�tat haut /!\
+-- A l'inverse de RAM_CEL !!!
+--==================================================================================
 SRAM : syncram_2p
-generic map(tech,abits,DataSz)
-port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata);
-
+    generic map(tech,abits,DataSz)
+    port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
+--================================================================================== 
 --RAM0: entity work.RAM_CEL
---    generic map(abits, DataSz)
---    port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn);
-
+--    port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
+--================================================================================== 
 
 --=============================
 --     Read section
 --=============================
-sREN    <= not REN and not sempty;
+sREN    <= REN or sEmpty;
+sRE     <= not sREN;
+
+sEmpty_s <= '0' when ReUse = '1' and Enable_ReUse='1' else
+            '1' when sEmpty = '1' and Wen = '1' else
+            '1' when sEmpty = '0' and (Wen = '1' and Ren = '0' and Raddr_vect_s = Waddr_vect) else
+            '0';
+
+Raddr_vect_s   <= std_logic_vector(unsigned(Raddr_vect) +1);
 
 process (rclk,rstn)
 begin
     if(rstn='0')then
         Raddr_vect   <=  (others =>'0');
-        Raddr_vect_d <=  (others =>'1');
         sempty  <= '1';
-    elsif(rclk'event and rclk='1')then
-        if(ReUse = '1' and Enable_ReUse='1')then   --27/01/12
-            sempty  <= '0';    --27/01/12
-        elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then
-            sempty  <= '1';
-        elsif(Raddr_vect/=Waddr_vect) then
-            sempty  <= '0';
+    elsif(rclk'event and rclk='1')then 
+        sEmpty <= sempty_s;
+        
+        if(sREN='0' and sempty = '0')then
+            Raddr_vect  <= Raddr_vect_s;
         end if;
-        if(sREN='1' and sempty = '0') then
-            Raddr_vect  <= std_logic_vector(unsigned(Raddr_vect) + 1);
-            Raddr_vect_d  <=  Raddr_vect;
-        end if;
-                            
+
     end if;
 end process;
 
 --=============================
 --     Write section
 --=============================
-sWEN    <= not WEN and not sfull;
+sWEN    <= WEN or sFull;
+sWE     <= not sWEN;
+
+sFull_s <= '1' when ReUse = '1' and Enable_ReUse='1' else
+           '1' when Waddr_vect_s = Raddr_vect and REN = '1' and WEN = '0' else
+           '1' when sFull = '1' and REN = '1' else
+           '0';
+           
+Waddr_vect_s   <= std_logic_vector(unsigned(Waddr_vect) +1);
 
 process (wclk,rstn)
 begin
     if(rstn='0')then
         Waddr_vect   <=  (others =>'0');
-        Waddr_vect_d <=  (others =>'1');
         sfull        <=   '0';
     elsif(wclk'event and wclk='1')then
-        if(ReUse = '1' and Enable_ReUse='1')then   --27/01/12
-            sfull  <= '1';    --27/01/12
-        elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then
-            sfull  <= '1';
-        elsif(Raddr_vect/=Waddr_vect) then
-            sfull  <= '0';
+        sfull <= sfull_s;
+
+        if(sWEN='0' and sfull='0')then
+            Waddr_vect <= Waddr_vect_s;
         end if;
-        if(sWEN='1' and sfull='0') then
-            Waddr_vect   <= std_logic_vector(unsigned(Waddr_vect) +1);
-            Waddr_vect_d <= Waddr_vect;
-        end if;
-
-                   
+        
     end if;
 end process;
 
 
-full    <= sFull;
-empty   <= sEmpty;
+full    <= sFull_s;
+empty   <= sEmpty_s;
 waddr   <= Waddr_vect;
 raddr   <= Raddr_vect;
 
diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd
--- a/lib/lpp/lpp_memory/lpp_memory.vhd
+++ b/lib/lpp/lpp_memory/lpp_memory.vhd
@@ -116,6 +116,43 @@ port(
 );
 end component;
 
+component lppFIFOx5 is
+generic(
+    tech          :   integer := 0;
+    Data_sz       :   integer range 1 to 32 := 16;
+    Addr_sz       :   integer range 2 to 12 := 8;
+    Enable_ReUse  :   std_logic := '0'
+    );
+port(
+    rst     :   in std_logic;
+    wclk    :   in std_logic;    
+    rclk    :   in std_logic;
+    ReUse   :   in std_logic_vector(4 downto 0);
+    wen     :   in std_logic_vector(4 downto 0); 
+    ren     :   in std_logic_vector(4 downto 0);
+    wdata   :   in std_logic_vector((5*Data_sz)-1 downto 0);
+    rdata   :   out std_logic_vector((5*Data_sz)-1 downto 0);
+    full    :   out std_logic_vector(4 downto 0);
+    empty   :   out std_logic_vector(4 downto 0)    
+);
+end component;
+
+component Bridge is
+generic(
+    Data_sz  : integer range 1 to 32 := 16
+    );
+port(
+    clk         : in std_logic;
+    raz        : in std_logic;
+    Start : in std_logic;
+    FullUp : in std_logic;
+    EmptyUp : in std_logic;
+    FullDown : in std_logic;
+    EmptyDown : in std_logic;
+    Write : out std_logic;
+    Read : out std_logic
+);
+end component;
 
 component ssram_plugin is
 generic (tech : integer := 0);