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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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-- Author : Martin Morlot
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-- Mail : martin.morlot@lpp.polytechnique.fr
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library lpp;
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use lpp.lpp_memory.all;
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library techmap;
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use techmap.gencomp.all;
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entity lpp_fifo is
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generic(
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tech : integer := 0;
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Enable_ReUse : std_logic := '0';
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DataSz : integer range 1 to 32 := 8;
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abits : integer range 2 to 12 := 8
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);
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port(
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rstn : in std_logic;
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ReUse : in std_logic; --27/01/12
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rclk : in std_logic;
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ren : in std_logic;
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rdata : out std_logic_vector(DataSz-1 downto 0);
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empty : out std_logic;
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raddr : out std_logic_vector(abits-1 downto 0);
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wclk : in std_logic;
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wen : in std_logic;
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wdata : in std_logic_vector(DataSz-1 downto 0);
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full : out std_logic;
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waddr : out std_logic_vector(abits-1 downto 0)
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);
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end entity;
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architecture ar_lpp_fifo of lpp_fifo is
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signal sFull : std_logic:='0';
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signal sEmpty : std_logic:='1';
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signal sREN : std_logic:='0';
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signal sWEN : std_logic:='0';
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signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
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signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
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signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
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signal Raddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
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begin
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SRAM : syncram_2p
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generic map(tech,abits,DataSz)
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port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata);
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--RAM0: entity work.RAM_CEL
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-- generic map(abits, DataSz)
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-- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn);
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--=============================
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-- Read section
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--=============================
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sREN <= not REN and not sempty;
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process (rclk,rstn)
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begin
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if(rstn='0')then
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Raddr_vect <= (others =>'0');
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Raddr_vect_d <= (others =>'1');
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sempty <= '1';
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elsif(rclk'event and rclk='1')then
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if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
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sempty <= '0'; --27/01/12
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elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then
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sempty <= '1';
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elsif(Raddr_vect/=Waddr_vect) then
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sempty <= '0';
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end if;
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if(sREN='1' and sempty = '0') then
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Raddr_vect <= std_logic_vector(unsigned(Raddr_vect) + 1);
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Raddr_vect_d <= Raddr_vect;
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end if;
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end if;
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end process;
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--=============================
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-- Write section
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--=============================
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sWEN <= not WEN and not sfull;
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process (wclk,rstn)
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begin
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if(rstn='0')then
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Waddr_vect <= (others =>'0');
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Waddr_vect_d <= (others =>'1');
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sfull <= '0';
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elsif(wclk'event and wclk='1')then
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if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
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sfull <= '1'; --27/01/12
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elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then
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sfull <= '1';
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elsif(Raddr_vect/=Waddr_vect) then
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sfull <= '0';
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end if;
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if(sWEN='1' and sfull='0') then
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Waddr_vect <= std_logic_vector(unsigned(Waddr_vect) +1);
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Waddr_vect_d <= Waddr_vect;
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end if;
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end if;
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end process;
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full <= sFull;
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empty <= sEmpty;
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waddr <= Waddr_vect;
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raddr <= Raddr_vect;
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end architecture;
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