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Débug de la FIFO...
martin -
r103:e52d1f932b5e martin
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1 -- FFTamont.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity FFTamont is
7 generic(
8 Data_sz : integer range 1 to 32 := 16
9 );
10 port(
11 clk : in std_logic;
12 rstn : in std_logic;
13 Load : in std_logic;
14 Empty : in std_logic;
15 Full : in std_logic;
16 DATA : in std_logic_vector(Data_sz-1 downto 0);
17 Valid : out std_logic;
18 Read : out std_logic;
19 Data_re : out std_logic_vector(Data_sz-1 downto 0);
20 Data_im : out std_logic_vector(Data_sz-1 downto 0)
21 );
22 end entity;
23
24
25 architecture ar_FFTamont of FFTamont is
26
27 type etat is (eX,e0,e1,e2);
28 signal ect : etat;
29
30
31 begin
32
33 process(clk,rstn)
34 begin
35 if(rstn='0')then
36 ect <= eX;
37 Read <= '1';
38 Valid <= '0';
39 Data_re <= (others => '0');
40 Data_im <= (others => '0');
41
42 elsif(clk'event and clk='1')then
43
44 case ect is
45
46 when eX =>
47 if(Full='1')then
48 ect <= e0;
49 end if;
50
51 when e0 =>
52 Valid <= '0';
53 if(Load='1' and Empty='0')then
54 Read <= '0';
55 ect <= e1;
56 elsif(Empty='1')then
57 ect <= eX;
58 end if;
59
60 when e1 =>
61 Read <= '1';
62 Data_re <= DATA;
63 Data_im <= (others => '0');
64 Valid <= '1';
65 ect <= e0;
66
67 when e2 =>
68 null;
69
70 end case;
71 end if;
72 end process;
73
74 end architecture;
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1 -- FFTaval.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity FFTaval is
7 generic(
8 Data_sz : integer range 1 to 32 := 8
9 );
10 port(
11 clk : in std_logic;
12 rstn : in std_logic;
13 Ready : in std_logic;
14 Valid : in std_logic;
15 Full : in std_logic;
16 Data_re : in std_logic_vector(Data_sz-1 downto 0);
17 Data_im : in std_logic_vector(Data_sz-1 downto 0);
18 Read : out std_logic;
19 Write : out std_logic;
20 ReUse : out std_logic;
21 DATA : out std_logic_vector(Data_sz-1 downto 0)
22 );
23 end entity;
24
25
26 architecture ar_FFTaval of FFTaval is
27
28 type etat is (eX,e0,e1,e2,e3);
29 signal ect : etat;
30
31 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
32
33 signal sReady : std_logic;
34
35 begin
36
37 process(clk,rstn)
38 begin
39 if(rstn='0')then
40 ect <= e0;
41 Read <= '0';
42 Write <= '1';
43 Reuse <= '0';
44
45 elsif(clk'event and clk='1')then
46 sReady <= Ready;
47
48 case ect is
49
50 when e0 =>
51 Write <= '1';
52 if(sReady='0' and Ready='1' and full='0')then
53 Read <= '1';
54 ect <= e1;
55 end if;
56
57 when e1 =>
58 Read <= '0';
59 if(Valid='1' and full='0')then
60 DataTmp <= Data_im;
61 DATA <= Data_re;
62 Write <= '0';
63 ect <= e2;
64 elsif(full='1')then
65 ReUse <= '1';
66 ect <= e0;
67 end if;
68
69 when e2 =>
70 DATA <= DataTmp;
71 ect <= e3;
72
73 when e3 =>
74 Write <= '1';
75 if(Ready='1' and full='0')then
76 Read <= '1';
77 ect <= e1;
78 end if;
79
80 when eX =>
81 null;
82
83 end case;
84 end if;
85 end process;
86
87
88
89 end architecture;
90
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@@ -0,0 +1,109
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
26
27 entity Dispatch is
28 generic(
29 Data_SZ : integer := 32);
30 port(
31 clk : in std_logic;
32 reset : in std_logic;
33 Acq : in std_logic;
34 Data : in std_logic_vector(Data_SZ-1 downto 0);
35 Write : in std_logic;
36 Full : in std_logic_vector(1 downto 0);
37 -- Empty : in std_logic_vector(1 downto 0);
38 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
39 FifoWrite : out std_logic_vector(1 downto 0);
40 -- FifoFull : out std_logic;
41 Pong : out std_logic;
42 Error : out std_logic
43
44 );
45 end entity;
46
47
48 architecture ar_Dispatch of Dispatch is
49
50 type etat is (e0,e1,e2,e3);
51 signal ect : etat;
52
53 begin
54
55 process (clk,reset)
56 begin
57 if(reset='0')then
58 Pong <= '0';
59 Error <= '0';
60
61 elsif(clk' event and clk='1')then
62
63 case ect is
64
65 when e0 =>
66 if(Full(0) = '1')then
67 pong <= '1';
68 ect <= e1;
69 end if;
70
71 when e1 =>
72 if(Acq <= '1')then
73 Error <= '0';
74 pong <= '0';
75 ect <= e2;
76 else
77 Error <= '1';
78 ect <= e1;
79 end if;
80
81 when e2 =>
82 if(Full(1) = '1')then
83 pong <= '1';
84 ect <= e3;
85 end if;
86
87 when e3 =>
88 if(Acq <= '1')then
89 Error <= '0';
90 pong <= '0';
91 ect <= e0;
92 else
93 Error <= '1';
94 ect <= e3;
95 end if;
96
97 end case;
98
99 end if;
100 end process;
101
102 FifoData <= Data & Data;
103
104 with ect select
105 FifoWrite <= '1' & not Write when e0,
106 not Write & '1' when e2,
107 "11" when others;
108
109 end architecture; No newline at end of file
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@@ -0,0 +1,78
1 -- Bridge.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity Bridge is
7 generic(
8 Data_sz : integer range 1 to 32 := 16
9 );
10 port(
11 clk : in std_logic;
12 raz : in std_logic;
13 Start : in std_logic;
14 FullUp : in std_logic;
15 EmptyUp : in std_logic;
16 FullDown : in std_logic;
17 EmptyDown : in std_logic;
18 Write : out std_logic;
19 Read : out std_logic
20 );
21 end entity;
22
23
24 architecture ar_Bridge of Bridge is
25
26 type etat is (eX,e1,e2,e3);
27 signal ect : etat;
28
29 signal i : integer;
30
31 begin
32
33 process(clk,raz)
34 begin
35 if(raz='0')then
36 Write <= '1';
37 Read <= '1';
38 i <= 0;
39 ect <= eX;
40
41 elsif(clk'event and clk='1')then
42
43 case ect is
44
45 when eX =>
46 if(FullUp='1' and EmptyDown='1' and start='0')then
47 ect <= e1;
48 end if;
49
50 when e1 =>
51 Write <= '1';
52 if(EmptyUp='0')then
53 Read <= '0';
54 ect <= e2;
55 else
56 Read <= '1';
57 ect <= e3;
58 end if;
59
60 when e2 =>
61 Read <= '1';
62 if(FullDown='0')then
63 Write <= '0';
64 ect <= e1;
65 else
66 Write <= '1';
67 ect <= e3;
68 end if;
69
70 when e3 =>
71 null;
72
73 end case;
74 end if;
75 end process;
76
77
78 end architecture; No newline at end of file
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@@ -0,0 +1,77
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27 library techmap;
28 use techmap.gencomp.all;
29
30 entity lppFIFOx5 is
31 generic(
32 tech : integer := 0;
33 Data_sz : integer range 1 to 32 := 8;
34 Enable_ReUse : std_logic := '0'
35 );
36 port(
37 rst : in std_logic;
38 wclk : in std_logic;
39 rclk : in std_logic;
40 ReUse : in std_logic_vector(4 downto 0);
41 wen : in std_logic_vector(4 downto 0);
42 ren : in std_logic_vector(4 downto 0);
43 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
44 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
45 full : out std_logic_vector(4 downto 0);
46 empty : out std_logic_vector(4 downto 0)
47 );
48 end entity;
49
50
51 architecture ar_lppFIFOx5 of lppFIFOx5 is
52
53 begin
54
55 fifoB1 : entity work.lpp_fifo
56 generic map (tech,Enable_ReUse,Data_sz,8)
57 port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open);
58
59 fifoB2 : entity work.lpp_fifo
60 generic map (tech,Enable_ReUse,Data_sz,8)
61 port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open);
62
63 fifoB3 : entity work.lpp_fifo
64 generic map (tech,Enable_ReUse,Data_sz,8)
65 port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open);
66
67 fifoE1 : entity work.lpp_fifo
68 generic map (tech,Enable_ReUse,Data_sz,8)
69 port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open);
70
71 fifoE2 : entity work.lpp_fifo
72 generic map (tech,Enable_ReUse,Data_sz,8)
73 port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open);
74
75
76 end architecture;
77
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@@ -36,7 +36,7 package FILTERcfg is
36 36 --Bus Width and chanels number|
37 37 --____________________________|
38 38 constant ChanelsCount : integer := 1;
39 constant Sample_SZ : integer := 20;
39 constant Sample_SZ : integer := 18;
40 40 constant Coef_SZ : integer := 9;
41 41 constant CoefCntPerCel: integer := 6;
42 42 constant Cels_count : integer := 5;
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@@ -24,8 +24,8 use ieee.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25
26 26 entity RAM_CEL is
27 port( WD : in std_logic_vector(35 downto 0); RD : out
28 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
27 port( WD : in std_logic_vector(15 downto 0); RD : out
28 std_logic_vector(15 downto 0);WEN, REN : in std_logic;
29 29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
30 30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
31 31 ) ;
@@ -34,9 +34,9 end RAM_CEL;
34 34
35 35
36 36 architecture ar_RAM_CEL of RAM_CEL is
37 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
38 signal RAMarray : RAMarrayT:=(others => X"000000000");
39 signal RD_int : std_logic_vector(35 downto 0);
37 type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
38 signal RAMarray : RAMarrayT:=(others => X"0000");
39 signal RD_int : std_logic_vector(15 downto 0);
40 40
41 41 begin
42 42
@@ -46,7 +46,7 RD_int <= RAMarray(to_integer(unsigned
46 46 process(RWclk,reset)
47 47 begin
48 48 if reset = '0' then
49 RD <= (X"000000000");
49 RD <= (X"0000");
50 50 rst:for i in 0 to 255 loop
51 51 RAMarray(i) <= (others => '0');
52 52 end loop;
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@@ -66,7 +66,7 signal RADDR : std_logic_vector
66 66 signal WADDR : std_logic_vector(7 downto 0);
67 67 signal WADDR_D : std_logic_vector(7 downto 0);
68 68
69
69 SIGNAL WADDR_back_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
70 70
71 71 begin
72 72
@@ -150,25 +150,42 port map(
150 150 );
151 151
152 152
153
153 WADDR_backreg : REG
154 generic map(size => 8,initial_VALUE =>ChanelsCount*Cels_count*4-2)
155 port map(
156 reset => reset,
157 clk => clk, --SVG_ADDR,
158 D => WADDR_back_s,--RADDR,
159 Q => WADDR_back
160 );
161 WADDR_back_s <= RADDR WHEN SVG_ADDR = '1' ELSE WADDR_back;
154 162
155 WADDR_backreg :REG
156 generic map(size => 8,initial_VALUE =>ChanelsCouNT*Cels_count*4-2)
157 port map(
158 reset => reset,
159 clk => SVG_ADDR,
160 D => RADDR,
161 Q => WADDR_back
162 );
163 WADDR_backreg2 :entity work.REG
164 generic map(size => 8)
165 port map(
166 reset => reset,
167 clk => clk, --SVG_ADDR,
168 D => WADDR_back,
169 Q => WADDR_back_D
170 );
163 171
164 WADDR_backreg2 :REG
165 generic map(size => 8)
166 port map(
167 reset => reset,
168 clk => SVG_ADDR,
169 D => WADDR_back,
170 Q => WADDR_back_D
171 );
172 --WADDR_backreg :REG
173 --generic map(size => 8,initial_VALUE =>ChanelsCouNT*Cels_count*4-2)
174 --port map(
175 -- reset => reset,
176 -- clk => SVG_ADDR,
177 -- D => RADDR,
178 -- Q => WADDR_back
179 --);
180 --
181 --WADDR_backreg2 :REG
182 --generic map(size => 8)
183 --port map(
184 -- reset => reset,
185 -- clk => SVG_ADDR,
186 -- D => WADDR_back,
187 -- Q => WADDR_back_D
188 --
172 189
173 190 WDRreg :REG
174 191 generic map(size => Input_SZ_1)
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@@ -7,7 +7,7 use lpp.iir_filter.all;
7 7
8 8 entity Top_IIR is
9 9 generic(
10 Sample_SZ : integer := 20;
10 Sample_SZ : integer := 18;
11 11 ChanelsCount : integer := 1;
12 12 Coef_SZ : integer := 9;
13 13 CoefCntPerCel: integer := 6;
@@ -17,8 +17,8 generic(
17 17 clk : in std_logic;
18 18 sample_clk : in std_logic;
19 19 -- BP : in std_logic;
20 BPinput : in std_logic_vector(3 downto 0);
21 LVLinput : in std_logic_vector(11 downto 0);
20 -- BPinput : in std_logic_vector(3 downto 0);
21 LVLinput : in std_logic_vector(15 downto 0);
22 22 INsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
23 23 OUTsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
24 24 );
@@ -48,7 +48,7 end generate;
48 48 -- sample_temp(k) <= BP;
49 49 --end generate;
50 50
51 sample_int <= BPinput(3) & BPinput(3) & BPinput(3) & BPinput(3) & BPinput & LVLinput;
51 sample_int <= LVLinput(15) & LVLinput(15) & LVLinput;
52 52 INsample <= sample_in;
53 53 OUTsample <= sample_out;
54 54
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@@ -102,7 +102,7 end component;
102 102
103 103 component Top_IIR is
104 104 generic(
105 Sample_SZ : integer := 20;
105 Sample_SZ : integer := 18;
106 106 ChanelsCount : integer := 1;
107 107 Coef_SZ : integer := 9;
108 108 CoefCntPerCel: integer := 6;
@@ -112,8 +112,8 generic(
112 112 clk : in std_logic;
113 113 sample_clk : in std_logic;
114 114 -- BP : in std_logic;
115 BPinput : in std_logic_vector(3 downto 0);
116 LVLinput : in std_logic_vector(11 downto 0);
115 -- BPinput : in std_logic_vector(3 downto 0);
116 LVLinput : in std_logic_vector(15 downto 0);
117 117 INsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
118 118 OUTsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
119 119 );
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@@ -63,6 +63,8 begin
63 63 Read <= (others => '1');
64 64 Valid <= '0';
65 65 FifoCpt <= 1;
66 Data_re <= (others => '0');
67 Data_im <= (others => '0');
66 68
67 69 elsif(clk'event and clk='1')then
68 70
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@@ -125,6 +125,42 port(
125 125 );
126 126 end component;
127 127
128 component FFTamont is
129 generic(
130 Data_sz : integer range 1 to 32 := 16
131 );
132 port(
133 clk : in std_logic;
134 rstn : in std_logic;
135 Load : in std_logic;
136 Empty : in std_logic;
137 Full : in std_logic;
138 DATA : in std_logic_vector(Data_sz-1 downto 0);
139 Valid : out std_logic;
140 Read : out std_logic;
141 Data_re : out std_logic_vector(Data_sz-1 downto 0);
142 Data_im : out std_logic_vector(Data_sz-1 downto 0)
143 );
144 end component;
145
146 component FFTaval is
147 generic(
148 Data_sz : integer range 1 to 32 := 8
149 );
150 port(
151 clk : in std_logic;
152 rstn : in std_logic;
153 Ready : in std_logic;
154 Valid : in std_logic;
155 Full : in std_logic;
156 Data_re : in std_logic_vector(Data_sz-1 downto 0);
157 Data_im : in std_logic_vector(Data_sz-1 downto 0);
158 Read : out std_logic;
159 Write : out std_logic;
160 ReUse : out std_logic;
161 DATA : out std_logic_vector(Data_sz-1 downto 0)
162 );
163 end component;
128 164 --==============================================================|
129 165 --================== IP VHDL de la FFT actel ===================|
130 166 --================ non partag� dans la VHD_Lib =================|
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@@ -32,7 +32,7 port(
32 32 Valid : in std_logic;
33 33 Conjugate : in std_logic;
34 34 Res : in std_logic_vector(Result_SZ-1 downto 0);
35 Full : in std_logic;
35 -- Full : in std_logic;
36 36 WriteFIFO : out std_logic;
37 37 Received : out std_logic;
38 38 Result : out std_logic_vector(Result_SZ-1 downto 0)
@@ -63,7 +63,7 begin
63 63
64 64 case ect is
65 65 when st0 =>
66 if(Full='0' and Valid='1')then
66 if(Valid='1')then--if(Full='0' and Valid='1')then
67 67 Result <= Res;
68 68 WriteFIFO <= '1';
69 69 Received <= '1';
@@ -84,7 +84,7 begin
84 84 end if;
85 85
86 86 when st1 =>
87 if(Full='0' and Valid='1')then
87 if(Valid='1')then--if(Full='0' and Valid='1')then
88 88 Result <= Res;
89 89 WriteFIFO <= '1';
90 90 Received <= '0';
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@@ -35,7 +35,7 port(
35 35 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
36 36 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
37 37 Statu : in std_logic_vector(3 downto 0);
38 FullFIFO : in std_logic;
38 -- FullFIFO : in std_logic;
39 39 ReadFIFO : out std_logic_vector(1 downto 0);
40 40 WriteFIFO : out std_logic;
41 41 Result : out std_logic_vector(Result_SZ-1 downto 0)
@@ -70,7 +70,7 CALC0 : Matrix
70 70
71 71 RES0 : GetResult
72 72 generic map(Result_SZ)
73 port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,FullFIFO,WriteFIFO,Received_int,Result);
73 port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO
74 74
75 75
76 76 With Statu select
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@@ -86,7 +86,7 port(
86 86 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
87 87 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
88 88 Statu : in std_logic_vector(3 downto 0);
89 FullFIFO : in std_logic;
89 -- FullFIFO : in std_logic;
90 90 ReadFIFO : out std_logic_vector(1 downto 0);
91 91 WriteFIFO : out std_logic;
92 92 Result : out std_logic_vector(Result_SZ-1 downto 0)
@@ -120,7 +120,7 port(
120 120 Valid : in std_logic;
121 121 Conjugate : in std_logic;
122 122 Res : in std_logic_vector(Result_SZ-1 downto 0);
123 Full : in std_logic;
123 -- Full : in std_logic;
124 124 WriteFIFO : out std_logic;
125 125 Received : out std_logic;
126 126 Result : out std_logic_vector(Result_SZ-1 downto 0)
@@ -148,6 +148,24 port(
148 148 end component;
149 149
150 150
151 component Dispatch is
152 generic(
153 Data_SZ : integer := 32);
154 port(
155 clk : in std_logic;
156 reset : in std_logic;
157 Acq : in std_logic;
158 Data : in std_logic_vector(Data_SZ-1 downto 0);
159 Write : in std_logic;
160 Full : in std_logic_vector(1 downto 0);
161 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
162 FifoWrite : out std_logic_vector(1 downto 0);
163 Pong : out std_logic;
164 Error : out std_logic
165 );
166 end component;
167
168
151 169 component DriveInputs is
152 170 port(
153 171 clk : in std_logic;
Show file before | Show file after | Hide comments
@@ -87,37 +87,41 type FIFO_ctrlr_Reg_Vec is array(FifoCnt
87 87 type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0);
88 88 type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0);
89 89
90 signal Rec : FIFO_ctrlr_Reg_Vec;
91 signal PRdata : std_logic_vector(31 downto 0);
92 signal FIFO_ID : std_logic_vector(31 downto 0);
93 signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
94 signal sFull : std_logic_vector(FifoCnt-1 downto 0);
95 signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
96 signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
97 signal sWen : std_logic_vector(FifoCnt-1 downto 0);
98 signal sRen : std_logic_vector(FifoCnt-1 downto 0);
99 signal sRclk : std_logic;
100 signal sWclk : std_logic;
101 signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
102 signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
103 signal sRDATA : fifodatabus;
104 signal sWDATA : fifodatabus;
105 signal sWADDR : fifoaddressbus;
106 signal sRADDR : fifoaddressbus;
107 signal sReUse : std_logic_vector(FifoCnt-1 downto 0); --05/06/12
108 signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0); --05/06/12
90 signal Rec : FIFO_ctrlr_Reg_Vec;
91 signal PRdata : std_logic_vector(31 downto 0);
92 signal FIFO_ID : std_logic_vector(31 downto 0);
93 signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
94 signal sFull : std_logic_vector(FifoCnt-1 downto 0);
95 signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
96 signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
97 signal sWen : std_logic_vector(FifoCnt-1 downto 0);
98 signal sRen : std_logic_vector(FifoCnt-1 downto 0);
99 signal sRclk : std_logic;
100 signal sWclk : std_logic;
101 signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
102 signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
103 signal sRDATA : fifodatabus;
104 signal sWDATA : fifodatabus;
105 signal sWADDR : fifoaddressbus;
106 signal sRADDR : fifoaddressbus;
107 signal sReUse : std_logic_vector(FifoCnt-1 downto 0);
108 signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0);
109
110 signal regDataValid : std_logic_vector(FifoCnt-1 downto 0);
111 signal regData : fifodatabus;
112 signal regREN : std_logic_vector(FifoCnt-1 downto 0);
109 113
110 114 type state_t is (idle,Read);
111 115 signal fiforeadfsmst : state_t;
112 116
113 117 begin
114 118
115 FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
116 FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
117 FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
119 FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
120 FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
121 FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
118 122
119 123
120 Write : if W /= 0 generate
124 Writeint : if W /= 0 generate
121 125 FIFO_ID(4) <= '1';
122 126 sWen <= sWen_APB;
123 127 sReUse <= sReUse_APB;
@@ -137,7 +141,7 Writeext : if W = 0 generate
137 141 end generate;
138 142 end generate;
139 143
140 Read : if R /= 0 generate
144 Readint : if R /= 0 generate
141 145 FIFO_ID(5) <= '1';
142 146 sRen <= sRen_APB;
143 147 srclk <= clk;
@@ -159,18 +163,16 ctrlregs: for i in 0 to FifoCnt-1 genera
159 163 RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
160 164 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
161 165 Rec(i).FIFO_Ctrl(16) <= sFull(i);
162 --Rec(i).FIFO_Ctrl(17) <= Rec(i).FIFO_Ctrl(1); --27/01/12
163 sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12
164 Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; --27/01/12
165 Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; --27/01/12
166 sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1);
167 Rec(i).FIFO_Ctrl(3 downto 2) <= "00";
168 Rec(i).FIFO_Ctrl(19 downto 17) <= "000";
166 169 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
167 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i); ---|free|Waddrs|Full||free|Raddrs|empty|
168 end generate; -- 31 17 16 15 1 0
170 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);
171 end generate;
169 172
170 173 Empty <= sEmpty;
171 174 Full <= sFull;
172 175
173
174 176 fifos: for i in 0 to FifoCnt-1 generate
175 177 FIFO0 : lpp_fifo
176 178 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
@@ -182,17 +184,16 end generate;
182 184 if(rst='0')then
183 185 rstloop1: for i in 0 to FifoCnt-1 loop
184 186 Rec(i).FIFO_Wdata <= (others => '0');
185 Rec(i).FIFO_Ctrl(1) <= '0'; --27/01/12
186 --Rec(i).FIFO_Ctrl(17) <= '0';
187 Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse
187 188 sWen_APB(i) <= '1';
188 189 end loop;
189 190 elsif(clk'event and clk='1')then
191
190 192 --APB Write OP
191 193 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
192 194 writelp: for i in 0 to FifoCnt-1 loop
193 195 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
194 196 Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
195 --Rec(i).FIFO_Ctrl(17) <= apbi.pwdata(17);
196 197 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
197 198 Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
198 199 sWen_APB(i) <= '0';
@@ -201,6 +202,7 end generate;
201 202 else
202 203 sWen_APB <= (others =>'1');
203 204 end if;
205
204 206 --APB Read OP
205 207 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
206 208 if(apbi.paddr(abits-1 downto 2)="000000") then
@@ -212,16 +214,16 end generate;
212 214 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
213 215 PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
214 216 end if;
215 end loop;
216 end if;
217 end loop;
218 end if;
217 219 end if;
218 220 end if;
221
219 222 apbo.pconfig <= pconfig;
223
220 224 end process;
221 225 apbo.prdata <= PRdata when apbi.penable = '1';
222 226
223
224
225 227 process(rst,clk)
226 228 begin
227 229 if(rst='0')then
@@ -256,35 +258,6 process(rst,clk)
256 258 fiforeadfsmst <= idle;
257 259 end case;
258 260 end if;
259 end process;
260
261
262 end ar_APB_FIFO;
263
264
265
266
267
268
269
270
271
272
273
261 end process;
274 262
275
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281
282
283
284
285
286
287
288
289
290
263 end ar_APB_FIFO; No newline at end of file
Show file before | Show file after | Hide comments
@@ -24,6 +24,7 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 library lpp;
26 26 use lpp.lpp_memory.all;
27 use lpp.iir_filter.all;
27 28 library techmap;
28 29 use techmap.gencomp.all;
29 30
@@ -36,7 +37,7 generic(
36 37 );
37 38 port(
38 39 rstn : in std_logic;
39 ReUse : in std_logic; --27/01/12
40 ReUse : in std_logic;
40 41 rclk : in std_logic;
41 42 ren : in std_logic;
42 43 rdata : out std_logic_vector(DataSz-1 downto 0);
@@ -53,85 +54,94 end entity;
53 54
54 55 architecture ar_lpp_fifo of lpp_fifo is
55 56
56 signal sFull : std_logic:='0';
57 signal sEmpty : std_logic:='1';
58 signal sREN : std_logic:='0';
59 signal sWEN : std_logic:='0';
57 signal sFull : std_logic;
58 signal sFull_s : std_logic;
59 signal sEmpty_s : std_logic;
60
61 signal sEmpty : std_logic;
62 signal sREN : std_logic;
63 signal sWEN : std_logic;
64 signal sRE : std_logic;
65 signal sWE : std_logic;
60 66
61 67 signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
62 68 signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
63 signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
64 signal Raddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
69 signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
70 signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
65 71
66 72 begin
67 73
74 --==================================================================================
75 -- /!\ syncram_2p Write et Read actif a l'�tat haut /!\
76 -- A l'inverse de RAM_CEL !!!
77 --==================================================================================
68 78 SRAM : syncram_2p
69 generic map(tech,abits,DataSz)
70 port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata);
71
79 generic map(tech,abits,DataSz)
80 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
81 --==================================================================================
72 82 --RAM0: entity work.RAM_CEL
73 -- generic map(abits, DataSz)
74 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn);
75
83 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
84 --==================================================================================
76 85
77 86 --=============================
78 87 -- Read section
79 88 --=============================
80 sREN <= not REN and not sempty;
89 sREN <= REN or sEmpty;
90 sRE <= not sREN;
91
92 sEmpty_s <= '0' when ReUse = '1' and Enable_ReUse='1' else
93 '1' when sEmpty = '1' and Wen = '1' else
94 '1' when sEmpty = '0' and (Wen = '1' and Ren = '0' and Raddr_vect_s = Waddr_vect) else
95 '0';
96
97 Raddr_vect_s <= std_logic_vector(unsigned(Raddr_vect) +1);
81 98
82 99 process (rclk,rstn)
83 100 begin
84 101 if(rstn='0')then
85 102 Raddr_vect <= (others =>'0');
86 Raddr_vect_d <= (others =>'1');
87 103 sempty <= '1';
88 elsif(rclk'event and rclk='1')then
89 if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
90 sempty <= '0'; --27/01/12
91 elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then
92 sempty <= '1';
93 elsif(Raddr_vect/=Waddr_vect) then
94 sempty <= '0';
104 elsif(rclk'event and rclk='1')then
105 sEmpty <= sempty_s;
106
107 if(sREN='0' and sempty = '0')then
108 Raddr_vect <= Raddr_vect_s;
95 109 end if;
96 if(sREN='1' and sempty = '0') then
97 Raddr_vect <= std_logic_vector(unsigned(Raddr_vect) + 1);
98 Raddr_vect_d <= Raddr_vect;
99 end if;
100
110
101 111 end if;
102 112 end process;
103 113
104 114 --=============================
105 115 -- Write section
106 116 --=============================
107 sWEN <= not WEN and not sfull;
117 sWEN <= WEN or sFull;
118 sWE <= not sWEN;
119
120 sFull_s <= '1' when ReUse = '1' and Enable_ReUse='1' else
121 '1' when Waddr_vect_s = Raddr_vect and REN = '1' and WEN = '0' else
122 '1' when sFull = '1' and REN = '1' else
123 '0';
124
125 Waddr_vect_s <= std_logic_vector(unsigned(Waddr_vect) +1);
108 126
109 127 process (wclk,rstn)
110 128 begin
111 129 if(rstn='0')then
112 130 Waddr_vect <= (others =>'0');
113 Waddr_vect_d <= (others =>'1');
114 131 sfull <= '0';
115 132 elsif(wclk'event and wclk='1')then
116 if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
117 sfull <= '1'; --27/01/12
118 elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then
119 sfull <= '1';
120 elsif(Raddr_vect/=Waddr_vect) then
121 sfull <= '0';
133 sfull <= sfull_s;
134
135 if(sWEN='0' and sfull='0')then
136 Waddr_vect <= Waddr_vect_s;
122 137 end if;
123 if(sWEN='1' and sfull='0') then
124 Waddr_vect <= std_logic_vector(unsigned(Waddr_vect) +1);
125 Waddr_vect_d <= Waddr_vect;
126 end if;
127
128
138
129 139 end if;
130 140 end process;
131 141
132 142
133 full <= sFull;
134 empty <= sEmpty;
143 full <= sFull_s;
144 empty <= sEmpty_s;
135 145 waddr <= Waddr_vect;
136 146 raddr <= Raddr_vect;
137 147
Show file before | Show file after | Hide comments
@@ -116,6 +116,43 port(
116 116 );
117 117 end component;
118 118
119 component lppFIFOx5 is
120 generic(
121 tech : integer := 0;
122 Data_sz : integer range 1 to 32 := 16;
123 Addr_sz : integer range 2 to 12 := 8;
124 Enable_ReUse : std_logic := '0'
125 );
126 port(
127 rst : in std_logic;
128 wclk : in std_logic;
129 rclk : in std_logic;
130 ReUse : in std_logic_vector(4 downto 0);
131 wen : in std_logic_vector(4 downto 0);
132 ren : in std_logic_vector(4 downto 0);
133 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
134 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
135 full : out std_logic_vector(4 downto 0);
136 empty : out std_logic_vector(4 downto 0)
137 );
138 end component;
139
140 component Bridge is
141 generic(
142 Data_sz : integer range 1 to 32 := 16
143 );
144 port(
145 clk : in std_logic;
146 raz : in std_logic;
147 Start : in std_logic;
148 FullUp : in std_logic;
149 EmptyUp : in std_logic;
150 FullDown : in std_logic;
151 EmptyDown : in std_logic;
152 Write : out std_logic;
153 Read : out std_logic
154 );
155 end component;
119 156
120 157 component ssram_plugin is
121 158 generic (tech : integer := 0);
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