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ajout de 3 registres apb_lfr pour donner un acces direct aux données V,E1,E2 du channel a f3
pellion -
r474:e1a66be1bcbe (MINI-LFR) WFP_MS-0-1-37 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_50 : STD_LOGIC;
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
195
196 BEGIN -- beh
196 BEGIN -- beh
197
197
198 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
199 -- CLK
199 -- CLK
200 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
201
201
202 --PROCESS(clk_50)
202 --PROCESS(clk_50)
203 --BEGIN
203 --BEGIN
204 -- IF clk_50'EVENT AND clk_50 = '1' THEN
204 -- IF clk_50'EVENT AND clk_50 = '1' THEN
205 -- clk_50_s <= NOT clk_50_s;
205 -- clk_50_s <= NOT clk_50_s;
206 -- END IF;
206 -- END IF;
207 --END PROCESS;
207 --END PROCESS;
208
208
209 --PROCESS(clk_50_s)
209 --PROCESS(clk_50_s)
210 --BEGIN
210 --BEGIN
211 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
211 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
212 -- clk_25 <= NOT clk_25;
212 -- clk_25 <= NOT clk_25;
213 -- END IF;
213 -- END IF;
214 --END PROCESS;
214 --END PROCESS;
215
215
216 --PROCESS(clk_49)
216 --PROCESS(clk_49)
217 --BEGIN
217 --BEGIN
218 -- IF clk_49'EVENT AND clk_49 = '1' THEN
218 -- IF clk_49'EVENT AND clk_49 = '1' THEN
219 -- clk_24 <= NOT clk_24;
219 -- clk_24 <= NOT clk_24;
220 -- END IF;
220 -- END IF;
221 --END PROCESS;
221 --END PROCESS;
222
222
223 --PROCESS(clk_25)
223 --PROCESS(clk_25)
224 --BEGIN
224 --BEGIN
225 -- IF clk_25'EVENT AND clk_25 = '1' THEN
225 -- IF clk_25'EVENT AND clk_25 = '1' THEN
226 -- rstn_25 <= reset;
226 -- rstn_25 <= reset;
227 -- END IF;
227 -- END IF;
228 --END PROCESS;
228 --END PROCESS;
229
229
230 PROCESS (clk_50, reset)
230 PROCESS (clk_50, reset)
231 BEGIN -- PROCESS
231 BEGIN -- PROCESS
232 IF reset = '0' THEN -- asynchronous reset (active low)
232 IF reset = '0' THEN -- asynchronous reset (active low)
233 clk_50_s <= '0';
233 clk_50_s <= '0';
234 rstn_50 <= '0';
234 rstn_50 <= '0';
235 rstn_50_d1 <= '0';
235 rstn_50_d1 <= '0';
236 rstn_50_d2 <= '0';
236 rstn_50_d2 <= '0';
237 rstn_50_d3 <= '0';
237 rstn_50_d3 <= '0';
238
238
239 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
239 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
240 clk_50_s <= NOT clk_50_s;
240 clk_50_s <= NOT clk_50_s;
241 rstn_50_d1 <= '1';
241 rstn_50_d1 <= '1';
242 rstn_50_d2 <= rstn_50_d1;
242 rstn_50_d2 <= rstn_50_d1;
243 rstn_50_d3 <= rstn_50_d2;
243 rstn_50_d3 <= rstn_50_d2;
244 rstn_50 <= rstn_50_d3;
244 rstn_50 <= rstn_50_d3;
245 END IF;
245 END IF;
246 END PROCESS;
246 END PROCESS;
247
247
248 PROCESS (clk_50_s, rstn_50)
248 PROCESS (clk_50_s, rstn_50)
249 BEGIN -- PROCESS
249 BEGIN -- PROCESS
250 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
250 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
251 clk_25 <= '0';
251 clk_25 <= '0';
252 rstn_25 <= '0';
252 rstn_25 <= '0';
253 rstn_25_d1 <= '0';
253 rstn_25_d1 <= '0';
254 rstn_25_d2 <= '0';
254 rstn_25_d2 <= '0';
255 rstn_25_d3 <= '0';
255 rstn_25_d3 <= '0';
256 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
256 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
257 clk_25 <= NOT clk_25;
257 clk_25 <= NOT clk_25;
258 rstn_25_d1 <= '1';
258 rstn_25_d1 <= '1';
259 rstn_25_d2 <= rstn_25_d1;
259 rstn_25_d2 <= rstn_25_d1;
260 rstn_25_d3 <= rstn_25_d2;
260 rstn_25_d3 <= rstn_25_d2;
261 rstn_25 <= rstn_25_d3;
261 rstn_25 <= rstn_25_d3;
262 END IF;
262 END IF;
263 END PROCESS;
263 END PROCESS;
264
264
265 PROCESS (clk_49, reset)
265 PROCESS (clk_49, reset)
266 BEGIN -- PROCESS
266 BEGIN -- PROCESS
267 IF reset = '0' THEN -- asynchronous reset (active low)
267 IF reset = '0' THEN -- asynchronous reset (active low)
268 clk_24 <= '0';
268 clk_24 <= '0';
269 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
269 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
270 clk_24 <= NOT clk_24;
270 clk_24 <= NOT clk_24;
271 END IF;
271 END IF;
272 END PROCESS;
272 END PROCESS;
273
273
274 -----------------------------------------------------------------------------
274 -----------------------------------------------------------------------------
275
275
276 PROCESS (clk_25, rstn_25)
276 PROCESS (clk_25, rstn_25)
277 BEGIN -- PROCESS
277 BEGIN -- PROCESS
278 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
278 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
279 LED0 <= '0';
279 LED0 <= '0';
280 LED1 <= '0';
280 LED1 <= '0';
281 LED2 <= '0';
281 LED2 <= '0';
282 --IO1 <= '0';
282 --IO1 <= '0';
283 --IO2 <= '1';
283 --IO2 <= '1';
284 --IO3 <= '0';
284 --IO3 <= '0';
285 --IO4 <= '0';
285 --IO4 <= '0';
286 --IO5 <= '0';
286 --IO5 <= '0';
287 --IO6 <= '0';
287 --IO6 <= '0';
288 --IO7 <= '0';
288 --IO7 <= '0';
289 --IO8 <= '0';
289 --IO8 <= '0';
290 --IO9 <= '0';
290 --IO9 <= '0';
291 --IO10 <= '0';
291 --IO10 <= '0';
292 --IO11 <= '0';
292 --IO11 <= '0';
293 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
293 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
294 LED0 <= '0';
294 LED0 <= '0';
295 LED1 <= '1';
295 LED1 <= '1';
296 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
296 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
297 --IO1 <= '1';
297 --IO1 <= '1';
298 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
298 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
299 --IO3 <= ADC_SDO(0);
299 --IO3 <= ADC_SDO(0);
300 --IO4 <= ADC_SDO(1);
300 --IO4 <= ADC_SDO(1);
301 --IO5 <= ADC_SDO(2);
301 --IO5 <= ADC_SDO(2);
302 --IO6 <= ADC_SDO(3);
302 --IO6 <= ADC_SDO(3);
303 --IO7 <= ADC_SDO(4);
303 --IO7 <= ADC_SDO(4);
304 --IO8 <= ADC_SDO(5);
304 --IO8 <= ADC_SDO(5);
305 --IO9 <= ADC_SDO(6);
305 --IO9 <= ADC_SDO(6);
306 --IO10 <= ADC_SDO(7);
306 --IO10 <= ADC_SDO(7);
307 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
307 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
308 END IF;
308 END IF;
309 END PROCESS;
309 END PROCESS;
310
310
311 PROCESS (clk_24, rstn_25)
311 PROCESS (clk_24, rstn_25)
312 BEGIN -- PROCESS
312 BEGIN -- PROCESS
313 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
313 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
314 I00_s <= '0';
314 I00_s <= '0';
315 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
315 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
316 I00_s <= NOT I00_s;
316 I00_s <= NOT I00_s;
317 END IF;
317 END IF;
318 END PROCESS;
318 END PROCESS;
319 -- IO0 <= I00_s;
319 -- IO0 <= I00_s;
320
320
321 --UARTs
321 --UARTs
322 nCTS1 <= '1';
322 nCTS1 <= '1';
323 nCTS2 <= '1';
323 nCTS2 <= '1';
324 nDCD2 <= '1';
324 nDCD2 <= '1';
325
325
326 --EXT CONNECTOR
326 --EXT CONNECTOR
327
327
328 --SPACE WIRE
328 --SPACE WIRE
329
329
330 leon3_soc_1 : leon3_soc
330 leon3_soc_1 : leon3_soc
331 GENERIC MAP (
331 GENERIC MAP (
332 fabtech => apa3e,
332 fabtech => apa3e,
333 memtech => apa3e,
333 memtech => apa3e,
334 padtech => inferred,
334 padtech => inferred,
335 clktech => inferred,
335 clktech => inferred,
336 disas => 0,
336 disas => 0,
337 dbguart => 0,
337 dbguart => 0,
338 pclow => 2,
338 pclow => 2,
339 clk_freq => 25000,
339 clk_freq => 25000,
340 NB_CPU => 1,
340 NB_CPU => 1,
341 ENABLE_FPU => 1,
341 ENABLE_FPU => 1,
342 FPU_NETLIST => 0,
342 FPU_NETLIST => 0,
343 ENABLE_DSU => 1,
343 ENABLE_DSU => 1,
344 ENABLE_AHB_UART => 1,
344 ENABLE_AHB_UART => 1,
345 ENABLE_APB_UART => 1,
345 ENABLE_APB_UART => 1,
346 ENABLE_IRQMP => 1,
346 ENABLE_IRQMP => 1,
347 ENABLE_GPT => 1,
347 ENABLE_GPT => 1,
348 NB_AHB_MASTER => NB_AHB_MASTER,
348 NB_AHB_MASTER => NB_AHB_MASTER,
349 NB_AHB_SLAVE => NB_AHB_SLAVE,
349 NB_AHB_SLAVE => NB_AHB_SLAVE,
350 NB_APB_SLAVE => NB_APB_SLAVE,
350 NB_APB_SLAVE => NB_APB_SLAVE,
351 ADDRESS_SIZE => 20)
351 ADDRESS_SIZE => 20)
352 PORT MAP (
352 PORT MAP (
353 clk => clk_25,
353 clk => clk_25,
354 reset => rstn_25,
354 reset => rstn_25,
355 errorn => errorn,
355 errorn => errorn,
356 ahbrxd => TXD1,
356 ahbrxd => TXD1,
357 ahbtxd => RXD1,
357 ahbtxd => RXD1,
358 urxd1 => TXD2,
358 urxd1 => TXD2,
359 utxd1 => RXD2,
359 utxd1 => RXD2,
360 address => SRAM_A,
360 address => SRAM_A,
361 data => SRAM_DQ,
361 data => SRAM_DQ,
362 nSRAM_BE0 => SRAM_nBE(0),
362 nSRAM_BE0 => SRAM_nBE(0),
363 nSRAM_BE1 => SRAM_nBE(1),
363 nSRAM_BE1 => SRAM_nBE(1),
364 nSRAM_BE2 => SRAM_nBE(2),
364 nSRAM_BE2 => SRAM_nBE(2),
365 nSRAM_BE3 => SRAM_nBE(3),
365 nSRAM_BE3 => SRAM_nBE(3),
366 nSRAM_WE => SRAM_nWE,
366 nSRAM_WE => SRAM_nWE,
367 nSRAM_CE => SRAM_CE,
367 nSRAM_CE => SRAM_CE,
368 nSRAM_OE => SRAM_nOE,
368 nSRAM_OE => SRAM_nOE,
369
369
370 apbi_ext => apbi_ext,
370 apbi_ext => apbi_ext,
371 apbo_ext => apbo_ext,
371 apbo_ext => apbo_ext,
372 ahbi_s_ext => ahbi_s_ext,
372 ahbi_s_ext => ahbi_s_ext,
373 ahbo_s_ext => ahbo_s_ext,
373 ahbo_s_ext => ahbo_s_ext,
374 ahbi_m_ext => ahbi_m_ext,
374 ahbi_m_ext => ahbi_m_ext,
375 ahbo_m_ext => ahbo_m_ext);
375 ahbo_m_ext => ahbo_m_ext);
376
376
377 -------------------------------------------------------------------------------
377 -------------------------------------------------------------------------------
378 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
378 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
379 -------------------------------------------------------------------------------
379 -------------------------------------------------------------------------------
380 apb_lfr_time_management_1 : apb_lfr_time_management
380 apb_lfr_time_management_1 : apb_lfr_time_management
381 GENERIC MAP (
381 GENERIC MAP (
382 pindex => 6,
382 pindex => 6,
383 paddr => 6,
383 paddr => 6,
384 pmask => 16#fff#,
384 pmask => 16#fff#,
385 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
385 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
386 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
386 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
387 PORT MAP (
387 PORT MAP (
388 clk25MHz => clk_25,
388 clk25MHz => clk_25,
389 clk24_576MHz => clk_24, -- 49.152MHz/2
389 clk24_576MHz => clk_24, -- 49.152MHz/2
390 resetn => rstn_25,
390 resetn => rstn_25,
391 grspw_tick => swno.tickout,
391 grspw_tick => swno.tickout,
392 apbi => apbi_ext,
392 apbi => apbi_ext,
393 apbo => apbo_ext(6),
393 apbo => apbo_ext(6),
394 coarse_time => coarse_time,
394 coarse_time => coarse_time,
395 fine_time => fine_time,
395 fine_time => fine_time,
396 LFR_soft_rstn => LFR_soft_rstn
396 LFR_soft_rstn => LFR_soft_rstn
397 );
397 );
398
398
399 -----------------------------------------------------------------------
399 -----------------------------------------------------------------------
400 --- SpaceWire --------------------------------------------------------
400 --- SpaceWire --------------------------------------------------------
401 -----------------------------------------------------------------------
401 -----------------------------------------------------------------------
402
402
403 SPW_EN <= '1';
403 SPW_EN <= '1';
404
404
405 spw_clk <= clk_50_s;
405 spw_clk <= clk_50_s;
406 spw_rxtxclk <= spw_clk;
406 spw_rxtxclk <= spw_clk;
407 spw_rxclkn <= NOT spw_rxtxclk;
407 spw_rxclkn <= NOT spw_rxtxclk;
408
408
409 -- PADS for SPW1
409 -- PADS for SPW1
410 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
410 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
411 PORT MAP (SPW_NOM_DIN, dtmp(0));
411 PORT MAP (SPW_NOM_DIN, dtmp(0));
412 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
412 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
413 PORT MAP (SPW_NOM_SIN, stmp(0));
413 PORT MAP (SPW_NOM_SIN, stmp(0));
414 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
414 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
415 PORT MAP (SPW_NOM_DOUT, swno.d(0));
415 PORT MAP (SPW_NOM_DOUT, swno.d(0));
416 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
416 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_NOM_SOUT, swno.s(0));
417 PORT MAP (SPW_NOM_SOUT, swno.s(0));
418 -- PADS FOR SPW2
418 -- PADS FOR SPW2
419 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
419 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
420 PORT MAP (SPW_RED_SIN, dtmp(1));
420 PORT MAP (SPW_RED_SIN, dtmp(1));
421 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
421 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
422 PORT MAP (SPW_RED_DIN, stmp(1));
422 PORT MAP (SPW_RED_DIN, stmp(1));
423 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
423 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
424 PORT MAP (SPW_RED_DOUT, swno.d(1));
424 PORT MAP (SPW_RED_DOUT, swno.d(1));
425 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
425 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
426 PORT MAP (SPW_RED_SOUT, swno.s(1));
426 PORT MAP (SPW_RED_SOUT, swno.s(1));
427
427
428 -- GRSPW PHY
428 -- GRSPW PHY
429 --spw1_input: if CFG_SPW_GRSPW = 1 generate
429 --spw1_input: if CFG_SPW_GRSPW = 1 generate
430 spw_inputloop : FOR j IN 0 TO 1 GENERATE
430 spw_inputloop : FOR j IN 0 TO 1 GENERATE
431 spw_phy0 : grspw_phy
431 spw_phy0 : grspw_phy
432 GENERIC MAP(
432 GENERIC MAP(
433 tech => apa3e,
433 tech => apa3e,
434 rxclkbuftype => 1,
434 rxclkbuftype => 1,
435 scantest => 0)
435 scantest => 0)
436 PORT MAP(
436 PORT MAP(
437 rxrst => swno.rxrst,
437 rxrst => swno.rxrst,
438 di => dtmp(j),
438 di => dtmp(j),
439 si => stmp(j),
439 si => stmp(j),
440 rxclko => spw_rxclk(j),
440 rxclko => spw_rxclk(j),
441 do => swni.d(j),
441 do => swni.d(j),
442 ndo => swni.nd(j*5+4 DOWNTO j*5),
442 ndo => swni.nd(j*5+4 DOWNTO j*5),
443 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
443 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
444 END GENERATE spw_inputloop;
444 END GENERATE spw_inputloop;
445
445
446 swni.rmapnodeaddr <= (OTHERS => '0');
446 swni.rmapnodeaddr <= (OTHERS => '0');
447
447
448 -- SPW core
448 -- SPW core
449 sw0 : grspwm GENERIC MAP(
449 sw0 : grspwm GENERIC MAP(
450 tech => apa3e,
450 tech => apa3e,
451 hindex => 1,
451 hindex => 1,
452 pindex => 5,
452 pindex => 5,
453 paddr => 5,
453 paddr => 5,
454 pirq => 11,
454 pirq => 11,
455 sysfreq => 25000, -- CPU_FREQ
455 sysfreq => 25000, -- CPU_FREQ
456 rmap => 1,
456 rmap => 1,
457 rmapcrc => 1,
457 rmapcrc => 1,
458 fifosize1 => 16,
458 fifosize1 => 16,
459 fifosize2 => 16,
459 fifosize2 => 16,
460 rxclkbuftype => 1,
460 rxclkbuftype => 1,
461 rxunaligned => 0,
461 rxunaligned => 0,
462 rmapbufs => 4,
462 rmapbufs => 4,
463 ft => 0,
463 ft => 0,
464 netlist => 0,
464 netlist => 0,
465 ports => 2,
465 ports => 2,
466 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
466 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
467 memtech => apa3e,
467 memtech => apa3e,
468 destkey => 2,
468 destkey => 2,
469 spwcore => 1
469 spwcore => 1
470 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
470 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
471 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
471 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
472 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
472 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
473 )
473 )
474 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
474 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
475 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
475 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
476 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
476 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
477 swni, swno);
477 swni, swno);
478
478
479 swni.tickin <= '0';
479 swni.tickin <= '0';
480 swni.rmapen <= '1';
480 swni.rmapen <= '1';
481 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
481 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
482 swni.tickinraw <= '0';
482 swni.tickinraw <= '0';
483 swni.timein <= (OTHERS => '0');
483 swni.timein <= (OTHERS => '0');
484 swni.dcrstval <= (OTHERS => '0');
484 swni.dcrstval <= (OTHERS => '0');
485 swni.timerrstval <= (OTHERS => '0');
485 swni.timerrstval <= (OTHERS => '0');
486
486
487 -------------------------------------------------------------------------------
487 -------------------------------------------------------------------------------
488 -- LFR ------------------------------------------------------------------------
488 -- LFR ------------------------------------------------------------------------
489 -------------------------------------------------------------------------------
489 -------------------------------------------------------------------------------
490
490
491
491
492 LFR_rstn <= LFR_soft_rstn AND rstn_25;
492 LFR_rstn <= LFR_soft_rstn AND rstn_25;
493 --LFR_rstn <= rstn_25;
493 --LFR_rstn <= rstn_25;
494
494
495 lpp_lfr_1 : lpp_lfr
495 lpp_lfr_1 : lpp_lfr
496 GENERIC MAP (
496 GENERIC MAP (
497 Mem_use => use_RAM,
497 Mem_use => use_RAM,
498 nb_data_by_buffer_size => 32,
498 nb_data_by_buffer_size => 32,
499 nb_snapshot_param_size => 32,
499 nb_snapshot_param_size => 32,
500 delta_vector_size => 32,
500 delta_vector_size => 32,
501 delta_vector_size_f0_2 => 7, -- log2(96)
501 delta_vector_size_f0_2 => 7, -- log2(96)
502 pindex => 15,
502 pindex => 15,
503 paddr => 15,
503 paddr => 15,
504 pmask => 16#fff#,
504 pmask => 16#fff#,
505 pirq_ms => 6,
505 pirq_ms => 6,
506 pirq_wfp => 14,
506 pirq_wfp => 14,
507 hindex => 2,
507 hindex => 2,
508 top_lfr_version => X"000124") -- aa.bb.cc version
508 top_lfr_version => X"000125") -- aa.bb.cc version
509 PORT MAP (
509 PORT MAP (
510 clk => clk_25,
510 clk => clk_25,
511 rstn => LFR_rstn,
511 rstn => LFR_rstn,
512 sample_B => sample_s(2 DOWNTO 0),
512 sample_B => sample_s(2 DOWNTO 0),
513 sample_E => sample_s(7 DOWNTO 3),
513 sample_E => sample_s(7 DOWNTO 3),
514 sample_val => sample_val,
514 sample_val => sample_val,
515 apbi => apbi_ext,
515 apbi => apbi_ext,
516 apbo => apbo_ext(15),
516 apbo => apbo_ext(15),
517 ahbi => ahbi_m_ext,
517 ahbi => ahbi_m_ext,
518 ahbo => ahbo_m_ext(2),
518 ahbo => ahbo_m_ext(2),
519 coarse_time => coarse_time,
519 coarse_time => coarse_time,
520 fine_time => fine_time,
520 fine_time => fine_time,
521 data_shaping_BW => bias_fail_sw_sig,
521 data_shaping_BW => bias_fail_sw_sig,
522 debug_vector => lfr_debug_vector,
522 debug_vector => lfr_debug_vector,
523 debug_vector_ms => lfr_debug_vector_ms
523 debug_vector_ms => lfr_debug_vector_ms
524 );
524 );
525
525
526 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
526 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
527 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
527 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
528 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
528 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
529 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
529 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
530 IO0 <= rstn_25;
530 IO0 <= rstn_25;
531 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
531 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
532 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
532 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
533 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
533 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
534 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
534 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
535 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
535 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
536 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
536 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
537 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
537 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
538
538
539 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
539 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
540 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
540 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
541 END GENERATE all_sample;
541 END GENERATE all_sample;
542
542
543 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
543 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
544 GENERIC MAP(
544 GENERIC MAP(
545 ChannelCount => 8,
545 ChannelCount => 8,
546 SampleNbBits => 14,
546 SampleNbBits => 14,
547 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
547 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
548 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
548 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
549 PORT MAP (
549 PORT MAP (
550 -- CONV
550 -- CONV
551 cnv_clk => clk_24,
551 cnv_clk => clk_24,
552 cnv_rstn => rstn_25,
552 cnv_rstn => rstn_25,
553 cnv => ADC_nCS_sig,
553 cnv => ADC_nCS_sig,
554 -- DATA
554 -- DATA
555 clk => clk_25,
555 clk => clk_25,
556 rstn => rstn_25,
556 rstn => rstn_25,
557 sck => ADC_CLK_sig,
557 sck => ADC_CLK_sig,
558 sdo => ADC_SDO_sig,
558 sdo => ADC_SDO_sig,
559 -- SAMPLE
559 -- SAMPLE
560 sample => sample,
560 sample => sample,
561 sample_val => sample_val);
561 sample_val => sample_val);
562
562
563 --IO10 <= ADC_SDO_sig(5);
563 --IO10 <= ADC_SDO_sig(5);
564 --IO9 <= ADC_SDO_sig(4);
564 --IO9 <= ADC_SDO_sig(4);
565 --IO8 <= ADC_SDO_sig(3);
565 --IO8 <= ADC_SDO_sig(3);
566
566
567 ADC_nCS <= ADC_nCS_sig;
567 ADC_nCS <= ADC_nCS_sig;
568 ADC_CLK <= ADC_CLK_sig;
568 ADC_CLK <= ADC_CLK_sig;
569 ADC_SDO_sig <= ADC_SDO;
569 ADC_SDO_sig <= ADC_SDO;
570
570
571 ----------------------------------------------------------------------
571 ----------------------------------------------------------------------
572 --- GPIO -----------------------------------------------------------
572 --- GPIO -----------------------------------------------------------
573 ----------------------------------------------------------------------
573 ----------------------------------------------------------------------
574
574
575 grgpio0 : grgpio
575 grgpio0 : grgpio
576 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
576 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
577 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
577 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
578
578
579 gpioi.sig_en <= (OTHERS => '0');
579 gpioi.sig_en <= (OTHERS => '0');
580 gpioi.sig_in <= (OTHERS => '0');
580 gpioi.sig_in <= (OTHERS => '0');
581 gpioi.din <= (OTHERS => '0');
581 gpioi.din <= (OTHERS => '0');
582 --pio_pad_0 : iopad
582 --pio_pad_0 : iopad
583 -- GENERIC MAP (tech => CFG_PADTECH)
583 -- GENERIC MAP (tech => CFG_PADTECH)
584 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
584 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
585 --pio_pad_1 : iopad
585 --pio_pad_1 : iopad
586 -- GENERIC MAP (tech => CFG_PADTECH)
586 -- GENERIC MAP (tech => CFG_PADTECH)
587 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
587 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
588 --pio_pad_2 : iopad
588 --pio_pad_2 : iopad
589 -- GENERIC MAP (tech => CFG_PADTECH)
589 -- GENERIC MAP (tech => CFG_PADTECH)
590 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
590 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
591 --pio_pad_3 : iopad
591 --pio_pad_3 : iopad
592 -- GENERIC MAP (tech => CFG_PADTECH)
592 -- GENERIC MAP (tech => CFG_PADTECH)
593 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
593 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
594 --pio_pad_4 : iopad
594 --pio_pad_4 : iopad
595 -- GENERIC MAP (tech => CFG_PADTECH)
595 -- GENERIC MAP (tech => CFG_PADTECH)
596 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
596 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
597 --pio_pad_5 : iopad
597 --pio_pad_5 : iopad
598 -- GENERIC MAP (tech => CFG_PADTECH)
598 -- GENERIC MAP (tech => CFG_PADTECH)
599 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
599 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
600 --pio_pad_6 : iopad
600 --pio_pad_6 : iopad
601 -- GENERIC MAP (tech => CFG_PADTECH)
601 -- GENERIC MAP (tech => CFG_PADTECH)
602 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
602 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
603 --pio_pad_7 : iopad
603 --pio_pad_7 : iopad
604 -- GENERIC MAP (tech => CFG_PADTECH)
604 -- GENERIC MAP (tech => CFG_PADTECH)
605 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
605 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
606
606
607 PROCESS (clk_25, rstn_25)
607 PROCESS (clk_25, rstn_25)
608 BEGIN -- PROCESS
608 BEGIN -- PROCESS
609 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
609 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
610 -- --IO0 <= '0';
610 -- --IO0 <= '0';
611 -- IO1 <= '0';
611 -- IO1 <= '0';
612 -- IO2 <= '0';
612 -- IO2 <= '0';
613 -- IO3 <= '0';
613 -- IO3 <= '0';
614 -- IO4 <= '0';
614 -- IO4 <= '0';
615 -- IO5 <= '0';
615 -- IO5 <= '0';
616 -- IO6 <= '0';
616 -- IO6 <= '0';
617 -- IO7 <= '0';
617 -- IO7 <= '0';
618 IO8 <= '0';
618 IO8 <= '0';
619 IO9 <= '0';
619 IO9 <= '0';
620 IO10 <= '0';
620 IO10 <= '0';
621 IO11 <= '0';
621 IO11 <= '0';
622 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
622 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
623 CASE gpioo.dout(2 DOWNTO 0) IS
623 CASE gpioo.dout(2 DOWNTO 0) IS
624 WHEN "011" =>
624 WHEN "011" =>
625 -- --IO0 <= observation_reg(0 );
625 -- --IO0 <= observation_reg(0 );
626 -- IO1 <= observation_reg(1 );
626 -- IO1 <= observation_reg(1 );
627 -- IO2 <= observation_reg(2 );
627 -- IO2 <= observation_reg(2 );
628 -- IO3 <= observation_reg(3 );
628 -- IO3 <= observation_reg(3 );
629 -- IO4 <= observation_reg(4 );
629 -- IO4 <= observation_reg(4 );
630 -- IO5 <= observation_reg(5 );
630 -- IO5 <= observation_reg(5 );
631 -- IO6 <= observation_reg(6 );
631 -- IO6 <= observation_reg(6 );
632 -- IO7 <= observation_reg(7 );
632 -- IO7 <= observation_reg(7 );
633 IO8 <= observation_reg(8);
633 IO8 <= observation_reg(8);
634 IO9 <= observation_reg(9);
634 IO9 <= observation_reg(9);
635 IO10 <= observation_reg(10);
635 IO10 <= observation_reg(10);
636 IO11 <= observation_reg(11);
636 IO11 <= observation_reg(11);
637 WHEN "001" =>
637 WHEN "001" =>
638 -- --IO0 <= observation_reg(0 + 12);
638 -- --IO0 <= observation_reg(0 + 12);
639 -- IO1 <= observation_reg(1 + 12);
639 -- IO1 <= observation_reg(1 + 12);
640 -- IO2 <= observation_reg(2 + 12);
640 -- IO2 <= observation_reg(2 + 12);
641 -- IO3 <= observation_reg(3 + 12);
641 -- IO3 <= observation_reg(3 + 12);
642 -- IO4 <= observation_reg(4 + 12);
642 -- IO4 <= observation_reg(4 + 12);
643 -- IO5 <= observation_reg(5 + 12);
643 -- IO5 <= observation_reg(5 + 12);
644 -- IO6 <= observation_reg(6 + 12);
644 -- IO6 <= observation_reg(6 + 12);
645 -- IO7 <= observation_reg(7 + 12);
645 -- IO7 <= observation_reg(7 + 12);
646 IO8 <= observation_reg(8 + 12);
646 IO8 <= observation_reg(8 + 12);
647 IO9 <= observation_reg(9 + 12);
647 IO9 <= observation_reg(9 + 12);
648 IO10 <= observation_reg(10 + 12);
648 IO10 <= observation_reg(10 + 12);
649 IO11 <= observation_reg(11 + 12);
649 IO11 <= observation_reg(11 + 12);
650 WHEN "010" =>
650 WHEN "010" =>
651 -- --IO0 <= observation_reg(0 + 12 + 12);
651 -- --IO0 <= observation_reg(0 + 12 + 12);
652 -- IO1 <= observation_reg(1 + 12 + 12);
652 -- IO1 <= observation_reg(1 + 12 + 12);
653 -- IO2 <= observation_reg(2 + 12 + 12);
653 -- IO2 <= observation_reg(2 + 12 + 12);
654 -- IO3 <= observation_reg(3 + 12 + 12);
654 -- IO3 <= observation_reg(3 + 12 + 12);
655 -- IO4 <= observation_reg(4 + 12 + 12);
655 -- IO4 <= observation_reg(4 + 12 + 12);
656 -- IO5 <= observation_reg(5 + 12 + 12);
656 -- IO5 <= observation_reg(5 + 12 + 12);
657 -- IO6 <= observation_reg(6 + 12 + 12);
657 -- IO6 <= observation_reg(6 + 12 + 12);
658 -- IO7 <= observation_reg(7 + 12 + 12);
658 -- IO7 <= observation_reg(7 + 12 + 12);
659 IO8 <= '0';
659 IO8 <= '0';
660 IO9 <= '0';
660 IO9 <= '0';
661 IO10 <= '0';
661 IO10 <= '0';
662 IO11 <= '0';
662 IO11 <= '0';
663 WHEN "000" =>
663 WHEN "000" =>
664 -- --IO0 <= observation_vector_0(0 );
664 -- --IO0 <= observation_vector_0(0 );
665 -- IO1 <= observation_vector_0(1 );
665 -- IO1 <= observation_vector_0(1 );
666 -- IO2 <= observation_vector_0(2 );
666 -- IO2 <= observation_vector_0(2 );
667 -- IO3 <= observation_vector_0(3 );
667 -- IO3 <= observation_vector_0(3 );
668 -- IO4 <= observation_vector_0(4 );
668 -- IO4 <= observation_vector_0(4 );
669 -- IO5 <= observation_vector_0(5 );
669 -- IO5 <= observation_vector_0(5 );
670 -- IO6 <= observation_vector_0(6 );
670 -- IO6 <= observation_vector_0(6 );
671 -- IO7 <= observation_vector_0(7 );
671 -- IO7 <= observation_vector_0(7 );
672 IO8 <= observation_vector_0(8);
672 IO8 <= observation_vector_0(8);
673 IO9 <= observation_vector_0(9);
673 IO9 <= observation_vector_0(9);
674 IO10 <= observation_vector_0(10);
674 IO10 <= observation_vector_0(10);
675 IO11 <= observation_vector_0(11);
675 IO11 <= observation_vector_0(11);
676 WHEN "100" =>
676 WHEN "100" =>
677 -- --IO0 <= observation_vector_1(0 );
677 -- --IO0 <= observation_vector_1(0 );
678 -- IO1 <= observation_vector_1(1 );
678 -- IO1 <= observation_vector_1(1 );
679 -- IO2 <= observation_vector_1(2 );
679 -- IO2 <= observation_vector_1(2 );
680 -- IO3 <= observation_vector_1(3 );
680 -- IO3 <= observation_vector_1(3 );
681 -- IO4 <= observation_vector_1(4 );
681 -- IO4 <= observation_vector_1(4 );
682 -- IO5 <= observation_vector_1(5 );
682 -- IO5 <= observation_vector_1(5 );
683 -- IO6 <= observation_vector_1(6 );
683 -- IO6 <= observation_vector_1(6 );
684 -- IO7 <= observation_vector_1(7 );
684 -- IO7 <= observation_vector_1(7 );
685 IO8 <= observation_vector_1(8);
685 IO8 <= observation_vector_1(8);
686 IO9 <= observation_vector_1(9);
686 IO9 <= observation_vector_1(9);
687 IO10 <= observation_vector_1(10);
687 IO10 <= observation_vector_1(10);
688 IO11 <= observation_vector_1(11);
688 IO11 <= observation_vector_1(11);
689 WHEN OTHERS => NULL;
689 WHEN OTHERS => NULL;
690 END CASE;
690 END CASE;
691
691
692 END IF;
692 END IF;
693 END PROCESS;
693 END PROCESS;
694 -----------------------------------------------------------------------------
694 -----------------------------------------------------------------------------
695 --
695 --
696 -----------------------------------------------------------------------------
696 -----------------------------------------------------------------------------
697 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
697 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
698 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
698 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
699 apbo_ext(I) <= apb_none;
699 apbo_ext(I) <= apb_none;
700 END GENERATE apbo_ext_not_used;
700 END GENERATE apbo_ext_not_used;
701 END GENERATE all_apbo_ext;
701 END GENERATE all_apbo_ext;
702
702
703
703
704 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
704 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
705 ahbo_s_ext(I) <= ahbs_none;
705 ahbo_s_ext(I) <= ahbs_none;
706 END GENERATE all_ahbo_ext;
706 END GENERATE all_ahbo_ext;
707
707
708 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
708 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
709 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
709 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
710 ahbo_m_ext(I) <= ahbm_none;
710 ahbo_m_ext(I) <= ahbm_none;
711 END GENERATE ahbo_m_ext_not_used;
711 END GENERATE ahbo_m_ext_not_used;
712 END GENERATE all_ahbo_m_ext;
712 END GENERATE all_ahbo_m_ext;
713
713
714 END beh;
714 END beh;
Show file before | Show file after | Hide comments
@@ -1,519 +1,524
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_snapshot_param_size : INTEGER := 11;
29 nb_snapshot_param_size : INTEGER := 11;
30 delta_vector_size : INTEGER := 20;
30 delta_vector_size : INTEGER := 20;
31 delta_vector_size_f0_2 : INTEGER := 7;
31 delta_vector_size_f0_2 : INTEGER := 7;
32
32
33 pindex : INTEGER := 4;
33 pindex : INTEGER := 4;
34 paddr : INTEGER := 4;
34 paddr : INTEGER := 4;
35 pmask : INTEGER := 16#fff#;
35 pmask : INTEGER := 16#fff#;
36 pirq_ms : INTEGER := 0;
36 pirq_ms : INTEGER := 0;
37 pirq_wfp : INTEGER := 1;
37 pirq_wfp : INTEGER := 1;
38
38
39 hindex : INTEGER := 2;
39 hindex : INTEGER := 2;
40
40
41 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
41 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42
42
43 );
43 );
44 PORT (
44 PORT (
45 clk : IN STD_LOGIC;
45 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
47 -- SAMPLE
47 -- SAMPLE
48 sample_B : IN Samples(2 DOWNTO 0);
48 sample_B : IN Samples(2 DOWNTO 0);
49 sample_E : IN Samples(4 DOWNTO 0);
49 sample_E : IN Samples(4 DOWNTO 0);
50 sample_val : IN STD_LOGIC;
50 sample_val : IN STD_LOGIC;
51 -- APB
51 -- APB
52 apbi : IN apb_slv_in_type;
52 apbi : IN apb_slv_in_type;
53 apbo : OUT apb_slv_out_type;
53 apbo : OUT apb_slv_out_type;
54 -- AHB
54 -- AHB
55 ahbi : IN AHB_Mst_In_Type;
55 ahbi : IN AHB_Mst_In_Type;
56 ahbo : OUT AHB_Mst_Out_Type;
56 ahbo : OUT AHB_Mst_Out_Type;
57 -- TIME
57 -- TIME
58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 --
60 --
61 data_shaping_BW : OUT STD_LOGIC;
61 data_shaping_BW : OUT STD_LOGIC;
62 --
62 --
63 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
63 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
64 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
64 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
65 );
65 );
66 END lpp_lfr;
66 END lpp_lfr;
67
67
68 ARCHITECTURE beh OF lpp_lfr IS
68 ARCHITECTURE beh OF lpp_lfr IS
69 SIGNAL sample_s : Samples(7 DOWNTO 0);
69 SIGNAL sample_s : Samples(7 DOWNTO 0);
70 --
70 --
71 SIGNAL data_shaping_SP0 : STD_LOGIC;
71 SIGNAL data_shaping_SP0 : STD_LOGIC;
72 SIGNAL data_shaping_SP1 : STD_LOGIC;
72 SIGNAL data_shaping_SP1 : STD_LOGIC;
73 SIGNAL data_shaping_R0 : STD_LOGIC;
73 SIGNAL data_shaping_R0 : STD_LOGIC;
74 SIGNAL data_shaping_R1 : STD_LOGIC;
74 SIGNAL data_shaping_R1 : STD_LOGIC;
75 SIGNAL data_shaping_R2 : STD_LOGIC;
75 SIGNAL data_shaping_R2 : STD_LOGIC;
76 --
76 --
77 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
79 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
79 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 --
80 --
81 SIGNAL sample_f0_val : STD_LOGIC;
81 SIGNAL sample_f0_val : STD_LOGIC;
82 SIGNAL sample_f1_val : STD_LOGIC;
82 SIGNAL sample_f1_val : STD_LOGIC;
83 SIGNAL sample_f2_val : STD_LOGIC;
83 SIGNAL sample_f2_val : STD_LOGIC;
84 SIGNAL sample_f3_val : STD_LOGIC;
84 SIGNAL sample_f3_val : STD_LOGIC;
85 --
85 --
86 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
86 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
88 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
88 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
89 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
89 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
90 --
90 --
91 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
92 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
92 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
93 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
93 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
94
94
95 -- SM
95 -- SM
96 SIGNAL ready_matrix_f0 : STD_LOGIC;
96 SIGNAL ready_matrix_f0 : STD_LOGIC;
97 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
97 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
98 SIGNAL ready_matrix_f1 : STD_LOGIC;
98 SIGNAL ready_matrix_f1 : STD_LOGIC;
99 SIGNAL ready_matrix_f2 : STD_LOGIC;
99 SIGNAL ready_matrix_f2 : STD_LOGIC;
100 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
100 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
101 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
101 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
102 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
102 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
103 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
103 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
104 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
104 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
105 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
105 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
106 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
106 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
107 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
108 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
108 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
109 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
109 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
110
110
111 -- WFP
111 -- WFP
112 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
112 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
113 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
115 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
116 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118
118
119 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
119 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
120 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
120 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
121 SIGNAL enable_f0 : STD_LOGIC;
121 SIGNAL enable_f0 : STD_LOGIC;
122 SIGNAL enable_f1 : STD_LOGIC;
122 SIGNAL enable_f1 : STD_LOGIC;
123 SIGNAL enable_f2 : STD_LOGIC;
123 SIGNAL enable_f2 : STD_LOGIC;
124 SIGNAL enable_f3 : STD_LOGIC;
124 SIGNAL enable_f3 : STD_LOGIC;
125 SIGNAL burst_f0 : STD_LOGIC;
125 SIGNAL burst_f0 : STD_LOGIC;
126 SIGNAL burst_f1 : STD_LOGIC;
126 SIGNAL burst_f1 : STD_LOGIC;
127 SIGNAL burst_f2 : STD_LOGIC;
127 SIGNAL burst_f2 : STD_LOGIC;
128
128
129 --SIGNAL run : STD_LOGIC;
129 --SIGNAL run : STD_LOGIC;
130 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
130 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
131
131
132 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
133 --
133 --
134 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
135 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
136 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
137 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
137 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
138 --f1
138 --f1
139 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
140 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
141 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
141 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
142 --f2
142 --f2
143 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
144 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
145 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
145 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
146 --f3
146 --f3
147 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
148 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
149 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
149 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
150
150
151 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
152 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
153 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
153 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
154 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
155 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
156 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 -----------------------------------------------------------------------------
157 -----------------------------------------------------------------------------
158 -- DMA RR
158 -- DMA RR
159 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
160 -- SIGNAL dma_sel_valid : STD_LOGIC;
160 -- SIGNAL dma_sel_valid : STD_LOGIC;
161 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
165
165
166 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
168
168
169 -----------------------------------------------------------------------------
169 -----------------------------------------------------------------------------
170 -- DMA_REG
170 -- DMA_REG
171 -----------------------------------------------------------------------------
171 -----------------------------------------------------------------------------
172 -- SIGNAL ongoing_reg : STD_LOGIC;
172 -- SIGNAL ongoing_reg : STD_LOGIC;
173 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 -- SIGNAL dma_send_reg : STD_LOGIC;
174 -- SIGNAL dma_send_reg : STD_LOGIC;
175 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
175 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
176 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
178
178
179
179
180 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
181 -- DMA
181 -- DMA
182 -----------------------------------------------------------------------------
182 -----------------------------------------------------------------------------
183 -- SIGNAL dma_send : STD_LOGIC;
183 -- SIGNAL dma_send : STD_LOGIC;
184 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
184 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
185 -- SIGNAL dma_done : STD_LOGIC;
185 -- SIGNAL dma_done : STD_LOGIC;
186 -- SIGNAL dma_ren : STD_LOGIC;
186 -- SIGNAL dma_ren : STD_LOGIC;
187 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190
190
191 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
192 -- MS
192 -- MS
193 -----------------------------------------------------------------------------
193 -----------------------------------------------------------------------------
194
194
195 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 -- SIGNAL data_ms_valid : STD_LOGIC;
197 -- SIGNAL data_ms_valid : STD_LOGIC;
198 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
198 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
199 -- SIGNAL data_ms_ren : STD_LOGIC;
199 -- SIGNAL data_ms_ren : STD_LOGIC;
200 -- SIGNAL data_ms_done : STD_LOGIC;
200 -- SIGNAL data_ms_done : STD_LOGIC;
201 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
201 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
202
202
203 -- SIGNAL run_ms : STD_LOGIC;
203 -- SIGNAL run_ms : STD_LOGIC;
204 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
204 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
205
205
206 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
206 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
207 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
207 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
208 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
208 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
209 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
209 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
210
210
211
211
212 SIGNAL error_buffer_full : STD_LOGIC;
212 SIGNAL error_buffer_full : STD_LOGIC;
213 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
213 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
214
214
215 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
215 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
217
217
218 -----------------------------------------------------------------------------
218 -----------------------------------------------------------------------------
219 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
219 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
220 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
220 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
221 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
221 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
223 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
224 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
224 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
225 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
226 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
226 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
227 SIGNAL dma_grant_error : STD_LOGIC;
227 SIGNAL dma_grant_error : STD_LOGIC;
228
228
229 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
229 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
230 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
231 -- SIGNAL run_dma : STD_LOGIC;
231 -- SIGNAL run_dma : STD_LOGIC;
232 BEGIN
232 BEGIN
233
233
234 debug_vector <= apb_reg_debug_vector;
234 debug_vector <= apb_reg_debug_vector;
235 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
236
236
237 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
237 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
238 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
238 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
239
239
240 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
240 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
241 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
241 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
242 --END GENERATE all_channel;
242 --END GENERATE all_channel;
243
243
244 -----------------------------------------------------------------------------
244 -----------------------------------------------------------------------------
245 lpp_lfr_filter_1 : lpp_lfr_filter
245 lpp_lfr_filter_1 : lpp_lfr_filter
246 GENERIC MAP (
246 GENERIC MAP (
247 Mem_use => Mem_use)
247 Mem_use => Mem_use)
248 PORT MAP (
248 PORT MAP (
249 sample => sample_s,
249 sample => sample_s,
250 sample_val => sample_val,
250 sample_val => sample_val,
251 clk => clk,
251 clk => clk,
252 rstn => rstn,
252 rstn => rstn,
253 data_shaping_SP0 => data_shaping_SP0,
253 data_shaping_SP0 => data_shaping_SP0,
254 data_shaping_SP1 => data_shaping_SP1,
254 data_shaping_SP1 => data_shaping_SP1,
255 data_shaping_R0 => data_shaping_R0,
255 data_shaping_R0 => data_shaping_R0,
256 data_shaping_R1 => data_shaping_R1,
256 data_shaping_R1 => data_shaping_R1,
257 data_shaping_R2 => data_shaping_R2,
257 data_shaping_R2 => data_shaping_R2,
258 sample_f0_val => sample_f0_val,
258 sample_f0_val => sample_f0_val,
259 sample_f1_val => sample_f1_val,
259 sample_f1_val => sample_f1_val,
260 sample_f2_val => sample_f2_val,
260 sample_f2_val => sample_f2_val,
261 sample_f3_val => sample_f3_val,
261 sample_f3_val => sample_f3_val,
262 sample_f0_wdata => sample_f0_data,
262 sample_f0_wdata => sample_f0_data,
263 sample_f1_wdata => sample_f1_data,
263 sample_f1_wdata => sample_f1_data,
264 sample_f2_wdata => sample_f2_data,
264 sample_f2_wdata => sample_f2_data,
265 sample_f3_wdata => sample_f3_data);
265 sample_f3_wdata => sample_f3_data);
266
266
267 -----------------------------------------------------------------------------
267 -----------------------------------------------------------------------------
268 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
268 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
269 GENERIC MAP (
269 GENERIC MAP (
270 nb_data_by_buffer_size => nb_data_by_buffer_size,
270 nb_data_by_buffer_size => nb_data_by_buffer_size,
271 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
271 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
272 nb_snapshot_param_size => nb_snapshot_param_size,
272 nb_snapshot_param_size => nb_snapshot_param_size,
273 delta_vector_size => delta_vector_size,
273 delta_vector_size => delta_vector_size,
274 delta_vector_size_f0_2 => delta_vector_size_f0_2,
274 delta_vector_size_f0_2 => delta_vector_size_f0_2,
275 pindex => pindex,
275 pindex => pindex,
276 paddr => paddr,
276 paddr => paddr,
277 pmask => pmask,
277 pmask => pmask,
278 pirq_ms => pirq_ms,
278 pirq_ms => pirq_ms,
279 pirq_wfp => pirq_wfp,
279 pirq_wfp => pirq_wfp,
280 top_lfr_version => top_lfr_version)
280 top_lfr_version => top_lfr_version)
281 PORT MAP (
281 PORT MAP (
282 HCLK => clk,
282 HCLK => clk,
283 HRESETn => rstn,
283 HRESETn => rstn,
284 apbi => apbi,
284 apbi => apbi,
285 apbo => apbo,
285 apbo => apbo,
286
286
287 run_ms => OPEN,--run_ms,
287 run_ms => OPEN,--run_ms,
288
288
289 ready_matrix_f0 => ready_matrix_f0,
289 ready_matrix_f0 => ready_matrix_f0,
290 ready_matrix_f1 => ready_matrix_f1,
290 ready_matrix_f1 => ready_matrix_f1,
291 ready_matrix_f2 => ready_matrix_f2,
291 ready_matrix_f2 => ready_matrix_f2,
292 error_buffer_full => error_buffer_full, -- TODO
292 error_buffer_full => error_buffer_full, -- TODO
293 error_input_fifo_write => error_input_fifo_write, -- TODO
293 error_input_fifo_write => error_input_fifo_write, -- TODO
294 status_ready_matrix_f0 => status_ready_matrix_f0,
294 status_ready_matrix_f0 => status_ready_matrix_f0,
295 status_ready_matrix_f1 => status_ready_matrix_f1,
295 status_ready_matrix_f1 => status_ready_matrix_f1,
296 status_ready_matrix_f2 => status_ready_matrix_f2,
296 status_ready_matrix_f2 => status_ready_matrix_f2,
297
297
298 matrix_time_f0 => matrix_time_f0,
298 matrix_time_f0 => matrix_time_f0,
299 matrix_time_f1 => matrix_time_f1,
299 matrix_time_f1 => matrix_time_f1,
300 matrix_time_f2 => matrix_time_f2,
300 matrix_time_f2 => matrix_time_f2,
301
301
302 addr_matrix_f0 => addr_matrix_f0,
302 addr_matrix_f0 => addr_matrix_f0,
303 addr_matrix_f1 => addr_matrix_f1,
303 addr_matrix_f1 => addr_matrix_f1,
304 addr_matrix_f2 => addr_matrix_f2,
304 addr_matrix_f2 => addr_matrix_f2,
305
305
306 length_matrix_f0 => length_matrix_f0,
306 length_matrix_f0 => length_matrix_f0,
307 length_matrix_f1 => length_matrix_f1,
307 length_matrix_f1 => length_matrix_f1,
308 length_matrix_f2 => length_matrix_f2,
308 length_matrix_f2 => length_matrix_f2,
309 -------------------------------------------------------------------------
309 -------------------------------------------------------------------------
310 --status_full => status_full, -- TODo
310 --status_full => status_full, -- TODo
311 --status_full_ack => status_full_ack, -- TODo
311 --status_full_ack => status_full_ack, -- TODo
312 --status_full_err => status_full_err, -- TODo
312 --status_full_err => status_full_err, -- TODo
313 status_new_err => status_new_err,
313 status_new_err => status_new_err,
314 data_shaping_BW => data_shaping_BW,
314 data_shaping_BW => data_shaping_BW,
315 data_shaping_SP0 => data_shaping_SP0,
315 data_shaping_SP0 => data_shaping_SP0,
316 data_shaping_SP1 => data_shaping_SP1,
316 data_shaping_SP1 => data_shaping_SP1,
317 data_shaping_R0 => data_shaping_R0,
317 data_shaping_R0 => data_shaping_R0,
318 data_shaping_R1 => data_shaping_R1,
318 data_shaping_R1 => data_shaping_R1,
319 data_shaping_R2 => data_shaping_R2,
319 data_shaping_R2 => data_shaping_R2,
320 delta_snapshot => delta_snapshot,
320 delta_snapshot => delta_snapshot,
321 delta_f0 => delta_f0,
321 delta_f0 => delta_f0,
322 delta_f0_2 => delta_f0_2,
322 delta_f0_2 => delta_f0_2,
323 delta_f1 => delta_f1,
323 delta_f1 => delta_f1,
324 delta_f2 => delta_f2,
324 delta_f2 => delta_f2,
325 nb_data_by_buffer => nb_data_by_buffer,
325 nb_data_by_buffer => nb_data_by_buffer,
326 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
326 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
327 nb_snapshot_param => nb_snapshot_param,
327 nb_snapshot_param => nb_snapshot_param,
328 enable_f0 => enable_f0,
328 enable_f0 => enable_f0,
329 enable_f1 => enable_f1,
329 enable_f1 => enable_f1,
330 enable_f2 => enable_f2,
330 enable_f2 => enable_f2,
331 enable_f3 => enable_f3,
331 enable_f3 => enable_f3,
332 burst_f0 => burst_f0,
332 burst_f0 => burst_f0,
333 burst_f1 => burst_f1,
333 burst_f1 => burst_f1,
334 burst_f2 => burst_f2,
334 burst_f2 => burst_f2,
335 run => OPEN, --run,
335 run => OPEN, --run,
336 start_date => start_date,
336 start_date => start_date,
337 -- debug_signal => debug_signal,
337 -- debug_signal => debug_signal,
338 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
338 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
339 wfp_addr_buffer => wfp_addr_buffer,-- TODO
339 wfp_addr_buffer => wfp_addr_buffer,-- TODO
340 wfp_length_buffer => wfp_length_buffer,-- TODO
340 wfp_length_buffer => wfp_length_buffer,-- TODO
341
341
342 wfp_ready_buffer => wfp_ready_buffer,-- TODO
342 wfp_ready_buffer => wfp_ready_buffer,-- TODO
343 wfp_buffer_time => wfp_buffer_time,-- TODO
343 wfp_buffer_time => wfp_buffer_time,-- TODO
344 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
344 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
345 -------------------------------------------------------------------------
346 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
347 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
348 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
349 sample_f3_valid => sample_f3_val,
345 debug_vector => apb_reg_debug_vector
350 debug_vector => apb_reg_debug_vector
346 );
351 );
347
352
348 -----------------------------------------------------------------------------
353 -----------------------------------------------------------------------------
349 -----------------------------------------------------------------------------
354 -----------------------------------------------------------------------------
350 lpp_waveform_1 : lpp_waveform
355 lpp_waveform_1 : lpp_waveform
351 GENERIC MAP (
356 GENERIC MAP (
352 tech => inferred,
357 tech => inferred,
353 data_size => 6*16,
358 data_size => 6*16,
354 nb_data_by_buffer_size => nb_data_by_buffer_size,
359 nb_data_by_buffer_size => nb_data_by_buffer_size,
355 nb_snapshot_param_size => nb_snapshot_param_size,
360 nb_snapshot_param_size => nb_snapshot_param_size,
356 delta_vector_size => delta_vector_size,
361 delta_vector_size => delta_vector_size,
357 delta_vector_size_f0_2 => delta_vector_size_f0_2
362 delta_vector_size_f0_2 => delta_vector_size_f0_2
358 )
363 )
359 PORT MAP (
364 PORT MAP (
360 clk => clk,
365 clk => clk,
361 rstn => rstn,
366 rstn => rstn,
362
367
363 reg_run => '1',--run,
368 reg_run => '1',--run,
364 reg_start_date => start_date,
369 reg_start_date => start_date,
365 reg_delta_snapshot => delta_snapshot,
370 reg_delta_snapshot => delta_snapshot,
366 reg_delta_f0 => delta_f0,
371 reg_delta_f0 => delta_f0,
367 reg_delta_f0_2 => delta_f0_2,
372 reg_delta_f0_2 => delta_f0_2,
368 reg_delta_f1 => delta_f1,
373 reg_delta_f1 => delta_f1,
369 reg_delta_f2 => delta_f2,
374 reg_delta_f2 => delta_f2,
370
375
371 enable_f0 => enable_f0,
376 enable_f0 => enable_f0,
372 enable_f1 => enable_f1,
377 enable_f1 => enable_f1,
373 enable_f2 => enable_f2,
378 enable_f2 => enable_f2,
374 enable_f3 => enable_f3,
379 enable_f3 => enable_f3,
375 burst_f0 => burst_f0,
380 burst_f0 => burst_f0,
376 burst_f1 => burst_f1,
381 burst_f1 => burst_f1,
377 burst_f2 => burst_f2,
382 burst_f2 => burst_f2,
378
383
379 nb_data_by_buffer => nb_data_by_buffer,
384 nb_data_by_buffer => nb_data_by_buffer,
380 nb_snapshot_param => nb_snapshot_param,
385 nb_snapshot_param => nb_snapshot_param,
381 status_new_err => status_new_err,
386 status_new_err => status_new_err,
382
387
383 status_buffer_ready => wfp_status_buffer_ready,
388 status_buffer_ready => wfp_status_buffer_ready,
384 addr_buffer => wfp_addr_buffer,
389 addr_buffer => wfp_addr_buffer,
385 length_buffer => wfp_length_buffer,
390 length_buffer => wfp_length_buffer,
386 ready_buffer => wfp_ready_buffer,
391 ready_buffer => wfp_ready_buffer,
387 buffer_time => wfp_buffer_time,
392 buffer_time => wfp_buffer_time,
388 error_buffer_full => wfp_error_buffer_full,
393 error_buffer_full => wfp_error_buffer_full,
389
394
390 coarse_time => coarse_time,
395 coarse_time => coarse_time,
391 fine_time => fine_time,
396 fine_time => fine_time,
392
397
393 --f0
398 --f0
394 data_f0_in_valid => sample_f0_val,
399 data_f0_in_valid => sample_f0_val,
395 data_f0_in => sample_f0_data,
400 data_f0_in => sample_f0_data,
396 --f1
401 --f1
397 data_f1_in_valid => sample_f1_val,
402 data_f1_in_valid => sample_f1_val,
398 data_f1_in => sample_f1_data,
403 data_f1_in => sample_f1_data,
399 --f2
404 --f2
400 data_f2_in_valid => sample_f2_val,
405 data_f2_in_valid => sample_f2_val,
401 data_f2_in => sample_f2_data,
406 data_f2_in => sample_f2_data,
402 --f3
407 --f3
403 data_f3_in_valid => sample_f3_val,
408 data_f3_in_valid => sample_f3_val,
404 data_f3_in => sample_f3_data,
409 data_f3_in => sample_f3_data,
405 -- OUTPUT -- DMA interface
410 -- OUTPUT -- DMA interface
406
411
407 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
412 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
408 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
413 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
409 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
414 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
410 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
415 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
411 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
416 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
412 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
417 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
413 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
418 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
414 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
419 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
415
420
416 );
421 );
417
422
418 -----------------------------------------------------------------------------
423 -----------------------------------------------------------------------------
419 -- Matrix Spectral
424 -- Matrix Spectral
420 -----------------------------------------------------------------------------
425 -----------------------------------------------------------------------------
421 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
426 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
422 NOT(sample_f0_val) & NOT(sample_f0_val);
427 NOT(sample_f0_val) & NOT(sample_f0_val);
423 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
428 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
424 NOT(sample_f1_val) & NOT(sample_f1_val);
429 NOT(sample_f1_val) & NOT(sample_f1_val);
425 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
430 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
426 NOT(sample_f2_val) & NOT(sample_f2_val);
431 NOT(sample_f2_val) & NOT(sample_f2_val);
427
432
428 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
433 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
429 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
434 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
430 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
435 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
431
436
432 -------------------------------------------------------------------------------
437 -------------------------------------------------------------------------------
433
438
434 --ms_softandhard_rstn <= rstn AND run_ms AND run;
439 --ms_softandhard_rstn <= rstn AND run_ms AND run;
435
440
436 -----------------------------------------------------------------------------
441 -----------------------------------------------------------------------------
437 lpp_lfr_ms_1 : lpp_lfr_ms
442 lpp_lfr_ms_1 : lpp_lfr_ms
438 GENERIC MAP (
443 GENERIC MAP (
439 Mem_use => Mem_use)
444 Mem_use => Mem_use)
440 PORT MAP (
445 PORT MAP (
441 clk => clk,
446 clk => clk,
442 --rstn => ms_softandhard_rstn, --rstn,
447 --rstn => ms_softandhard_rstn, --rstn,
443 rstn => rstn,
448 rstn => rstn,
444
449
445 run => '1',--run_ms,
450 run => '1',--run_ms,
446
451
447 start_date => start_date,
452 start_date => start_date,
448
453
449 coarse_time => coarse_time,
454 coarse_time => coarse_time,
450 fine_time => fine_time,
455 fine_time => fine_time,
451
456
452 sample_f0_wen => sample_f0_wen,
457 sample_f0_wen => sample_f0_wen,
453 sample_f0_wdata => sample_f0_wdata,
458 sample_f0_wdata => sample_f0_wdata,
454 sample_f1_wen => sample_f1_wen,
459 sample_f1_wen => sample_f1_wen,
455 sample_f1_wdata => sample_f1_wdata,
460 sample_f1_wdata => sample_f1_wdata,
456 sample_f2_wen => sample_f2_wen,
461 sample_f2_wen => sample_f2_wen,
457 sample_f2_wdata => sample_f2_wdata,
462 sample_f2_wdata => sample_f2_wdata,
458
463
459 --DMA
464 --DMA
460 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
465 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
461 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
466 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
462 dma_fifo_ren => dma_fifo_ren(4), -- IN
467 dma_fifo_ren => dma_fifo_ren(4), -- IN
463 dma_buffer_new => dma_buffer_new(4), -- OUT
468 dma_buffer_new => dma_buffer_new(4), -- OUT
464 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
469 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
465 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
470 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
466 dma_buffer_full => dma_buffer_full(4), -- IN
471 dma_buffer_full => dma_buffer_full(4), -- IN
467 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
472 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
468
473
469
474
470
475
471 --REG
476 --REG
472 ready_matrix_f0 => ready_matrix_f0,
477 ready_matrix_f0 => ready_matrix_f0,
473 ready_matrix_f1 => ready_matrix_f1,
478 ready_matrix_f1 => ready_matrix_f1,
474 ready_matrix_f2 => ready_matrix_f2,
479 ready_matrix_f2 => ready_matrix_f2,
475 error_buffer_full => error_buffer_full,
480 error_buffer_full => error_buffer_full,
476 error_input_fifo_write => error_input_fifo_write,
481 error_input_fifo_write => error_input_fifo_write,
477
482
478 status_ready_matrix_f0 => status_ready_matrix_f0,
483 status_ready_matrix_f0 => status_ready_matrix_f0,
479 status_ready_matrix_f1 => status_ready_matrix_f1,
484 status_ready_matrix_f1 => status_ready_matrix_f1,
480 status_ready_matrix_f2 => status_ready_matrix_f2,
485 status_ready_matrix_f2 => status_ready_matrix_f2,
481 addr_matrix_f0 => addr_matrix_f0,
486 addr_matrix_f0 => addr_matrix_f0,
482 addr_matrix_f1 => addr_matrix_f1,
487 addr_matrix_f1 => addr_matrix_f1,
483 addr_matrix_f2 => addr_matrix_f2,
488 addr_matrix_f2 => addr_matrix_f2,
484
489
485 length_matrix_f0 => length_matrix_f0,
490 length_matrix_f0 => length_matrix_f0,
486 length_matrix_f1 => length_matrix_f1,
491 length_matrix_f1 => length_matrix_f1,
487 length_matrix_f2 => length_matrix_f2,
492 length_matrix_f2 => length_matrix_f2,
488
493
489 matrix_time_f0 => matrix_time_f0,
494 matrix_time_f0 => matrix_time_f0,
490 matrix_time_f1 => matrix_time_f1,
495 matrix_time_f1 => matrix_time_f1,
491 matrix_time_f2 => matrix_time_f2,
496 matrix_time_f2 => matrix_time_f2,
492
497
493 debug_vector => debug_vector_ms);
498 debug_vector => debug_vector_ms);
494
499
495 -----------------------------------------------------------------------------
500 -----------------------------------------------------------------------------
496 --run_dma <= run_ms OR run;
501 --run_dma <= run_ms OR run;
497
502
498 DMA_SubSystem_1 : DMA_SubSystem
503 DMA_SubSystem_1 : DMA_SubSystem
499 GENERIC MAP (
504 GENERIC MAP (
500 hindex => hindex)
505 hindex => hindex)
501 PORT MAP (
506 PORT MAP (
502 clk => clk,
507 clk => clk,
503 rstn => rstn,
508 rstn => rstn,
504 run => '1',--run_dma,
509 run => '1',--run_dma,
505 ahbi => ahbi,
510 ahbi => ahbi,
506 ahbo => ahbo,
511 ahbo => ahbo,
507
512
508 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
513 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
509 fifo_data => dma_fifo_data, --fifo_data,
514 fifo_data => dma_fifo_data, --fifo_data,
510 fifo_ren => dma_fifo_ren, --fifo_ren,
515 fifo_ren => dma_fifo_ren, --fifo_ren,
511
516
512 buffer_new => dma_buffer_new, --buffer_new,
517 buffer_new => dma_buffer_new, --buffer_new,
513 buffer_addr => dma_buffer_addr, --buffer_addr,
518 buffer_addr => dma_buffer_addr, --buffer_addr,
514 buffer_length => dma_buffer_length, --buffer_length,
519 buffer_length => dma_buffer_length, --buffer_length,
515 buffer_full => dma_buffer_full, --buffer_full,
520 buffer_full => dma_buffer_full, --buffer_full,
516 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
521 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
517 grant_error => dma_grant_error); --grant_error);
522 grant_error => dma_grant_error); --grant_error);
518
523
519 END beh;
524 END beh;
Show file before | Show file after | Hide comments
@@ -1,792 +1,825
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31
31
32 LIBRARY lpp;
32 LIBRARY lpp;
33 USE lpp.lpp_lfr_pkg.ALL;
33 USE lpp.lpp_lfr_pkg.ALL;
34 USE lpp.apb_devices_list.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37
37
38 LIBRARY techmap;
38 LIBRARY techmap;
39 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
40
40
41 ENTITY lpp_lfr_apbreg IS
41 ENTITY lpp_lfr_apbreg IS
42 GENERIC (
42 GENERIC (
43 nb_data_by_buffer_size : INTEGER := 11;
43 nb_data_by_buffer_size : INTEGER := 11;
44 nb_snapshot_param_size : INTEGER := 11;
44 nb_snapshot_param_size : INTEGER := 11;
45 delta_vector_size : INTEGER := 20;
45 delta_vector_size : INTEGER := 20;
46 delta_vector_size_f0_2 : INTEGER := 3;
46 delta_vector_size_f0_2 : INTEGER := 3;
47
47
48 pindex : INTEGER := 4;
48 pindex : INTEGER := 4;
49 paddr : INTEGER := 4;
49 paddr : INTEGER := 4;
50 pmask : INTEGER := 16#fff#;
50 pmask : INTEGER := 16#fff#;
51 pirq_ms : INTEGER := 0;
51 pirq_ms : INTEGER := 0;
52 pirq_wfp : INTEGER := 1;
52 pirq_wfp : INTEGER := 1;
53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
54 PORT (
54 PORT (
55 -- AMBA AHB system signals
55 -- AMBA AHB system signals
56 HCLK : IN STD_ULOGIC;
56 HCLK : IN STD_ULOGIC;
57 HRESETn : IN STD_ULOGIC;
57 HRESETn : IN STD_ULOGIC;
58
58
59 -- AMBA APB Slave Interface
59 -- AMBA APB Slave Interface
60 apbi : IN apb_slv_in_type;
60 apbi : IN apb_slv_in_type;
61 apbo : OUT apb_slv_out_type;
61 apbo : OUT apb_slv_out_type;
62
62
63 ---------------------------------------------------------------------------
63 ---------------------------------------------------------------------------
64 -- Spectral Matrix Reg
64 -- Spectral Matrix Reg
65 run_ms : OUT STD_LOGIC;
65 run_ms : OUT STD_LOGIC;
66 -- IN
66 -- IN
67 ready_matrix_f0 : IN STD_LOGIC;
67 ready_matrix_f0 : IN STD_LOGIC;
68 ready_matrix_f1 : IN STD_LOGIC;
68 ready_matrix_f1 : IN STD_LOGIC;
69 ready_matrix_f2 : IN STD_LOGIC;
69 ready_matrix_f2 : IN STD_LOGIC;
70
70
71 -- error_bad_component_error : IN STD_LOGIC;
71 -- error_bad_component_error : IN STD_LOGIC;
72 error_buffer_full : IN STD_LOGIC; -- TODO
72 error_buffer_full : IN STD_LOGIC; -- TODO
73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
74
74
75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76
76
77 -- OUT
77 -- OUT
78 status_ready_matrix_f0 : OUT STD_LOGIC;
78 status_ready_matrix_f0 : OUT STD_LOGIC;
79 status_ready_matrix_f1 : OUT STD_LOGIC;
79 status_ready_matrix_f1 : OUT STD_LOGIC;
80 status_ready_matrix_f2 : OUT STD_LOGIC;
80 status_ready_matrix_f2 : OUT STD_LOGIC;
81
81
82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
83 --config_active_interruption_onError : OUT STD_LOGIC;
83 --config_active_interruption_onError : OUT STD_LOGIC;
84
84
85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88
88
89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92
92
93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
96
96
97 ---------------------------------------------------------------------------
97 ---------------------------------------------------------------------------
98 ---------------------------------------------------------------------------
98 ---------------------------------------------------------------------------
99 -- WaveForm picker Reg
99 -- WaveForm picker Reg
100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
104
104
105 -- OUT
105 -- OUT
106 data_shaping_BW : OUT STD_LOGIC;
106 data_shaping_BW : OUT STD_LOGIC;
107 data_shaping_SP0 : OUT STD_LOGIC;
107 data_shaping_SP0 : OUT STD_LOGIC;
108 data_shaping_SP1 : OUT STD_LOGIC;
108 data_shaping_SP1 : OUT STD_LOGIC;
109 data_shaping_R0 : OUT STD_LOGIC;
109 data_shaping_R0 : OUT STD_LOGIC;
110 data_shaping_R1 : OUT STD_LOGIC;
110 data_shaping_R1 : OUT STD_LOGIC;
111 data_shaping_R2 : OUT STD_LOGIC;
111 data_shaping_R2 : OUT STD_LOGIC;
112
112
113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
121
121
122 enable_f0 : OUT STD_LOGIC;
122 enable_f0 : OUT STD_LOGIC;
123 enable_f1 : OUT STD_LOGIC;
123 enable_f1 : OUT STD_LOGIC;
124 enable_f2 : OUT STD_LOGIC;
124 enable_f2 : OUT STD_LOGIC;
125 enable_f3 : OUT STD_LOGIC;
125 enable_f3 : OUT STD_LOGIC;
126
126
127 burst_f0 : OUT STD_LOGIC;
127 burst_f0 : OUT STD_LOGIC;
128 burst_f1 : OUT STD_LOGIC;
128 burst_f1 : OUT STD_LOGIC;
129 burst_f2 : OUT STD_LOGIC;
129 burst_f2 : OUT STD_LOGIC;
130
130
131 run : OUT STD_LOGIC;
131 run : OUT STD_LOGIC;
132
132
133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
134
134
135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
141 ---------------------------------------------------------------------------
141 ---------------------------------------------------------------------------
142 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
143 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
144 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
145 sample_f3_valid : IN STD_LOGIC;
146 ---------------------------------------------------------------------------
142 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
147 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
143
148
144 );
149 );
145
150
146 END lpp_lfr_apbreg;
151 END lpp_lfr_apbreg;
147
152
148 ARCHITECTURE beh OF lpp_lfr_apbreg IS
153 ARCHITECTURE beh OF lpp_lfr_apbreg IS
149
154
150 CONSTANT REVISION : INTEGER := 1;
155 CONSTANT REVISION : INTEGER := 1;
151
156
152 CONSTANT pconfig : apb_config_type := (
157 CONSTANT pconfig : apb_config_type := (
153 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
158 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
154 1 => apb_iobar(paddr, pmask));
159 1 => apb_iobar(paddr, pmask));
155
160
156 --CONSTANT pconfig : apb_config_type := (
161 --CONSTANT pconfig : apb_config_type := (
157 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
162 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
158 -- 1 => apb_iobar(paddr, pmask));
163 -- 1 => apb_iobar(paddr, pmask));
159
164
160 TYPE lpp_SpectralMatrix_regs IS RECORD
165 TYPE lpp_SpectralMatrix_regs IS RECORD
161 config_active_interruption_onNewMatrix : STD_LOGIC;
166 config_active_interruption_onNewMatrix : STD_LOGIC;
162 config_active_interruption_onError : STD_LOGIC;
167 config_active_interruption_onError : STD_LOGIC;
163 config_ms_run : STD_LOGIC;
168 config_ms_run : STD_LOGIC;
164 status_ready_matrix_f0_0 : STD_LOGIC;
169 status_ready_matrix_f0_0 : STD_LOGIC;
165 status_ready_matrix_f1_0 : STD_LOGIC;
170 status_ready_matrix_f1_0 : STD_LOGIC;
166 status_ready_matrix_f2_0 : STD_LOGIC;
171 status_ready_matrix_f2_0 : STD_LOGIC;
167 status_ready_matrix_f0_1 : STD_LOGIC;
172 status_ready_matrix_f0_1 : STD_LOGIC;
168 status_ready_matrix_f1_1 : STD_LOGIC;
173 status_ready_matrix_f1_1 : STD_LOGIC;
169 status_ready_matrix_f2_1 : STD_LOGIC;
174 status_ready_matrix_f2_1 : STD_LOGIC;
170 -- status_error_bad_component_error : STD_LOGIC;
175 -- status_error_bad_component_error : STD_LOGIC;
171 status_error_buffer_full : STD_LOGIC;
176 status_error_buffer_full : STD_LOGIC;
172 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
177 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
173
178
174 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180
185
181 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
186 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
182
187
183 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
184 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
189 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
185 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
190 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
186 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
191 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
192 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
193 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
189 END RECORD;
194 END RECORD;
190 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
195 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
191
196
192 TYPE lpp_WaveformPicker_regs IS RECORD
197 TYPE lpp_WaveformPicker_regs IS RECORD
193 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
198 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
199 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
195 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
200 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
196 data_shaping_BW : STD_LOGIC;
201 data_shaping_BW : STD_LOGIC;
197 data_shaping_SP0 : STD_LOGIC;
202 data_shaping_SP0 : STD_LOGIC;
198 data_shaping_SP1 : STD_LOGIC;
203 data_shaping_SP1 : STD_LOGIC;
199 data_shaping_R0 : STD_LOGIC;
204 data_shaping_R0 : STD_LOGIC;
200 data_shaping_R1 : STD_LOGIC;
205 data_shaping_R1 : STD_LOGIC;
201 data_shaping_R2 : STD_LOGIC;
206 data_shaping_R2 : STD_LOGIC;
202 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
207 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
203 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
208 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
204 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
209 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
205 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
210 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
206 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
211 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
207 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
212 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
208 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
213 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
209 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
214 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
210 enable_f0 : STD_LOGIC;
215 enable_f0 : STD_LOGIC;
211 enable_f1 : STD_LOGIC;
216 enable_f1 : STD_LOGIC;
212 enable_f2 : STD_LOGIC;
217 enable_f2 : STD_LOGIC;
213 enable_f3 : STD_LOGIC;
218 enable_f3 : STD_LOGIC;
214 burst_f0 : STD_LOGIC;
219 burst_f0 : STD_LOGIC;
215 burst_f1 : STD_LOGIC;
220 burst_f1 : STD_LOGIC;
216 burst_f2 : STD_LOGIC;
221 burst_f2 : STD_LOGIC;
217 run : STD_LOGIC;
222 run : STD_LOGIC;
218 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
223 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
219 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
224 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
220 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
225 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
221 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
226 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
222 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
227 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
223 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
228 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
224 END RECORD;
229 END RECORD;
225 SIGNAL reg_wp : lpp_WaveformPicker_regs;
230 SIGNAL reg_wp : lpp_WaveformPicker_regs;
226
231
227 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
228
233
229 -----------------------------------------------------------------------------
234 -----------------------------------------------------------------------------
230 -- IRQ
235 -- IRQ
231 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
232 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
237 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
233 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
238 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
234 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
239 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
235 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
240 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
236 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
241 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
237 SIGNAL ored_irq_wfp : STD_LOGIC;
242 SIGNAL ored_irq_wfp : STD_LOGIC;
238
243
239 -----------------------------------------------------------------------------
244 -----------------------------------------------------------------------------
240 --
245 --
241 -----------------------------------------------------------------------------
246 -----------------------------------------------------------------------------
242 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
247 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
243 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
249 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
245
250
246 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
251 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
247 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
253 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
249
254
250 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
255 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
251 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
256 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
257 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
253
258
254 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
259 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
255 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
256 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
261 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
257
262
258 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
263 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
259 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
264 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
265 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
261
266
262 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
267 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
263 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
264 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
269 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
265 SIGNAL apbo_irq_ms : STD_LOGIC;
270 SIGNAL apbo_irq_ms : STD_LOGIC;
266 SIGNAL apbo_irq_wfp : STD_LOGIC;
271 SIGNAL apbo_irq_wfp : STD_LOGIC;
267 -----------------------------------------------------------------------------
272 -----------------------------------------------------------------------------
268 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
273 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
269
274
270 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
271
276
277 SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
278 SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
279 SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
280
272 BEGIN -- beh
281 BEGIN -- beh
273
282
274 debug_vector(0) <= error_buffer_full;
283 debug_vector(0) <= error_buffer_full;
275 debug_vector(1) <= reg_sp.status_error_buffer_full;
284 debug_vector(1) <= reg_sp.status_error_buffer_full;
276 debug_vector(4 DOWNTO 2) <= error_input_fifo_write;
285 debug_vector(4 DOWNTO 2) <= error_input_fifo_write;
277 debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write;
286 debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write;
278 debug_vector(8) <= ready_matrix_f2;
287 debug_vector(8) <= ready_matrix_f2;
279 debug_vector(9) <= reg0_ready_matrix_f2;
288 debug_vector(9) <= reg0_ready_matrix_f2;
280 debug_vector(10) <= reg1_ready_matrix_f2;
289 debug_vector(10) <= reg1_ready_matrix_f2;
281 debug_vector(11) <= HRESETn;
290 debug_vector(11) <= HRESETn;
282
291
283 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
292 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
284 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
293 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
285 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
294 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
286
295
287 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
296 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
288 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
297 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
289
298
290
299
291 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
300 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
292 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
301 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
293 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
302 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
294
303
295
304
296 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
305 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
297 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
306 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
298 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
307 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
299 data_shaping_R0 <= reg_wp.data_shaping_R0;
308 data_shaping_R0 <= reg_wp.data_shaping_R0;
300 data_shaping_R1 <= reg_wp.data_shaping_R1;
309 data_shaping_R1 <= reg_wp.data_shaping_R1;
301 data_shaping_R2 <= reg_wp.data_shaping_R2;
310 data_shaping_R2 <= reg_wp.data_shaping_R2;
302
311
303 delta_snapshot <= reg_wp.delta_snapshot;
312 delta_snapshot <= reg_wp.delta_snapshot;
304 delta_f0 <= reg_wp.delta_f0;
313 delta_f0 <= reg_wp.delta_f0;
305 delta_f0_2 <= reg_wp.delta_f0_2;
314 delta_f0_2 <= reg_wp.delta_f0_2;
306 delta_f1 <= reg_wp.delta_f1;
315 delta_f1 <= reg_wp.delta_f1;
307 delta_f2 <= reg_wp.delta_f2;
316 delta_f2 <= reg_wp.delta_f2;
308 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
317 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
309 nb_snapshot_param <= reg_wp.nb_snapshot_param;
318 nb_snapshot_param <= reg_wp.nb_snapshot_param;
310
319
311 enable_f0 <= reg_wp.enable_f0;
320 enable_f0 <= reg_wp.enable_f0;
312 enable_f1 <= reg_wp.enable_f1;
321 enable_f1 <= reg_wp.enable_f1;
313 enable_f2 <= reg_wp.enable_f2;
322 enable_f2 <= reg_wp.enable_f2;
314 enable_f3 <= reg_wp.enable_f3;
323 enable_f3 <= reg_wp.enable_f3;
315
324
316 burst_f0 <= reg_wp.burst_f0;
325 burst_f0 <= reg_wp.burst_f0;
317 burst_f1 <= reg_wp.burst_f1;
326 burst_f1 <= reg_wp.burst_f1;
318 burst_f2 <= reg_wp.burst_f2;
327 burst_f2 <= reg_wp.burst_f2;
319
328
320 run <= reg_wp.run;
329 run <= reg_wp.run;
321
330
322 --addr_data_f0 <= reg_wp.addr_data_f0;
331 --addr_data_f0 <= reg_wp.addr_data_f0;
323 --addr_data_f1 <= reg_wp.addr_data_f1;
332 --addr_data_f1 <= reg_wp.addr_data_f1;
324 --addr_data_f2 <= reg_wp.addr_data_f2;
333 --addr_data_f2 <= reg_wp.addr_data_f2;
325 --addr_data_f3 <= reg_wp.addr_data_f3;
334 --addr_data_f3 <= reg_wp.addr_data_f3;
326
335
327 start_date <= reg_wp.start_date;
336 start_date <= reg_wp.start_date;
328
337
329 length_matrix_f0 <= reg_sp.length_matrix;
338 length_matrix_f0 <= reg_sp.length_matrix;
330 length_matrix_f1 <= reg_sp.length_matrix;
339 length_matrix_f1 <= reg_sp.length_matrix;
331 length_matrix_f2 <= reg_sp.length_matrix;
340 length_matrix_f2 <= reg_sp.length_matrix;
332 wfp_length_buffer <= reg_wp.length_buffer;
341 wfp_length_buffer <= reg_wp.length_buffer;
342
343
344
345 PROCESS (HCLK, HRESETn)
346 BEGIN -- PROCESS
347 IF HRESETn = '0' THEN -- asynchronous reset (active low)
348 sample_f3_v_reg <= (OTHERS => '0');
349 sample_f3_e1_reg <= (OTHERS => '0');
350 sample_f3_e2_reg <= (OTHERS => '0');
351 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
352 IF sample_f3_valid = '1' THEN
353 sample_f3_v_reg <= sample_f3_v;
354 sample_f3_e1_reg <= sample_f3_e1;
355 sample_f3_e2_reg <= sample_f3_e2;
356 END IF;
357 END IF;
358 END PROCESS;
333
359
334
360
335 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
361 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
336 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
362 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
337 BEGIN -- PROCESS lpp_dma_top
363 BEGIN -- PROCESS lpp_dma_top
338 IF HRESETn = '0' THEN -- asynchronous reset (active low)
364 IF HRESETn = '0' THEN -- asynchronous reset (active low)
339 reg_sp.config_active_interruption_onNewMatrix <= '0';
365 reg_sp.config_active_interruption_onNewMatrix <= '0';
340 reg_sp.config_active_interruption_onError <= '0';
366 reg_sp.config_active_interruption_onError <= '0';
341 reg_sp.config_ms_run <= '0';
367 reg_sp.config_ms_run <= '0';
342 reg_sp.status_ready_matrix_f0_0 <= '0';
368 reg_sp.status_ready_matrix_f0_0 <= '0';
343 reg_sp.status_ready_matrix_f1_0 <= '0';
369 reg_sp.status_ready_matrix_f1_0 <= '0';
344 reg_sp.status_ready_matrix_f2_0 <= '0';
370 reg_sp.status_ready_matrix_f2_0 <= '0';
345 reg_sp.status_ready_matrix_f0_1 <= '0';
371 reg_sp.status_ready_matrix_f0_1 <= '0';
346 reg_sp.status_ready_matrix_f1_1 <= '0';
372 reg_sp.status_ready_matrix_f1_1 <= '0';
347 reg_sp.status_ready_matrix_f2_1 <= '0';
373 reg_sp.status_ready_matrix_f2_1 <= '0';
348 reg_sp.status_error_buffer_full <= '0';
374 reg_sp.status_error_buffer_full <= '0';
349 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
375 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
350
376
351 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
377 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
352 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
378 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
353 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
379 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
354
380
355 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
381 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
356 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
382 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
357 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
383 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
358
384
359 reg_sp.length_matrix <= (OTHERS => '0');
385 reg_sp.length_matrix <= (OTHERS => '0');
360
386
361 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
387 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
362 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
388 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
363 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
389 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
364
390
365 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
391 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
366 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
392 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
367 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
393 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
368
394
369 prdata <= (OTHERS => '0');
395 prdata <= (OTHERS => '0');
370
396
371
397
372 apbo_irq_ms <= '0';
398 apbo_irq_ms <= '0';
373 apbo_irq_wfp <= '0';
399 apbo_irq_wfp <= '0';
374
400
375
401
376 -- status_full_ack <= (OTHERS => '0');
402 -- status_full_ack <= (OTHERS => '0');
377
403
378 reg_wp.data_shaping_BW <= '0';
404 reg_wp.data_shaping_BW <= '0';
379 reg_wp.data_shaping_SP0 <= '0';
405 reg_wp.data_shaping_SP0 <= '0';
380 reg_wp.data_shaping_SP1 <= '0';
406 reg_wp.data_shaping_SP1 <= '0';
381 reg_wp.data_shaping_R0 <= '0';
407 reg_wp.data_shaping_R0 <= '0';
382 reg_wp.data_shaping_R1 <= '0';
408 reg_wp.data_shaping_R1 <= '0';
383 reg_wp.data_shaping_R2 <= '0';
409 reg_wp.data_shaping_R2 <= '0';
384 reg_wp.enable_f0 <= '0';
410 reg_wp.enable_f0 <= '0';
385 reg_wp.enable_f1 <= '0';
411 reg_wp.enable_f1 <= '0';
386 reg_wp.enable_f2 <= '0';
412 reg_wp.enable_f2 <= '0';
387 reg_wp.enable_f3 <= '0';
413 reg_wp.enable_f3 <= '0';
388 reg_wp.burst_f0 <= '0';
414 reg_wp.burst_f0 <= '0';
389 reg_wp.burst_f1 <= '0';
415 reg_wp.burst_f1 <= '0';
390 reg_wp.burst_f2 <= '0';
416 reg_wp.burst_f2 <= '0';
391 reg_wp.run <= '0';
417 reg_wp.run <= '0';
392 -- reg_wp.status_full <= (OTHERS => '0');
418 -- reg_wp.status_full <= (OTHERS => '0');
393 -- reg_wp.status_full_err <= (OTHERS => '0');
419 -- reg_wp.status_full_err <= (OTHERS => '0');
394 reg_wp.status_new_err <= (OTHERS => '0');
420 reg_wp.status_new_err <= (OTHERS => '0');
395 reg_wp.error_buffer_full <= (OTHERS => '0');
421 reg_wp.error_buffer_full <= (OTHERS => '0');
396 reg_wp.delta_snapshot <= (OTHERS => '0');
422 reg_wp.delta_snapshot <= (OTHERS => '0');
397 reg_wp.delta_f0 <= (OTHERS => '0');
423 reg_wp.delta_f0 <= (OTHERS => '0');
398 reg_wp.delta_f0_2 <= (OTHERS => '0');
424 reg_wp.delta_f0_2 <= (OTHERS => '0');
399 reg_wp.delta_f1 <= (OTHERS => '0');
425 reg_wp.delta_f1 <= (OTHERS => '0');
400 reg_wp.delta_f2 <= (OTHERS => '0');
426 reg_wp.delta_f2 <= (OTHERS => '0');
401 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
427 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
402 reg_wp.nb_snapshot_param <= (OTHERS => '0');
428 reg_wp.nb_snapshot_param <= (OTHERS => '0');
403 reg_wp.start_date <= (OTHERS => '1');
429 reg_wp.start_date <= (OTHERS => '1');
404
430
405 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
431 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
406 reg_wp.length_buffer <= (OTHERS => '0');
432 reg_wp.length_buffer <= (OTHERS => '0');
407
433
408 pirq_temp <= (OTHERS => '0');
434 pirq_temp <= (OTHERS => '0');
409
435
410 reg_wp.addr_buffer_f <= (OTHERS => '0');
436 reg_wp.addr_buffer_f <= (OTHERS => '0');
411
437
412 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
438 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
413
439
414 -- status_full_ack <= (OTHERS => '0');
440 -- status_full_ack <= (OTHERS => '0');
415
441
416 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
442 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
417 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
443 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
418 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
444 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
419
445
420 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
446 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
421 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
447 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
422 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
448 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
423
449
424 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
450 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
425 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
451 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
426 END LOOP all_status_ready_buffer_bit;
452 END LOOP all_status_ready_buffer_bit;
427
453
428
454
429 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
455 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
430 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
456 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
431 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
457 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
432 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
458 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
433
459
434
460
435
461
436 all_status : FOR I IN 3 DOWNTO 0 LOOP
462 all_status : FOR I IN 3 DOWNTO 0 LOOP
437 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
463 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
438 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
464 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
439 END LOOP all_status;
465 END LOOP all_status;
440
466
441 paddr := "000000";
467 paddr := "000000";
442 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
468 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
443 prdata <= (OTHERS => '0');
469 prdata <= (OTHERS => '0');
444 IF apbi.psel(pindex) = '1' THEN
470 IF apbi.psel(pindex) = '1' THEN
445 -- APB DMA READ --
471 -- APB DMA READ --
446 CASE paddr(7 DOWNTO 2) IS
472 CASE paddr(7 DOWNTO 2) IS
447
473
448 WHEN ADDR_LFR_SM_CONFIG =>
474 WHEN ADDR_LFR_SM_CONFIG =>
449 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
475 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
450 prdata(1) <= reg_sp.config_active_interruption_onError;
476 prdata(1) <= reg_sp.config_active_interruption_onError;
451 prdata(2) <= reg_sp.config_ms_run;
477 prdata(2) <= reg_sp.config_ms_run;
452
478
453 WHEN ADDR_LFR_SM_STATUS =>
479 WHEN ADDR_LFR_SM_STATUS =>
454 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
480 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
455 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
481 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
456 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
482 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
457 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
483 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
458 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
484 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
459 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
485 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
460 -- prdata(6) <= reg_sp.status_error_bad_component_error;
486 -- prdata(6) <= reg_sp.status_error_bad_component_error;
461 prdata(7) <= reg_sp.status_error_buffer_full;
487 prdata(7) <= reg_sp.status_error_buffer_full;
462 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
488 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
463 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
489 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
464 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
490 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
465
491
466 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
492 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
467 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
493 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
468 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
494 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
469 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
495 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
470 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
496 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
471 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
497 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
472 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
498 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
473 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
499 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
474 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
500 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
475 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
501 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
476 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
502 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
477 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
503 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
478 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
504 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
479 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
505 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
480 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
506 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
481 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
507 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
482 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
508 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
483 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
509 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
484 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
510 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
485 ---------------------------------------------------------------------
511 ---------------------------------------------------------------------
486 WHEN ADDR_LFR_WP_DATASHAPING =>
512 WHEN ADDR_LFR_WP_DATASHAPING =>
487 prdata(0) <= reg_wp.data_shaping_BW;
513 prdata(0) <= reg_wp.data_shaping_BW;
488 prdata(1) <= reg_wp.data_shaping_SP0;
514 prdata(1) <= reg_wp.data_shaping_SP0;
489 prdata(2) <= reg_wp.data_shaping_SP1;
515 prdata(2) <= reg_wp.data_shaping_SP1;
490 prdata(3) <= reg_wp.data_shaping_R0;
516 prdata(3) <= reg_wp.data_shaping_R0;
491 prdata(4) <= reg_wp.data_shaping_R1;
517 prdata(4) <= reg_wp.data_shaping_R1;
492 prdata(5) <= reg_wp.data_shaping_R2;
518 prdata(5) <= reg_wp.data_shaping_R2;
493 WHEN ADDR_LFR_WP_CONTROL =>
519 WHEN ADDR_LFR_WP_CONTROL =>
494 prdata(0) <= reg_wp.enable_f0;
520 prdata(0) <= reg_wp.enable_f0;
495 prdata(1) <= reg_wp.enable_f1;
521 prdata(1) <= reg_wp.enable_f1;
496 prdata(2) <= reg_wp.enable_f2;
522 prdata(2) <= reg_wp.enable_f2;
497 prdata(3) <= reg_wp.enable_f3;
523 prdata(3) <= reg_wp.enable_f3;
498 prdata(4) <= reg_wp.burst_f0;
524 prdata(4) <= reg_wp.burst_f0;
499 prdata(5) <= reg_wp.burst_f1;
525 prdata(5) <= reg_wp.burst_f1;
500 prdata(6) <= reg_wp.burst_f2;
526 prdata(6) <= reg_wp.burst_f2;
501 prdata(7) <= reg_wp.run;
527 prdata(7) <= reg_wp.run;
502 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
528 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
503 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
529 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
504 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
530 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
505 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
531 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
506 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
532 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
507 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
533 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
508 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
534 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
509 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
535 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
510
536
511 WHEN ADDR_LFR_WP_STATUS =>
537 WHEN ADDR_LFR_WP_STATUS =>
512 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
538 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
513 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
539 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
514 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
540 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
515
541
516 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
542 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
517 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
543 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
518 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
544 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
519 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
545 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
520 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
546 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
521 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
547 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
522 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
548 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
523 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
549 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
524
550
525 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
551 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
526 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
552 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
527 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
553 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
528 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
554 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
529
555
530 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
556 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
531 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
557 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
532 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
558 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
533 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
559 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
534
560
535 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
561 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
536 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
562 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
537 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
563 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
538 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
564 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
539
565
540 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
566 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
541 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
567 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
542 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
568 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
543 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
569 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
544
570
545 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
571 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
572
573 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
574 prdata(31 DOWNTO 16) <= (OTHERS => '0');
575 WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg;
576 prdata(31 DOWNTO 16) <= (OTHERS => '0');
577 WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg;
578 prdata(31 DOWNTO 16) <= (OTHERS => '0');
546 ---------------------------------------------------------------------
579 ---------------------------------------------------------------------
547 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
580 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
548 WHEN OTHERS => NULL;
581 WHEN OTHERS => NULL;
549
582
550 END CASE;
583 END CASE;
551 IF (apbi.pwrite AND apbi.penable) = '1' THEN
584 IF (apbi.pwrite AND apbi.penable) = '1' THEN
552 -- APB DMA WRITE --
585 -- APB DMA WRITE --
553 CASE paddr(7 DOWNTO 2) IS
586 CASE paddr(7 DOWNTO 2) IS
554 --
587 --
555 WHEN ADDR_LFR_SM_CONFIG =>
588 WHEN ADDR_LFR_SM_CONFIG =>
556 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
589 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
557 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
590 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
558 reg_sp.config_ms_run <= apbi.pwdata(2);
591 reg_sp.config_ms_run <= apbi.pwdata(2);
559
592
560 WHEN ADDR_LFR_SM_STATUS =>
593 WHEN ADDR_LFR_SM_STATUS =>
561 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
594 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
562 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
595 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
563 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
596 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
564 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
597 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
565 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
598 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
566 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
599 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
567 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
600 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
568 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
601 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
569 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
602 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
570 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
603 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
571 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
604 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
572 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
605 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
573 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
606 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
574 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
607 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
575 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
608 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
576 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
609 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
577
610
578 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
611 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
579 ---------------------------------------------------------------------
612 ---------------------------------------------------------------------
580 WHEN ADDR_LFR_WP_DATASHAPING =>
613 WHEN ADDR_LFR_WP_DATASHAPING =>
581 reg_wp.data_shaping_BW <= apbi.pwdata(0);
614 reg_wp.data_shaping_BW <= apbi.pwdata(0);
582 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
615 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
583 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
616 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
584 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
617 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
585 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
618 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
586 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
619 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
587 WHEN ADDR_LFR_WP_CONTROL =>
620 WHEN ADDR_LFR_WP_CONTROL =>
588 reg_wp.enable_f0 <= apbi.pwdata(0);
621 reg_wp.enable_f0 <= apbi.pwdata(0);
589 reg_wp.enable_f1 <= apbi.pwdata(1);
622 reg_wp.enable_f1 <= apbi.pwdata(1);
590 reg_wp.enable_f2 <= apbi.pwdata(2);
623 reg_wp.enable_f2 <= apbi.pwdata(2);
591 reg_wp.enable_f3 <= apbi.pwdata(3);
624 reg_wp.enable_f3 <= apbi.pwdata(3);
592 reg_wp.burst_f0 <= apbi.pwdata(4);
625 reg_wp.burst_f0 <= apbi.pwdata(4);
593 reg_wp.burst_f1 <= apbi.pwdata(5);
626 reg_wp.burst_f1 <= apbi.pwdata(5);
594 reg_wp.burst_f2 <= apbi.pwdata(6);
627 reg_wp.burst_f2 <= apbi.pwdata(6);
595 reg_wp.run <= apbi.pwdata(7);
628 reg_wp.run <= apbi.pwdata(7);
596 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
629 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
597 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
630 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
598 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
631 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
599 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
632 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
600 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
633 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
601 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
634 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
602 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
635 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
603 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
636 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
604 WHEN ADDR_LFR_WP_STATUS =>
637 WHEN ADDR_LFR_WP_STATUS =>
605 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
638 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
606 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
639 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
607 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
640 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
608 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
641 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
609 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
642 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
610 END LOOP all_reg_wp_status_bit;
643 END LOOP all_reg_wp_status_bit;
611
644
612 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
645 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
613 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
646 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
614 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
647 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
615 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
648 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
616 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
649 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
617 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
650 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
618 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
651 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
619 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
652 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
620
653
621 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
654 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
622
655
623 WHEN OTHERS => NULL;
656 WHEN OTHERS => NULL;
624 END CASE;
657 END CASE;
625 END IF;
658 END IF;
626 END IF;
659 END IF;
627 --apbo.pirq(pirq_ms) <=
660 --apbo.pirq(pirq_ms) <=
628 pirq_temp( pirq_ms) <= apbo_irq_ms;
661 pirq_temp( pirq_ms) <= apbo_irq_ms;
629 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
662 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
630 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
663 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
631 ready_matrix_f1 OR
664 ready_matrix_f1 OR
632 ready_matrix_f2)
665 ready_matrix_f2)
633 )
666 )
634 OR
667 OR
635 (reg_sp.config_active_interruption_onError AND (
668 (reg_sp.config_active_interruption_onError AND (
636 -- error_bad_component_error OR
669 -- error_bad_component_error OR
637 error_buffer_full
670 error_buffer_full
638 OR error_input_fifo_write(0)
671 OR error_input_fifo_write(0)
639 OR error_input_fifo_write(1)
672 OR error_input_fifo_write(1)
640 OR error_input_fifo_write(2))
673 OR error_input_fifo_write(2))
641 ));
674 ));
642 -- apbo.pirq(pirq_wfp)
675 -- apbo.pirq(pirq_wfp)
643 apbo_irq_wfp<= ored_irq_wfp;
676 apbo_irq_wfp<= ored_irq_wfp;
644
677
645 END IF;
678 END IF;
646 END PROCESS lpp_lfr_apbreg;
679 END PROCESS lpp_lfr_apbreg;
647
680
648 apbo.pirq <= pirq_temp;
681 apbo.pirq <= pirq_temp;
649
682
650
683
651 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
684 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
652 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
685 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
653 -- apbo.pirq(I) <= apbo_irq_ms;
686 -- apbo.pirq(I) <= apbo_irq_ms;
654 -- END GENERATE IRQ_is_PIRQ_MS;
687 -- END GENERATE IRQ_is_PIRQ_MS;
655 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
688 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
656 -- apbo.pirq(I) <= apbo_irq_wfp;
689 -- apbo.pirq(I) <= apbo_irq_wfp;
657 -- END GENERATE IRQ_is_PIRQ_WFP;
690 -- END GENERATE IRQ_is_PIRQ_WFP;
658 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
691 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
659 -- apbo.pirq(I) <= '0';
692 -- apbo.pirq(I) <= '0';
660 -- END GENERATE IRQ_OTHERS;
693 -- END GENERATE IRQ_OTHERS;
661
694
662 --END GENERATE all_irq;
695 --END GENERATE all_irq;
663
696
664
697
665
698
666 apbo.pindex <= pindex;
699 apbo.pindex <= pindex;
667 apbo.pconfig <= pconfig;
700 apbo.pconfig <= pconfig;
668 apbo.prdata <= prdata;
701 apbo.prdata <= prdata;
669
702
670 -----------------------------------------------------------------------------
703 -----------------------------------------------------------------------------
671 -- IRQ
704 -- IRQ
672 -----------------------------------------------------------------------------
705 -----------------------------------------------------------------------------
673 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
706 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
674
707
675 PROCESS (HCLK, HRESETn)
708 PROCESS (HCLK, HRESETn)
676 BEGIN -- PROCESS
709 BEGIN -- PROCESS
677 IF HRESETn = '0' THEN -- asynchronous reset (active low)
710 IF HRESETn = '0' THEN -- asynchronous reset (active low)
678 irq_wfp_reg <= (OTHERS => '0');
711 irq_wfp_reg <= (OTHERS => '0');
679 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
712 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
680 irq_wfp_reg <= irq_wfp_reg_s;
713 irq_wfp_reg <= irq_wfp_reg_s;
681 END IF;
714 END IF;
682 END PROCESS;
715 END PROCESS;
683
716
684 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
717 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
685 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
718 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
686 END GENERATE all_irq_wfp;
719 END GENERATE all_irq_wfp;
687
720
688 irq_wfp_ZERO <= (OTHERS => '0');
721 irq_wfp_ZERO <= (OTHERS => '0');
689 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
722 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
690
723
691 run_ms <= reg_sp.config_ms_run;
724 run_ms <= reg_sp.config_ms_run;
692
725
693 -----------------------------------------------------------------------------
726 -----------------------------------------------------------------------------
694 --
727 --
695 -----------------------------------------------------------------------------
728 -----------------------------------------------------------------------------
696 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
729 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
697 PORT MAP (
730 PORT MAP (
698 clk => HCLK,
731 clk => HCLK,
699 rstn => HRESETn,
732 rstn => HRESETn,
700
733
701 run => '1',--reg_sp.config_ms_run,
734 run => '1',--reg_sp.config_ms_run,
702
735
703 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
736 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
704 reg0_ready_matrix => reg0_ready_matrix_f0,
737 reg0_ready_matrix => reg0_ready_matrix_f0,
705 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
738 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
706 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
739 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
707
740
708 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
741 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
709 reg1_ready_matrix => reg1_ready_matrix_f0,
742 reg1_ready_matrix => reg1_ready_matrix_f0,
710 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
743 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
711 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
744 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
712
745
713 ready_matrix => ready_matrix_f0,
746 ready_matrix => ready_matrix_f0,
714 status_ready_matrix => status_ready_matrix_f0,
747 status_ready_matrix => status_ready_matrix_f0,
715 addr_matrix => addr_matrix_f0,
748 addr_matrix => addr_matrix_f0,
716 matrix_time => matrix_time_f0);
749 matrix_time => matrix_time_f0);
717
750
718 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
751 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
719 PORT MAP (
752 PORT MAP (
720 clk => HCLK,
753 clk => HCLK,
721 rstn => HRESETn,
754 rstn => HRESETn,
722
755
723 run => '1',--reg_sp.config_ms_run,
756 run => '1',--reg_sp.config_ms_run,
724
757
725 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
758 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
726 reg0_ready_matrix => reg0_ready_matrix_f1,
759 reg0_ready_matrix => reg0_ready_matrix_f1,
727 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
760 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
728 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
761 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
729
762
730 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
763 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
731 reg1_ready_matrix => reg1_ready_matrix_f1,
764 reg1_ready_matrix => reg1_ready_matrix_f1,
732 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
765 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
733 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
766 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
734
767
735 ready_matrix => ready_matrix_f1,
768 ready_matrix => ready_matrix_f1,
736 status_ready_matrix => status_ready_matrix_f1,
769 status_ready_matrix => status_ready_matrix_f1,
737 addr_matrix => addr_matrix_f1,
770 addr_matrix => addr_matrix_f1,
738 matrix_time => matrix_time_f1);
771 matrix_time => matrix_time_f1);
739
772
740 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
773 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
741 PORT MAP (
774 PORT MAP (
742 clk => HCLK,
775 clk => HCLK,
743 rstn => HRESETn,
776 rstn => HRESETn,
744
777
745 run => '1',--reg_sp.config_ms_run,
778 run => '1',--reg_sp.config_ms_run,
746
779
747 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
780 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
748 reg0_ready_matrix => reg0_ready_matrix_f2,
781 reg0_ready_matrix => reg0_ready_matrix_f2,
749 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
782 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
750 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
783 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
751
784
752 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
785 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
753 reg1_ready_matrix => reg1_ready_matrix_f2,
786 reg1_ready_matrix => reg1_ready_matrix_f2,
754 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
787 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
755 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
788 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
756
789
757 ready_matrix => ready_matrix_f2,
790 ready_matrix => ready_matrix_f2,
758 status_ready_matrix => status_ready_matrix_f2,
791 status_ready_matrix => status_ready_matrix_f2,
759 addr_matrix => addr_matrix_f2,
792 addr_matrix => addr_matrix_f2,
760 matrix_time => matrix_time_f2);
793 matrix_time => matrix_time_f2);
761
794
762 -----------------------------------------------------------------------------
795 -----------------------------------------------------------------------------
763 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
796 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
764 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
797 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
765 PORT MAP (
798 PORT MAP (
766 clk => HCLK,
799 clk => HCLK,
767 rstn => HRESETn,
800 rstn => HRESETn,
768
801
769 run => '1',--reg_wp.run,
802 run => '1',--reg_wp.run,
770
803
771 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
804 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
772 reg0_ready_matrix => reg_ready_buffer_f(2*I),
805 reg0_ready_matrix => reg_ready_buffer_f(2*I),
773 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
806 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
774 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
807 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
775
808
776 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
809 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
777 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
810 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
778 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
811 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
779 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
812 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
780
813
781 ready_matrix => wfp_ready_buffer(I),
814 ready_matrix => wfp_ready_buffer(I),
782 status_ready_matrix => wfp_status_buffer_ready(I),
815 status_ready_matrix => wfp_status_buffer_ready(I),
783 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
816 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
784 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
817 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
785 );
818 );
786
819
787 END GENERATE all_wfp_pointer;
820 END GENERATE all_wfp_pointer;
788 -----------------------------------------------------------------------------
821 -----------------------------------------------------------------------------
789
822
790 END beh;
823 END beh;
791
824
792 ------------------------------------------------------------------------------
825 ------------------------------------------------------------------------------
Show file before | Show file after | Hide comments
@@ -1,90 +1,94
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 PACKAGE lpp_lfr_apbreg_pkg IS
5 PACKAGE lpp_lfr_apbreg_pkg IS
6
6
7 -----------------------------------------------------------------------------
7 -----------------------------------------------------------------------------
8 -- SPECTRAL_MATRIX
8 -- SPECTRAL_MATRIX
9 -----------------------------------------------------------------------------
9 -----------------------------------------------------------------------------
10 CONSTANT ADDR_LFR_SM_CONFIG : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
10 CONSTANT ADDR_LFR_SM_CONFIG : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
11 CONSTANT ADDR_LFR_SM_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
11 CONSTANT ADDR_LFR_SM_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
12 CONSTANT ADDR_LFR_SM_F0_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
12 CONSTANT ADDR_LFR_SM_F0_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
13 CONSTANT ADDR_LFR_SM_F0_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
13 CONSTANT ADDR_LFR_SM_F0_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
14
14
15 CONSTANT ADDR_LFR_SM_F1_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
15 CONSTANT ADDR_LFR_SM_F1_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
16 CONSTANT ADDR_LFR_SM_F1_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
16 CONSTANT ADDR_LFR_SM_F1_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
17 CONSTANT ADDR_LFR_SM_F2_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
17 CONSTANT ADDR_LFR_SM_F2_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
18 CONSTANT ADDR_LFR_SM_F2_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111";
18 CONSTANT ADDR_LFR_SM_F2_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111";
19
19
20 CONSTANT ADDR_LFR_SM_F0_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000";
20 CONSTANT ADDR_LFR_SM_F0_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000";
21 CONSTANT ADDR_LFR_SM_F0_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
21 CONSTANT ADDR_LFR_SM_F0_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001";
22 CONSTANT ADDR_LFR_SM_F0_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
22 CONSTANT ADDR_LFR_SM_F0_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010";
23 CONSTANT ADDR_LFR_SM_F0_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
23 CONSTANT ADDR_LFR_SM_F0_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011";
24
24
25 CONSTANT ADDR_LFR_SM_F1_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001100";
25 CONSTANT ADDR_LFR_SM_F1_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001100";
26 CONSTANT ADDR_LFR_SM_F1_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001101";
26 CONSTANT ADDR_LFR_SM_F1_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001101";
27 CONSTANT ADDR_LFR_SM_F1_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001110";
27 CONSTANT ADDR_LFR_SM_F1_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001110";
28 CONSTANT ADDR_LFR_SM_F1_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001111";
28 CONSTANT ADDR_LFR_SM_F1_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001111";
29
29
30 CONSTANT ADDR_LFR_SM_F2_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010000";
30 CONSTANT ADDR_LFR_SM_F2_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010000";
31 CONSTANT ADDR_LFR_SM_F2_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010001";
31 CONSTANT ADDR_LFR_SM_F2_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010001";
32 CONSTANT ADDR_LFR_SM_F2_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010010";
32 CONSTANT ADDR_LFR_SM_F2_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010010";
33 CONSTANT ADDR_LFR_SM_F2_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010011";
33 CONSTANT ADDR_LFR_SM_F2_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010011";
34
34
35 CONSTANT ADDR_LFR_SM_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010100";
35 CONSTANT ADDR_LFR_SM_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010100";
36 -----------------------------------------------------------------------------
36 -----------------------------------------------------------------------------
37 -- WAVEFORM PICKER
37 -- WAVEFORM PICKER
38 -----------------------------------------------------------------------------
38 -----------------------------------------------------------------------------
39 CONSTANT ADDR_LFR_WP_DATASHAPING : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010101";
39 CONSTANT ADDR_LFR_WP_DATASHAPING : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010101";
40 CONSTANT ADDR_LFR_WP_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010110";
40 CONSTANT ADDR_LFR_WP_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010110";
41 CONSTANT ADDR_LFR_WP_F0_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010111";
41 CONSTANT ADDR_LFR_WP_F0_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010111";
42
42
43 CONSTANT ADDR_LFR_WP_F0_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011000";
43 CONSTANT ADDR_LFR_WP_F0_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011000";
44 CONSTANT ADDR_LFR_WP_F1_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011001";
44 CONSTANT ADDR_LFR_WP_F1_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011001";
45 CONSTANT ADDR_LFR_WP_F1_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011010";
45 CONSTANT ADDR_LFR_WP_F1_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011010";
46 CONSTANT ADDR_LFR_WP_F2_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011011";
46 CONSTANT ADDR_LFR_WP_F2_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011011";
47
47
48 CONSTANT ADDR_LFR_WP_F2_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011100";
48 CONSTANT ADDR_LFR_WP_F2_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011100";
49 CONSTANT ADDR_LFR_WP_F3_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011101";
49 CONSTANT ADDR_LFR_WP_F3_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011101";
50 CONSTANT ADDR_LFR_WP_F3_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011110";
50 CONSTANT ADDR_LFR_WP_F3_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011110";
51 CONSTANT ADDR_LFR_WP_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011111";
51 CONSTANT ADDR_LFR_WP_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011111";
52
52
53 CONSTANT ADDR_LFR_WP_DELTASNAPSHOT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100000";
53 CONSTANT ADDR_LFR_WP_DELTASNAPSHOT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100000";
54 CONSTANT ADDR_LFR_WP_DELTA_F0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100001";
54 CONSTANT ADDR_LFR_WP_DELTA_F0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100001";
55 CONSTANT ADDR_LFR_WP_DELTA_F0_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100010";
55 CONSTANT ADDR_LFR_WP_DELTA_F0_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100010";
56 CONSTANT ADDR_LFR_WP_DELTA_F1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100011";
56 CONSTANT ADDR_LFR_WP_DELTA_F1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100011";
57
57
58 CONSTANT ADDR_LFR_WP_DELTA_F2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100100";
58 CONSTANT ADDR_LFR_WP_DELTA_F2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100100";
59 CONSTANT ADDR_LFR_WP_DATA_IN_BUFFER : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100101";
59 CONSTANT ADDR_LFR_WP_DATA_IN_BUFFER : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100101";
60 CONSTANT ADDR_LFR_WP_NBSNAPSHOT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100110";
60 CONSTANT ADDR_LFR_WP_NBSNAPSHOT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100110";
61 CONSTANT ADDR_LFR_WP_START_DATE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100111";
61 CONSTANT ADDR_LFR_WP_START_DATE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100111";
62
62
63 CONSTANT ADDR_LFR_WP_F0_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101000";
63 CONSTANT ADDR_LFR_WP_F0_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101000";
64 CONSTANT ADDR_LFR_WP_F0_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101001";
64 CONSTANT ADDR_LFR_WP_F0_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101001";
65 CONSTANT ADDR_LFR_WP_F0_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101010";
65 CONSTANT ADDR_LFR_WP_F0_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101010";
66 CONSTANT ADDR_LFR_WP_F0_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101011";
66 CONSTANT ADDR_LFR_WP_F0_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101011";
67
67
68 CONSTANT ADDR_LFR_WP_F1_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101100";
68 CONSTANT ADDR_LFR_WP_F1_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101100";
69 CONSTANT ADDR_LFR_WP_F1_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101101";
69 CONSTANT ADDR_LFR_WP_F1_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101101";
70 CONSTANT ADDR_LFR_WP_F1_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101110";
70 CONSTANT ADDR_LFR_WP_F1_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101110";
71 CONSTANT ADDR_LFR_WP_F1_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101111";
71 CONSTANT ADDR_LFR_WP_F1_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101111";
72
72
73 CONSTANT ADDR_LFR_WP_F2_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110000";
73 CONSTANT ADDR_LFR_WP_F2_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110000";
74 CONSTANT ADDR_LFR_WP_F2_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110001";
74 CONSTANT ADDR_LFR_WP_F2_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110001";
75 CONSTANT ADDR_LFR_WP_F2_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110010";
75 CONSTANT ADDR_LFR_WP_F2_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110010";
76 CONSTANT ADDR_LFR_WP_F2_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110011";
76 CONSTANT ADDR_LFR_WP_F2_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110011";
77
77
78 CONSTANT ADDR_LFR_WP_F3_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110100";
78 CONSTANT ADDR_LFR_WP_F3_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110100";
79 CONSTANT ADDR_LFR_WP_F3_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110101";
79 CONSTANT ADDR_LFR_WP_F3_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110101";
80 CONSTANT ADDR_LFR_WP_F3_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110110";
80 CONSTANT ADDR_LFR_WP_F3_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110110";
81 CONSTANT ADDR_LFR_WP_F3_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110111";
81 CONSTANT ADDR_LFR_WP_F3_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110111";
82
82
83 CONSTANT ADDR_LFR_WP_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111000";
83 CONSTANT ADDR_LFR_WP_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111000";
84
85 CONSTANT ADDR_LFR_WP_F3_V : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111001";
86 CONSTANT ADDR_LFR_WP_F3_E1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111010";
87 CONSTANT ADDR_LFR_WP_F3_E2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111011";
84 -----------------------------------------------------------------------------
88 -----------------------------------------------------------------------------
85 -- LFR
89 -- LFR
86 -----------------------------------------------------------------------------
90 -----------------------------------------------------------------------------
87 CONSTANT ADDR_LFR_VERSION : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111100";
91 CONSTANT ADDR_LFR_VERSION : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111100";
88
92
89
93
90 END lpp_lfr_apbreg_pkg;
94 END lpp_lfr_apbreg_pkg;
Show file before | Show file after | Hide comments
@@ -1,391 +1,395
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
16 -----------------------------------------------------------------------------
17 -- TEMP
17 -- TEMP
18 -----------------------------------------------------------------------------
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
20 GENERIC (
21 Mem_use : INTEGER);
21 Mem_use : INTEGER);
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
25
26 -- TIME
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38
38
39
39
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
43
44 --
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
51
52 -- IN
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
54
55 -----------------------------------------------------------------------------
55 -----------------------------------------------------------------------------
56
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
61
62 SM_correlation_start : OUT STD_LOGIC;
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
64 SM_correlation_done : IN STD_LOGIC
65 );
65 );
66 END COMPONENT;
66 END COMPONENT;
67
67
68
68
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70 COMPONENT lpp_lfr_ms
70 COMPONENT lpp_lfr_ms
71 GENERIC (
71 GENERIC (
72 Mem_use : INTEGER);
72 Mem_use : INTEGER);
73 PORT (
73 PORT (
74 clk : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 run : IN STD_LOGIC;
76 run : IN STD_LOGIC;
77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
80 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 dma_fifo_burst_valid : OUT STD_LOGIC;
86 dma_fifo_burst_valid : OUT STD_LOGIC;
87 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 dma_fifo_ren : IN STD_LOGIC;
88 dma_fifo_ren : IN STD_LOGIC;
89 dma_buffer_new : OUT STD_LOGIC;
89 dma_buffer_new : OUT STD_LOGIC;
90 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92 dma_buffer_full : IN STD_LOGIC;
92 dma_buffer_full : IN STD_LOGIC;
93 dma_buffer_full_err : IN STD_LOGIC;
93 dma_buffer_full_err : IN STD_LOGIC;
94 ready_matrix_f0 : OUT STD_LOGIC;
94 ready_matrix_f0 : OUT STD_LOGIC;
95 ready_matrix_f1 : OUT STD_LOGIC;
95 ready_matrix_f1 : OUT STD_LOGIC;
96 ready_matrix_f2 : OUT STD_LOGIC;
96 ready_matrix_f2 : OUT STD_LOGIC;
97 error_buffer_full : OUT STD_LOGIC;
97 error_buffer_full : OUT STD_LOGIC;
98 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
98 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
99 status_ready_matrix_f0 : IN STD_LOGIC;
99 status_ready_matrix_f0 : IN STD_LOGIC;
100 status_ready_matrix_f1 : IN STD_LOGIC;
100 status_ready_matrix_f1 : IN STD_LOGIC;
101 status_ready_matrix_f2 : IN STD_LOGIC;
101 status_ready_matrix_f2 : IN STD_LOGIC;
102 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
105 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
108 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
110 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
110 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
111 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
111 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
112 END COMPONENT;
112 END COMPONENT;
113
113
114 COMPONENT lpp_lfr_ms_fsmdma
114 COMPONENT lpp_lfr_ms_fsmdma
115 PORT (
115 PORT (
116 clk : IN STD_ULOGIC;
116 clk : IN STD_ULOGIC;
117 rstn : IN STD_ULOGIC;
117 rstn : IN STD_ULOGIC;
118 run : IN STD_LOGIC;
118 run : IN STD_LOGIC;
119 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
119 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
120 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
120 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
121 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
121 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
122 fifo_empty : IN STD_LOGIC;
122 fifo_empty : IN STD_LOGIC;
123 fifo_empty_threshold : IN STD_LOGIC;
123 fifo_empty_threshold : IN STD_LOGIC;
124 fifo_ren : OUT STD_LOGIC;
124 fifo_ren : OUT STD_LOGIC;
125 dma_fifo_valid_burst : OUT STD_LOGIC;
125 dma_fifo_valid_burst : OUT STD_LOGIC;
126 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 dma_fifo_ren : IN STD_LOGIC;
127 dma_fifo_ren : IN STD_LOGIC;
128 dma_buffer_new : OUT STD_LOGIC;
128 dma_buffer_new : OUT STD_LOGIC;
129 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
130 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
131 dma_buffer_full : IN STD_LOGIC;
131 dma_buffer_full : IN STD_LOGIC;
132 dma_buffer_full_err : IN STD_LOGIC;
132 dma_buffer_full_err : IN STD_LOGIC;
133 status_ready_matrix_f0 : IN STD_LOGIC;
133 status_ready_matrix_f0 : IN STD_LOGIC;
134 status_ready_matrix_f1 : IN STD_LOGIC;
134 status_ready_matrix_f1 : IN STD_LOGIC;
135 status_ready_matrix_f2 : IN STD_LOGIC;
135 status_ready_matrix_f2 : IN STD_LOGIC;
136 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
141 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
141 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
142 ready_matrix_f0 : OUT STD_LOGIC;
142 ready_matrix_f0 : OUT STD_LOGIC;
143 ready_matrix_f1 : OUT STD_LOGIC;
143 ready_matrix_f1 : OUT STD_LOGIC;
144 ready_matrix_f2 : OUT STD_LOGIC;
144 ready_matrix_f2 : OUT STD_LOGIC;
145 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
147 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
147 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
148 error_buffer_full : OUT STD_LOGIC);
148 error_buffer_full : OUT STD_LOGIC);
149 END COMPONENT;
149 END COMPONENT;
150
150
151 COMPONENT lpp_lfr_ms_FFT
151 COMPONENT lpp_lfr_ms_FFT
152 PORT (
152 PORT (
153 clk : IN STD_LOGIC;
153 clk : IN STD_LOGIC;
154 rstn : IN STD_LOGIC;
154 rstn : IN STD_LOGIC;
155 sample_valid : IN STD_LOGIC;
155 sample_valid : IN STD_LOGIC;
156 fft_read : IN STD_LOGIC;
156 fft_read : IN STD_LOGIC;
157 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
157 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
158 sample_load : OUT STD_LOGIC;
158 sample_load : OUT STD_LOGIC;
159 fft_pong : OUT STD_LOGIC;
159 fft_pong : OUT STD_LOGIC;
160 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
160 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
161 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
161 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
162 fft_data_valid : OUT STD_LOGIC;
162 fft_data_valid : OUT STD_LOGIC;
163 fft_ready : OUT STD_LOGIC);
163 fft_ready : OUT STD_LOGIC);
164 END COMPONENT;
164 END COMPONENT;
165
165
166 COMPONENT lpp_lfr_filter
166 COMPONENT lpp_lfr_filter
167 GENERIC (
167 GENERIC (
168 Mem_use : INTEGER);
168 Mem_use : INTEGER);
169 PORT (
169 PORT (
170 sample : IN Samples(7 DOWNTO 0);
170 sample : IN Samples(7 DOWNTO 0);
171 sample_val : IN STD_LOGIC;
171 sample_val : IN STD_LOGIC;
172 clk : IN STD_LOGIC;
172 clk : IN STD_LOGIC;
173 rstn : IN STD_LOGIC;
173 rstn : IN STD_LOGIC;
174 data_shaping_SP0 : IN STD_LOGIC;
174 data_shaping_SP0 : IN STD_LOGIC;
175 data_shaping_SP1 : IN STD_LOGIC;
175 data_shaping_SP1 : IN STD_LOGIC;
176 data_shaping_R0 : IN STD_LOGIC;
176 data_shaping_R0 : IN STD_LOGIC;
177 data_shaping_R1 : IN STD_LOGIC;
177 data_shaping_R1 : IN STD_LOGIC;
178 data_shaping_R2 : IN STD_LOGIC;
178 data_shaping_R2 : IN STD_LOGIC;
179 sample_f0_val : OUT STD_LOGIC;
179 sample_f0_val : OUT STD_LOGIC;
180 sample_f1_val : OUT STD_LOGIC;
180 sample_f1_val : OUT STD_LOGIC;
181 sample_f2_val : OUT STD_LOGIC;
181 sample_f2_val : OUT STD_LOGIC;
182 sample_f3_val : OUT STD_LOGIC;
182 sample_f3_val : OUT STD_LOGIC;
183 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
185 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
185 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
186 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
186 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
187 END COMPONENT;
187 END COMPONENT;
188
188
189 COMPONENT lpp_lfr
189 COMPONENT lpp_lfr
190 GENERIC (
190 GENERIC (
191 Mem_use : INTEGER;
191 Mem_use : INTEGER;
192 nb_data_by_buffer_size : INTEGER;
192 nb_data_by_buffer_size : INTEGER;
193 -- nb_word_by_buffer_size : INTEGER;
193 -- nb_word_by_buffer_size : INTEGER;
194 nb_snapshot_param_size : INTEGER;
194 nb_snapshot_param_size : INTEGER;
195 delta_vector_size : INTEGER;
195 delta_vector_size : INTEGER;
196 delta_vector_size_f0_2 : INTEGER;
196 delta_vector_size_f0_2 : INTEGER;
197 pindex : INTEGER;
197 pindex : INTEGER;
198 paddr : INTEGER;
198 paddr : INTEGER;
199 pmask : INTEGER;
199 pmask : INTEGER;
200 pirq_ms : INTEGER;
200 pirq_ms : INTEGER;
201 pirq_wfp : INTEGER;
201 pirq_wfp : INTEGER;
202 hindex : INTEGER;
202 hindex : INTEGER;
203 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
203 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
204 );
204 );
205 PORT (
205 PORT (
206 clk : IN STD_LOGIC;
206 clk : IN STD_LOGIC;
207 rstn : IN STD_LOGIC;
207 rstn : IN STD_LOGIC;
208 sample_B : IN Samples(2 DOWNTO 0);
208 sample_B : IN Samples(2 DOWNTO 0);
209 sample_E : IN Samples(4 DOWNTO 0);
209 sample_E : IN Samples(4 DOWNTO 0);
210 sample_val : IN STD_LOGIC;
210 sample_val : IN STD_LOGIC;
211 apbi : IN apb_slv_in_type;
211 apbi : IN apb_slv_in_type;
212 apbo : OUT apb_slv_out_type;
212 apbo : OUT apb_slv_out_type;
213 ahbi : IN AHB_Mst_In_Type;
213 ahbi : IN AHB_Mst_In_Type;
214 ahbo : OUT AHB_Mst_Out_Type;
214 ahbo : OUT AHB_Mst_Out_Type;
215 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
216 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
217 data_shaping_BW : OUT STD_LOGIC ;
217 data_shaping_BW : OUT STD_LOGIC ;
218 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
218 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
219 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
219 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
220 );
220 );
221 END COMPONENT;
221 END COMPONENT;
222
222
223 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
224 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
224 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
225 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
226 COMPONENT lpp_lfr_WFP_nMS
226 COMPONENT lpp_lfr_WFP_nMS
227 GENERIC (
227 GENERIC (
228 Mem_use : INTEGER;
228 Mem_use : INTEGER;
229 nb_data_by_buffer_size : INTEGER;
229 nb_data_by_buffer_size : INTEGER;
230 nb_word_by_buffer_size : INTEGER;
230 nb_word_by_buffer_size : INTEGER;
231 nb_snapshot_param_size : INTEGER;
231 nb_snapshot_param_size : INTEGER;
232 delta_vector_size : INTEGER;
232 delta_vector_size : INTEGER;
233 delta_vector_size_f0_2 : INTEGER;
233 delta_vector_size_f0_2 : INTEGER;
234 pindex : INTEGER;
234 pindex : INTEGER;
235 paddr : INTEGER;
235 paddr : INTEGER;
236 pmask : INTEGER;
236 pmask : INTEGER;
237 pirq_ms : INTEGER;
237 pirq_ms : INTEGER;
238 pirq_wfp : INTEGER;
238 pirq_wfp : INTEGER;
239 hindex : INTEGER;
239 hindex : INTEGER;
240 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
240 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
241 PORT (
241 PORT (
242 clk : IN STD_LOGIC;
242 clk : IN STD_LOGIC;
243 rstn : IN STD_LOGIC;
243 rstn : IN STD_LOGIC;
244 sample_B : IN Samples(2 DOWNTO 0);
244 sample_B : IN Samples(2 DOWNTO 0);
245 sample_E : IN Samples(4 DOWNTO 0);
245 sample_E : IN Samples(4 DOWNTO 0);
246 sample_val : IN STD_LOGIC;
246 sample_val : IN STD_LOGIC;
247 apbi : IN apb_slv_in_type;
247 apbi : IN apb_slv_in_type;
248 apbo : OUT apb_slv_out_type;
248 apbo : OUT apb_slv_out_type;
249 ahbi : IN AHB_Mst_In_Type;
249 ahbi : IN AHB_Mst_In_Type;
250 ahbo : OUT AHB_Mst_Out_Type;
250 ahbo : OUT AHB_Mst_Out_Type;
251 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
251 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
252 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
252 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
253 data_shaping_BW : OUT STD_LOGIC;
253 data_shaping_BW : OUT STD_LOGIC;
254 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
254 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
255 END COMPONENT;
255 END COMPONENT;
256 -----------------------------------------------------------------------------
256 -----------------------------------------------------------------------------
257
257
258 COMPONENT lpp_lfr_apbreg
258 COMPONENT lpp_lfr_apbreg
259 GENERIC (
259 GENERIC (
260 nb_data_by_buffer_size : INTEGER;
260 nb_data_by_buffer_size : INTEGER;
261 nb_snapshot_param_size : INTEGER;
261 nb_snapshot_param_size : INTEGER;
262 delta_vector_size : INTEGER;
262 delta_vector_size : INTEGER;
263 delta_vector_size_f0_2 : INTEGER;
263 delta_vector_size_f0_2 : INTEGER;
264 pindex : INTEGER;
264 pindex : INTEGER;
265 paddr : INTEGER;
265 paddr : INTEGER;
266 pmask : INTEGER;
266 pmask : INTEGER;
267 pirq_ms : INTEGER;
267 pirq_ms : INTEGER;
268 pirq_wfp : INTEGER;
268 pirq_wfp : INTEGER;
269 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
269 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
270 PORT (
270 PORT (
271 HCLK : IN STD_ULOGIC;
271 HCLK : IN STD_ULOGIC;
272 HRESETn : IN STD_ULOGIC;
272 HRESETn : IN STD_ULOGIC;
273 apbi : IN apb_slv_in_type;
273 apbi : IN apb_slv_in_type;
274 apbo : OUT apb_slv_out_type;
274 apbo : OUT apb_slv_out_type;
275 run_ms : OUT STD_LOGIC;
275 run_ms : OUT STD_LOGIC;
276 ready_matrix_f0 : IN STD_LOGIC;
276 ready_matrix_f0 : IN STD_LOGIC;
277 ready_matrix_f1 : IN STD_LOGIC;
277 ready_matrix_f1 : IN STD_LOGIC;
278 ready_matrix_f2 : IN STD_LOGIC;
278 ready_matrix_f2 : IN STD_LOGIC;
279 error_buffer_full : IN STD_LOGIC;
279 error_buffer_full : IN STD_LOGIC;
280 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
280 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
281 status_ready_matrix_f0 : OUT STD_LOGIC;
281 status_ready_matrix_f0 : OUT STD_LOGIC;
282 status_ready_matrix_f1 : OUT STD_LOGIC;
282 status_ready_matrix_f1 : OUT STD_LOGIC;
283 status_ready_matrix_f2 : OUT STD_LOGIC;
283 status_ready_matrix_f2 : OUT STD_LOGIC;
284 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
287 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
287 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
288 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
288 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
289 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
289 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
290 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
290 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
291 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
291 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
292 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
292 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
293 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
293 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
294 data_shaping_BW : OUT STD_LOGIC;
294 data_shaping_BW : OUT STD_LOGIC;
295 data_shaping_SP0 : OUT STD_LOGIC;
295 data_shaping_SP0 : OUT STD_LOGIC;
296 data_shaping_SP1 : OUT STD_LOGIC;
296 data_shaping_SP1 : OUT STD_LOGIC;
297 data_shaping_R0 : OUT STD_LOGIC;
297 data_shaping_R0 : OUT STD_LOGIC;
298 data_shaping_R1 : OUT STD_LOGIC;
298 data_shaping_R1 : OUT STD_LOGIC;
299 data_shaping_R2 : OUT STD_LOGIC;
299 data_shaping_R2 : OUT STD_LOGIC;
300 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
300 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
301 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
301 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
302 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
302 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
303 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
303 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
304 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
304 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
305 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
305 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
306 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
306 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
307 enable_f0 : OUT STD_LOGIC;
307 enable_f0 : OUT STD_LOGIC;
308 enable_f1 : OUT STD_LOGIC;
308 enable_f1 : OUT STD_LOGIC;
309 enable_f2 : OUT STD_LOGIC;
309 enable_f2 : OUT STD_LOGIC;
310 enable_f3 : OUT STD_LOGIC;
310 enable_f3 : OUT STD_LOGIC;
311 burst_f0 : OUT STD_LOGIC;
311 burst_f0 : OUT STD_LOGIC;
312 burst_f1 : OUT STD_LOGIC;
312 burst_f1 : OUT STD_LOGIC;
313 burst_f2 : OUT STD_LOGIC;
313 burst_f2 : OUT STD_LOGIC;
314 run : OUT STD_LOGIC;
314 run : OUT STD_LOGIC;
315 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
315 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
316 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
316 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
317 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
317 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
318 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
318 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
319 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
319 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
320 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
320 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
321 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
321 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
322 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
323 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
324 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
325 sample_f3_valid : IN STD_LOGIC;
322 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
326 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
323 END COMPONENT;
327 END COMPONENT;
324
328
325 COMPONENT lpp_top_ms
329 COMPONENT lpp_top_ms
326 GENERIC (
330 GENERIC (
327 Mem_use : INTEGER;
331 Mem_use : INTEGER;
328 nb_burst_available_size : INTEGER;
332 nb_burst_available_size : INTEGER;
329 nb_snapshot_param_size : INTEGER;
333 nb_snapshot_param_size : INTEGER;
330 delta_snapshot_size : INTEGER;
334 delta_snapshot_size : INTEGER;
331 delta_f2_f0_size : INTEGER;
335 delta_f2_f0_size : INTEGER;
332 delta_f2_f1_size : INTEGER;
336 delta_f2_f1_size : INTEGER;
333 pindex : INTEGER;
337 pindex : INTEGER;
334 paddr : INTEGER;
338 paddr : INTEGER;
335 pmask : INTEGER;
339 pmask : INTEGER;
336 pirq_ms : INTEGER;
340 pirq_ms : INTEGER;
337 pirq_wfp : INTEGER;
341 pirq_wfp : INTEGER;
338 hindex_wfp : INTEGER;
342 hindex_wfp : INTEGER;
339 hindex_ms : INTEGER);
343 hindex_ms : INTEGER);
340 PORT (
344 PORT (
341 clk : IN STD_LOGIC;
345 clk : IN STD_LOGIC;
342 rstn : IN STD_LOGIC;
346 rstn : IN STD_LOGIC;
343 sample_B : IN Samples14v(2 DOWNTO 0);
347 sample_B : IN Samples14v(2 DOWNTO 0);
344 sample_E : IN Samples14v(4 DOWNTO 0);
348 sample_E : IN Samples14v(4 DOWNTO 0);
345 sample_val : IN STD_LOGIC;
349 sample_val : IN STD_LOGIC;
346 apbi : IN apb_slv_in_type;
350 apbi : IN apb_slv_in_type;
347 apbo : OUT apb_slv_out_type;
351 apbo : OUT apb_slv_out_type;
348 ahbi_ms : IN AHB_Mst_In_Type;
352 ahbi_ms : IN AHB_Mst_In_Type;
349 ahbo_ms : OUT AHB_Mst_Out_Type;
353 ahbo_ms : OUT AHB_Mst_Out_Type;
350 data_shaping_BW : OUT STD_LOGIC;
354 data_shaping_BW : OUT STD_LOGIC;
351 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
355 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
352 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
356 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
353 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
357 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
354 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
358 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
355 );
359 );
356 END COMPONENT;
360 END COMPONENT;
357
361
358 COMPONENT lpp_apbreg_ms_pointer
362 COMPONENT lpp_apbreg_ms_pointer
359 PORT (
363 PORT (
360 clk : IN STD_LOGIC;
364 clk : IN STD_LOGIC;
361 rstn : IN STD_LOGIC;
365 rstn : IN STD_LOGIC;
362 run : IN STD_LOGIC;
366 run : IN STD_LOGIC;
363 reg0_status_ready_matrix : IN STD_LOGIC;
367 reg0_status_ready_matrix : IN STD_LOGIC;
364 reg0_ready_matrix : OUT STD_LOGIC;
368 reg0_ready_matrix : OUT STD_LOGIC;
365 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
369 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
366 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
370 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
367 reg1_status_ready_matrix : IN STD_LOGIC;
371 reg1_status_ready_matrix : IN STD_LOGIC;
368 reg1_ready_matrix : OUT STD_LOGIC;
372 reg1_ready_matrix : OUT STD_LOGIC;
369 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
373 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
370 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
374 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
371 ready_matrix : IN STD_LOGIC;
375 ready_matrix : IN STD_LOGIC;
372 status_ready_matrix : OUT STD_LOGIC;
376 status_ready_matrix : OUT STD_LOGIC;
373 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
377 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
374 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
378 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
375 END COMPONENT;
379 END COMPONENT;
376
380
377 COMPONENT lpp_lfr_ms_reg_head
381 COMPONENT lpp_lfr_ms_reg_head
378 PORT (
382 PORT (
379 clk : IN STD_LOGIC;
383 clk : IN STD_LOGIC;
380 rstn : IN STD_LOGIC;
384 rstn : IN STD_LOGIC;
381 in_wen : IN STD_LOGIC;
385 in_wen : IN STD_LOGIC;
382 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
386 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
383 in_full : IN STD_LOGIC;
387 in_full : IN STD_LOGIC;
384 in_empty : IN STD_LOGIC;
388 in_empty : IN STD_LOGIC;
385 out_write_error : OUT STD_LOGIC;
389 out_write_error : OUT STD_LOGIC;
386 out_wen : OUT STD_LOGIC;
390 out_wen : OUT STD_LOGIC;
387 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
391 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
388 out_full : OUT STD_LOGIC);
392 out_full : OUT STD_LOGIC);
389 END COMPONENT;
393 END COMPONENT;
390
394
391 END lpp_lfr_pkg;
395 END lpp_lfr_pkg;
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