# HG changeset patch # User pellion # Date 2015-01-07 12:35:51 # Node ID e1a66be1bcbe3ea2868d9f0422689b305113f5d6 # Parent 90fb35b1613e66dc54b840424b20f9195c180f25 ajout de 3 registres apb_lfr pour donner un acces direct aux données V,E1,E2 du channel a f3 diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -505,7 +505,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000124") -- aa.bb.cc version + top_lfr_version => X"000125") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -342,6 +342,11 @@ BEGIN wfp_ready_buffer => wfp_ready_buffer,-- TODO wfp_buffer_time => wfp_buffer_time,-- TODO wfp_error_buffer_full => wfp_error_buffer_full, -- TODO + ------------------------------------------------------------------------- + sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16), + sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16), + sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16), + sample_f3_valid => sample_f3_val, debug_vector => apb_reg_debug_vector ); diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -139,6 +139,11 @@ ENTITY lpp_lfr_apbreg IS wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --------------------------------------------------------------------------- + sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_valid : IN STD_LOGIC; + --------------------------------------------------------------------------- debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); @@ -269,6 +274,10 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + BEGIN -- beh debug_vector(0) <= error_buffer_full; @@ -330,6 +339,23 @@ BEGIN -- beh length_matrix_f1 <= reg_sp.length_matrix; length_matrix_f2 <= reg_sp.length_matrix; wfp_length_buffer <= reg_wp.length_buffer; + + + + PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS + IF HRESETn = '0' THEN -- asynchronous reset (active low) + sample_f3_v_reg <= (OTHERS => '0'); + sample_f3_e1_reg <= (OTHERS => '0'); + sample_f3_e2_reg <= (OTHERS => '0'); + ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge + IF sample_f3_valid = '1' THEN + sample_f3_v_reg <= sample_f3_v; + sample_f3_e1_reg <= sample_f3_e1; + sample_f3_e2_reg <= sample_f3_e2; + END IF; + END IF; + END PROCESS; lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) @@ -542,7 +568,14 @@ BEGIN -- beh WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7); WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32); - WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; + WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; + + WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg; + prdata(31 DOWNTO 16) <= (OTHERS => '0'); + WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg; + prdata(31 DOWNTO 16) <= (OTHERS => '0'); + WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg; + prdata(31 DOWNTO 16) <= (OTHERS => '0'); --------------------------------------------------------------------- WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); WHEN OTHERS => NULL; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd @@ -80,7 +80,11 @@ PACKAGE lpp_lfr_apbreg_pkg IS CONSTANT ADDR_LFR_WP_F3_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110110"; CONSTANT ADDR_LFR_WP_F3_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110111"; - CONSTANT ADDR_LFR_WP_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111000"; + CONSTANT ADDR_LFR_WP_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111000"; + + CONSTANT ADDR_LFR_WP_F3_V : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111001"; + CONSTANT ADDR_LFR_WP_F3_E1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111010"; + CONSTANT ADDR_LFR_WP_F3_E2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111011"; ----------------------------------------------------------------------------- -- LFR ----------------------------------------------------------------------------- diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -319,6 +319,10 @@ PACKAGE lpp_lfr_pkg IS wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_valid : IN STD_LOGIC; debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); END COMPONENT;