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ajout de 3 registres apb_lfr pour donner un acces direct aux données V,E1,E2 du channel a f3
pellion -
r474:e1a66be1bcbe (MINI-LFR) WFP_MS-0-1-37 JC
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@@ -505,7 +505,7 BEGIN -- beh
505 pirq_ms => 6,
505 pirq_ms => 6,
506 pirq_wfp => 14,
506 pirq_wfp => 14,
507 hindex => 2,
507 hindex => 2,
508 top_lfr_version => X"000124") -- aa.bb.cc version
508 top_lfr_version => X"000125") -- aa.bb.cc version
509 PORT MAP (
509 PORT MAP (
510 clk => clk_25,
510 clk => clk_25,
511 rstn => LFR_rstn,
511 rstn => LFR_rstn,
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@@ -342,6 +342,11 BEGIN
342 wfp_ready_buffer => wfp_ready_buffer,-- TODO
342 wfp_ready_buffer => wfp_ready_buffer,-- TODO
343 wfp_buffer_time => wfp_buffer_time,-- TODO
343 wfp_buffer_time => wfp_buffer_time,-- TODO
344 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
344 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
345 -------------------------------------------------------------------------
346 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
347 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
348 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
349 sample_f3_valid => sample_f3_val,
345 debug_vector => apb_reg_debug_vector
350 debug_vector => apb_reg_debug_vector
346 );
351 );
347
352
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@@ -139,6 +139,11 ENTITY lpp_lfr_apbreg IS
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
141 ---------------------------------------------------------------------------
141 ---------------------------------------------------------------------------
142 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
143 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
144 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
145 sample_f3_valid : IN STD_LOGIC;
146 ---------------------------------------------------------------------------
142 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
147 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
143
148
144 );
149 );
@@ -269,6 +274,10 ARCHITECTURE beh OF lpp_lfr_apbreg IS
269
274
270 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
271
276
277 SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
278 SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
279 SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
280
272 BEGIN -- beh
281 BEGIN -- beh
273
282
274 debug_vector(0) <= error_buffer_full;
283 debug_vector(0) <= error_buffer_full;
@@ -330,6 +339,23 BEGIN -- beh
330 length_matrix_f1 <= reg_sp.length_matrix;
339 length_matrix_f1 <= reg_sp.length_matrix;
331 length_matrix_f2 <= reg_sp.length_matrix;
340 length_matrix_f2 <= reg_sp.length_matrix;
332 wfp_length_buffer <= reg_wp.length_buffer;
341 wfp_length_buffer <= reg_wp.length_buffer;
342
343
344
345 PROCESS (HCLK, HRESETn)
346 BEGIN -- PROCESS
347 IF HRESETn = '0' THEN -- asynchronous reset (active low)
348 sample_f3_v_reg <= (OTHERS => '0');
349 sample_f3_e1_reg <= (OTHERS => '0');
350 sample_f3_e2_reg <= (OTHERS => '0');
351 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
352 IF sample_f3_valid = '1' THEN
353 sample_f3_v_reg <= sample_f3_v;
354 sample_f3_e1_reg <= sample_f3_e1;
355 sample_f3_e2_reg <= sample_f3_e2;
356 END IF;
357 END IF;
358 END PROCESS;
333
359
334
360
335 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
361 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
@@ -542,7 +568,14 BEGIN -- beh
542 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
568 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
543 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
569 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
544
570
545 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
571 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
572
573 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
574 prdata(31 DOWNTO 16) <= (OTHERS => '0');
575 WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg;
576 prdata(31 DOWNTO 16) <= (OTHERS => '0');
577 WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg;
578 prdata(31 DOWNTO 16) <= (OTHERS => '0');
546 ---------------------------------------------------------------------
579 ---------------------------------------------------------------------
547 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
580 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
548 WHEN OTHERS => NULL;
581 WHEN OTHERS => NULL;
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@@ -80,7 +80,11 PACKAGE lpp_lfr_apbreg_pkg IS
80 CONSTANT ADDR_LFR_WP_F3_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110110";
80 CONSTANT ADDR_LFR_WP_F3_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110110";
81 CONSTANT ADDR_LFR_WP_F3_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110111";
81 CONSTANT ADDR_LFR_WP_F3_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110111";
82
82
83 CONSTANT ADDR_LFR_WP_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111000";
83 CONSTANT ADDR_LFR_WP_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111000";
84
85 CONSTANT ADDR_LFR_WP_F3_V : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111001";
86 CONSTANT ADDR_LFR_WP_F3_E1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111010";
87 CONSTANT ADDR_LFR_WP_F3_E2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111011";
84 -----------------------------------------------------------------------------
88 -----------------------------------------------------------------------------
85 -- LFR
89 -- LFR
86 -----------------------------------------------------------------------------
90 -----------------------------------------------------------------------------
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@@ -319,6 +319,10 PACKAGE lpp_lfr_pkg IS
319 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
319 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
320 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
320 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
321 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
321 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
322 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
323 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
324 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
325 sample_f3_valid : IN STD_LOGIC;
322 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
326 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
323 END COMPONENT;
327 END COMPONENT;
324
328
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