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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 USE techmap.axcomp.ALL;
31
32 LIBRARY gaisler;
33 USE gaisler.sim.ALL;
34 USE gaisler.memctrl.ALL;
35 USE gaisler.leon3.ALL;
36 USE gaisler.uart.ALL;
37 USE gaisler.misc.ALL;
38 USE gaisler.spacewire.ALL;
39 LIBRARY esa;
40 USE esa.memoryctrl.ALL;
41 LIBRARY lpp;
42 USE lpp.lpp_memory.ALL;
43 USE lpp.lpp_ad_conv.ALL;
44 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
45 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
46 USE lpp.iir_filter.ALL;
47 USE lpp.general_purpose.ALL;
48 USE lpp.lpp_lfr_management.ALL;
49 USE lpp.lpp_leon3_soc_pkg.ALL;
50
51 --library proasic3l;
52 --use proasic3l.all;
53
54 ENTITY LFR_EQM IS
55 GENERIC (
56 Mem_use : INTEGER := use_RAM;
57 USE_BOOTLOADER : INTEGER := 0;
58 USE_ADCDRIVER : INTEGER := 1;
59 tech : INTEGER := inferred;
60 tech_leon : INTEGER := inferred;
61 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
62 USE_DEBUG_VECTOR : INTEGER := 0
63 );
64
65 PORT (
66 clk50MHz : IN STD_ULOGIC;
67 clk49_152MHz : IN STD_ULOGIC;
68 reset : IN STD_ULOGIC;
69
70 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
71
72 -- TAG --------------------------------------------------------------------
73 --TAG1 : IN STD_ULOGIC; -- DSU rx data
74 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
75 -- UART APB ---------------------------------------------------------------
76 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
77 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
78 -- RAM --------------------------------------------------------------------
79 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
80 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81
82 nSRAM_MBE : INOUT STD_LOGIC; -- new
83 nSRAM_E1 : OUT STD_LOGIC; -- new
84 nSRAM_E2 : OUT STD_LOGIC; -- new
85 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
86 nSRAM_W : OUT STD_LOGIC; -- new
87 nSRAM_G : OUT STD_LOGIC; -- new
88 nSRAM_BUSY : IN STD_LOGIC; -- new
89 -- SPW --------------------------------------------------------------------
90 spw1_en : OUT STD_LOGIC; -- new
91 spw1_din : IN STD_LOGIC;
92 spw1_sin : IN STD_LOGIC;
93 spw1_dout : OUT STD_LOGIC;
94 spw1_sout : OUT STD_LOGIC;
95 spw2_en : OUT STD_LOGIC; -- new
96 spw2_din : IN STD_LOGIC;
97 spw2_sin : IN STD_LOGIC;
98 spw2_dout : OUT STD_LOGIC;
99 spw2_sout : OUT STD_LOGIC;
100 -- ADC --------------------------------------------------------------------
101 bias_fail_sw : OUT STD_LOGIC;
102 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
103 ADC_smpclk : OUT STD_LOGIC;
104 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
105 -- DAC --------------------------------------------------------------------
106 DAC_SDO : OUT STD_LOGIC;
107 DAC_SCK : OUT STD_LOGIC;
108 DAC_SYNC : OUT STD_LOGIC;
109 DAC_CAL_EN : OUT STD_LOGIC;
110 -- HK ---------------------------------------------------------------------
111 HK_smpclk : OUT STD_LOGIC;
112 ADC_OEB_bar_HK : OUT STD_LOGIC;
113 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
114 );
115
116 END LFR_EQM;
117
118
119 ARCHITECTURE beh OF LFR_EQM IS
120
121 SIGNAL clk_25_int : STD_LOGIC := '0';
122 SIGNAL clk_25 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
124 -----------------------------------------------------------------------------
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127
128 -- CONSTANTS
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133
134 SIGNAL apbi_ext : apb_slv_in_type;
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140
141 -- Spacewire signals
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 SIGNAL swni : grspw_in_type;
146 SIGNAL swno : grspw_out_type;
147
148 --GPIO
149 SIGNAL gpioi : gpio_in_type;
150 SIGNAL gpioo : gpio_out_type;
151
152 -- AD Converter ADS7886
153 SIGNAL sample : Samples14v(8 DOWNTO 0);
154 SIGNAL sample_s : Samples(8 DOWNTO 0);
155 SIGNAL sample_val : STD_LOGIC;
156 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
157
158 -----------------------------------------------------------------------------
159 SIGNAL LFR_rstn_int : STD_LOGIC := '0';
160 SIGNAL rstn_25_int : STD_LOGIC := '0';
161 SIGNAL rstn_25 : STD_LOGIC;
162 SIGNAL rstn_24 : STD_LOGIC;
163
164 SIGNAL LFR_soft_rstn : STD_LOGIC;
165 SIGNAL LFR_rstn : STD_LOGIC;
166
167 SIGNAL ADC_smpclk_s : STD_LOGIC;
168
169 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
171 SIGNAL clk50MHz_int : STD_LOGIC := '0';
172
173 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
174
175 SIGNAL rstn_50 : STD_LOGIC;
176 SIGNAL clk_lock : STD_LOGIC;
177 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
179
180 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
181 SIGNAL ahbrxd: STD_LOGIC;
182 SIGNAL ahbtxd: STD_LOGIC;
183 SIGNAL urxd1 : STD_LOGIC;
184 SIGNAL utxd1 : STD_LOGIC;
185 BEGIN -- beh
186
187 -----------------------------------------------------------------------------
188 -- CLK_LOCK
189 -----------------------------------------------------------------------------
190 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
191
192 PROCESS (clk50MHz_int, rstn_50)
193 BEGIN -- PROCESS
194 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
195 clk_lock <= '0';
196 clk_busy_counter <= (OTHERS => '0');
197 nSRAM_BUSY_reg <= '0';
198 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
199 nSRAM_BUSY_reg <= nSRAM_BUSY;
200 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
201 IF clk_busy_counter = "1111" THEN
202 clk_lock <= '1';
203 ELSE
204 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
205 END IF;
206 END IF;
207 END IF;
208 END PROCESS;
209
210 -----------------------------------------------------------------------------
211 -- CLK
212 -----------------------------------------------------------------------------
213 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25_int, OPEN);
214 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
215
216 rstn_pad_25 : clkint port map (A => rstn_25_int, Y => rstn_25 );
217
218 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
219 clk50MHz_int <= clk50MHz;
220
221 PROCESS(clk50MHz_int)
222 BEGIN
223 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
224 clk_25_int <= NOT clk_25_int;
225 --clk_25 <= NOT clk_25;
226 END IF;
227 END PROCESS;
228 clk_pad_25 : hclkint port map (A => clk_25_int, Y => clk_25 );
229
230 PROCESS(clk49_152MHz)
231 BEGIN
232 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
233 clk_24 <= NOT clk_24;
234 END IF;
235 END PROCESS;
236 -- clk_49 <= clk49_152MHz;
237
238 -----------------------------------------------------------------------------
239 leon3_soc_1 : leon3_soc
240 GENERIC MAP (
241 fabtech => axcel,--inferred,--axdsp,
242 memtech => axcel,--inferred,--tech_leon,
243 padtech => axcel,--inferred,
244 clktech => axcel,--inferred,
245 disas => 0,
246 dbguart => 0,
247 pclow => 2,
248 clk_freq => 25000,
249 IS_RADHARD => 1,
250 NB_CPU => 1,
251 ENABLE_FPU => 1,
252 FPU_NETLIST => 0,
253 ENABLE_DSU => 1,
254 ENABLE_AHB_UART => 0,
255 ENABLE_APB_UART => 1,
256 ENABLE_IRQMP => 1,
257 ENABLE_GPT => 1,
258 NB_AHB_MASTER => NB_AHB_MASTER,
259 NB_AHB_SLAVE => NB_AHB_SLAVE,
260 NB_APB_SLAVE => NB_APB_SLAVE,
261 ADDRESS_SIZE => 19,
262 USES_IAP_MEMCTRLR => 1,
263 BYPASS_EDAC_MEMCTRLR => '0',
264 SRBANKSZ => 8)
265 PORT MAP (
266 clk => clk_25,
267 reset => rstn_25,
268 errorn => OPEN,
269
270 ahbrxd => ahbrxd, -- INPUT
271 ahbtxd => ahbtxd, -- OUTPUT
272 urxd1 => urxd1, -- INPUT
273 utxd1 => utxd1, -- OUTPUT
274
275 address => address,
276 data => data,
277 nSRAM_BE0 => OPEN,
278 nSRAM_BE1 => OPEN,
279 nSRAM_BE2 => OPEN,
280 nSRAM_BE3 => OPEN,
281 nSRAM_WE => nSRAM_W,
282 nSRAM_CE => nSRAM_CE,
283 nSRAM_OE => nSRAM_G,
284 nSRAM_READY => nSRAM_BUSY,
285 SRAM_MBE => nSRAM_MBE,
286
287 apbi_ext => apbi_ext,
288 apbo_ext => apbo_ext,
289 ahbi_s_ext => ahbi_s_ext,
290 ahbo_s_ext => ahbo_s_ext,
291 ahbi_m_ext => ahbi_m_ext,
292 ahbo_m_ext => ahbo_m_ext);
293
294
295 nSRAM_E1 <= nSRAM_CE(0);
296 nSRAM_E2 <= nSRAM_CE(1);
297
298 -------------------------------------------------------------------------------
299 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
300 -------------------------------------------------------------------------------
301 apb_lfr_management_1 : apb_lfr_management
302 GENERIC MAP (
303 tech => tech,
304 pindex => 6,
305 paddr => 6,
306 pmask => 16#fff#,
307 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
308 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
309 PORT MAP (
310 clk25MHz => clk_25,
311 resetn_25MHz => rstn_25, -- TODO
312 --clk24_576MHz => clk_24, -- 49.152MHz/2
313 --resetn_24_576MHz => rstn_24, -- TODO
314
315 grspw_tick => swno.tickout,
316 apbi => apbi_ext,
317 apbo => apbo_ext(6),
318
319 HK_sample => sample_s(8),
320 HK_val => sample_val,
321 HK_sel => HK_SEL,
322
323 DAC_SDO => DAC_SDO,
324 DAC_SCK => DAC_SCK,
325 DAC_SYNC => DAC_SYNC,
326 DAC_CAL_EN => DAC_CAL_EN,
327
328 coarse_time => coarse_time,
329 fine_time => fine_time,
330 LFR_soft_rstn => LFR_soft_rstn
331 );
332
333 -----------------------------------------------------------------------
334 --- SpaceWire --------------------------------------------------------
335 -----------------------------------------------------------------------
336
337 ------------------------------------------------------------------------------
338 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
339 ------------------------------------------------------------------------------
340 spw1_en <= '1';
341 spw2_en <= '1';
342 ------------------------------------------------------------------------------
343 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
344 ------------------------------------------------------------------------------
345
346 --spw_clk <= clk50MHz;
347 --spw_rxtxclk <= spw_clk;
348 --spw_rxclkn <= NOT spw_rxtxclk;
349
350 -- PADS for SPW1
351 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
352 PORT MAP (spw1_din, dtmp(0));
353 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
354 PORT MAP (spw1_sin, stmp(0));
355 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
356 PORT MAP (spw1_dout, swno.d(0));
357 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
358 PORT MAP (spw1_sout, swno.s(0));
359 -- PADS FOR SPW2
360 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
361 PORT MAP (spw2_din, dtmp(1));
362 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
363 PORT MAP (spw2_sin, stmp(1));
364 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
365 PORT MAP (spw2_dout, swno.d(1));
366 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
367 PORT MAP (spw2_sout, swno.s(1));
368
369 -- GRSPW PHY
370 --spw1_input: if CFG_SPW_GRSPW = 1 generate
371 spw_inputloop : FOR j IN 0 TO 1 GENERATE
372 spw_phy0 : grspw_phy
373 GENERIC MAP(
374 tech => axcel,-- inferred,--axdsp,--tech_leon,
375 rxclkbuftype => 1,
376 scantest => 0)
377 PORT MAP(
378 rxrst => swno.rxrst,
379 di => dtmp(j),
380 si => stmp(j),
381 rxclko => spw_rxclk(j),
382 do => swni.d(j),
383 ndo => swni.nd(j*5+4 DOWNTO j*5),
384 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
385 END GENERATE spw_inputloop;
386
387 -- SPW core
388 sw0 : grspwm GENERIC MAP(
389 tech => axcel,--inferred,--axdsp,--tech_leon,
390 hindex => 1,
391 pindex => 5,
392 paddr => 5,
393 pirq => 11,
394 sysfreq => 25000, -- CPU_FREQ
395 rmap => 1,
396 rmapcrc => 1,
397 fifosize1 => 16,
398 fifosize2 => 16,
399 rxclkbuftype => 1,
400 rxunaligned => 0,
401 rmapbufs => 4,
402 ft => 1,
403 netlist => 0,
404 ports => 2,
405 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
406 memtech => axcel,--inferred,--tech_leon,
407 destkey => 2,
408 spwcore => 1
409 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
410 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
411 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
412 )
413 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
414 spw_rxclk(1),
415 clk50MHz_int,
416 clk50MHz_int,
417 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
418 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
419 swni, swno);
420
421 swni.tickin <= '0';
422 swni.rmapen <= '1';
423 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
424 swni.tickinraw <= '0';
425 swni.timein <= (OTHERS => '0');
426 swni.dcrstval <= (OTHERS => '0');
427 swni.timerrstval <= (OTHERS => '0');
428
429 -------------------------------------------------------------------------------
430 -- LFR ------------------------------------------------------------------------
431 -------------------------------------------------------------------------------
432 --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN);
433 LFR_rstn_int <= LFR_soft_rstn AND rstn_25_int;
434
435 rstn_pad_lfr : clkint port map (A => LFR_rstn_int, Y => LFR_rstn );
436
437 lpp_lfr_1 : lpp_lfr
438 GENERIC MAP (
439 Mem_use => Mem_use,
440 tech => inferred,--tech,
441 nb_data_by_buffer_size => 32,
442 --nb_word_by_buffer_size => 30,
443 nb_snapshot_param_size => 32,
444 delta_vector_size => 32,
445 delta_vector_size_f0_2 => 7, -- log2(96)
446 pindex => 15,
447 paddr => 15,
448 pmask => 16#fff#,
449 pirq_ms => 6,
450 pirq_wfp => 14,
451 hindex => 2,
452 top_lfr_version => X"020159", -- aa.bb.cc version
453 -- AA : BOARD NUMBER
454 -- 0 => MINI_LFR
455 -- 1 => EM
456 -- 2 => EQM (with A3PE3000)
457 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA,
458 RTL_DESIGN_LIGHT =>0,
459 WINDOWS_HAANNING_PARAM_SIZE => 15)
460 PORT MAP (
461 clk => clk_25,
462 rstn => LFR_rstn,
463 sample_B => sample_s(2 DOWNTO 0),
464 sample_E => sample_s(7 DOWNTO 3),
465 sample_val => sample_val,
466 apbi => apbi_ext,
467 apbo => apbo_ext(15),
468 ahbi => ahbi_m_ext,
469 ahbo => ahbo_m_ext(2),
470 coarse_time => coarse_time,
471 fine_time => fine_time,
472 data_shaping_BW => bias_fail_sw,
473 debug_vector => debug_vector,
474 debug_vector_ms => OPEN); --,
475 --observation_vector_0 => OPEN,
476 --observation_vector_1 => OPEN,
477 --observation_reg => observation_reg);
478
479
480 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
481 sample_s(I) <= sample(I) & '0' & '0';
482 END GENERATE all_sample;
483 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
484
485 -----------------------------------------------------------------------------
486 --
487 -----------------------------------------------------------------------------
488 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
489 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
490 GENERIC MAP (
491 ChanelCount => 9,
492 ncycle_cnv_high => 12,
493 ncycle_cnv => 25,
494 FILTER_ENABLED => 16#FF#)
495 PORT MAP (
496 cnv_clk => clk_24,
497 cnv_rstn => rstn_24,
498 cnv => ADC_smpclk_s,
499 clk => clk_25,
500 rstn => rstn_25,
501 ADC_data => ADC_data,
502 ADC_nOE => ADC_OEB_bar_CH_s,
503 sample => sample,
504 sample_val => sample_val);
505
506 END GENERATE USE_ADCDRIVER_true;
507
508 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
509 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
510 GENERIC MAP (
511 ChanelCount => 9,
512 ncycle_cnv_high => 25,
513 ncycle_cnv => 50,
514 FILTER_ENABLED => 16#FF#)
515 PORT MAP (
516 cnv_clk => clk_24,
517 cnv_rstn => rstn_24,
518 cnv => ADC_smpclk_s,
519 clk => clk_25,
520 rstn => rstn_25,
521 ADC_data => ADC_data,
522 ADC_nOE => OPEN,
523 sample => OPEN,
524 sample_val => sample_val);
525
526 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
527
528 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
529 ramp_generator_1: ramp_generator
530 GENERIC MAP (
531 DATA_SIZE => 14,
532 VALUE_UNSIGNED_INIT => 2**I,
533 VALUE_UNSIGNED_INCR => 0,
534 VALUE_UNSIGNED_MASK => 16#3FFF#)
535 PORT MAP (
536 clk => clk_25,
537 rstn => rstn_25,
538 new_data => sample_val,
539 output_data => sample(I) );
540 END GENERATE all_sample;
541
542
543 END GENERATE USE_ADCDRIVER_false;
544
545
546
547
548 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
549
550 ADC_smpclk <= ADC_smpclk_s;
551 HK_smpclk <= ADC_smpclk_s;
552
553
554 -----------------------------------------------------------------------------
555 -- HK
556 -----------------------------------------------------------------------------
557 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
558
559 -----------------------------------------------------------------------------
560 --
561 -----------------------------------------------------------------------------
562 --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
563 -- lpp_bootloader_1: lpp_bootloader
564 -- GENERIC MAP (
565 -- pindex => 13,
566 -- paddr => 13,
567 -- pmask => 16#fff#,
568 -- hindex => 3,
569 -- haddr => 0,
570 -- hmask => 16#fff#)
571 -- PORT MAP (
572 -- HCLK => clk_25,
573 -- HRESETn => rstn_25,
574 -- apbi => apbi_ext,
575 -- apbo => apbo_ext(13),
576 -- ahbsi => ahbi_s_ext,
577 -- ahbso => ahbo_s_ext(3));
578 --END GENERATE inst_bootloader;
579
580 -----------------------------------------------------------------------------
581 --
582 -----------------------------------------------------------------------------
583 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
584 PROCESS (clk_25, rstn_25)
585 BEGIN -- PROCESS
586 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
587 TAG <= (OTHERS => '0');
588 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
589 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
590 END IF;
591 END PROCESS;
592
593
594 END GENERATE USE_DEBUG_VECTOR_IF;
595
596 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
597 --ahbrxd <= TAG(1); -- AHB UART
598 --TAG(3) <= ahbtxd;
599
600 urxd1 <= TAG(2); -- APB UART
601 TAG(4) <= utxd1;
602 --TAG(8) <= nSRAM_BUSY;
603 END GENERATE USE_DEBUG_VECTOR_IF2;
604
605 END beh; No newline at end of file
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4
5 TOP=LFR_EQM
6 BOARD=LFR-EQM
7
8 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
9
10 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
11 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
12 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
13 EFFORT=high
14 XSTOPT=
15
16 VHDLSYNFILES=LFR-EQM.vhd
17 VHDLSIMFILES=testbench.vhd
18
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
21
22 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 CLEAN=soft-clean
24
25 TECHLIBS = axcelerator
26
27 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX
29
30 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 ./amba_lcd_16x2_ctrlr \
33 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_delay \
36 ./lpp_bootloader \
37 ./dsp/lpp_fft \
38 ./lpp_uart \
39 ./lpp_usb \
40 ./lpp_sim/CY7C1061DV33 \
41
42 FILESKIP = i2cmst.vhd \
43 APB_MULTI_DIODE.vhd \
44 APB_MULTI_DIODE.vhd \
45 Top_MatrixSpec.vhd \
46 APB_FFT.vhd\
47 CoreFFT_simu.vhd \
48 lpp_lfr_apbreg_simu.vhd \
49 sgmii.vhd
50
51 include $(GRLIB)/bin/Makefile
52 include $(GRLIB)/software/leon3/Makefile
53
54 ################## project specific targets ##########################
55
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: CoreFFT.vhd
10 -- Description: CoreFFT
11 -- Top level FFT module
12 -- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
13 -- Notes: FFT In/out pins:
14 -- Input | Output | Comments
15 -- ------------+------------+------------------
16 -- clk | ifoPong |
17 -- ifiNreset | |async reset active low
18 -- start | |sync reset active high
19 -- Load Input data group |
20 -- d_im[15:0] | load |when high the inBuf is being loaded
21 -- d_re[15:0] | |
22 -- d_valid | |
23 -- Upload Output data group |
24 -- read_y | y_im[15:0] |
25 -- | y_re[15:0] |
26 -- | y_valid |marks a new output sample)
27 -- | y_rdy |when high the results are being uploaded
28 --------------------------------------------------------------------------------
29 library IEEE;
30 use IEEE.STD_LOGIC_1164.all;
31 USE work.fft_components.all;
32
33 ENTITY CoreFFT IS
34 GENERIC (
35 LOGPTS : integer := gLOGPTS;
36 LOGLOGPTS : integer := gLOGLOGPTS;
37 WSIZE : integer := gWSIZE;
38 TWIDTH : integer := gTWIDTH;
39 DWIDTH : integer := gDWIDTH;
40 TDWIDTH : integer := gTDWIDTH;
41 RND_MODE : integer := gRND_MODE;
42 SCALE_MODE : integer := gSCALE_MODE;
43 PTS : integer := gPTS;
44 HALFPTS : integer := gHALFPTS;
45 inBuf_RWDLY : integer := gInBuf_RWDLY );
46 PORT (
47 clk,ifiStart,ifiNreset : IN std_logic;
48 ifiD_valid, ifiRead_y : IN std_logic;
49 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
50 ifoLoad, ifoPong : OUT std_logic;
51 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
52 ifoY_valid, ifoY_rdy : OUT std_logic);
53 END ENTITY CoreFFT;
54
55 ARCHITECTURE translated OF CoreFFT IS
56
57 COMPONENT autoScale
58 GENERIC (SCALE_MODE : integer := 1 );
59 PORT (clk, clkEn, wLastStage : IN std_logic;
60 ldRiskOV, bflyRiskOV : IN std_logic;
61 startLoad, ifo_loadOn : IN std_logic;
62 bflyOutValid, startFFT : IN std_logic;
63 wEn_even, wEn_odd : IN std_logic;
64 upScale : OUT std_logic);
65 END COMPONENT;
66
67 COMPONENT bfly2
68 GENERIC ( RND_MODE : integer := 0;
69 WSIZE : integer := 16;
70 DWIDTH : integer := 32;
71 TWIDTH : integer := 16;
72 TDWIDTH : integer := 32 );
73 PORT (clk, validIn : IN std_logic;
74 swCrossIn : IN std_logic;
75 upScale : IN std_logic;
76 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
77 T : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
78 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
79 validOut, swCrossOut : OUT std_logic);
80 END COMPONENT;
81
82 COMPONENT sm_top
83 GENERIC ( PTS : integer := 256;
84 HALFPTS : integer := 128;
85 LOGPTS : integer := 8;
86 LOGLOGPTS : integer := 3;
87 inBuf_RWDLY : integer := 12 );
88 PORT (clk,clkEn : IN std_logic;
89 ifiStart, ifiNreset : IN std_logic;
90 ifiD_valid, ifiRead_y : IN std_logic;
91 ldA, rA, wA, tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
92 twid_wA, outBuf_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
93 outBuf_rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
94 wEn_even, wEn_odd : OUT std_logic;
95 preSwCross, twid_wEn : OUT std_logic;
96 inBuf_wEn, outBuf_wEn : OUT std_logic;
97 smPong, ldValid : OUT std_logic;
98 inBuf_rdValid : OUT std_logic;
99 wLastStage : OUT std_logic;
100 smStartFFTrd : OUT std_logic;
101 smStartLoad, ifoLoad : OUT std_logic;
102 ifoY_valid, ifoY_rdy : OUT std_logic);
103 END COMPONENT;
104
105 COMPONENT twiddle
106 PORT (A : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
107 T : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0));
108 END COMPONENT;
109
110 COMPONENT pipoBuffer
111 GENERIC ( LOGPTS : integer := 8;
112 DWIDTH : integer := 32 );
113 PORT (
114 clk, clkEn, pong, rEn : IN std_logic;
115 rA, wA_load, wA_bfly : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
116 ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
117 wEn_bfly,wEn_even,wEn_odd : IN std_logic;
118 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) );
119 END COMPONENT;
120
121 COMPONENT switch
122 GENERIC ( DWIDTH : integer := 16 );
123 PORT (clk, sel, validIn : IN std_logic;
124 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
125 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
126 validOut : OUT std_logic);
127 END COMPONENT;
128
129 COMPONENT twidLUT
130 GENERIC ( LOGPTS : integer := 8;
131 TDWIDTH : integer := 32 );
132 PORT (clk, wEn : IN std_logic;
133 wA, rA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
134 D : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
135 Q : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0));
136 END COMPONENT;
137
138 COMPONENT outBuff
139 GENERIC ( LOGPTS : integer := 8;
140 DWIDTH : integer := 32 );
141 PORT (clk, clkEn, wEn : IN std_logic;
142 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
143 wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
144 rA : IN std_logic_vector(LOGPTS-1 DOWNTO 0);
145 outD : OUT std_logic_vector(DWIDTH-1 DOWNTO 0));
146 END COMPONENT;
147
148 SIGNAL ldA_w, rA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
149 SIGNAL wA_w, tA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
150 SIGNAL twid_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
151 SIGNAL outBuf_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
152 SIGNAL outBuf_rA_w : std_logic_vector(LOGPTS-1 DOWNTO 0);
153 SIGNAL wEn_even_w : std_logic;
154 SIGNAL wEn_odd_w : std_logic;
155 SIGNAL inBuf_wEn_w : std_logic;
156 SIGNAL preSwCross_w : std_logic;
157 SIGNAL postSwCross_w : std_logic;
158 SIGNAL twid_wEn_w : std_logic;
159 SIGNAL outBuf_wEn_w : std_logic;
160 SIGNAL ldRiskOV_w : std_logic;
161 SIGNAL bflyRiskOV_w : std_logic;
162 SIGNAL readP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
163 SIGNAL readQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
164 SIGNAL bflyInP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
165 SIGNAL bflyInQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
166 SIGNAL bflyOutP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
167 SIGNAL bflyOutQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
168 SIGNAL T_w : std_logic_vector(TDWIDTH-1 DOWNTO 0);
169 SIGNAL twidData_w : std_logic_vector(TDWIDTH-1 DOWNTO 0);
170 SIGNAL outEven_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
171 SIGNAL outOdd_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
172 SIGNAL inBufValid_w : std_logic;
173 SIGNAL preSwValid_w : std_logic;
174 SIGNAL bflyValid_w : std_logic;
175 SIGNAL wLastStage_w : std_logic;
176 SIGNAL startFFTrd_w : std_logic;
177 SIGNAL startLoad_w : std_logic;
178 SIGNAL upScale_w : std_logic;
179 SIGNAL port_xhdl15 : std_logic;
180 SIGNAL xhdl_17 : std_logic_vector(DWIDTH-1 DOWNTO 0);
181 SIGNAL xhdl_23 : std_logic_vector(DWIDTH-1 DOWNTO 0);
182 SIGNAL clkEn_const : std_logic;
183 SIGNAL ifoLoad_xhdl1 : std_logic;
184 SIGNAL ifoY_im_xhdl2 : std_logic_vector(WSIZE-1 DOWNTO 0);
185 SIGNAL ifoY_re_xhdl3 : std_logic_vector(WSIZE-1 DOWNTO 0);
186 SIGNAL ifoPong_xhdl4 : std_logic;
187 SIGNAL ifoY_valid_xhdl5 : std_logic;
188 SIGNAL ifoY_rdy_xhdl6 : std_logic;
189 SIGNAL displayBflyOutP : std_logic;
190 SIGNAL displayBflyOutQ : std_logic;
191 SIGNAL displayInBuf_wEn : std_logic;
192 SIGNAL ldValid_w : std_logic;
193
194 BEGIN
195 ifoLoad <= ifoLoad_xhdl1;
196 ifoY_im <= ifoY_im_xhdl2;
197 ifoY_re <= ifoY_re_xhdl3;
198 ifoPong <= ifoPong_xhdl4;
199 ifoY_valid <= ifoY_valid_xhdl5;
200 ifoY_rdy <= ifoY_rdy_xhdl6;
201 -- debug only
202 displayBflyOutP <= bflyOutP_w(0) ;
203 displayBflyOutQ <= bflyOutQ_w(0) ;
204 displayInBuf_wEn <= inBuf_wEn_w ;
205 port_xhdl15 <= '1';
206
207 smTop_0 : sm_top
208 GENERIC MAP ( PTS => PTS, HALFPTS => HALFPTS,
209 LOGPTS => LOGPTS, LOGLOGPTS => LOGLOGPTS, inBuf_RWDLY => inBuf_RWDLY )
210 PORT MAP (
211 clk => clk,
212 clkEn => port_xhdl15,
213 ifiStart => ifiStart,
214 ifiNreset => ifiNreset,
215 ifiD_valid => ifiD_valid,
216 ifiRead_y => ifiRead_y,
217 ldA => ldA_w,
218 rA => rA_w,
219 wA => wA_w,
220 tA => tA_w,
221 twid_wA => twid_wA_w,
222 outBuf_wA => outBuf_wA_w,
223 outBuf_rA => outBuf_rA_w,
224 wEn_even => wEn_even_w,
225 wEn_odd => wEn_odd_w,
226 preSwCross => preSwCross_w,
227 twid_wEn => twid_wEn_w,
228 inBuf_wEn => inBuf_wEn_w,
229 outBuf_wEn => outBuf_wEn_w,
230 smPong => ifoPong_xhdl4,
231 ldValid => ldValid_w,
232 inBuf_rdValid => inBufValid_w,
233 wLastStage => wLastStage_w,
234 smStartFFTrd => startFFTrd_w,
235 smStartLoad => startLoad_w,
236 ifoLoad => ifoLoad_xhdl1,
237 ifoY_valid => ifoY_valid_xhdl5,
238 ifoY_rdy => ifoY_rdy_xhdl6);
239
240 xhdl_17 <= ifiD_im & ifiD_re;
241
242 inBuf_0 : pipoBuffer
243 GENERIC MAP ( LOGPTS => LOGPTS,
244 DWIDTH => DWIDTH )
245 PORT MAP (
246 clk => clk,
247 clkEn => '1',
248 rEn => '1',
249 rA => rA_w,
250 wA_load => ldA_w,
251 wA_bfly => wA_w,
252 ldData => xhdl_17,
253 wP_bfly => outEven_w,
254 wQ_bfly => outOdd_w,
255 wEn_bfly => inBuf_wEn_w,
256 wEn_even => wEn_even_w,
257 wEn_odd => wEn_odd_w,
258 pong => ifoPong_xhdl4,
259 outP => readP_w,
260 outQ => readQ_w);
261
262 preBflySw_0 : switch
263 GENERIC MAP ( DWIDTH => DWIDTH )
264 PORT MAP (
265 clk => clk,
266 inP => readP_w,
267 inQ => readQ_w,
268 sel => preSwCross_w,
269 outP => bflyInP_w,
270 outQ => bflyInQ_w,
271 validIn => inBufValid_w,
272 validOut => preSwValid_w);
273
274 bfly_0 : bfly2
275 GENERIC MAP (RND_MODE => RND_MODE, WSIZE => WSIZE, DWIDTH => DWIDTH,
276 TWIDTH => TWIDTH, TDWIDTH => TDWIDTH )
277 PORT MAP (
278 clk => clk,
279 upScale => upScale_w,
280 inP => bflyInP_w,
281 inQ => bflyInQ_w,
282 T => T_w,
283 outP => bflyOutP_w,
284 outQ => bflyOutQ_w,
285 validIn => preSwValid_w,
286 validOut => bflyValid_w,
287 swCrossIn => preSwCross_w,
288 swCrossOut => postSwCross_w);
289
290 lut_0 : twiddle
291 PORT MAP (A => twid_wA_w, T => twidData_w);
292
293 twidLUT_1 : twidLUT
294 GENERIC MAP ( LOGPTS => LOGPTS, TDWIDTH => TDWIDTH )
295 PORT MAP (
296 clk => clk,
297 wA => twid_wA_w,
298 wEn => twid_wEn_w,
299 rA => tA_w,
300 D => twidData_w,
301 Q => T_w);
302
303 postBflySw_0 : switch
304 GENERIC MAP ( DWIDTH => DWIDTH )
305 PORT MAP (
306 clk => clk,
307 inP => bflyOutP_w,
308 inQ => bflyOutQ_w,
309 sel => postSwCross_w,
310 outP => outEven_w,
311 outQ => outOdd_w,
312 validIn => bflyValid_w,
313 validOut => open);
314
315 ifoY_im_xhdl2 <= xhdl_23(DWIDTH-1 DOWNTO WSIZE);
316 ifoY_re_xhdl3 <= xhdl_23(WSIZE-1 DOWNTO 0);
317 outBuff_0 : outBuff
318 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
319 PORT MAP (
320 clk => clk, clkEn => '1',
321 rA => outBuf_rA_w,
322 wA => outBuf_wA_w,
323 inP => outEven_w,
324 inQ => outOdd_w,
325 wEn => outBuf_wEn_w,
326 outD => xhdl_23);
327
328 -- Autoscaling
329 -- monitor if input data .im and .re have MSB == sign
330 ldRiskOV_w <= to_logic(
331 NOT ((ifiD_im(WSIZE-1) = ifiD_im(WSIZE-2))
332 AND (ifiD_re(WSIZE-1) = ifiD_re(WSIZE-2))) );
333
334 bflyRiskOV_w <= to_logic(
335 NOT ((((bflyOutP_w(DWIDTH-1) = bflyOutP_w(DWIDTH- 2))
336 AND (bflyOutP_w(WSIZE-1) = bflyOutP_w(WSIZE-2)))
337 AND (bflyOutQ_w(DWIDTH-1) = bflyOutQ_w(DWIDTH-2)))
338 AND (bflyOutQ_w(WSIZE-1) = bflyOutQ_w(WSIZE-2))) );
339 clkEn_const <= '1';
340 autoScale_0 : autoScale
341 GENERIC MAP (SCALE_MODE => SCALE_MODE)
342 PORT MAP (
343 clk => clk,
344 clkEn => clkEn_const,
345 ldRiskOV => ldRiskOV_w,
346 bflyRiskOV => bflyRiskOV_w,
347 startLoad => startLoad_w,
348 startFFT => startFFTrd_w,
349 bflyOutValid => bflyValid_w,
350 wLastStage => wLastStage_w,
351 wEn_even => wEn_even_w,
352 wEn_odd => wEn_odd_w,
353 ifo_loadOn => ifoLoad_xhdl1,
354 upScale => upScale_w);
355
356 END ARCHITECTURE translated; No newline at end of file
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: CoreFFT.vhd
10 -- Description: CoreFFT
11 -- Top level FFT module
12 -- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
13 -- Notes: FFT In/out pins:
14 -- Input | Output | Comments
15 -- ------------+------------+------------------
16 -- clk | ifoPong |
17 -- ifiNreset | |async reset active low
18 -- start | |sync reset active high
19 -- Load Input data group |
20 -- d_im[15:0] | load |when high the inBuf is being loaded
21 -- d_re[15:0] | |
22 -- d_valid | |
23 -- Upload Output data group |
24 -- read_y | y_im[15:0] |
25 -- | y_re[15:0] |
26 -- | y_valid |marks a new output sample)
27 -- | y_rdy |when high the results are being uploaded
28 --------------------------------------------------------------------------------
29 LIBRARY IEEE;
30 USE IEEE.STD_LOGIC_1164.ALL;
31 USE IEEE.numeric_std.ALL;
32 USE work.fft_components.ALL;
33
34 LIBRARY lpp;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.iir_filter.ALL;
37
38 ENTITY CoreFFT IS
39 GENERIC (
40 LOGPTS : INTEGER := gLOGPTS;
41 LOGLOGPTS : INTEGER := gLOGLOGPTS;
42 WSIZE : INTEGER := gWSIZE;
43 TWIDTH : INTEGER := gTWIDTH;
44 DWIDTH : INTEGER := gDWIDTH;
45 TDWIDTH : INTEGER := gTDWIDTH;
46 RND_MODE : INTEGER := gRND_MODE;
47 SCALE_MODE : INTEGER := gSCALE_MODE;
48 PTS : INTEGER := gPTS;
49 HALFPTS : INTEGER := gHALFPTS;
50 inBuf_RWDLY : INTEGER := gInBuf_RWDLY);
51 PORT (
52 clk : IN STD_LOGIC;
53 ifiStart : IN STD_LOGIC; -- start -- cste
54 ifiNreset : IN STD_LOGIC;
55 ifiD_valid : IN STD_LOGIC; -- d_valid
56 ifiRead_y : IN STD_LOGIC; -- read_y
57 ifiD_im, ifiD_re : IN STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0);
58 ifoLoad : OUT STD_LOGIC; -- load
59 ifoPong : OUT STD_LOGIC; -- pong -- UNUSED
60 ifoY_im, ifoY_re : OUT STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0);
61 ifoY_valid : OUT STD_LOGIC; -- y_valid
62 ifoY_rdy : OUT STD_LOGIC); -- y_rdy
63 END ENTITY CoreFFT;
64
65 ARCHITECTURE translated OF CoreFFT IS
66 SIGNAL fft_ongoing : STD_LOGIC;
67 SIGNAL fft_done : STD_LOGIC;
68 SIGNAL counter : INTEGER;
69 SIGNAL counter_out : INTEGER;
70 SIGNAL counter_wait : INTEGER;
71 SIGNAL fft_ongoing_ok : STD_LOGIC;
72 SIGNAL fft_ongoing_ok_1 : STD_LOGIC;
73 SIGNAL fft_ongoing_ok_2 : STD_LOGIC;
74 SIGNAL fft_ongoing_ok_3 : STD_LOGIC;
75 SIGNAL fft_ongoing_ok_4 : STD_LOGIC;
76 --
77 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 SIGNAL ren : STD_LOGIC;
80 SIGNAL wen : STD_LOGIC;
81 --
82 SIGNAL ifoLoad_s : STD_LOGIC; -- load
83 SIGNAL ifoY_rdy_s : STD_LOGIC; -- y_rdy
84 SIGNAL ifoY_rdy_s2 : STD_LOGIC; -- y_rdy
85 SIGNAL ifoY_rdy_s3 : STD_LOGIC; -- y_rdy
86 SIGNAL ifoY_valid_s : STD_LOGIC; -- y_valid
87 SIGNAL ifoPong_s : STD_LOGIC; -- pong -- UNUSED
88 SIGNAL ifoPong_first : STD_LOGIC; -- pong -- UNUSED
89
90 -----------------------------------------------------------------------------
91 SIGNAL ifoY_im_counter : INTEGER;
92 BEGIN
93
94 -----------------------------------------------------------------------------
95 -- INPUT INTERFACE
96 -----------------------------------------------------------------------------
97 -- in ifiD_valid
98 -- in (internal) fft_done
99
100 -- out(internal) fft_ongoing
101 -- out ifoLoad_s
102 PROCESS (clk, ifiNreset)
103 BEGIN
104 IF ifiNreset = '0' THEN
105 counter <= 0;
106 fft_ongoing <= '0';
107 ifoLoad_s <= '0';
108 ELSIF clk'EVENT AND clk = '1' THEN
109 IF fft_ongoing = '0' THEN
110 ifoLoad_s <= '1';
111 fft_ongoing <= '0';
112 IF ifiD_valid = '1' THEN
113 ifoLoad_s <= '1';
114 IF counter = 255 THEN
115 ifoLoad_s <= '0';
116 fft_ongoing <= '1';
117 counter <= 0;
118 ELSE
119 counter <= counter + 1;
120 END IF;
121 END IF;
122 ELSIF fft_ongoing_ok = '1' THEN--fft_done
123 fft_ongoing <= '0';
124 END IF;
125 END IF;
126 END PROCESS;
127
128 -----------------------------------------------------------------------------
129 -- WAIT PROCESS
130 -----------------------------------------------------------------------------
131 PROCESS (clk, ifiNreset)
132 BEGIN
133 IF ifiNreset = '0' THEN
134 -- fft_done <= '0';
135
136 counter_wait <= 0;
137 fft_ongoing_ok <= '0';
138 ELSIF clk'EVENT AND clk = '1' THEN
139 fft_done <= '0';
140 fft_ongoing_ok <= '0';
141 IF fft_ongoing = '0' THEN
142 -- fft_done <= '1';
143 counter_wait <= 1140;--1000;--1140;--855;--936;
144 ELSE
145 IF counter_wait > 0 THEN
146 counter_wait <= counter_wait -1;
147 IF counter_wait = 1 THEN
148 fft_ongoing_ok <= '1';
149 END IF;
150 END IF;
151 END IF;
152 END IF;
153 END PROCESS;
154
155 -----------------------------------------------------------------------------
156 -- OUTPUT INTERFACE
157 -----------------------------------------------------------------------------
158 PROCESS (clk, ifiNreset)
159 BEGIN -- PROCESS
160 IF ifiNreset = '0' THEN -- asynchronous reset (active low)
161 fft_ongoing_ok_1 <= '0';
162 fft_ongoing_ok_2 <= '0';
163 fft_ongoing_ok_3 <= '0';
164 fft_ongoing_ok_4 <= '0';
165 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
166 fft_ongoing_ok_1 <= fft_ongoing_ok;
167 fft_ongoing_ok_2 <= fft_ongoing_ok_1;
168 fft_ongoing_ok_3 <= fft_ongoing_ok_2;
169 fft_ongoing_ok_4 <= fft_ongoing_ok_3;
170
171 END IF;
172 END PROCESS;
173
174
175 -- in ifiRead_y
176 -- in(internal) fft_ongoing_ok
177
178 -- out (internal) fft_done
179 -- out ifoY_im
180 -- out ifoY_re
181 -- out ifoY_valid_s
182 -- out ifoY_rdy_s
183 PROCESS (clk, ifiNreset)
184 BEGIN
185 IF ifiNreset = '0' THEN
186 -- fft_done <= '0';
187 --ifoY_im <= (OTHERS => '0');
188 --ifoY_re <= (OTHERS => '0');
189 ifoY_valid_s <= '0';
190 ifoY_rdy_s <= '0';
191 counter_out <= 0;
192 ELSIF clk'EVENT AND clk = '1' THEN
193 -- fft_done <= '0';
194
195 IF fft_ongoing_ok_4 = '1' THEN
196 counter_out <= 256;
197 END IF;
198
199 ifoY_valid_s <= '0';
200 ifoY_rdy_s <= '0';
201 IF counter_out > 0 THEN
202 ifoY_valid_s <= '1';
203 ifoY_rdy_s <= '1';
204 IF ifiRead_y = '1' THEN
205 counter_out <= counter_out - 1;
206 --IF counter_out = 1 THEN
207 -- fft_done <= '1';
208 --END IF;
209 END IF;
210 END IF;
211
212 END IF;
213 END PROCESS;
214
215 -----------------------------------------------------------------------------
216 -- DATA
217 -----------------------------------------------------------------------------
218 lpp_fifo_1: lpp_fifo
219 GENERIC MAP (
220 tech => 0,
221 Mem_use => use_CEL,
222 DataSz => 32,
223 AddrSz => 7)
224 PORT MAP (
225 clk => clk,
226 rstn => ifiNreset,
227
228 ReUse => '0',
229
230 wen => wen,
231 wdata => wdata,
232
233 ren => ren,
234 rdata => rdata,
235
236 empty => OPEN,
237 full => OPEN,
238 almost_full => OPEN);
239
240 wen <= '0' WHEN ifoLoad_s = '1' AND ifiD_valid = '1' ELSE '1';
241 wdata <= ifiD_im & ifiD_re;
242
243
244 ren <= '0' WHEN ifoY_rdy_s = '1' AND ifiRead_y = '1' ELSE '1';
245 ifoY_im <= STD_LOGIC_VECTOR(to_unsigned(ifoY_im_counter,16));--rdata(31 DOWNTO 16);
246 ifoY_re <= rdata(15 DOWNTO 0);
247
248 PROCESS (clk, ifiNreset)
249 BEGIN
250 IF ifiNreset = '0' THEN
251 ifoY_im_counter <= 0;
252 ELSIF clk'event AND clk = '1' THEN
253 IF ifoY_rdy_s = '1' AND ifiRead_y = '1' THEN
254 ifoY_im_counter <= ifoY_im_counter + 1;
255 END IF;
256 END IF;
257 END PROCESS;
258
259
260
261 ifoLoad <= ifoLoad_s;
262 ifoY_rdy <= ifoY_rdy_s OR ifoY_rdy_s2 OR ifoY_rdy_s3;
263
264
265 PROCESS (clk, ifiNreset)
266 BEGIN
267 IF ifiNreset = '0' THEN
268 ifoY_valid <= '0';
269 ifoY_rdy_s2 <= '0';
270 ifoY_rdy_s3 <= '0';
271 ifoPong_s <= '0';
272 ifoPong_first <= '0';
273 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
274 ifoY_valid <= ifoY_valid_s;
275 ifoY_rdy_s2 <= ifoY_rdy_s;
276 ifoY_rdy_s3 <= ifoY_rdy_s2;
277 IF fft_ongoing_ok = '1' THEN
278 IF ifoPong_first = '1' THEN
279 ifoPong_s <= NOT ifoPong_s;
280 END IF;
281 ifoPong_first <= '1';
282 END IF;
283 END IF;
284 END PROCESS;
285
286 ifoPong <= ifoPong_s;
287
288 END ARCHITECTURE translated;
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: CoreFFT.vhd
10 -- Description: CoreFFT
11 -- Top level FFT module
12 -- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
13 -- Notes: FFT In/out pins:
14 -- Input | Output | Comments
15 -- ------------+------------+------------------
16 -- clk | ifoPong |
17 -- ifiNreset | |async reset active low
18 -- start | |sync reset active high
19 -- Load Input data group |
20 -- d_im[15:0] | load |when high the inBuf is being loaded
21 -- d_re[15:0] | |
22 -- d_valid | |
23 -- Upload Output data group |
24 -- read_y | y_im[15:0] |
25 -- | y_re[15:0] |
26 -- | y_valid |marks a new output sample)
27 -- | y_rdy |when high the results are being uploaded
28 --------------------------------------------------------------------------------
29 LIBRARY IEEE;
30 USE IEEE.STD_LOGIC_1164.ALL;
31 USE IEEE.numeric_std.ALL;
32 USE work.fft_components.ALL;
33
34 LIBRARY lpp;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.iir_filter.ALL;
37
38 ENTITY CoreFFT IS
39 GENERIC (
40 LOGPTS : INTEGER := gLOGPTS;
41 LOGLOGPTS : INTEGER := gLOGLOGPTS;
42 WSIZE : INTEGER := gWSIZE;
43 TWIDTH : INTEGER := gTWIDTH;
44 DWIDTH : INTEGER := gDWIDTH;
45 TDWIDTH : INTEGER := gTDWIDTH;
46 RND_MODE : INTEGER := gRND_MODE;
47 SCALE_MODE : INTEGER := gSCALE_MODE;
48 PTS : INTEGER := gPTS;
49 HALFPTS : INTEGER := gHALFPTS;
50 inBuf_RWDLY : INTEGER := gInBuf_RWDLY);
51 PORT (
52 clk : IN STD_LOGIC;
53 ifiStart : IN STD_LOGIC; -- start -- cste
54 ifiNreset : IN STD_LOGIC;
55 ifiD_valid : IN STD_LOGIC; -- d_valid
56 ifiRead_y : IN STD_LOGIC; -- read_y
57 ifiD_im, ifiD_re : IN STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0);
58 ifoLoad : OUT STD_LOGIC; -- load
59 ifoPong : OUT STD_LOGIC; -- pong -- UNUSED
60 ifoY_im, ifoY_re : OUT STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0);
61 ifoY_valid : OUT STD_LOGIC; -- y_valid
62 ifoY_rdy : OUT STD_LOGIC); -- y_rdy
63 END ENTITY CoreFFT;
64
65 ARCHITECTURE translated OF CoreFFT IS
66
67
68 SIGNAL fft_ongoing : STD_LOGIC;
69 SIGNAL fft_done : STD_LOGIC;
70 SIGNAL counter : INTEGER;
71 SIGNAL counter_out : INTEGER;
72 SIGNAL counter_wait : INTEGER;
73 SIGNAL fft_ongoing_ok : STD_LOGIC;
74 SIGNAL fft_ongoing_ok_1 : STD_LOGIC;
75 SIGNAL fft_ongoing_ok_2 : STD_LOGIC;
76 SIGNAL fft_ongoing_ok_3 : STD_LOGIC;
77 SIGNAL fft_ongoing_ok_4 : STD_LOGIC;
78 --
79 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
80 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
81 SIGNAL ren : STD_LOGIC;
82 SIGNAL wen : STD_LOGIC;
83 --
84 SIGNAL ifoLoad_s : STD_LOGIC; -- load
85 SIGNAL ifoY_rdy_s : STD_LOGIC; -- y_rdy
86 SIGNAL ifoY_rdy_s2 : STD_LOGIC; -- y_rdy
87 SIGNAL ifoY_rdy_s3 : STD_LOGIC; -- y_rdy
88 SIGNAL ifoY_valid_s : STD_LOGIC; -- y_valid
89 SIGNAL ifoPong_s : STD_LOGIC; -- pong -- UNUSED
90 SIGNAL ifoPong_first : STD_LOGIC; -- pong -- UNUSED
91
92 -----------------------------------------------------------------------------
93 SIGNAL ifoY_im_counter : INTEGER;
94
95
96
97 SIGNAL counter_in : INTEGER;
98 SIGNAL fft_start : STD_LOGIC;
99 SIGNAL fft_done : STD_LOGIC;
100
101 SIGNAL ifoLoad_s : STD_LOGIC;
102 SIGNAL ifoLoad_s2 : STD_LOGIC;
103 BEGIN
104
105 --clk : IN STD_LOGIC;
106 --ifiNreset : IN STD_LOGIC;
107 -----------------------------------------------------------------------------
108 --INPUT INTERFACE
109 --ifoLoad : OUT STD_LOGIC; -- load
110 --ifiD_valid : IN STD_LOGIC; -- d_valid
111 --ifiD_im, ifiD_re : IN STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0);
112
113 ifoLoad <= ifoLoad_s;
114
115 PROCESS (clk, ifiNreset)
116 BEGIN -- PROCESS
117 IF ifiNreset = '0' THEN -- asynchronous reset (active low)
118 counter_in <= 0;
119 fft_start <= '0';
120 ifoLoad_s <= '0';
121 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
122 IF counter_in < 256 AND ifoLoad_s = '1'THEN
123 IF ifiD_valid = '1' THEN
124 counter_in <= counter_in + 1;
125 IF counter_in = 255 THEN
126 ifoLoad_s <= '0';
127 fft_start <= '1';
128 END IF;
129 END IF;
130 ELSE
131 ifoLoad_s <= fft_done AND (NOT fft_start);
132 counter_in <= 0;
133 fft_start <= '0';
134 END IF;
135 END IF;
136 END PROCESS;
137
138 PROCESS (clk, ifiNreset)
139 BEGIN -- PROCESS
140 IF ifiNreset = '0' THEN -- asynchronous reset (active low)
141 fft_done <= '1';
142 counter_wait <= 0;
143 output_start <= '0';
144 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
145 output_start <= '0';
146 IF counter_wait > 0 THEN
147 IF output_done = '1' THEN
148 counter_wait <= counter_wait - 1;
149 IF counter_wait = 1 THEN
150 output_start <= '1';
151 END IF;
152 END IF;
153 ELSE
154 fft_done <= '1';
155 IF fft_start = '1' THEN
156 counter_wait <= 855;
157 fft_done <= '0';
158 END IF;
159 counter_wait <= 0;
160 END IF;
161 END IF;
162 END PROCESS;
163
164 PROCESS (clk, ifiNreset)
165 BEGIN -- PROCESS
166 IF ifiNreset = '0' THEN -- asynchronous reset (active low)
167 output_done <= '1';
168 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
169 IF output_start = '1' THEN
170 output_done <= '0';
171 counter_output <= 0;
172 ELSE
173
174 END IF;
175
176 END IF;
177 END PROCESS;
178
179 -----------------------------------------------------------------------------
180 ifiStart : IN STD_LOGIC; -- start -- cste
181
182 ifiRead_y : IN STD_LOGIC; -- read_y
183
184
185 ifoPong : OUT STD_LOGIC; -- pong -- UNUSED
186 ifoY_im, ifoY_re : OUT STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0);
187 ifoY_valid : OUT STD_LOGIC; -- y_valid
188 ifoY_rdy : OUT STD_LOGIC); -- y_rdy
189
190
191
192 -----------------------------------------------------------------------------
193 -- INPUT INTERFACE
194 -----------------------------------------------------------------------------
195 -- in ifiD_valid
196 -- in (internal) fft_done
197
198 -- out(internal) fft_ongoing
199 -- out ifoLoad_s
200 PROCESS (clk, ifiNreset)
201 BEGIN
202 IF ifiNreset = '0' THEN
203 counter <= 0;
204 fft_ongoing <= '0';
205 ifoLoad_s <= '0';
206 ELSIF clk'EVENT AND clk = '1' THEN
207 IF fft_ongoing = '0' THEN
208 ifoLoad_s <= '1';
209 fft_ongoing <= '0';
210 IF ifiD_valid = '1' THEN
211 ifoLoad_s <= '1';
212 IF counter = 255 THEN
213 ifoLoad_s <= '0';
214 fft_ongoing <= '1';
215 counter <= 0;
216 ELSE
217 counter <= counter + 1;
218 END IF;
219 END IF;
220 ELSIF fft_ongoing_ok = '1' THEN--fft_done
221 fft_ongoing <= '0';
222 END IF;
223 END IF;
224 END PROCESS;
225
226 -----------------------------------------------------------------------------
227 -- WAIT PROCESS
228 -----------------------------------------------------------------------------
229 PROCESS (clk, ifiNreset)
230 BEGIN
231 IF ifiNreset = '0' THEN
232 -- fft_done <= '0';
233
234 counter_wait <= 0;
235 fft_ongoing_ok <= '0';
236 ELSIF clk'EVENT AND clk = '1' THEN
237 fft_done <= '0';
238 fft_ongoing_ok <= '0';
239 IF fft_ongoing = '0' THEN
240 -- fft_done <= '1';
241 counter_wait <= 855;--936;--1000;--1140;--936;
242 ELSE
243 IF counter_wait > 0 THEN
244 counter_wait <= counter_wait -1;
245 IF counter_wait = 1 THEN
246 fft_ongoing_ok <= '1';
247 END IF;
248 END IF;
249 END IF;
250 END IF;
251 END PROCESS;
252
253 -----------------------------------------------------------------------------
254 -- OUTPUT INTERFACE
255 -----------------------------------------------------------------------------
256 PROCESS (clk, ifiNreset)
257 BEGIN -- PROCESS
258 IF ifiNreset = '0' THEN -- asynchronous reset (active low)
259 fft_ongoing_ok_1 <= '0';
260 fft_ongoing_ok_2 <= '0';
261 fft_ongoing_ok_3 <= '0';
262 fft_ongoing_ok_4 <= '0';
263 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
264 fft_ongoing_ok_1 <= fft_ongoing_ok;
265 fft_ongoing_ok_2 <= fft_ongoing_ok_1;
266 fft_ongoing_ok_3 <= fft_ongoing_ok_2;
267 fft_ongoing_ok_4 <= fft_ongoing_ok_3;
268
269 END IF;
270 END PROCESS;
271
272
273 -- in ifiRead_y
274 -- in(internal) fft_ongoing_ok
275
276 -- out (internal) fft_done
277 -- out ifoY_im
278 -- out ifoY_re
279 -- out ifoY_valid_s
280 -- out ifoY_rdy_s
281 PROCESS (clk, ifiNreset)
282 BEGIN
283 IF ifiNreset = '0' THEN
284 -- fft_done <= '0';
285 --ifoY_im <= (OTHERS => '0');
286 --ifoY_re <= (OTHERS => '0');
287 ifoY_valid_s <= '0';
288 ifoY_rdy_s <= '0';
289 counter_out <= 0;
290 ELSIF clk'EVENT AND clk = '1' THEN
291 -- fft_done <= '0';
292
293 IF fft_ongoing_ok_4 = '1' THEN
294 counter_out <= 256;
295 END IF;
296
297 ifoY_valid_s <= '0';
298 ifoY_rdy_s <= '0';
299 IF counter_out > 0 THEN
300 ifoY_valid_s <= '1';
301 ifoY_rdy_s <= '1';
302 IF ifiRead_y = '1' THEN
303 counter_out <= counter_out - 1;
304 --IF counter_out = 1 THEN
305 -- fft_done <= '1';
306 --END IF;
307 END IF;
308 END IF;
309
310 END IF;
311 END PROCESS;
312
313 -----------------------------------------------------------------------------
314 -- DATA
315 -----------------------------------------------------------------------------
316 lpp_fifo_1: lpp_fifo
317 GENERIC MAP (
318 tech => 0,
319 Mem_use => use_CEL,
320 DataSz => 32,
321 AddrSz => 7)
322 PORT MAP (
323 clk => clk,
324 rstn => ifiNreset,
325
326 ReUse => '0',
327
328 wen => wen,
329 wdata => wdata,
330
331 ren => ren,
332 rdata => rdata,
333
334 empty => OPEN,
335 full => OPEN,
336 almost_full => OPEN);
337
338 wen <= '0' WHEN ifoLoad_s = '1' AND ifiD_valid = '1' ELSE '1';
339 wdata <= ifiD_im & ifiD_re;
340
341
342 ren <= '0' WHEN ifoY_rdy_s = '1' AND ifiRead_y = '1' ELSE '1';
343 ifoY_im <= STD_LOGIC_VECTOR(to_unsigned(ifoY_im_counter,16));--rdata(31 DOWNTO 16);
344 ifoY_re <= rdata(15 DOWNTO 0);
345
346 PROCESS (clk, ifiNreset)
347 BEGIN
348 IF ifiNreset = '0' THEN
349 ifoY_im_counter <= 0;
350 ELSIF clk'event AND clk = '1' THEN
351 IF ifoY_rdy_s = '1' AND ifiRead_y = '1' THEN
352 ifoY_im_counter <= ifoY_im_counter + 1;
353 END IF;
354 END IF;
355 END PROCESS;
356
357
358
359 ifoLoad <= ifoLoad_s;
360 ifoY_rdy <= ifoY_rdy_s OR ifoY_rdy_s2 OR ifoY_rdy_s3;
361
362
363 PROCESS (clk, ifiNreset)
364 BEGIN
365 IF ifiNreset = '0' THEN
366 ifoY_valid <= '0';
367 ifoY_rdy_s2 <= '0';
368 ifoY_rdy_s3 <= '0';
369 ifoPong_s <= '0';
370 ifoPong_first <= '0';
371 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
372 ifoY_valid <= ifoY_valid_s;
373 ifoY_rdy_s2 <= ifoY_rdy_s;
374 ifoY_rdy_s3 <= ifoY_rdy_s2;
375 IF fft_ongoing_ok = '1' THEN
376 IF ifoPong_first = '1' THEN
377 ifoPong_s <= NOT ifoPong_s;
378 END IF;
379 ifoPong_first <= '1';
380 END IF;
381 END IF;
382 END PROCESS;
383
384 ifoPong <= ifoPong_s;
385
386 END ARCHITECTURE translated;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 ENTITY Driver_FFT IS
27 GENERIC(
28 Data_sz : INTEGER RANGE 1 TO 32 := 16;
29 NbData : INTEGER RANGE 1 TO 512 := 256
30 );
31 PORT(
32 clk : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34 Load : IN STD_LOGIC; -- (CoreFFT) FFT_Load
35 -- Load
36 Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- FifoIN_Empty
37 DATA : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); -- FifoIN_Data
38 Valid : OUT STD_LOGIC; --(CoreFFT) Drive_write
39 Read : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- Read
40 Data_re : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --(CoreFFT) Drive_DataRE
41 Data_im : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0) --(CoreFFT) Drive_DataIM
42 );
43 END ENTITY;
44
45
46 ARCHITECTURE ar_Driver OF Driver_FFT IS
47
48 TYPE etat IS (eX, e0, e1, e2);
49 SIGNAL ect : etat;
50
51 SIGNAL DataCount : INTEGER RANGE 0 TO 255 := 0;
52 SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0;
53
54 SIGNAL sLoad : STD_LOGIC;
55
56 BEGIN
57
58 PROCESS(clk, rstn)
59 BEGIN
60 IF(rstn = '0')then
61 ect <= e0;
62 Read <= (OTHERS => '1');
63 Valid <= '0';
64 Data_re <= (OTHERS => '0');
65 Data_im <= (OTHERS => '0');
66 DataCount <= 0;
67 FifoCpt <= 0;
68 sLoad <= '0';
69
70 ELSIF(clk'EVENT AND clk = '1')then
71 sLoad <= Load;
72
73 IF(sLoad = '1' and Load = '0')THEN
74 IF(FifoCpt = 4)THEN
75 FifoCpt <= 0;
76 ELSE
77 FifoCpt <= FifoCpt + 1;
78 END IF;
79 END IF;
80
81 CASE ect IS
82
83 WHEN e0 =>
84 IF(Load = '1' and Empty(FifoCpt) = '0')THEN
85 Read(FifoCpt) <= '0';
86 ect <= e1;
87 END IF;
88
89 WHEN e1 =>
90 Valid <= '0';
91 Read(FifoCpt) <= '1';
92 ect <= e2;
93
94 WHEN e2 =>
95 Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz));
96 Data_im <= (OTHERS => '0');
97 Valid <= '1';
98 IF(DataCount = NbData-1)THEN
99 DataCount <= 0;
100 ect <= eX;
101 ELSE
102 DataCount <= DataCount + 1;
103 IF(Load = '1' and Empty(FifoCpt) = '0')THEN
104 Read(FifoCpt) <= '0';
105 ect <= e1;
106 ELSE
107 ect <= eX;
108 END IF;
109 END IF;
110
111 WHEN eX =>
112 Valid <= '0';
113 ect <= e0;
114
115 WHEN OTHERS =>
116 NULL;
117
118 END CASE;
119 END IF;
120 END PROCESS;
121
122 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_fft.all;
27 use lpp.fft_components.all;
28
29 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "cr�neau"
30
31 entity FFT is
32 generic(
33 Data_sz : integer := 16;
34 NbData : integer := 256);
35 port(
36 clkm : in std_logic;
37 rstn : in std_logic;
38 FifoIN_Empty : in std_logic_vector(4 downto 0);
39 FifoIN_Data : in std_logic_vector(79 downto 0);
40 FifoOUT_Full : in std_logic_vector(4 downto 0);
41 Load : out std_logic;
42 Read : out std_logic_vector(4 downto 0);
43 Write : out std_logic_vector(4 downto 0);
44 ReUse : out std_logic_vector(4 downto 0);
45 Data : out std_logic_vector(79 downto 0)
46 );
47 end entity;
48
49
50 architecture ar_FFT of FFT is
51
52 signal Drive_Write : std_logic;
53 signal Drive_DataRE : std_logic_vector(15 downto 0);
54 signal Drive_DataIM : std_logic_vector(15 downto 0);
55
56 signal Start : std_logic;
57 signal FFT_Load : std_logic;
58 signal FFT_Ready : std_logic;
59 signal FFT_Valid : std_logic;
60 signal FFT_DataRE : std_logic_vector(15 downto 0);
61 signal FFT_DataIM : std_logic_vector(15 downto 0);
62
63 signal Link_Read : std_logic;
64
65 begin
66
67 Start <= '0';
68 Load <= FFT_Load;
69
70 DRIVE : Driver_FFT
71 generic map(Data_sz,NbData)
72 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
73
74 FFT0 : CoreFFT
75 generic map(
76 LOGPTS => gLOGPTS,
77 LOGLOGPTS => gLOGLOGPTS,
78 WSIZE => gWSIZE,
79 TWIDTH => gTWIDTH,
80 DWIDTH => gDWIDTH,
81 TDWIDTH => gTDWIDTH,
82 RND_MODE => gRND_MODE,
83 SCALE_MODE => gSCALE_MODE,
84 PTS => gPTS,
85 HALFPTS => gHALFPTS,
86 inBuf_RWDLY => gInBuf_RWDLY)
87 port map(clkm,start,rstn,
88 Drive_Write, -- ifiD_valid
89 Link_Read, -- ifiRead_y
90 Drive_DataIM, -- ifiD_im
91 Drive_DataRE, -- ifiD_re
92 FFT_Load, -- ifoLoad
93 open, -- ifoPong
94 FFT_DataIM, -- ifoY_im
95 FFT_DataRE, -- ifoY_re
96 FFT_Valid, -- ifiY_valid
97 FFT_Ready); -- ifiY_rdy
98
99
100 LINK : Linker_FFT
101 generic map(Data_sz,NbData)
102 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
103
104
105 end architecture;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 ENTITY Linker_FFT IS
27 GENERIC(
28 Data_sz : INTEGER RANGE 1 TO 32 := 16;
29 NbData : INTEGER RANGE 1 TO 512 := 256
30 );
31 PORT(
32 clk : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34 Ready : IN STD_LOGIC; --
35 Valid : IN STD_LOGIC; --
36 Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --
37 Data_re : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --
38 Data_im : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --
39
40 Read : OUT STD_LOGIC; -- Link_Read
41 Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --
42 ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
43 DATA : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0)
44 );
45 END ENTITY;
46
47
48 ARCHITECTURE ar_Linker OF Linker_FFT IS
49
50 TYPE etat IS (eX, e0, e1, e2);
51 SIGNAL ect : etat;
52
53 SIGNAL DataTmp : STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0);
54
55 SIGNAL sRead : STD_LOGIC;
56 SIGNAL sReady : STD_LOGIC;
57
58 SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0;
59
60 BEGIN
61
62 PROCESS(clk, rstn)
63 BEGIN
64 IF(rstn = '0')then
65 ect <= e0;
66 sRead <= '0';
67 sReady <= '0';
68 Write <= (OTHERS => '1');
69 Reuse <= (OTHERS => '0');
70 FifoCpt <= 0;
71
72 ELSIF(clk'EVENT AND clk = '1')then
73 sReady <= Ready;
74
75 IF(sReady = '1' and Ready = '0')THEN
76 IF(FifoCpt = 4)THEN
77 FifoCpt <= 0;
78 ELSE
79 FifoCpt <= FifoCpt + 1;
80 END IF;
81 ELSIF(Ready = '1')then
82 sRead <= NOT sRead;
83 ELSE
84 sRead <= '0';
85 END IF;
86
87 CASE ect IS
88
89 WHEN e0 =>
90 Write(FifoCpt) <= '1';
91 IF(Valid = '1' and Full(FifoCpt) = '0')THEN
92 DataTmp <= Data_im;
93 DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= Data_re;
94 Write(FifoCpt) <= '0';
95 ect <= e1;
96 ELSIF(Full(FifoCpt) = '1')then
97 ReUse(FifoCpt) <= '1';
98 END IF;
99
100 WHEN e1 =>
101 DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= DataTmp;
102 ect <= e0;
103
104 WHEN OTHERS =>
105 NULL;
106
107 END CASE;
108 END IF;
109 END PROCESS;
110
111 Read <= sRead;
112
113 END ARCHITECTURE;
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1 -- Version: 9.1 SP5 9.1.5.1
2
3 library ieee;
4 use ieee.std_logic_1164.all;
5 library Axcelerator;
6 use Axcelerator.all;
7
8 entity actar is
9 port( DataA : in std_logic_vector(15 downto 0); DataB : in
10 std_logic_vector(15 downto 0); Mult : out
11 std_logic_vector(31 downto 0);Clock : in std_logic) ;
12 end actar;
13
14
15 architecture DEF_ARCH of actar is
16
17 component DF1
18 port(D, CLK : in std_logic := 'U'; Q : out std_logic) ;
19 end component;
20
21 component XOR2
22 port(A, B : in std_logic := 'U'; Y : out std_logic) ;
23 end component;
24
25 component AO6
26 port(A, B, C, D : in std_logic := 'U'; Y : out std_logic
27 ) ;
28 end component;
29
30 component FA1
31 port(A, B, CI : in std_logic := 'U'; CO, S : out
32 std_logic) ;
33 end component;
34
35 component MX2
36 port(A, B, S : in std_logic := 'U'; Y : out std_logic) ;
37 end component;
38
39 component ADD1
40 port(A, B, FCI : in std_logic := 'U'; S, FCO : out
41 std_logic) ;
42 end component;
43
44 component BUFF
45 port(A : in std_logic := 'U'; Y : out std_logic) ;
46 end component;
47
48 component HA1
49 port(A, B : in std_logic := 'U'; CO, S : out std_logic) ;
50 end component;
51
52 component OR3
53 port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
54 end component;
55
56 component AND3
57 port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
58 end component;
59
60 component AO16
61 port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
62 end component;
63
64 component AO1
65 port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
66 end component;
67
68 component AND2
69 port(A, B : in std_logic := 'U'; Y : out std_logic) ;
70 end component;
71
72 component FCINIT_BUFF
73 port(A : in std_logic := 'U'; FCO : out std_logic) ;
74 end component;
75
76 component AND2A
77 port(A, B : in std_logic := 'U'; Y : out std_logic) ;
78 end component;
79
80 component AOI1
81 port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
82 end component;
83
84 component FCEND_BUFF
85 port(FCI : in std_logic := 'U'; CO : out std_logic) ;
86 end component;
87
88 component VCC
89 port( Y : out std_logic);
90 end component;
91
92 component GND
93 port( Y : out std_logic);
94 end component;
95
96 signal S_0_net, S_1_net, S_2_net, S_3_net, S_4_net, S_5_net,
97 S_6_net, S_7_net, E_0_net, E_1_net, E_2_net, E_3_net,
98 E_4_net, E_5_net, E_6_net, E_7_net, EBAR, PP0_0_net,
99 PP0_1_net, PP0_2_net, PP0_3_net, PP0_4_net, PP0_5_net,
100 PP0_6_net, PP0_7_net, PP0_8_net, PP0_9_net, PP0_10_net,
101 PP0_11_net, PP0_12_net, PP0_13_net, PP0_14_net,
102 PP0_15_net, PP0_16_net, PP1_0_net, PP1_1_net, PP1_2_net,
103 PP1_3_net, PP1_4_net, PP1_5_net, PP1_6_net, PP1_7_net,
104 PP1_8_net, PP1_9_net, PP1_10_net, PP1_11_net, PP1_12_net,
105 PP1_13_net, PP1_14_net, PP1_15_net, PP1_16_net, PP2_0_net,
106 PP2_1_net, PP2_2_net, PP2_3_net, PP2_4_net, PP2_5_net,
107 PP2_6_net, PP2_7_net, PP2_8_net, PP2_9_net, PP2_10_net,
108 PP2_11_net, PP2_12_net, PP2_13_net, PP2_14_net,
109 PP2_15_net, PP2_16_net, PP3_0_net, PP3_1_net, PP3_2_net,
110 PP3_3_net, PP3_4_net, PP3_5_net, PP3_6_net, PP3_7_net,
111 PP3_8_net, PP3_9_net, PP3_10_net, PP3_11_net, PP3_12_net,
112 PP3_13_net, PP3_14_net, PP3_15_net, PP3_16_net, PP4_0_net,
113 PP4_1_net, PP4_2_net, PP4_3_net, PP4_4_net, PP4_5_net,
114 PP4_6_net, PP4_7_net, PP4_8_net, PP4_9_net, PP4_10_net,
115 PP4_11_net, PP4_12_net, PP4_13_net, PP4_14_net,
116 PP4_15_net, PP4_16_net, PP5_0_net, PP5_1_net, PP5_2_net,
117 PP5_3_net, PP5_4_net, PP5_5_net, PP5_6_net, PP5_7_net,
118 PP5_8_net, PP5_9_net, PP5_10_net, PP5_11_net, PP5_12_net,
119 PP5_13_net, PP5_14_net, PP5_15_net, PP5_16_net, PP6_0_net,
120 PP6_1_net, PP6_2_net, PP6_3_net, PP6_4_net, PP6_5_net,
121 PP6_6_net, PP6_7_net, PP6_8_net, PP6_9_net, PP6_10_net,
122 PP6_11_net, PP6_12_net, PP6_13_net, PP6_14_net,
123 PP6_15_net, PP6_16_net, PP7_0_net, PP7_1_net, PP7_2_net,
124 PP7_3_net, PP7_4_net, PP7_5_net, PP7_6_net, PP7_7_net,
125 PP7_8_net, PP7_9_net, PP7_10_net, PP7_11_net, PP7_12_net,
126 PP7_13_net, PP7_14_net, PP7_15_net, PP7_16_net,
127 SumA_0_net, SumA_1_net, SumA_2_net, SumA_3_net,
128 SumA_4_net, SumA_5_net, SumA_6_net, SumA_7_net,
129 SumA_8_net, SumA_9_net, SumA_10_net, SumA_11_net,
130 SumA_12_net, SumA_13_net, SumA_14_net, SumA_15_net,
131 SumA_16_net, SumA_17_net, SumA_18_net, SumA_19_net,
132 SumA_20_net, SumA_21_net, SumA_22_net, SumA_23_net,
133 SumA_24_net, SumA_25_net, SumA_26_net, SumA_27_net,
134 SumA_28_net, SumA_29_net, SumA_30_net, SumB_0_net,
135 SumB_1_net, SumB_2_net, SumB_3_net, SumB_4_net,
136 SumB_5_net, SumB_6_net, SumB_7_net, SumB_8_net,
137 SumB_9_net, SumB_10_net, SumB_11_net, SumB_12_net,
138 SumB_13_net, SumB_14_net, SumB_15_net, SumB_16_net,
139 SumB_17_net, SumB_18_net, SumB_19_net, SumB_20_net,
140 SumB_21_net, SumB_22_net, SumB_23_net, SumB_24_net,
141 SumB_25_net, SumB_26_net, SumB_27_net, SumB_28_net,
142 SumB_29_net, SumB_30_net, DF1_117_Q, DF1_114_Q, DF1_25_Q,
143 DF1_111_Q, DF1_143_Q, DF1_124_Q, DF1_18_Q, DF1_30_Q,
144 DF1_97_Q, DF1_90_Q, DF1_102_Q, DF1_63_Q, DF1_140_Q,
145 DF1_137_Q, DF1_45_Q, DF1_73_Q, DF1_23_Q, DF1_120_Q,
146 DF1_36_Q, DF1_130_Q, DF1_42_Q, DF1_8_Q, DF1_79_Q,
147 DF1_78_Q, DF1_135_Q, DF1_20_Q, DF1_112_Q, DF1_61_Q,
148 DF1_123_Q, DF1_70_Q, DF1_55_Q, DF1_28_Q, DF1_95_Q,
149 DF1_94_Q, DF1_2_Q, DF1_34_Q, DF1_125_Q, DF1_77_Q,
150 DF1_145_Q, DF1_88_Q, DF1_49_Q, DF1_17_Q, DF1_85_Q,
151 DF1_84_Q, DF1_147_Q, DF1_27_Q, DF1_115_Q, DF1_66_Q,
152 DF1_133_Q, DF1_76_Q, DF1_10_Q, DF1_127_Q, DF1_51_Q,
153 DF1_50_Q, DF1_107_Q, DF1_144_Q, DF1_81_Q, DF1_33_Q,
154 DF1_98_Q, DF1_43_Q, DF1_122_Q, DF1_96_Q, DF1_13_Q,
155 DF1_11_Q, DF1_67_Q, DF1_106_Q, DF1_48_Q, DF1_151_Q,
156 DF1_58_Q, DF1_6_Q, DF1_103_Q, DF1_64_Q, DF1_141_Q,
157 DF1_138_Q, DF1_46_Q, DF1_74_Q, DF1_24_Q, DF1_121_Q,
158 DF1_37_Q, DF1_131_Q, DF1_59_Q, DF1_31_Q, DF1_100_Q,
159 DF1_99_Q, DF1_5_Q, DF1_41_Q, DF1_132_Q, DF1_82_Q,
160 DF1_150_Q, DF1_91_Q, DF1_101_Q, DF1_62_Q, DF1_139_Q,
161 DF1_136_Q, DF1_44_Q, DF1_72_Q, DF1_22_Q, DF1_119_Q,
162 DF1_35_Q, DF1_129_Q, DF1_68_Q, DF1_118_Q, DF1_16_Q,
163 DF1_3_Q, DF1_86_Q, DF1_109_Q, DF1_60_Q, DF1_83_Q,
164 DF1_54_Q, DF1_53_Q, DF1_19_Q, DF1_69_Q, DF1_113_Q,
165 DF1_105_Q, DF1_38_Q, DF1_56_Q, DF1_12_Q, DF1_32_Q,
166 DF1_4_Q, DF1_1_Q, DF1_152_Q, DF1_52_Q, DF1_93_Q, DF1_80_Q,
167 DF1_14_Q, DF1_39_Q, DF1_146_Q, DF1_9_Q, DF1_134_Q,
168 DF1_126_Q, DF1_7_Q, DF1_57_Q, DF1_104_Q, DF1_89_Q,
169 DF1_26_Q, DF1_47_Q, DF1_0_Q, DF1_21_Q, DF1_148_Q,
170 DF1_142_Q, DF1_92_Q, DF1_149_Q, DF1_40_Q, DF1_29_Q,
171 DF1_110_Q, DF1_128_Q, DF1_87_Q, DF1_108_Q, DF1_75_Q,
172 DF1_71_Q, DF1_65_Q, DF1_116_Q, DF1_15_Q, HA1_13_S,
173 HA1_13_CO, FA1_94_S, FA1_94_CO, FA1_63_S, FA1_63_CO,
174 HA1_0_S, HA1_0_CO, FA1_71_S, FA1_71_CO, FA1_26_S,
175 FA1_26_CO, FA1_42_S, FA1_42_CO, FA1_24_S, FA1_24_CO,
176 HA1_12_S, HA1_12_CO, FA1_43_S, FA1_43_CO, FA1_90_S,
177 FA1_90_CO, HA1_6_S, HA1_6_CO, FA1_41_S, FA1_41_CO,
178 FA1_83_S, FA1_83_CO, HA1_9_S, HA1_9_CO, FA1_85_S,
179 FA1_85_CO, FA1_10_S, FA1_10_CO, HA1_2_S, HA1_2_CO,
180 FA1_67_S, FA1_67_CO, FA1_6_S, FA1_6_CO, HA1_1_S, HA1_1_CO,
181 FA1_86_S, FA1_86_CO, FA1_55_S, FA1_55_CO, FA1_3_S,
182 FA1_3_CO, HA1_8_S, HA1_8_CO, HA1_7_S, HA1_7_CO, FA1_30_S,
183 FA1_30_CO, FA1_29_S, FA1_29_CO, HA1_15_S, HA1_15_CO,
184 FA1_28_S, FA1_28_CO, FA1_14_S, FA1_14_CO, FA1_89_S,
185 FA1_89_CO, FA1_62_S, FA1_62_CO, FA1_5_S, FA1_5_CO,
186 FA1_12_S, FA1_12_CO, FA1_9_S, FA1_9_CO, FA1_38_S,
187 FA1_38_CO, FA1_37_S, FA1_37_CO, FA1_87_S, FA1_87_CO,
188 FA1_34_S, FA1_34_CO, FA1_44_S, FA1_44_CO, FA1_13_S,
189 FA1_13_CO, FA1_77_S, FA1_77_CO, FA1_33_S, FA1_33_CO,
190 FA1_40_S, FA1_40_CO, FA1_36_S, FA1_36_CO, FA1_61_S,
191 FA1_61_CO, FA1_60_S, FA1_60_CO, FA1_11_S, FA1_11_CO,
192 FA1_56_S, FA1_56_CO, FA1_27_S, FA1_27_CO, FA1_1_S,
193 FA1_1_CO, FA1_68_S, FA1_68_CO, FA1_18_S, FA1_18_CO,
194 FA1_22_S, FA1_22_CO, FA1_21_S, FA1_21_CO, FA1_51_S,
195 FA1_51_CO, FA1_50_S, FA1_50_CO, HA1_14_S, HA1_14_CO,
196 FA1_47_S, FA1_47_CO, HA1_10_S, HA1_10_CO, HA1_11_S,
197 HA1_11_CO, FA1_75_S, FA1_75_CO, FA1_31_S, FA1_31_CO,
198 FA1_35_S, FA1_35_CO, FA1_32_S, FA1_32_CO, FA1_58_S,
199 FA1_58_CO, FA1_57_S, FA1_57_CO, FA1_7_S, FA1_7_CO,
200 FA1_54_S, FA1_54_CO, FA1_25_S, FA1_25_CO, FA1_0_S,
201 FA1_0_CO, FA1_66_S, FA1_66_CO, FA1_15_S, FA1_15_CO,
202 FA1_20_S, FA1_20_CO, FA1_17_S, FA1_17_CO, FA1_49_S,
203 FA1_49_CO, FA1_48_S, FA1_48_CO, FA1_92_S, FA1_92_CO,
204 FA1_45_S, FA1_45_CO, FA1_70_S, FA1_70_CO, FA1_52_S,
205 FA1_52_CO, FA1_8_S, FA1_8_CO, FA1_65_S, FA1_65_CO,
206 HA1_5_S, HA1_5_CO, FA1_74_CO, FA1_74_S, HA1_3_CO, HA1_3_S,
207 FA1_78_CO, FA1_78_S, FA1_72_CO, FA1_72_S, HA1_4_CO,
208 HA1_4_S, FA1_73_CO, FA1_73_S, FA1_39_CO, FA1_39_S,
209 FA1_81_CO, FA1_81_S, FA1_2_CO, FA1_2_S, FA1_16_CO,
210 FA1_16_S, FA1_91_CO, FA1_91_S, FA1_93_CO, FA1_93_S,
211 FA1_88_CO, FA1_88_S, FA1_76_CO, FA1_76_S, FA1_82_CO,
212 FA1_82_S, FA1_95_CO, FA1_95_S, FA1_84_CO, FA1_84_S,
213 FA1_4_CO, FA1_4_S, FA1_46_CO, FA1_46_S, FA1_96_CO,
214 FA1_96_S, FA1_59_CO, FA1_59_S, FA1_80_CO, FA1_80_S,
215 FA1_69_CO, FA1_69_S, FA1_53_CO, FA1_53_S, FA1_79_CO,
216 FA1_79_S, FA1_64_CO, FA1_64_S, FA1_23_CO, FA1_23_S,
217 FA1_19_CO, FA1_19_S, BUF_29_Y, BUF_8_Y, BUF_21_Y,
218 BUF_35_Y, BUF_27_Y, BUF_25_Y, BUF_28_Y, BUF_4_Y, BUF_39_Y,
219 BUF_2_Y, BUF_45_Y, BUF_36_Y, BUF_7_Y, BUF_13_Y, BUF_5_Y,
220 BUF_44_Y, BUF_14_Y, BUF_19_Y, BUF_10_Y, BUF_38_Y,
221 BUF_43_Y, BUF_9_Y, BUF_42_Y, BUF_15_Y, BUF_24_Y, BUF_1_Y,
222 BUF_16_Y, BUF_32_Y, BUF_0_Y, BUF_31_Y, BUF_46_Y, BUF_40_Y,
223 BUF_47_Y, BUF_41_Y, XOR2_24_Y, XOR2_19_Y, AO1_4_Y,
224 XOR2_6_Y, AO16_2_Y, AO6_57_Y, AO6_107_Y, AO6_104_Y,
225 AO6_82_Y, MX2_3_Y, AO6_115_Y, AO6_13_Y, AO6_42_Y,
226 XOR2_29_Y, AO16_4_Y, AO6_25_Y, AO6_36_Y, AO6_65_Y,
227 AND2_6_Y, AO6_28_Y, AO6_50_Y, AO6_72_Y, AO6_60_Y,
228 AO6_52_Y, OR3_3_Y, AND3_5_Y, BUF_17_Y, BUF_6_Y, XOR2_1_Y,
229 XOR2_7_Y, AO1_6_Y, XOR2_3_Y, AO16_8_Y, AO6_91_Y, AO6_93_Y,
230 AO6_56_Y, AO6_54_Y, MX2_5_Y, AO6_74_Y, AO6_102_Y, AO6_3_Y,
231 XOR2_8_Y, AO16_5_Y, AO6_44_Y, AO6_0_Y, AO6_97_Y, AND2_3_Y,
232 AO6_40_Y, AO6_67_Y, AO6_64_Y, AO6_90_Y, AO6_55_Y, OR3_0_Y,
233 AND3_3_Y, BUF_18_Y, BUF_11_Y, XOR2_27_Y, XOR2_13_Y,
234 AO1_5_Y, XOR2_4_Y, AO16_3_Y, AO6_23_Y, AO6_113_Y,
235 AO6_22_Y, AO6_1_Y, MX2_1_Y, AO6_78_Y, AO6_84_Y, AO6_33_Y,
236 XOR2_25_Y, AO16_13_Y, AO6_105_Y, AO6_46_Y, AO6_61_Y,
237 AND2_2_Y, AO6_68_Y, AO6_35_Y, AO6_29_Y, AO6_98_Y,
238 AO6_66_Y, OR3_2_Y, AND3_6_Y, BUF_26_Y, BUF_23_Y,
239 XOR2_16_Y, XOR2_26_Y, AND2A_1_Y, AO6_88_Y, AO6_51_Y,
240 AO6_48_Y, AO6_41_Y, MX2_2_Y, AO6_30_Y, AO6_92_Y, AO6_11_Y,
241 AND2A_0_Y, AO6_76_Y, AO6_73_Y, AO6_114_Y, AND2_0_Y,
242 AO6_63_Y, AO6_32_Y, AO6_45_Y, AO6_38_Y, AO6_4_Y, OR3_1_Y,
243 AND3_1_Y, BUF_22_Y, BUF_20_Y, XOR2_12_Y, XOR2_11_Y,
244 AO1_3_Y, XOR2_18_Y, AO16_6_Y, AO6_69_Y, AO6_21_Y,
245 AO6_34_Y, AO6_6_Y, MX2_4_Y, AO6_95_Y, AO6_101_Y,
246 AO6_117_Y, XOR2_2_Y, AO16_12_Y, AO6_109_Y, AO6_7_Y,
247 AO6_14_Y, AND2_7_Y, AO6_31_Y, AO6_111_Y, AO6_118_Y,
248 AO6_2_Y, AO6_96_Y, OR3_4_Y, AND3_7_Y, BUF_37_Y, BUF_33_Y,
249 XOR2_0_Y, XOR2_20_Y, AO1_0_Y, XOR2_5_Y, AO16_0_Y,
250 AO6_75_Y, AO6_53_Y, AO6_20_Y, AO6_49_Y, MX2_6_Y, AO6_94_Y,
251 AO6_87_Y, AO6_37_Y, XOR2_10_Y, AO16_1_Y, AO6_89_Y,
252 AO6_83_Y, AO6_10_Y, AND2_4_Y, AO6_85_Y, AO6_71_Y,
253 AO6_58_Y, AO6_26_Y, AO6_112_Y, OR3_7_Y, AND3_0_Y,
254 BUF_12_Y, BUF_3_Y, XOR2_14_Y, XOR2_15_Y, AO1_1_Y,
255 XOR2_28_Y, AO16_7_Y, AO6_15_Y, AO6_59_Y, AO6_12_Y,
256 AO6_86_Y, MX2_7_Y, AO6_8_Y, AO6_99_Y, AO6_100_Y,
257 XOR2_17_Y, AO16_11_Y, AO6_103_Y, AO6_43_Y, AO6_16_Y,
258 AND2_5_Y, AO6_110_Y, AO6_62_Y, AO6_108_Y, AO6_70_Y,
259 AO6_18_Y, OR3_5_Y, AND3_4_Y, BUF_34_Y, BUF_30_Y, XOR2_9_Y,
260 XOR2_22_Y, AO1_2_Y, XOR2_23_Y, AO16_9_Y, AO6_79_Y,
261 AO6_5_Y, AO6_119_Y, AO6_116_Y, MX2_0_Y, AO6_39_Y,
262 AO6_81_Y, AO6_17_Y, XOR2_21_Y, AO16_10_Y, AO6_9_Y,
263 AO6_77_Y, AO6_24_Y, AND2_1_Y, AO6_80_Y, AO6_27_Y,
264 AO6_106_Y, AO6_47_Y, AO6_19_Y, OR3_6_Y, AND3_2_Y,
265 FCEND_BUFF_0_CO, FCINIT_BUFF_0_FCO, ADD1_Mult_1_FCO,
266 ADD1_Mult_2_FCO, ADD1_Mult_3_FCO, ADD1_Mult_4_FCO,
267 ADD1_Mult_5_FCO, ADD1_Mult_6_FCO, ADD1_Mult_7_FCO,
268 ADD1_Mult_8_FCO, ADD1_Mult_9_FCO, ADD1_Mult_10_FCO,
269 ADD1_Mult_11_FCO, ADD1_Mult_12_FCO, ADD1_Mult_13_FCO,
270 ADD1_Mult_14_FCO, ADD1_Mult_15_FCO, ADD1_Mult_16_FCO,
271 ADD1_Mult_17_FCO, ADD1_Mult_18_FCO, ADD1_Mult_19_FCO,
272 ADD1_Mult_20_FCO, ADD1_Mult_21_FCO, ADD1_Mult_22_FCO,
273 ADD1_Mult_23_FCO, ADD1_Mult_24_FCO, ADD1_Mult_25_FCO,
274 ADD1_Mult_26_FCO, ADD1_Mult_27_FCO, ADD1_Mult_28_FCO,
275 ADD1_Mult_29_FCO, ADD1_Mult_30_FCO, ADD1_Mult_31_FCO,
276 VCC_1_net, GND_1_net : std_logic ;
277 begin
278
279 VCC_2_net : VCC port map(Y => VCC_1_net);
280 GND_2_net : GND port map(Y => GND_1_net);
281 DF1_SumB_0_inst : DF1
282 port map(D => DF1_0_Q, CLK => Clock, Q => SumB_0_net);
283 XOR2_PP7_9_inst : XOR2
284 port map(A => AO6_6_Y, B => BUF_20_Y, Y => PP7_9_net);
285 DF1_145 : DF1
286 port map(D => PP2_4_net, CLK => Clock, Q => DF1_145_Q);
287 DF1_SumA_17_inst : DF1
288 port map(D => FA1_93_CO, CLK => Clock, Q => SumA_17_net);
289 AO6_7 : AO6
290 port map(A => BUF_4_Y, B => AO16_12_Y, C => BUF_2_Y, D =>
291 XOR2_2_Y, Y => AO6_7_Y);
292 DF1_60 : DF1
293 port map(D => PP6_4_net, CLK => Clock, Q => DF1_60_Q);
294 FA1_33 : FA1
295 port map(A => FA1_90_CO, B => HA1_6_CO, CI => FA1_83_S,
296 CO => FA1_33_CO, S => FA1_33_S);
297 FA1_46 : FA1
298 port map(A => HA1_11_CO, B => DF1_127_Q, CI => FA1_75_S,
299 CO => FA1_46_CO, S => FA1_46_S);
300 DF1_SumA_6_inst : DF1
301 port map(D => FA1_46_CO, CLK => Clock, Q => SumA_6_net);
302 MX2_PP1_16_inst : MX2
303 port map(A => MX2_1_Y, B => AO1_5_Y, S => AO16_3_Y, Y =>
304 PP1_16_net);
305 DF1_65 : DF1
306 port map(D => E_6_net, CLK => Clock, Q => DF1_65_Q);
307 ADD1_Mult_23_inst : ADD1
308 port map(A => SumA_22_net, B => SumB_22_net, FCI =>
309 ADD1_Mult_22_FCO, S => Mult(23), FCO => ADD1_Mult_23_FCO);
310 DF1_SumB_6_inst : DF1
311 port map(D => FA1_81_S, CLK => Clock, Q => SumB_6_net);
312 FA1_86 : FA1
313 port map(A => DF1_106_Q, B => VCC_1_net, CI => DF1_72_Q,
314 CO => FA1_86_CO, S => FA1_86_S);
315 DF1_SumB_13_inst : DF1
316 port map(D => FA1_96_S, CLK => Clock, Q => SumB_13_net);
317 FA1_44 : FA1
318 port map(A => FA1_71_CO, B => HA1_12_S, CI => FA1_42_S,
319 CO => FA1_44_CO, S => FA1_44_S);
320 FA1_9 : FA1
321 port map(A => DF1_40_Q, B => DF1_150_Q, CI => FA1_94_CO,
322 CO => FA1_9_CO, S => FA1_9_S);
323 FA1_90 : FA1
324 port map(A => DF1_96_Q, B => DF1_28_Q, CI => DF1_62_Q,
325 CO => FA1_90_CO, S => FA1_90_S);
326 DF1_SumA_22_inst : DF1
327 port map(D => FA1_74_CO, CLK => Clock, Q => SumA_22_net);
328 BUF_36 : BUFF
329 port map(A => DataA(5), Y => BUF_36_Y);
330 AO6_30 : AO6
331 port map(A => BUF_16_Y, B => AND2A_1_Y, C => BUF_0_Y, D =>
332 DataB(0), Y => AO6_30_Y);
333 DF1_SumB_4_inst : DF1
334 port map(D => FA1_82_S, CLK => Clock, Q => SumB_4_net);
335 XOR2_PP0_13_inst : XOR2
336 port map(A => AO6_51_Y, B => BUF_23_Y, Y => PP0_13_net);
337 XOR2_PP5_4_inst : XOR2
338 port map(A => AO6_36_Y, B => BUF_47_Y, Y => PP5_4_net);
339 AO6_8 : AO6
340 port map(A => BUF_16_Y, B => AO16_7_Y, C => BUF_0_Y, D =>
341 XOR2_28_Y, Y => AO6_8_Y);
342 FA1_84 : FA1
343 port map(A => DF1_130_Q, B => DF1_143_Q, CI => DF1_2_Q,
344 CO => FA1_84_CO, S => FA1_84_S);
345 HA1_11 : HA1
346 port map(A => DF1_42_Q, B => DF1_124_Q, CO => HA1_11_CO,
347 S => HA1_11_S);
348 XOR2_PP6_6_inst : XOR2
349 port map(A => AO6_44_Y, B => BUF_17_Y, Y => PP6_6_net);
350 AO6_25 : AO6
351 port map(A => BUF_36_Y, B => AO16_4_Y, C => BUF_13_Y, D =>
352 XOR2_29_Y, Y => AO6_25_Y);
353 FA1_63 : FA1
354 port map(A => DF1_123_Q, B => DF1_137_Q, CI => DF1_84_Q,
355 CO => FA1_63_CO, S => FA1_63_S);
356 AO6_51 : AO6
357 port map(A => BUF_24_Y, B => AND2A_1_Y, C => BUF_16_Y, D =>
358 DataB(0), Y => AO6_51_Y);
359 FA1_75 : FA1
360 port map(A => DF1_8_Q, B => DF1_18_Q, CI => DF1_125_Q,
361 CO => FA1_75_CO, S => FA1_75_S);
362 AO6_16 : AO6
363 port map(A => BUF_29_Y, B => AO16_11_Y, C => BUF_21_Y, D =>
364 XOR2_17_Y, Y => AO6_16_Y);
365 XOR2_PP6_4_inst : XOR2
366 port map(A => AO6_0_Y, B => BUF_17_Y, Y => PP6_4_net);
367 XOR2_PP6_10_inst : XOR2
368 port map(A => AO6_56_Y, B => BUF_6_Y, Y => PP6_10_net);
369 XOR2_PP5_13_inst : XOR2
370 port map(A => AO6_107_Y, B => BUF_41_Y, Y => PP5_13_net);
371 DF1_SumA_30_inst : DF1
372 port map(D => DF1_116_Q, CLK => Clock, Q => SumA_30_net);
373 DF1_88 : DF1
374 port map(D => PP2_5_net, CLK => Clock, Q => DF1_88_Q);
375 OR3_6 : OR3
376 port map(A => DataB(3), B => DataB(4), C => DataB(5), Y =>
377 OR3_6_Y);
378 DF1_SumB_5_inst : DF1
379 port map(D => FA1_46_S, CLK => Clock, Q => SumB_5_net);
380 FA1_26 : FA1
381 port map(A => DF1_43_Q, B => DF1_70_Q, CI => DF1_91_Q,
382 CO => FA1_26_CO, S => FA1_26_S);
383 BUF_43 : BUFF
384 port map(A => DataA(10), Y => BUF_43_Y);
385 DF1_134 : DF1
386 port map(D => PP7_9_net, CLK => Clock, Q => DF1_134_Q);
387 DF1_13 : DF1
388 port map(D => PP3_11_net, CLK => Clock, Q => DF1_13_Q);
389 ADD1_Mult_28_inst : ADD1
390 port map(A => SumA_27_net, B => SumB_27_net, FCI =>
391 ADD1_Mult_27_FCO, S => Mult(28), FCO => ADD1_Mult_28_FCO);
392 XOR2_PP2_4_inst : XOR2
393 port map(A => AO6_77_Y, B => BUF_34_Y, Y => PP2_4_net);
394 FA1_24 : FA1
395 port map(A => DF1_122_Q, B => DF1_55_Q, CI => DF1_101_Q,
396 CO => FA1_24_CO, S => FA1_24_S);
397 MX2_1 : MX2
398 port map(A => BUF_11_Y, B => XOR2_13_Y, S => XOR2_4_Y, Y =>
399 MX2_1_Y);
400 ADD1_Mult_6_inst : ADD1
401 port map(A => SumA_5_net, B => SumB_5_net, FCI =>
402 ADD1_Mult_5_FCO, S => Mult(6), FCO => ADD1_Mult_6_FCO);
403 AO6_35 : AO6
404 port map(A => BUF_39_Y, B => AO16_13_Y, C => BUF_45_Y, D =>
405 XOR2_25_Y, Y => AO6_35_Y);
406 AO6_74 : AO6
407 port map(A => BUF_32_Y, B => AO16_8_Y, C => BUF_31_Y, D =>
408 XOR2_3_Y, Y => AO6_74_Y);
409 DF1_104 : DF1
410 port map(D => PP7_13_net, CLK => Clock, Q => DF1_104_Q);
411 XOR2_PP2_11_inst : XOR2
412 port map(A => AO6_81_Y, B => BUF_30_Y, Y => PP2_11_net);
413 DF1_10 : DF1
414 port map(D => PP2_16_net, CLK => Clock, Q => DF1_10_Q);
415 DF1_33 : DF1
416 port map(D => PP3_6_net, CLK => Clock, Q => DF1_33_Q);
417 AO6_108 : AO6
418 port map(A => BUF_21_Y, B => AO16_11_Y, C => BUF_27_Y, D =>
419 XOR2_17_Y, Y => AO6_108_Y);
420 FA1_51 : FA1
421 port map(A => DF1_105_Q, B => DF1_99_Q, CI => HA1_8_CO,
422 CO => FA1_51_CO, S => FA1_51_S);
423 XOR2_PP1_15_inst : XOR2
424 port map(A => AO6_23_Y, B => BUF_11_Y, Y => PP1_15_net);
425 DF1_0 : DF1
426 port map(D => S_0_net, CLK => Clock, Q => DF1_0_Q);
427 DF1_9 : DF1
428 port map(D => PP7_8_net, CLK => Clock, Q => DF1_9_Q);
429 AO6_67 : AO6
430 port map(A => BUF_2_Y, B => AO16_5_Y, C => BUF_36_Y, D =>
431 XOR2_8_Y, Y => AO6_67_Y);
432 BUF_15 : BUFF
433 port map(A => DataA(11), Y => BUF_15_Y);
434 AO6_2 : AO6
435 port map(A => BUF_44_Y, B => AO16_12_Y, C => BUF_19_Y, D =>
436 XOR2_2_Y, Y => AO6_2_Y);
437 DF1_15 : DF1
438 port map(D => EBAR, CLK => Clock, Q => DF1_15_Q);
439 DF1_72 : DF1
440 port map(D => PP5_10_net, CLK => Clock, Q => DF1_72_Q);
441 DF1_41 : DF1
442 port map(D => PP5_0_net, CLK => Clock, Q => DF1_41_Q);
443 FA1_57 : FA1
444 port map(A => FA1_28_CO, B => FA1_14_CO, CI => FA1_62_S,
445 CO => FA1_57_CO, S => FA1_57_S);
446 BUF_25 : BUFF
447 port map(A => DataA(2), Y => BUF_25_Y);
448 DF1_30 : DF1
449 port map(D => PP0_7_net, CLK => Clock, Q => DF1_30_Q);
450 XOR2_PP4_7_inst : XOR2
451 port map(A => AO6_85_Y, B => BUF_37_Y, Y => PP4_7_net);
452 AO6_84 : AO6
453 port map(A => BUF_43_Y, B => AO16_3_Y, C => BUF_42_Y, D =>
454 XOR2_4_Y, Y => AO6_84_Y);
455 FA1_0 : FA1
456 port map(A => FA1_37_CO, B => FA1_87_CO, CI => FA1_44_S,
457 CO => FA1_0_CO, S => FA1_0_S);
458 DF1_47 : DF1
459 port map(D => PP7_16_net, CLK => Clock, Q => DF1_47_Q);
460 FA1_15 : FA1
461 port map(A => FA1_13_CO, B => FA1_77_CO, CI => FA1_40_S,
462 CO => FA1_15_CO, S => FA1_15_S);
463 FA1_36 : FA1
464 port map(A => FA1_83_CO, B => HA1_9_CO, CI => FA1_10_S,
465 CO => FA1_36_CO, S => FA1_36_S);
466 XOR2_24 : XOR2
467 port map(A => AND2_6_Y, B => BUF_47_Y, Y => XOR2_24_Y);
468 DF1_35 : DF1
469 port map(D => PP5_13_net, CLK => Clock, Q => DF1_35_Q);
470 AO6_68 : AO6
471 port map(A => BUF_7_Y, B => AO16_13_Y, C => BUF_5_Y, D =>
472 XOR2_25_Y, Y => AO6_68_Y);
473 XOR2_PP2_14_inst : XOR2
474 port map(A => AO6_39_Y, B => BUF_30_Y, Y => PP2_14_net);
475 FA1_34 : FA1
476 port map(A => FA1_26_CO, B => DF1_29_Q, CI => FA1_24_S,
477 CO => FA1_34_CO, S => FA1_34_S);
478 AO6_79 : AO6
479 port map(A => BUF_0_Y, B => AO16_9_Y, C => BUF_46_Y, D =>
480 XOR2_23_Y, Y => AO6_79_Y);
481 BUF_16 : BUFF
482 port map(A => DataA(13), Y => BUF_16_Y);
483 DF1_SumA_7_inst : DF1
484 port map(D => FA1_81_CO, CLK => Clock, Q => SumA_7_net);
485 OR3_4 : OR3
486 port map(A => DataB(13), B => DataB(14), C => DataB(15),
487 Y => OR3_4_Y);
488 MX2_0 : MX2
489 port map(A => BUF_30_Y, B => XOR2_22_Y, S => XOR2_23_Y,
490 Y => MX2_0_Y);
491 AO6_3 : AO6
492 port map(A => BUF_15_Y, B => AO16_8_Y, C => BUF_1_Y, D =>
493 XOR2_3_Y, Y => AO6_3_Y);
494 BUF_26 : BUFF
495 port map(A => DataB(1), Y => BUF_26_Y);
496 DF1_SumA_20_inst : DF1
497 port map(D => FA1_2_CO, CLK => Clock, Q => SumA_20_net);
498 AO6_115 : AO6
499 port map(A => BUF_32_Y, B => AO16_2_Y, C => BUF_31_Y, D =>
500 XOR2_6_Y, Y => AO6_115_Y);
501 FA1_66 : FA1
502 port map(A => FA1_34_CO, B => FA1_44_CO, CI => FA1_77_S,
503 CO => FA1_66_CO, S => FA1_66_S);
504 FA1_45 : FA1
505 port map(A => FA1_18_CO, B => FA1_22_CO, CI => FA1_51_S,
506 CO => FA1_45_CO, S => FA1_45_S);
507 AO6_103 : AO6
508 port map(A => BUF_45_Y, B => AO16_11_Y, C => BUF_7_Y, D =>
509 XOR2_17_Y, Y => AO6_103_Y);
510 AO6_89 : AO6
511 port map(A => BUF_36_Y, B => AO16_1_Y, C => BUF_13_Y, D =>
512 XOR2_10_Y, Y => AO6_89_Y);
513 DF1_SumB_27_inst : DF1
514 port map(D => FA1_19_S, CLK => Clock, Q => SumB_27_net);
515 DF1_53 : DF1
516 port map(D => PP6_7_net, CLK => Clock, Q => DF1_53_Q);
517 HA1_8 : HA1
518 port map(A => DF1_151_Q, B => VCC_1_net, CO => HA1_8_CO,
519 S => HA1_8_S);
520 DF1_SumA_25_inst : DF1
521 port map(D => FA1_69_CO, CLK => Clock, Q => SumA_25_net);
522 FA1_85 : FA1
523 port map(A => DF1_133_Q, B => DF1_15_Q, CI => DF1_37_Q,
524 CO => FA1_85_CO, S => FA1_85_S);
525 FA1_64 : FA1
526 port map(A => FA1_35_CO, B => FA1_29_S, CI => FA1_32_S,
527 CO => FA1_64_CO, S => FA1_64_S);
528 XOR2_PP7_11_inst : XOR2
529 port map(A => AO6_101_Y, B => BUF_20_Y, Y => PP7_11_net);
530 XOR2_PP5_1_inst : XOR2
531 port map(A => AO6_65_Y, B => BUF_47_Y, Y => PP5_1_net);
532 DF1_50 : DF1
533 port map(D => PP3_2_net, CLK => Clock, Q => DF1_50_Q);
534 XOR2_PP4_10_inst : XOR2
535 port map(A => AO6_20_Y, B => BUF_33_Y, Y => PP4_10_net);
536 AO6_24 : AO6
537 port map(A => BUF_29_Y, B => AO16_10_Y, C => BUF_21_Y, D =>
538 XOR2_21_Y, Y => AO6_24_Y);
539 XOR2_PP3_11_inst : XOR2
540 port map(A => AO6_99_Y, B => BUF_3_Y, Y => PP3_11_net);
541 XOR2_9 : XOR2
542 port map(A => AND2_1_Y, B => BUF_34_Y, Y => XOR2_9_Y);
543 XOR2_25 : XOR2
544 port map(A => DataB(1), B => DataB(2), Y => XOR2_25_Y);
545 DF1_24 : DF1
546 port map(D => PP4_8_net, CLK => Clock, Q => DF1_24_Q);
547 DF1_55 : DF1
548 port map(D => PP1_13_net, CLK => Clock, Q => DF1_55_Q);
549 FA1_7 : FA1
550 port map(A => FA1_89_CO, B => FA1_62_CO, CI => FA1_12_S,
551 CO => FA1_7_CO, S => FA1_7_S);
552 AND3_0 : AND3
553 port map(A => DataB(7), B => DataB(8), C => DataB(9), Y =>
554 AND3_0_Y);
555 FA1_70 : FA1
556 port map(A => FA1_51_CO, B => HA1_14_S, CI => FA1_21_CO,
557 CO => FA1_70_CO, S => FA1_70_S);
558 XOR2_PP1_1_inst : XOR2
559 port map(A => AO6_61_Y, B => BUF_18_Y, Y => PP1_1_net);
560 AO16_4 : AO16
561 port map(A => DataB(9), B => DataB(10), C => BUF_47_Y, Y =>
562 AO16_4_Y);
563 DF1_49 : DF1
564 port map(D => PP2_6_net, CLK => Clock, Q => DF1_49_Q);
565 MX2_7 : MX2
566 port map(A => BUF_3_Y, B => XOR2_15_Y, S => XOR2_28_Y, Y =>
567 MX2_7_Y);
568 DF1_SumB_16_inst : DF1
569 port map(D => FA1_93_S, CLK => Clock, Q => SumB_16_net);
570 HA1_13 : HA1
571 port map(A => DF1_112_Q, B => DF1_63_Q, CO => HA1_13_CO,
572 S => HA1_13_S);
573 FA1_25 : FA1
574 port map(A => FA1_9_CO, B => FA1_38_CO, CI => FA1_87_S,
575 CO => FA1_25_CO, S => FA1_25_S);
576 XOR2_PP7_14_inst : XOR2
577 port map(A => AO6_95_Y, B => BUF_20_Y, Y => PP7_14_net);
578 DF1_86 : DF1
579 port map(D => PP6_2_net, CLK => Clock, Q => DF1_86_Q);
580 AO1_3 : AO1
581 port map(A => XOR2_11_Y, B => OR3_4_Y, C => AND3_7_Y, Y =>
582 AO1_3_Y);
583 AND3_7 : AND3
584 port map(A => DataB(13), B => DataB(14), C => DataB(15),
585 Y => AND3_7_Y);
586 DF1_126 : DF1
587 port map(D => PP7_10_net, CLK => Clock, Q => DF1_126_Q);
588 OR3_0 : OR3
589 port map(A => DataB(11), B => DataB(12), C => DataB(13),
590 Y => OR3_0_Y);
591 MX2_6 : MX2
592 port map(A => BUF_33_Y, B => XOR2_20_Y, S => XOR2_5_Y, Y =>
593 MX2_6_Y);
594 AO6_34 : AO6
595 port map(A => BUF_38_Y, B => AO16_6_Y, C => BUF_9_Y, D =>
596 XOR2_18_Y, Y => AO6_34_Y);
597 XOR2_PP3_14_inst : XOR2
598 port map(A => AO6_8_Y, B => BUF_3_Y, Y => PP3_14_net);
599 AO16_1 : AO16
600 port map(A => DataB(7), B => DataB(8), C => BUF_37_Y, Y =>
601 AO16_1_Y);
602 ADD1_Mult_10_inst : ADD1
603 port map(A => SumA_9_net, B => SumB_9_net, FCI =>
604 ADD1_Mult_9_FCO, S => Mult(10), FCO => ADD1_Mult_10_FCO);
605 AO6_29 : AO6
606 port map(A => BUF_21_Y, B => AO16_13_Y, C => BUF_27_Y, D =>
607 XOR2_25_Y, Y => AO6_29_Y);
608 XOR2_PP0_12_inst : XOR2
609 port map(A => AO6_11_Y, B => BUF_23_Y, Y => PP0_12_net);
610 DF1_SumB_18_inst : DF1
611 port map(D => FA1_79_S, CLK => Clock, Q => SumB_18_net);
612 AO1_0 : AO1
613 port map(A => XOR2_20_Y, B => OR3_7_Y, C => AND3_0_Y, Y =>
614 AO1_0_Y);
615 DF1_SumB_7_inst : DF1
616 port map(D => FA1_80_S, CLK => Clock, Q => SumB_7_net);
617 DF1_149 : DF1
618 port map(D => S_5_net, CLK => Clock, Q => DF1_149_Q);
619 DF1_SumB_8_inst : DF1
620 port map(D => FA1_64_S, CLK => Clock, Q => SumB_8_net);
621 ADD1_Mult_16_inst : ADD1
622 port map(A => SumA_15_net, B => SumB_15_net, FCI =>
623 ADD1_Mult_15_FCO, S => Mult(16), FCO => ADD1_Mult_16_FCO);
624 AO16_7 : AO16
625 port map(A => DataB(5), B => DataB(6), C => BUF_3_Y, Y =>
626 AO16_7_Y);
627 DF1_64 : DF1
628 port map(D => PP4_3_net, CLK => Clock, Q => DF1_64_Q);
629 XOR2_18 : XOR2
630 port map(A => DataB(13), B => DataB(14), Y => XOR2_18_Y);
631 XOR2_PP5_12_inst : XOR2
632 port map(A => AO6_42_Y, B => BUF_41_Y, Y => PP5_12_net);
633 DF1_117 : DF1
634 port map(D => PP0_0_net, CLK => Clock, Q => DF1_117_Q);
635 XOR2_20 : XOR2
636 port map(A => BUF_40_Y, B => DataB(9), Y => XOR2_20_Y);
637 DF1_SumA_12_inst : DF1
638 port map(D => FA1_76_CO, CLK => Clock, Q => SumA_12_net);
639 FA1_1 : FA1
640 port map(A => DF1_146_Q, B => DF1_22_Q, CI => FA1_86_CO,
641 CO => FA1_1_CO, S => FA1_1_S);
642 FA1_35 : FA1
643 port map(A => DF1_58_Q, B => DF1_50_Q, CI => HA1_7_CO,
644 CO => FA1_35_CO, S => FA1_35_S);
645 FA1_53 : FA1
646 port map(A => FA1_49_CO, B => FA1_1_S, CI => FA1_48_S,
647 CO => FA1_53_CO, S => FA1_53_S);
648 MX2_PP3_16_inst : MX2
649 port map(A => MX2_7_Y, B => AO1_1_Y, S => AO16_7_Y, Y =>
650 PP3_16_net);
651 FA1_10 : FA1
652 port map(A => DF1_11_Q, B => DF1_94_Q, CI => DF1_136_Q,
653 CO => FA1_10_CO, S => FA1_10_S);
654 AO6_39 : AO6
655 port map(A => BUF_16_Y, B => AO16_9_Y, C => BUF_0_Y, D =>
656 XOR2_23_Y, Y => AO6_39_Y);
657 ADD1_Mult_30_inst : ADD1
658 port map(A => SumA_29_net, B => SumB_29_net, FCI =>
659 ADD1_Mult_29_FCO, S => Mult(30), FCO => ADD1_Mult_30_FCO);
660 AO6_76 : AO6
661 port map(A => BUF_45_Y, B => AND2A_0_Y, C => BUF_7_Y, D =>
662 DataB(0), Y => AO6_76_Y);
663 BUF_44 : BUFF
664 port map(A => DataA(7), Y => BUF_44_Y);
665 HA1_S_6_inst : HA1
666 port map(A => XOR2_1_Y, B => DataB(13), CO => S_6_net, S =>
667 PP6_0_net);
668 DF1_28 : DF1
669 port map(D => PP1_14_net, CLK => Clock, Q => DF1_28_Q);
670 DF1_93 : DF1
671 port map(D => PP7_3_net, CLK => Clock, Q => DF1_93_Q);
672 AND2_4 : AND2
673 port map(A => XOR2_10_Y, B => BUF_8_Y, Y => AND2_4_Y);
674 AO6_61 : AO6
675 port map(A => BUF_29_Y, B => AO16_13_Y, C => BUF_21_Y, D =>
676 XOR2_25_Y, Y => AO6_61_Y);
677 DF1_131 : DF1
678 port map(D => PP4_11_net, CLK => Clock, Q => DF1_131_Q);
679 MX2_PP6_16_inst : MX2
680 port map(A => MX2_5_Y, B => AO1_6_Y, S => AO16_8_Y, Y =>
681 PP6_16_net);
682 XOR2_PP7_8_inst : XOR2
683 port map(A => AO6_2_Y, B => BUF_22_Y, Y => PP7_8_net);
684 ADD1_Mult_13_inst : ADD1
685 port map(A => SumA_12_net, B => SumB_12_net, FCI =>
686 ADD1_Mult_12_FCO, S => Mult(13), FCO => ADD1_Mult_13_FCO);
687 AND2_0 : AND2
688 port map(A => DataB(0), B => BUF_29_Y, Y => AND2_0_Y);
689 DF1_90 : DF1
690 port map(D => PP0_9_net, CLK => Clock, Q => DF1_90_Q);
691 AO6_86 : AO6
692 port map(A => BUF_14_Y, B => AO16_7_Y, C => BUF_10_Y, D =>
693 XOR2_28_Y, Y => AO6_86_Y);
694 DF1_110 : DF1
695 port map(D => E_0_net, CLK => Clock, Q => DF1_110_Q);
696 FA1_65 : FA1
697 port map(A => DF1_32_Q, B => DF1_71_Q, CI => DF1_104_Q,
698 CO => FA1_65_CO, S => FA1_65_S);
699 BUF_38 : BUFF
700 port map(A => DataA(9), Y => BUF_38_Y);
701 FA1_4 : FA1
702 port map(A => FA1_15_CO, B => FA1_36_S, CI => FA1_20_S,
703 CO => FA1_4_CO, S => FA1_4_S);
704 AO6_90 : AO6
705 port map(A => BUF_44_Y, B => AO16_5_Y, C => BUF_19_Y, D =>
706 XOR2_8_Y, Y => AO6_90_Y);
707 AND2_6 : AND2
708 port map(A => XOR2_29_Y, B => BUF_8_Y, Y => AND2_6_Y);
709 XOR2_PP6_13_inst : XOR2
710 port map(A => AO6_93_Y, B => BUF_6_Y, Y => PP6_13_net);
711 DF1_101 : DF1
712 port map(D => PP5_5_net, CLK => Clock, Q => DF1_101_Q);
713 FA1_40 : FA1
714 port map(A => FA1_43_CO, B => HA1_9_S, CI => FA1_41_S,
715 CO => FA1_40_CO, S => FA1_40_S);
716 AO6_102 : AO6
717 port map(A => BUF_9_Y, B => AO16_8_Y, C => BUF_15_Y, D =>
718 XOR2_3_Y, Y => AO6_102_Y);
719 DF1_95 : DF1
720 port map(D => PP1_15_net, CLK => Clock, Q => DF1_95_Q);
721 DF1_138 : DF1
722 port map(D => PP4_5_net, CLK => Clock, Q => DF1_138_Q);
723 DF1_SumA_29_inst : DF1
724 port map(D => HA1_4_S, CLK => Clock, Q => SumA_29_net);
725 AO6_107 : AO6
726 port map(A => BUF_1_Y, B => AO16_2_Y, C => BUF_32_Y, D =>
727 XOR2_6_Y, Y => AO6_107_Y);
728 FA1_8 : FA1
729 port map(A => DF1_57_Q, B => DF1_12_Q, CI => HA1_10_S,
730 CO => FA1_8_CO, S => FA1_8_S);
731 FA1_80 : FA1
732 port map(A => FA1_31_CO, B => FA1_30_S, CI => FA1_35_S,
733 CO => FA1_80_CO, S => FA1_80_S);
734 DF1_81 : DF1
735 port map(D => PP3_5_net, CLK => Clock, Q => DF1_81_Q);
736 DF1_151 : DF1
737 port map(D => PP3_16_net, CLK => Clock, Q => DF1_151_Q);
738 XOR2_PP0_5_inst : XOR2
739 port map(A => AO6_32_Y, B => BUF_26_Y, Y => PP0_5_net);
740 HA1_5 : HA1
741 port map(A => DF1_4_Q, B => VCC_1_net, CO => HA1_5_CO, S =>
742 HA1_5_S);
743 DF1_7 : DF1
744 port map(D => PP7_11_net, CLK => Clock, Q => DF1_7_Q);
745 DF1_87 : DF1
746 port map(D => E_2_net, CLK => Clock, Q => DF1_87_Q);
747 BUF_5 : BUFF
748 port map(A => DataA(7), Y => BUF_5_Y);
749 DF1_144 : DF1
750 port map(D => PP3_4_net, CLK => Clock, Q => DF1_144_Q);
751 DF1_108 : DF1
752 port map(D => E_3_net, CLK => Clock, Q => DF1_108_Q);
753 HA1_14 : HA1
754 port map(A => DF1_126_Q, B => DF1_38_Q, CO => HA1_14_CO,
755 S => HA1_14_S);
756 DF1_14 : DF1
757 port map(D => PP7_5_net, CLK => Clock, Q => DF1_14_Q);
758 DF1_68 : DF1
759 port map(D => PP5_15_net, CLK => Clock, Q => DF1_68_Q);
760 OR3_2 : OR3
761 port map(A => DataB(1), B => DataB(2), C => DataB(3), Y =>
762 OR3_2_Y);
763 BUF_30 : BUFF
764 port map(A => DataB(5), Y => BUF_30_Y);
765 ADD1_Mult_18_inst : ADD1
766 port map(A => SumA_17_net, B => SumB_17_net, FCI =>
767 ADD1_Mult_17_FCO, S => Mult(18), FCO => ADD1_Mult_18_FCO);
768 XOR2_PP2_8_inst : XOR2
769 port map(A => AO6_47_Y, B => BUF_34_Y, Y => PP2_8_net);
770 XOR2_7 : XOR2
771 port map(A => BUF_40_Y, B => DataB(13), Y => XOR2_7_Y);
772 DF1_115 : DF1
773 port map(D => PP2_12_net, CLK => Clock, Q => DF1_115_Q);
774 BUF_0 : BUFF
775 port map(A => DataA(14), Y => BUF_0_Y);
776 DF1_34 : DF1
777 port map(D => PP2_1_net, CLK => Clock, Q => DF1_34_Q);
778 FA1_2 : FA1
779 port map(A => FA1_17_CO, B => FA1_56_S, CI => FA1_49_S,
780 CO => FA1_2_CO, S => FA1_2_S);
781 FA1_20 : FA1
782 port map(A => FA1_33_CO, B => FA1_40_CO, CI => FA1_61_S,
783 CO => FA1_20_CO, S => FA1_20_S);
784 DF1_132 : DF1
785 port map(D => PP5_1_net, CLK => Clock, Q => DF1_132_Q);
786 AO6_95 : AO6
787 port map(A => BUF_32_Y, B => AO16_6_Y, C => BUF_31_Y, D =>
788 XOR2_18_Y, Y => AO6_95_Y);
789 BUF_32 : BUFF
790 port map(A => DataA(13), Y => BUF_32_Y);
791 AO6_40 : AO6
792 port map(A => BUF_13_Y, B => AO16_5_Y, C => BUF_44_Y, D =>
793 XOR2_8_Y, Y => AO6_40_Y);
794 XOR2_23 : XOR2
795 port map(A => DataB(3), B => DataB(4), Y => XOR2_23_Y);
796 XOR2_PP5_2_inst : XOR2
797 port map(A => AO6_72_Y, B => BUF_47_Y, Y => PP5_2_net);
798 AO6_26 : AO6
799 port map(A => BUF_44_Y, B => AO16_1_Y, C => BUF_19_Y, D =>
800 XOR2_10_Y, Y => AO6_26_Y);
801 DF1_SumA_23_inst : DF1
802 port map(D => FA1_16_CO, CLK => Clock, Q => SumA_23_net);
803 XOR2_PP2_15_inst : XOR2
804 port map(A => AO6_79_Y, B => BUF_30_Y, Y => PP2_15_net);
805 XOR2_29 : XOR2
806 port map(A => DataB(9), B => DataB(10), Y => XOR2_29_Y);
807 FA1_56 : FA1
808 port map(A => FA1_6_CO, B => DF1_39_Q, CI => FA1_55_S,
809 CO => FA1_56_CO, S => FA1_56_S);
810 DF1_102 : DF1
811 port map(D => PP0_10_net, CLK => Clock, Q => DF1_102_Q);
812 DF1_SumA_10_inst : DF1
813 port map(D => FA1_23_CO, CLK => Clock, Q => SumA_10_net);
814 XOR2_PP3_5_inst : XOR2
815 port map(A => AO6_62_Y, B => BUF_12_Y, Y => PP3_5_net);
816 XOR2_PP0_9_inst : XOR2
817 port map(A => AO6_41_Y, B => BUF_23_Y, Y => PP0_9_net);
818 XOR2_PP2_6_inst : XOR2
819 port map(A => AO6_9_Y, B => BUF_34_Y, Y => PP2_6_net);
820 FA1_54 : FA1
821 port map(A => FA1_5_CO, B => FA1_12_CO, CI => FA1_38_S,
822 CO => FA1_54_CO, S => FA1_54_S);
823 DF1_152 : DF1
824 port map(D => PP7_1_net, CLK => Clock, Q => DF1_152_Q);
825 DF1_SumA_15_inst : DF1
826 port map(D => FA1_95_CO, CLK => Clock, Q => SumA_15_net);
827 XOR2_27 : XOR2
828 port map(A => AND2_2_Y, B => BUF_18_Y, Y => XOR2_27_Y);
829 DF1_SumA_3_inst : DF1
830 port map(D => HA1_3_CO, CLK => Clock, Q => SumA_3_net);
831 XOR2_6 : XOR2
832 port map(A => DataB(9), B => DataB(10), Y => XOR2_6_Y);
833 BUF_7 : BUFF
834 port map(A => DataA(6), Y => BUF_7_Y);
835 FCINIT_BUFF_0 : FCINIT_BUFF
836 port map(A => GND_1_net, FCO => FCINIT_BUFF_0_FCO);
837 AO6_36 : AO6
838 port map(A => BUF_4_Y, B => AO16_4_Y, C => BUF_2_Y, D =>
839 XOR2_29_Y, Y => AO6_36_Y);
840 BUF_4 : BUFF
841 port map(A => DataA(3), Y => BUF_4_Y);
842 FA1_3 : FA1
843 port map(A => DF1_48_Q, B => DF1_87_Q, CI => DF1_31_Q,
844 CO => FA1_3_CO, S => FA1_3_S);
845 BUF_18 : BUFF
846 port map(A => DataB(3), Y => BUF_18_Y);
847 FA1_30 : FA1
848 port map(A => DF1_78_Q, B => DF1_97_Q, CI => DF1_145_Q,
849 CO => FA1_30_CO, S => FA1_30_S);
850 DF1_123 : DF1
851 port map(D => PP1_11_net, CLK => Clock, Q => DF1_123_Q);
852 BUF_28 : BUFF
853 port map(A => DataA(3), Y => BUF_28_Y);
854 DF1_89 : DF1
855 port map(D => PP7_14_net, CLK => Clock, Q => DF1_89_Q);
856 MX2_PP0_16_inst : MX2
857 port map(A => MX2_2_Y, B => EBAR, S => AND2A_1_Y, Y =>
858 PP0_16_net);
859 AO6_9 : AO6
860 port map(A => BUF_45_Y, B => AO16_10_Y, C => BUF_7_Y, D =>
861 XOR2_21_Y, Y => AO6_9_Y);
862 DF1_18 : DF1
863 port map(D => PP0_6_net, CLK => Clock, Q => DF1_18_Q);
864 DF1_SumB_30_inst : DF1
865 port map(D => HA1_4_CO, CLK => Clock, Q => SumB_30_net);
866 DF1_SumB_22_inst : DF1
867 port map(D => FA1_16_S, CLK => Clock, Q => SumB_22_net);
868 AO6_45 : AO6
869 port map(A => BUF_21_Y, B => AND2A_0_Y, C => BUF_27_Y, D =>
870 DataB(0), Y => AO6_45_Y);
871 AO6_13 : AO6
872 port map(A => BUF_9_Y, B => AO16_2_Y, C => BUF_15_Y, D =>
873 XOR2_6_Y, Y => AO6_13_Y);
874 AO6_50 : AO6
875 port map(A => BUF_2_Y, B => AO16_4_Y, C => BUF_36_Y, D =>
876 XOR2_29_Y, Y => AO6_50_Y);
877 DF1_54 : DF1
878 port map(D => PP6_6_net, CLK => Clock, Q => DF1_54_Q);
879 AND2A_1 : AND2A
880 port map(A => DataB(0), B => BUF_23_Y, Y => AND2A_1_Y);
881 XOR2_PP6_5_inst : XOR2
882 port map(A => AO6_67_Y, B => BUF_17_Y, Y => PP6_5_net);
883 XOR2_PP6_8_inst : XOR2
884 port map(A => AO6_90_Y, B => BUF_17_Y, Y => PP6_8_net);
885 DF1_26 : DF1
886 port map(D => PP7_15_net, CLK => Clock, Q => DF1_26_Q);
887 DF1_38 : DF1
888 port map(D => PP6_12_net, CLK => Clock, Q => DF1_38_Q);
889 XOR2_PP4_13_inst : XOR2
890 port map(A => AO6_53_Y, B => BUF_33_Y, Y => PP4_13_net);
891 XOR2_PP4_3_inst : XOR2
892 port map(A => AO6_112_Y, B => BUF_37_Y, Y => PP4_3_net);
893 ADD1_Mult_9_inst : ADD1
894 port map(A => SumA_8_net, B => SumB_8_net, FCI =>
895 ADD1_Mult_8_FCO, S => Mult(9), FCO => ADD1_Mult_9_FCO);
896 BUF_10 : BUFF
897 port map(A => DataA(9), Y => BUF_10_Y);
898 AO6_12 : AO6
899 port map(A => BUF_10_Y, B => AO16_7_Y, C => BUF_43_Y, D =>
900 XOR2_28_Y, Y => AO6_12_Y);
901 FA1_6 : FA1
902 port map(A => DF1_67_Q, B => DF1_128_Q, CI => DF1_44_Q,
903 CO => FA1_6_CO, S => FA1_6_S);
904 ADD1_Mult_5_inst : ADD1
905 port map(A => SumA_4_net, B => SumB_4_net, FCI =>
906 ADD1_Mult_4_FCO, S => Mult(5), FCO => ADD1_Mult_5_FCO);
907 FA1_60 : FA1
908 port map(A => FA1_10_CO, B => HA1_2_CO, CI => FA1_6_S,
909 CO => FA1_60_CO, S => FA1_60_S);
910 BUF_20 : BUFF
911 port map(A => DataB(15), Y => BUF_20_Y);
912 XOR2_PP7_15_inst : XOR2
913 port map(A => AO6_69_Y, B => BUF_20_Y, Y => PP7_15_net);
914 DF1_SumB_11_inst : DF1
915 port map(D => FA1_76_S, CLK => Clock, Q => SumB_11_net);
916 XOR2_PP6_9_inst : XOR2
917 port map(A => AO6_54_Y, B => BUF_6_Y, Y => PP6_9_net);
918 XOR2_PP1_2_inst : XOR2
919 port map(A => AO6_29_Y, B => BUF_18_Y, Y => PP1_2_net);
920 HA1_15 : HA1
921 port map(A => DF1_6_Q, B => DF1_107_Q, CO => HA1_15_CO,
922 S => HA1_15_S);
923 BUF_12 : BUFF
924 port map(A => DataB(7), Y => BUF_12_Y);
925 AOI1_E_0_inst : AOI1
926 port map(A => XOR2_26_Y, B => OR3_1_Y, C => AND3_1_Y, Y =>
927 E_0_net);
928 XOR2_PP1_10_inst : XOR2
929 port map(A => AO6_22_Y, B => BUF_11_Y, Y => PP1_10_net);
930 XOR2_PP3_15_inst : XOR2
931 port map(A => AO6_15_Y, B => BUF_3_Y, Y => PP3_15_net);
932 MX2_PP5_16_inst : MX2
933 port map(A => MX2_3_Y, B => AO1_4_Y, S => AO16_2_Y, Y =>
934 PP5_16_net);
935 BUF_22 : BUFF
936 port map(A => DataB(15), Y => BUF_22_Y);
937 AO6_4 : AO6
938 port map(A => BUF_27_Y, B => AND2A_0_Y, C => BUF_28_Y, D =>
939 DataB(0), Y => AO6_4_Y);
940 BUF_31 : BUFF
941 port map(A => DataA(14), Y => BUF_31_Y);
942 AO6_55 : AO6
943 port map(A => BUF_25_Y, B => AO16_5_Y, C => BUF_4_Y, D =>
944 XOR2_8_Y, Y => AO6_55_Y);
945 XOR2_PP5_9_inst : XOR2
946 port map(A => AO6_82_Y, B => BUF_41_Y, Y => PP5_9_net);
947 AO6_114 : AO6
948 port map(A => BUF_29_Y, B => AND2A_0_Y, C => BUF_21_Y, D =>
949 DataB(0), Y => AO6_114_Y);
950 DF1_66 : DF1
951 port map(D => PP2_13_net, CLK => Clock, Q => DF1_66_Q);
952 XOR2_0 : XOR2
953 port map(A => AND2_4_Y, B => BUF_37_Y, Y => XOR2_0_Y);
954 DF1_SumA_9_inst : DF1
955 port map(D => FA1_64_CO, CLK => Clock, Q => SumA_9_net);
956 HA1_S_5_inst : HA1
957 port map(A => XOR2_24_Y, B => DataB(11), CO => S_5_net,
958 S => PP5_0_net);
959 AO6_94 : AO6
960 port map(A => BUF_32_Y, B => AO16_0_Y, C => BUF_31_Y, D =>
961 XOR2_5_Y, Y => AO6_94_Y);
962 AO6_116 : AO6
963 port map(A => BUF_14_Y, B => AO16_9_Y, C => BUF_10_Y, D =>
964 XOR2_23_Y, Y => AO6_116_Y);
965 DF1_73 : DF1
966 port map(D => PP0_15_net, CLK => Clock, Q => DF1_73_Q);
967 XOR2_PP6_12_inst : XOR2
968 port map(A => AO6_3_Y, B => BUF_6_Y, Y => PP6_12_net);
969 DF1_58 : DF1
970 port map(D => PP4_0_net, CLK => Clock, Q => DF1_58_Q);
971 XOR2_PP0_1_inst : XOR2
972 port map(A => AO6_114_Y, B => BUF_26_Y, Y => PP0_1_net);
973 XOR2_PP4_1_inst : XOR2
974 port map(A => AO6_10_Y, B => BUF_37_Y, Y => PP4_1_net);
975 XOR2_PP5_3_inst : XOR2
976 port map(A => AO6_52_Y, B => BUF_47_Y, Y => PP5_3_net);
977 FA1_55 : FA1
978 port map(A => DF1_59_Q, B => DF1_10_Q, CI => DF1_19_Q,
979 CO => FA1_55_CO, S => FA1_55_S);
980 DF1_70 : DF1
981 port map(D => PP1_12_net, CLK => Clock, Q => DF1_70_Q);
982 AO6_105 : AO6
983 port map(A => BUF_45_Y, B => AO16_13_Y, C => BUF_7_Y, D =>
984 XOR2_25_Y, Y => AO6_105_Y);
985 AOI1_E_2_inst : AOI1
986 port map(A => XOR2_22_Y, B => OR3_6_Y, C => AND3_2_Y, Y =>
987 E_2_net);
988 AO6_5 : AO6
989 port map(A => BUF_24_Y, B => AO16_9_Y, C => BUF_16_Y, D =>
990 XOR2_23_Y, Y => AO6_5_Y);
991 DF1_75 : DF1
992 port map(D => E_4_net, CLK => Clock, Q => DF1_75_Q);
993 DF1_SumB_20_inst : DF1
994 port map(D => FA1_53_S, CLK => Clock, Q => SumB_20_net);
995 DF1_21 : DF1
996 port map(D => S_1_net, CLK => Clock, Q => DF1_21_Q);
997 DF1_94 : DF1
998 port map(D => PP1_16_net, CLK => Clock, Q => DF1_94_Q);
999 AO6_99 : AO6
1000 port map(A => BUF_43_Y, B => AO16_7_Y, C => BUF_42_Y, D =>
1001 XOR2_28_Y, Y => AO6_99_Y);
1002 DF1_SumA_19_inst : DF1
1003 port map(D => FA1_79_CO, CLK => Clock, Q => SumA_19_net);
1004 DF1_27 : DF1
1005 port map(D => PP2_11_net, CLK => Clock, Q => DF1_27_Q);
1006 DF1_141 : DF1
1007 port map(D => PP4_4_net, CLK => Clock, Q => DF1_141_Q);
1008 DF1_SumA_26_inst : DF1
1009 port map(D => FA1_39_CO, CLK => Clock, Q => SumA_26_net);
1010 ADD1_Mult_7_inst : ADD1
1011 port map(A => SumA_6_net, B => SumB_6_net, FCI =>
1012 ADD1_Mult_6_FCO, S => Mult(7), FCO => ADD1_Mult_7_FCO);
1013 DF1_42 : DF1
1014 port map(D => PP1_3_net, CLK => Clock, Q => DF1_42_Q);
1015 AO6_44 : AO6
1016 port map(A => BUF_36_Y, B => AO16_5_Y, C => BUF_13_Y, D =>
1017 XOR2_8_Y, Y => AO6_44_Y);
1018 DF1_SumB_25_inst : DF1
1019 port map(D => FA1_39_S, CLK => Clock, Q => SumB_25_net);
1020 AOI1_E_7_inst : AOI1
1021 port map(A => XOR2_11_Y, B => OR3_4_Y, C => AND3_7_Y, Y =>
1022 E_7_net);
1023 XOR2_21 : XOR2
1024 port map(A => DataB(3), B => DataB(4), Y => XOR2_21_Y);
1025 AO6_17 : AO6
1026 port map(A => BUF_42_Y, B => AO16_9_Y, C => BUF_24_Y, D =>
1027 XOR2_23_Y, Y => AO6_17_Y);
1028 XOR2_PP0_2_inst : XOR2
1029 port map(A => AO6_45_Y, B => BUF_26_Y, Y => PP0_2_net);
1030 XOR2_PP6_3_inst : XOR2
1031 port map(A => AO6_55_Y, B => BUF_17_Y, Y => PP6_3_net);
1032 DF1_16 : DF1
1033 port map(D => PP6_0_net, CLK => Clock, Q => DF1_16_Q);
1034 DF1_148 : DF1
1035 port map(D => S_2_net, CLK => Clock, Q => DF1_148_Q);
1036 DF1_SumA_28_inst : DF1
1037 port map(D => FA1_19_CO, CLK => Clock, Q => SumA_28_net);
1038 XOR2_PP0_11_inst : XOR2
1039 port map(A => AO6_92_Y, B => BUF_23_Y, Y => PP0_11_net);
1040 XOR2_14 : XOR2
1041 port map(A => AND2_5_Y, B => BUF_12_Y, Y => XOR2_14_Y);
1042 AO1_EBAR : AO1
1043 port map(A => XOR2_26_Y, B => OR3_1_Y, C => AND3_1_Y, Y =>
1044 EBAR);
1045 BUF_11 : BUFF
1046 port map(A => DataB(3), Y => BUF_11_Y);
1047 DF1_119 : DF1
1048 port map(D => PP5_12_net, CLK => Clock, Q => DF1_119_Q);
1049 BUF_21 : BUFF
1050 port map(A => DataA(1), Y => BUF_21_Y);
1051 FA1_79 : FA1
1052 port map(A => FA1_20_CO, B => FA1_60_S, CI => FA1_17_S,
1053 CO => FA1_79_CO, S => FA1_79_S);
1054 DF1_36 : DF1
1055 port map(D => PP1_1_net, CLK => Clock, Q => DF1_36_Q);
1056 FA1_92 : FA1
1057 port map(A => FA1_1_CO, B => FA1_68_CO, CI => FA1_22_S,
1058 CO => FA1_92_CO, S => FA1_92_S);
1059 AO6_18 : AO6
1060 port map(A => BUF_27_Y, B => AO16_11_Y, C => BUF_28_Y, D =>
1061 XOR2_17_Y, Y => AO6_18_Y);
1062 DF1_61 : DF1
1063 port map(D => PP1_10_net, CLK => Clock, Q => DF1_61_Q);
1064 XOR2_PP5_11_inst : XOR2
1065 port map(A => AO6_13_Y, B => BUF_41_Y, Y => PP5_11_net);
1066 XOR2_4 : XOR2
1067 port map(A => DataB(1), B => DataB(2), Y => XOR2_4_Y);
1068 AO6_49 : AO6
1069 port map(A => BUF_19_Y, B => AO16_0_Y, C => BUF_38_Y, D =>
1070 XOR2_5_Y, Y => AO6_49_Y);
1071 DF1_SumA_13_inst : DF1
1072 port map(D => FA1_73_CO, CLK => Clock, Q => SumA_13_net);
1073 XOR2_PP1_9_inst : XOR2
1074 port map(A => AO6_1_Y, B => BUF_11_Y, Y => PP1_9_net);
1075 DF1_67 : DF1
1076 port map(D => PP3_13_net, CLK => Clock, Q => DF1_67_Q);
1077 AO6_0 : AO6
1078 port map(A => BUF_4_Y, B => AO16_5_Y, C => BUF_2_Y, D =>
1079 XOR2_8_Y, Y => AO6_0_Y);
1080 BUF_47 : BUFF
1081 port map(A => DataB(11), Y => BUF_47_Y);
1082 HA1_1 : HA1
1083 port map(A => DF1_14_Q, B => DF1_53_Q, CO => HA1_1_CO, S =>
1084 HA1_1_S);
1085 HA1_10 : HA1
1086 port map(A => DF1_118_Q, B => VCC_1_net, CO => HA1_10_CO,
1087 S => HA1_10_S);
1088 XOR2_PP5_6_inst : XOR2
1089 port map(A => AO6_25_Y, B => BUF_47_Y, Y => PP5_6_net);
1090 AO6_54 : AO6
1091 port map(A => BUF_19_Y, B => AO16_8_Y, C => BUF_38_Y, D =>
1092 XOR2_3_Y, Y => AO6_54_Y);
1093 DF1_136 : DF1
1094 port map(D => PP5_8_net, CLK => Clock, Q => DF1_136_Q);
1095 XOR2_PP0_14_inst : XOR2
1096 port map(A => AO6_30_Y, B => BUF_23_Y, Y => PP0_14_net);
1097 ADD1_Mult_4_inst : ADD1
1098 port map(A => SumA_3_net, B => SumB_3_net, FCI =>
1099 ADD1_Mult_3_FCO, S => Mult(4), FCO => ADD1_Mult_4_FCO);
1100 DF1_142 : DF1
1101 port map(D => S_3_net, CLK => Clock, Q => DF1_142_Q);
1102 DF1_98 : DF1
1103 port map(D => PP3_7_net, CLK => Clock, Q => DF1_98_Q);
1104 DF1_SumA_8_inst : DF1
1105 port map(D => FA1_80_CO, CLK => Clock, Q => SumA_8_net);
1106 AO6_110 : AO6
1107 port map(A => BUF_7_Y, B => AO16_11_Y, C => BUF_5_Y, D =>
1108 XOR2_17_Y, Y => AO6_110_Y);
1109 AND2_1 : AND2
1110 port map(A => XOR2_21_Y, B => BUF_29_Y, Y => AND2_1_Y);
1111 OR3_3 : OR3
1112 port map(A => DataB(9), B => DataB(10), C => DataB(11),
1113 Y => OR3_3_Y);
1114 DF1_29 : DF1
1115 port map(D => S_7_net, CLK => Clock, Q => DF1_29_Q);
1116 DF1_SumB_14_inst : DF1
1117 port map(D => FA1_95_S, CLK => Clock, Q => SumB_14_net);
1118 DF1_SumB_2_inst : DF1
1119 port map(D => HA1_3_S, CLK => Clock, Q => SumB_2_net);
1120 XOR2_PP4_12_inst : XOR2
1121 port map(A => AO6_37_Y, B => BUF_33_Y, Y => PP4_12_net);
1122 HA1_S_4_inst : HA1
1123 port map(A => XOR2_0_Y, B => DataB(9), CO => S_4_net, S =>
1124 PP4_0_net);
1125 DF1_106 : DF1
1126 port map(D => PP3_14_net, CLK => Clock, Q => DF1_106_Q);
1127 AND2_7 : AND2
1128 port map(A => XOR2_2_Y, B => BUF_8_Y, Y => AND2_7_Y);
1129 XOR2_PP5_14_inst : XOR2
1130 port map(A => AO6_115_Y, B => BUF_41_Y, Y => PP5_14_net);
1131 BUF_33 : BUFF
1132 port map(A => DataB(9), Y => BUF_33_Y);
1133 AO6_73 : AO6
1134 port map(A => BUF_28_Y, B => AND2A_0_Y, C => BUF_39_Y, D =>
1135 DataB(0), Y => AO6_73_Y);
1136 XOR2_PP0_6_inst : XOR2
1137 port map(A => AO6_76_Y, B => BUF_26_Y, Y => PP0_6_net);
1138 XOR2_PP3_1_inst : XOR2
1139 port map(A => AO6_16_Y, B => BUF_12_Y, Y => PP3_1_net);
1140 XOR2_15 : XOR2
1141 port map(A => BUF_46_Y, B => DataB(7), Y => XOR2_15_Y);
1142 HA1_6 : HA1
1143 port map(A => DF1_52_Q, B => DF1_60_Q, CO => HA1_6_CO, S =>
1144 HA1_6_S);
1145 FCEND_BUFF_0 : FCEND_BUFF
1146 port map(FCI => ADD1_Mult_31_FCO, CO => FCEND_BUFF_0_CO);
1147 AO6_111 : AO6
1148 port map(A => BUF_2_Y, B => AO16_12_Y, C => BUF_36_Y, D =>
1149 XOR2_2_Y, Y => AO6_111_Y);
1150 FA1_19 : FA1
1151 port map(A => HA1_5_S, B => DF1_89_Q, CI => FA1_65_CO,
1152 CO => FA1_19_CO, S => FA1_19_S);
1153 MX2_4 : MX2
1154 port map(A => BUF_20_Y, B => XOR2_11_Y, S => XOR2_18_Y,
1155 Y => MX2_4_Y);
1156 AO6_59 : AO6
1157 port map(A => BUF_24_Y, B => AO16_7_Y, C => BUF_16_Y, D =>
1158 XOR2_28_Y, Y => AO6_59_Y);
1159 AO6_60 : AO6
1160 port map(A => BUF_44_Y, B => AO16_4_Y, C => BUF_19_Y, D =>
1161 XOR2_29_Y, Y => AO6_60_Y);
1162 DF1_56 : DF1
1163 port map(D => PP6_13_net, CLK => Clock, Q => DF1_56_Q);
1164 FA1_5 : FA1
1165 port map(A => DF1_82_Q, B => DF1_33_Q, CI => HA1_13_CO,
1166 CO => FA1_5_CO, S => FA1_5_S);
1167 AND3_4 : AND3
1168 port map(A => DataB(5), B => DataB(6), C => DataB(7), Y =>
1169 AND3_4_Y);
1170 XOR2_PP2_2_inst : XOR2
1171 port map(A => AO6_106_Y, B => BUF_34_Y, Y => PP2_2_net);
1172 AO6_72 : AO6
1173 port map(A => BUF_35_Y, B => AO16_4_Y, C => BUF_25_Y, D =>
1174 XOR2_29_Y, Y => AO6_72_Y);
1175 FA1_50 : FA1
1176 port map(A => DF1_5_Q, B => VCC_1_net, CI => DF1_129_Q,
1177 CO => FA1_50_CO, S => FA1_50_S);
1178 AO6_83 : AO6
1179 port map(A => BUF_4_Y, B => AO16_1_Y, C => BUF_2_Y, D =>
1180 XOR2_10_Y, Y => AO6_83_Y);
1181 DF1_114 : DF1
1182 port map(D => PP0_1_net, CLK => Clock, Q => DF1_114_Q);
1183 DF1_11 : DF1
1184 port map(D => PP3_12_net, CLK => Clock, Q => DF1_11_Q);
1185 BUF_8 : BUFF
1186 port map(A => DataA(0), Y => BUF_8_Y);
1187 AO6_96 : AO6
1188 port map(A => BUF_25_Y, B => AO16_12_Y, C => BUF_4_Y, D =>
1189 XOR2_2_Y, Y => AO6_96_Y);
1190 HA1_3 : HA1
1191 port map(A => DF1_36_Q, B => DF1_111_Q, CO => HA1_3_CO,
1192 S => HA1_3_S);
1193 DF1_17 : DF1
1194 port map(D => PP2_7_net, CLK => Clock, Q => DF1_17_Q);
1195 AOI1_E_4_inst : AOI1
1196 port map(A => XOR2_20_Y, B => OR3_7_Y, C => AND3_0_Y, Y =>
1197 E_4_net);
1198 DF1_69 : DF1
1199 port map(D => PP6_9_net, CLK => Clock, Q => DF1_69_Q);
1200 AO6_82 : AO6
1201 port map(A => BUF_19_Y, B => AO16_2_Y, C => BUF_38_Y, D =>
1202 XOR2_6_Y, Y => AO6_82_Y);
1203 AND3_1 : AND3
1204 port map(A => GND_1_net, B => DataB(0), C => DataB(1), Y =>
1205 AND3_1_Y);
1206 XOR2_22 : XOR2
1207 port map(A => BUF_46_Y, B => DataB(5), Y => XOR2_22_Y);
1208 DF1_31 : DF1
1209 port map(D => PP4_13_net, CLK => Clock, Q => DF1_31_Q);
1210 FA1_49 : FA1
1211 port map(A => FA1_60_CO, B => FA1_11_CO, CI => FA1_27_S,
1212 CO => FA1_49_CO, S => FA1_49_S);
1213 DF1_SumB_29_inst : DF1
1214 port map(D => FA1_88_CO, CLK => Clock, Q => SumB_29_net);
1215 AO16_13 : AO16
1216 port map(A => DataB(1), B => DataB(2), C => BUF_18_Y, Y =>
1217 AO16_13_Y);
1218 DF1_127 : DF1
1219 port map(D => PP3_0_net, CLK => Clock, Q => DF1_127_Q);
1220 DF1_37 : DF1
1221 port map(D => PP4_10_net, CLK => Clock, Q => DF1_37_Q);
1222 XOR2_PP6_1_inst : XOR2
1223 port map(A => AO6_97_Y, B => BUF_17_Y, Y => PP6_1_net);
1224 AO6_119 : AO6
1225 port map(A => BUF_10_Y, B => AO16_9_Y, C => BUF_43_Y, D =>
1226 XOR2_23_Y, Y => AO6_119_Y);
1227 FA1_89 : FA1
1228 port map(A => DF1_64_Q, B => DF1_17_Q, CI => DF1_149_Q,
1229 CO => FA1_89_CO, S => FA1_89_S);
1230 XOR2_10 : XOR2
1231 port map(A => DataB(7), B => DataB(8), Y => XOR2_10_Y);
1232 XOR2_PP3_6_inst : XOR2
1233 port map(A => AO6_103_Y, B => BUF_12_Y, Y => PP3_6_net);
1234 AO6_65 : AO6
1235 port map(A => BUF_8_Y, B => AO16_4_Y, C => BUF_35_Y, D =>
1236 XOR2_29_Y, Y => AO6_65_Y);
1237 XOR2_PP1_13_inst : XOR2
1238 port map(A => AO6_113_Y, B => BUF_11_Y, Y => PP1_13_net);
1239 ADD1_Mult_22_inst : ADD1
1240 port map(A => SumA_21_net, B => SumB_21_net, FCI =>
1241 ADD1_Mult_21_FCO, S => Mult(22), FCO => ADD1_Mult_22_FCO);
1242 XOR2_26 : XOR2
1243 port map(A => BUF_46_Y, B => DataB(1), Y => XOR2_26_Y);
1244 HA1_S_7_inst : HA1
1245 port map(A => XOR2_12_Y, B => DataB(15), CO => S_7_net,
1246 S => PP7_0_net);
1247 AO6_23 : AO6
1248 port map(A => BUF_0_Y, B => AO16_3_Y, C => BUF_46_Y, D =>
1249 XOR2_4_Y, Y => AO6_23_Y);
1250 XOR2_PP2_1_inst : XOR2
1251 port map(A => AO6_24_Y, B => BUF_34_Y, Y => PP2_1_net);
1252 AO6_46 : AO6
1253 port map(A => BUF_28_Y, B => AO16_13_Y, C => BUF_39_Y, D =>
1254 XOR2_25_Y, Y => AO6_46_Y);
1255 XOR2_PP2_10_inst : XOR2
1256 port map(A => AO6_119_Y, B => BUF_30_Y, Y => PP2_10_net);
1257 BUF_13 : BUFF
1258 port map(A => DataA(6), Y => BUF_13_Y);
1259 DF1_120 : DF1
1260 port map(D => PP1_0_net, CLK => Clock, Q => DF1_120_Q);
1261 FA1_29 : FA1
1262 port map(A => DF1_135_Q, B => DF1_90_Q, CI => DF1_88_Q,
1263 CO => FA1_29_CO, S => FA1_29_S);
1264 AO6_11 : AO6
1265 port map(A => BUF_42_Y, B => AND2A_1_Y, C => BUF_24_Y, D =>
1266 DataB(0), Y => AO6_11_Y);
1267 AND2_3 : AND2
1268 port map(A => XOR2_8_Y, B => BUF_8_Y, Y => AND2_3_Y);
1269 BUF_23 : BUFF
1270 port map(A => DataB(1), Y => BUF_23_Y);
1271 XOR2_PP1_6_inst : XOR2
1272 port map(A => AO6_105_Y, B => BUF_18_Y, Y => PP1_6_net);
1273 FA1_78 : FA1
1274 port map(A => FA1_45_CO, B => FA1_50_S, CI => FA1_70_S,
1275 CO => FA1_78_CO, S => FA1_78_S);
1276 DF1_SumB_23_inst : DF1
1277 port map(D => FA1_78_S, CLK => Clock, Q => SumB_23_net);
1278 FA1_72 : FA1
1279 port map(A => FA1_58_CO, B => FA1_89_S, CI => FA1_57_S,
1280 CO => FA1_72_CO, S => FA1_72_S);
1281 XOR2_PP7_3_inst : XOR2
1282 port map(A => AO6_96_Y, B => BUF_22_Y, Y => PP7_3_net);
1283 AO6_22 : AO6
1284 port map(A => BUF_10_Y, B => AO16_3_Y, C => BUF_43_Y, D =>
1285 XOR2_4_Y, Y => AO6_22_Y);
1286 MX2_PP7_16_inst : MX2
1287 port map(A => MX2_4_Y, B => AO1_3_Y, S => AO16_6_Y, Y =>
1288 PP7_16_net);
1289 DF1_74 : DF1
1290 port map(D => PP4_7_net, CLK => Clock, Q => DF1_74_Q);
1291 DF1_82 : DF1
1292 port map(D => PP5_2_net, CLK => Clock, Q => DF1_82_Q);
1293 DF1_51 : DF1
1294 port map(D => PP3_1_net, CLK => Clock, Q => DF1_51_Q);
1295 BUF_39 : BUFF
1296 port map(A => DataA(4), Y => BUF_39_Y);
1297 XOR2_PP3_4_inst : XOR2
1298 port map(A => AO6_43_Y, B => BUF_12_Y, Y => PP3_4_net);
1299 AO6_6 : AO6
1300 port map(A => BUF_19_Y, B => AO16_6_Y, C => BUF_38_Y, D =>
1301 XOR2_18_Y, Y => AO6_6_Y);
1302 DF1_4 : DF1
1303 port map(D => PP6_16_net, CLK => Clock, Q => DF1_4_Q);
1304 DF1_19 : DF1
1305 port map(D => PP6_8_net, CLK => Clock, Q => DF1_19_Q);
1306 AO6_33 : AO6
1307 port map(A => BUF_42_Y, B => AO16_3_Y, C => BUF_24_Y, D =>
1308 XOR2_4_Y, Y => AO6_33_Y);
1309 DF1_96 : DF1
1310 port map(D => PP3_10_net, CLK => Clock, Q => DF1_96_Q);
1311 DF1_57 : DF1
1312 port map(D => PP7_12_net, CLK => Clock, Q => DF1_57_Q);
1313 DF1_SumA_16_inst : DF1
1314 port map(D => FA1_59_CO, CLK => Clock, Q => SumA_16_net);
1315 AO6_77 : AO6
1316 port map(A => BUF_28_Y, B => AO16_10_Y, C => BUF_39_Y, D =>
1317 XOR2_21_Y, Y => AO6_77_Y);
1318 AND2A_0 : AND2A
1319 port map(A => DataB(0), B => BUF_26_Y, Y => AND2A_0_Y);
1320 DF1_39 : DF1
1321 port map(D => PP7_6_net, CLK => Clock, Q => DF1_39_Q);
1322 DF1_SumA_1_inst : DF1
1323 port map(D => DF1_25_Q, CLK => Clock, Q => SumA_1_net);
1324 DF1_125 : DF1
1325 port map(D => PP2_2_net, CLK => Clock, Q => DF1_125_Q);
1326 XOR2_PP4_8_inst : XOR2
1327 port map(A => AO6_26_Y, B => BUF_37_Y, Y => PP4_8_net);
1328 AO6_56 : AO6
1329 port map(A => BUF_38_Y, B => AO16_8_Y, C => BUF_9_Y, D =>
1330 XOR2_3_Y, Y => AO6_56_Y);
1331 FA1_39 : FA1
1332 port map(A => FA1_52_CO, B => FA1_47_CO, CI => FA1_8_S,
1333 CO => FA1_39_CO, S => FA1_39_S);
1334 AO6_32 : AO6
1335 port map(A => BUF_39_Y, B => AND2A_0_Y, C => BUF_45_Y, D =>
1336 DataB(0), Y => AO6_32_Y);
1337 DF1_SumA_21_inst : DF1
1338 port map(D => FA1_53_CO, CLK => Clock, Q => SumA_21_net);
1339 ADD1_Mult_25_inst : ADD1
1340 port map(A => SumA_24_net, B => SumB_24_net, FCI =>
1341 ADD1_Mult_24_FCO, S => Mult(25), FCO => ADD1_Mult_25_FCO);
1342 AO16_8 : AO16
1343 port map(A => DataB(11), B => DataB(12), C => BUF_6_Y, Y =>
1344 AO16_8_Y);
1345 DF1_SumA_18_inst : DF1
1346 port map(D => FA1_4_CO, CLK => Clock, Q => SumA_18_net);
1347 AO6_78 : AO6
1348 port map(A => BUF_16_Y, B => AO16_3_Y, C => BUF_0_Y, D =>
1349 XOR2_4_Y, Y => AO6_78_Y);
1350 DF1_133 : DF1
1351 port map(D => PP2_14_net, CLK => Clock, Q => DF1_133_Q);
1352 AO6_87 : AO6
1353 port map(A => BUF_9_Y, B => AO16_0_Y, C => BUF_15_Y, D =>
1354 XOR2_5_Y, Y => AO6_87_Y);
1355 XOR2_13 : XOR2
1356 port map(A => BUF_46_Y, B => DataB(3), Y => XOR2_13_Y);
1357 XOR2_2 : XOR2
1358 port map(A => DataB(13), B => DataB(14), Y => XOR2_2_Y);
1359 XOR2_3 : XOR2
1360 port map(A => DataB(11), B => DataB(12), Y => XOR2_3_Y);
1361 FA1_18 : FA1
1362 port map(A => DF1_113_Q, B => DF1_100_Q, CI => HA1_8_S,
1363 CO => FA1_18_CO, S => FA1_18_S);
1364 XOR2_PP7_10_inst : XOR2
1365 port map(A => AO6_34_Y, B => BUF_20_Y, Y => PP7_10_net);
1366 FA1_12 : FA1
1367 port map(A => DF1_16_Q, B => DF1_141_Q, CI => FA1_94_S,
1368 CO => FA1_12_CO, S => FA1_12_S);
1369 XOR2_19 : XOR2
1370 port map(A => BUF_40_Y, B => DataB(11), Y => XOR2_19_Y);
1371 HA1_7 : HA1
1372 port map(A => DF1_79_Q, B => DF1_30_Q, CO => HA1_7_CO, S =>
1373 HA1_7_S);
1374 AO1_2 : AO1
1375 port map(A => XOR2_22_Y, B => OR3_6_Y, C => AND3_2_Y, Y =>
1376 AO1_2_Y);
1377 XOR2_PP3_7_inst : XOR2
1378 port map(A => AO6_110_Y, B => BUF_12_Y, Y => PP3_7_net);
1379 HA1_S_1_inst : HA1
1380 port map(A => XOR2_27_Y, B => DataB(3), CO => S_1_net, S =>
1381 PP1_0_net);
1382 DF1_103 : DF1
1383 port map(D => PP4_2_net, CLK => Clock, Q => DF1_103_Q);
1384 XOR2_PP0_4_inst : XOR2
1385 port map(A => AO6_73_Y, B => BUF_26_Y, Y => PP0_4_net);
1386 AO6_88 : AO6
1387 port map(A => BUF_0_Y, B => AND2A_1_Y, C => BUF_46_Y, D =>
1388 DataB(0), Y => AO6_88_Y);
1389 XOR2_PP3_10_inst : XOR2
1390 port map(A => AO6_12_Y, B => BUF_3_Y, Y => PP3_10_net);
1391 FA1_69 : FA1
1392 port map(A => FA1_70_CO, B => FA1_47_S, CI => FA1_52_S,
1393 CO => FA1_69_CO, S => FA1_69_S);
1394 XOR2_PP1_8_inst : XOR2
1395 port map(A => AO6_98_Y, B => BUF_18_Y, Y => PP1_8_net);
1396 XOR2_PP7_4_inst : XOR2
1397 port map(A => AO6_7_Y, B => BUF_22_Y, Y => PP7_4_net);
1398 BUF_34 : BUFF
1399 port map(A => DataB(5), Y => BUF_34_Y);
1400 HA1_2 : HA1
1401 port map(A => DF1_80_Q, B => DF1_54_Q, CO => HA1_2_CO, S =>
1402 HA1_2_S);
1403 DF1_78 : DF1
1404 port map(D => PP1_6_net, CLK => Clock, Q => DF1_78_Q);
1405 XOR2_PP3_9_inst : XOR2
1406 port map(A => AO6_86_Y, B => BUF_3_Y, Y => PP3_9_net);
1407 XOR2_PP6_11_inst : XOR2
1408 port map(A => AO6_102_Y, B => BUF_6_Y, Y => PP6_11_net);
1409 DF1_SumB_9_inst : DF1
1410 port map(D => FA1_23_S, CLK => Clock, Q => SumB_9_net);
1411 AO6_64 : AO6
1412 port map(A => BUF_35_Y, B => AO16_5_Y, C => BUF_25_Y, D =>
1413 XOR2_8_Y, Y => AO6_64_Y);
1414 XOR2_17 : XOR2
1415 port map(A => DataB(5), B => DataB(6), Y => XOR2_17_Y);
1416 AO6_104 : AO6
1417 port map(A => BUF_38_Y, B => AO16_2_Y, C => BUF_9_Y, D =>
1418 XOR2_6_Y, Y => AO6_104_Y);
1419 XOR2_PP0_15_inst : XOR2
1420 port map(A => AO6_88_Y, B => BUF_23_Y, Y => PP0_15_net);
1421 ADD1_Mult_27_inst : ADD1
1422 port map(A => SumA_26_net, B => SumB_26_net, FCI =>
1423 ADD1_Mult_26_FCO, S => Mult(27), FCO => ADD1_Mult_27_FCO);
1424 DF1_59 : DF1
1425 port map(D => PP4_12_net, CLK => Clock, Q => DF1_59_Q);
1426 FA1_48 : FA1
1427 port map(A => FA1_56_CO, B => FA1_27_CO, CI => FA1_68_S,
1428 CO => FA1_48_CO, S => FA1_48_S);
1429 OR3_1 : OR3
1430 port map(A => GND_1_net, B => DataB(0), C => DataB(1), Y =>
1431 OR3_1_Y);
1432 FA1_42 : FA1
1433 port map(A => DF1_27_Q, B => DF1_73_Q, CI => DF1_74_Q,
1434 CO => FA1_42_CO, S => FA1_42_S);
1435 DF1_SumB_1_inst : DF1
1436 port map(D => DF1_120_Q, CLK => Clock, Q => SumB_1_net);
1437 XOR2_PP5_8_inst : XOR2
1438 port map(A => AO6_60_Y, B => BUF_47_Y, Y => PP5_8_net);
1439 BUF_19 : BUFF
1440 port map(A => DataA(8), Y => BUF_19_Y);
1441 XOR2_PP6_7_inst : XOR2
1442 port map(A => AO6_40_Y, B => BUF_17_Y, Y => PP6_7_net);
1443 AO6_106 : AO6
1444 port map(A => BUF_21_Y, B => AO16_10_Y, C => BUF_27_Y, D =>
1445 XOR2_21_Y, Y => AO6_106_Y);
1446 FA1_88 : FA1
1447 port map(A => DF1_26_Q, B => DF1_65_Q, CI => HA1_5_CO,
1448 CO => FA1_88_CO, S => FA1_88_S);
1449 BUF_45 : BUFF
1450 port map(A => DataA(5), Y => BUF_45_Y);
1451 DF1_146 : DF1
1452 port map(D => PP7_7_net, CLK => Clock, Q => DF1_146_Q);
1453 FA1_82 : FA1
1454 port map(A => DF1_148_Q, B => DF1_34_Q, CI => HA1_11_S,
1455 CO => FA1_82_CO, S => FA1_82_S);
1456 DF1_SumB_17_inst : DF1
1457 port map(D => FA1_4_S, CLK => Clock, Q => SumB_17_net);
1458 XOR2_PP5_15_inst : XOR2
1459 port map(A => AO6_57_Y, B => BUF_41_Y, Y => PP5_15_net);
1460 BUF_29 : BUFF
1461 port map(A => DataA(0), Y => BUF_29_Y);
1462 DF1_91 : DF1
1463 port map(D => PP5_4_net, CLK => Clock, Q => DF1_91_Q);
1464 AO6_27 : AO6
1465 port map(A => BUF_39_Y, B => AO16_10_Y, C => BUF_45_Y, D =>
1466 XOR2_21_Y, Y => AO6_27_Y);
1467 XOR2_PP1_5_inst : XOR2
1468 port map(A => AO6_35_Y, B => BUF_18_Y, Y => PP1_5_net);
1469 XOR2_PP6_14_inst : XOR2
1470 port map(A => AO6_74_Y, B => BUF_6_Y, Y => PP6_14_net);
1471 DF1_97 : DF1
1472 port map(D => PP0_8_net, CLK => Clock, Q => DF1_97_Q);
1473 DF1_111 : DF1
1474 port map(D => PP0_3_net, CLK => Clock, Q => DF1_111_Q);
1475 XOR2_PP1_3_inst : XOR2
1476 port map(A => AO6_66_Y, B => BUF_18_Y, Y => PP1_3_net);
1477 XOR2_PP2_5_inst : XOR2
1478 port map(A => AO6_27_Y, B => BUF_34_Y, Y => PP2_5_net);
1479 AO6_69 : AO6
1480 port map(A => BUF_31_Y, B => AO16_6_Y, C => BUF_40_Y, D =>
1481 XOR2_18_Y, Y => AO6_69_Y);
1482 XOR2_PP2_7_inst : XOR2
1483 port map(A => AO6_80_Y, B => BUF_34_Y, Y => PP2_7_net);
1484 XOR2_PP4_4_inst : XOR2
1485 port map(A => AO6_83_Y, B => BUF_37_Y, Y => PP4_4_net);
1486 AO6_28 : AO6
1487 port map(A => BUF_13_Y, B => AO16_4_Y, C => BUF_44_Y, D =>
1488 XOR2_29_Y, Y => AO6_28_Y);
1489 BUF_46 : BUFF
1490 port map(A => DataA(15), Y => BUF_46_Y);
1491 FA1_91 : FA1
1492 port map(A => FA1_8_CO, B => HA1_10_CO, CI => FA1_65_S,
1493 CO => FA1_91_CO, S => FA1_91_S);
1494 AO16_3 : AO16
1495 port map(A => DataB(1), B => DataB(2), C => BUF_11_Y, Y =>
1496 AO16_3_Y);
1497 HA1_S_2_inst : HA1
1498 port map(A => XOR2_9_Y, B => DataB(5), CO => S_2_net, S =>
1499 PP2_0_net);
1500 XOR2_PP2_9_inst : XOR2
1501 port map(A => AO6_116_Y, B => BUF_30_Y, Y => PP2_9_net);
1502 FA1_28 : FA1
1503 port map(A => DF1_49_Q, B => DF1_102_Q, CI => DF1_103_Q,
1504 CO => FA1_28_CO, S => FA1_28_S);
1505 DF1_118 : DF1
1506 port map(D => PP5_16_net, CLK => Clock, Q => DF1_118_Q);
1507 FA1_22 : FA1
1508 port map(A => DF1_9_Q, B => DF1_119_Q, CI => FA1_3_CO,
1509 CO => FA1_22_CO, S => FA1_22_S);
1510 XOR2_PP1_12_inst : XOR2
1511 port map(A => AO6_33_Y, B => BUF_11_Y, Y => PP1_12_net);
1512 HA1_S_3_inst : HA1
1513 port map(A => XOR2_14_Y, B => DataB(7), CO => S_3_net, S =>
1514 PP3_0_net);
1515 AO6_37 : AO6
1516 port map(A => BUF_15_Y, B => AO16_0_Y, C => BUF_1_Y, D =>
1517 XOR2_5_Y, Y => AO6_37_Y);
1518 DF1_SumB_26_inst : DF1
1519 port map(D => FA1_91_S, CLK => Clock, Q => SumB_26_net);
1520 DF1_Mult_0_inst : DF1
1521 port map(D => DF1_117_Q, CLK => Clock, Q => Mult(0));
1522 DF1_SumA_0_inst : DF1
1523 port map(D => DF1_114_Q, CLK => Clock, Q => SumA_0_net);
1524 AOI1_E_6_inst : AOI1
1525 port map(A => XOR2_7_Y, B => OR3_0_Y, C => AND3_3_Y, Y =>
1526 E_6_net);
1527 AO6_38 : AO6
1528 port map(A => BUF_5_Y, B => AND2A_0_Y, C => BUF_14_Y, D =>
1529 DataB(0), Y => AO6_38_Y);
1530 BUF_14 : BUFF
1531 port map(A => DataA(8), Y => BUF_14_Y);
1532 DF1_SumA_2_inst : DF1
1533 port map(D => DF1_21_Q, CLK => Clock, Q => SumA_2_net);
1534 DF1_43 : DF1
1535 port map(D => PP3_8_net, CLK => Clock, Q => DF1_43_Q);
1536 AO16_5 : AO16
1537 port map(A => DataB(11), B => DataB(12), C => BUF_17_Y,
1538 Y => AO16_5_Y);
1539 BUF_24 : BUFF
1540 port map(A => DataA(12), Y => BUF_24_Y);
1541 DF1_SumB_28_inst : DF1
1542 port map(D => FA1_88_S, CLK => Clock, Q => SumB_28_net);
1543 DF1_112 : DF1
1544 port map(D => PP1_9_net, CLK => Clock, Q => DF1_112_Q);
1545 FA1_38 : FA1
1546 port map(A => HA1_0_S, B => DF1_3_Q, CI => FA1_63_S, CO =>
1547 FA1_38_CO, S => FA1_38_S);
1548 DF1_40 : DF1
1549 port map(D => S_6_net, CLK => Clock, Q => DF1_40_Q);
1550 FA1_32 : FA1
1551 port map(A => HA1_15_S, B => DF1_92_Q, CI => FA1_30_CO,
1552 CO => FA1_32_CO, S => FA1_32_S);
1553 AO6_71 : AO6
1554 port map(A => BUF_2_Y, B => AO16_1_Y, C => BUF_36_Y, D =>
1555 XOR2_10_Y, Y => AO6_71_Y);
1556 AO16_0 : AO16
1557 port map(A => DataB(7), B => DataB(8), C => BUF_33_Y, Y =>
1558 AO16_0_Y);
1559 AO1_1 : AO1
1560 port map(A => XOR2_15_Y, B => OR3_5_Y, C => AND3_4_Y, Y =>
1561 AO1_1_Y);
1562 BUF_6 : BUFF
1563 port map(A => DataB(13), Y => BUF_6_Y);
1564 XOR2_PP4_11_inst : XOR2
1565 port map(A => AO6_87_Y, B => BUF_33_Y, Y => PP4_11_net);
1566 DF1_SumA_24_inst : DF1
1567 port map(D => FA1_78_CO, CLK => Clock, Q => SumA_24_net);
1568 XOR2_PP7_1_inst : XOR2
1569 port map(A => AO6_14_Y, B => BUF_22_Y, Y => PP7_1_net);
1570 DF1_99 : DF1
1571 port map(D => PP4_15_net, CLK => Clock, Q => DF1_99_Q);
1572 BUF_3 : BUFF
1573 port map(A => DataB(7), Y => BUF_3_Y);
1574 DF1_22 : DF1
1575 port map(D => PP5_11_net, CLK => Clock, Q => DF1_22_Q);
1576 DF1_45 : DF1
1577 port map(D => PP0_14_net, CLK => Clock, Q => DF1_45_Q);
1578 DF1_8 : DF1
1579 port map(D => PP1_4_net, CLK => Clock, Q => DF1_8_Q);
1580 ADD1_Mult_12_inst : ADD1
1581 port map(A => SumA_11_net, B => SumB_11_net, FCI =>
1582 ADD1_Mult_11_FCO, S => Mult(12), FCO => ADD1_Mult_12_FCO);
1583 MX2_2 : MX2
1584 port map(A => BUF_23_Y, B => XOR2_26_Y, S => DataB(0), Y =>
1585 MX2_2_Y);
1586 XOR2_PP4_9_inst : XOR2
1587 port map(A => AO6_49_Y, B => BUF_33_Y, Y => PP4_9_net);
1588 XOR2_PP2_13_inst : XOR2
1589 port map(A => AO6_5_Y, B => BUF_30_Y, Y => PP2_13_net);
1590 AO6_81 : AO6
1591 port map(A => BUF_43_Y, B => AO16_9_Y, C => BUF_42_Y, D =>
1592 XOR2_23_Y, Y => AO6_81_Y);
1593 DF1_76 : DF1
1594 port map(D => PP2_15_net, CLK => Clock, Q => DF1_76_Q);
1595 AO6_100 : AO6
1596 port map(A => BUF_42_Y, B => AO16_7_Y, C => BUF_24_Y, D =>
1597 XOR2_28_Y, Y => AO6_100_Y);
1598 FA1_68 : FA1
1599 port map(A => FA1_55_CO, B => DF1_69_Q, CI => FA1_3_S,
1600 CO => FA1_68_CO, S => FA1_68_S);
1601 FA1_62 : FA1
1602 port map(A => DF1_132_Q, B => DF1_81_Q, CI => HA1_13_S,
1603 CO => FA1_62_CO, S => FA1_62_S);
1604 AO16_9 : AO16
1605 port map(A => DataB(3), B => DataB(4), C => BUF_30_Y, Y =>
1606 AO16_9_Y);
1607 XOR2_11 : XOR2
1608 port map(A => BUF_40_Y, B => DataB(15), Y => XOR2_11_Y);
1609 XOR2_PP4_14_inst : XOR2
1610 port map(A => AO6_94_Y, B => BUF_33_Y, Y => PP4_14_net);
1611 AO16_12 : AO16
1612 port map(A => DataB(13), B => DataB(14), C => BUF_22_Y,
1613 Y => AO16_12_Y);
1614 AO6_101 : AO6
1615 port map(A => BUF_9_Y, B => AO16_6_Y, C => BUF_15_Y, D =>
1616 XOR2_18_Y, Y => AO6_101_Y);
1617 XOR2_PP3_3_inst : XOR2
1618 port map(A => AO6_18_Y, B => BUF_12_Y, Y => PP3_3_net);
1619 ADD1_Mult_24_inst : ADD1
1620 port map(A => SumA_23_net, B => SumB_23_net, FCI =>
1621 ADD1_Mult_23_FCO, S => Mult(24), FCO => ADD1_Mult_24_FCO);
1622 DF1_129 : DF1
1623 port map(D => PP5_14_net, CLK => Clock, Q => DF1_129_Q);
1624 HA1_0 : HA1
1625 port map(A => DF1_138_Q, B => DF1_98_Q, CO => HA1_0_CO,
1626 S => HA1_0_S);
1627 XOR2_PP3_8_inst : XOR2
1628 port map(A => AO6_70_Y, B => BUF_12_Y, Y => PP3_8_net);
1629 AOI1_E_1_inst : AOI1
1630 port map(A => XOR2_13_Y, B => OR3_2_Y, C => AND3_6_Y, Y =>
1631 E_1_net);
1632 XOR2_PP0_3_inst : XOR2
1633 port map(A => AO6_4_Y, B => BUF_26_Y, Y => PP0_3_net);
1634 AO6_66 : AO6
1635 port map(A => BUF_27_Y, B => AO16_13_Y, C => BUF_28_Y, D =>
1636 XOR2_25_Y, Y => AO6_66_Y);
1637 DF1_SumA_11_inst : DF1
1638 port map(D => FA1_72_CO, CLK => Clock, Q => SumA_11_net);
1639 DF1_62 : DF1
1640 port map(D => PP5_6_net, CLK => Clock, Q => DF1_62_Q);
1641 AO16_11 : AO16
1642 port map(A => DataB(5), B => DataB(6), C => BUF_12_Y, Y =>
1643 AO16_11_Y);
1644 XOR2_5 : XOR2
1645 port map(A => DataB(7), B => DataB(8), Y => XOR2_5_Y);
1646 HA1_4 : HA1
1647 port map(A => DF1_47_Q, B => VCC_1_net, CO => HA1_4_CO,
1648 S => HA1_4_S);
1649 XOR2_PP4_6_inst : XOR2
1650 port map(A => AO6_89_Y, B => BUF_37_Y, Y => PP4_6_net);
1651 XOR2_PP0_8_inst : XOR2
1652 port map(A => AO6_38_Y, B => BUF_26_Y, Y => PP0_8_net);
1653 ADD1_Mult_29_inst : ADD1
1654 port map(A => SumA_28_net, B => SumB_28_net, FCI =>
1655 ADD1_Mult_28_FCO, S => Mult(29), FCO => ADD1_Mult_29_FCO);
1656 AO6_93 : AO6
1657 port map(A => BUF_1_Y, B => AO16_8_Y, C => BUF_32_Y, D =>
1658 XOR2_3_Y, Y => AO6_93_Y);
1659 FA1_59 : FA1
1660 port map(A => FA1_0_CO, B => FA1_13_S, CI => FA1_66_S,
1661 CO => FA1_59_CO, S => FA1_59_S);
1662 ADD1_Mult_21_inst : ADD1
1663 port map(A => SumA_20_net, B => SumB_20_net, FCI =>
1664 ADD1_Mult_20_FCO, S => Mult(21), FCO => ADD1_Mult_21_FCO);
1665 AO6_21 : AO6
1666 port map(A => BUF_1_Y, B => AO16_6_Y, C => BUF_32_Y, D =>
1667 XOR2_18_Y, Y => AO6_21_Y);
1668 XOR2_PP0_7_inst : XOR2
1669 port map(A => AO6_63_Y, B => BUF_26_Y, Y => PP0_7_net);
1670 ADD1_Mult_15_inst : ADD1
1671 port map(A => SumA_14_net, B => SumB_14_net, FCI =>
1672 ADD1_Mult_14_FCO, S => Mult(15), FCO => ADD1_Mult_15_FCO);
1673 DF1_143 : DF1
1674 port map(D => PP0_4_net, CLK => Clock, Q => DF1_143_Q);
1675 AO6_92 : AO6
1676 port map(A => BUF_43_Y, B => AND2A_1_Y, C => BUF_42_Y, D =>
1677 DataB(0), Y => AO6_92_Y);
1678 FA1_71 : FA1
1679 port map(A => DF1_147_Q, B => DF1_45_Q, CI => DF1_46_Q,
1680 CO => FA1_71_CO, S => FA1_71_S);
1681 FA1_93 : FA1
1682 port map(A => FA1_66_CO, B => FA1_33_S, CI => FA1_15_S,
1683 CO => FA1_93_CO, S => FA1_93_S);
1684 XOR2_PP7_13_inst : XOR2
1685 port map(A => AO6_21_Y, B => BUF_20_Y, Y => PP7_13_net);
1686 AO6_109 : AO6
1687 port map(A => BUF_36_Y, B => AO16_12_Y, C => BUF_13_Y, D =>
1688 XOR2_2_Y, Y => AO6_109_Y);
1689 AO16_6 : AO16
1690 port map(A => DataB(13), B => DataB(14), C => BUF_20_Y,
1691 Y => AO16_6_Y);
1692 BUF_1 : BUFF
1693 port map(A => DataA(12), Y => BUF_1_Y);
1694 FA1_77 : FA1
1695 port map(A => FA1_42_CO, B => HA1_6_S, CI => FA1_43_S,
1696 CO => FA1_77_CO, S => FA1_77_S);
1697 BUF_2 : BUFF
1698 port map(A => DataA(4), Y => BUF_2_Y);
1699 XOR2_PP3_13_inst : XOR2
1700 port map(A => AO6_59_Y, B => BUF_3_Y, Y => PP3_13_net);
1701 MX2_3 : MX2
1702 port map(A => BUF_41_Y, B => XOR2_19_Y, S => XOR2_6_Y, Y =>
1703 MX2_3_Y);
1704 DF1_137 : DF1
1705 port map(D => PP0_13_net, CLK => Clock, Q => DF1_137_Q);
1706 ADD1_Mult_3_inst : ADD1
1707 port map(A => SumA_2_net, B => SumB_2_net, FCI =>
1708 ADD1_Mult_2_FCO, S => Mult(3), FCO => ADD1_Mult_3_FCO);
1709 XOR2_PP7_6_inst : XOR2
1710 port map(A => AO6_109_Y, B => BUF_22_Y, Y => PP7_6_net);
1711 AO6_31 : AO6
1712 port map(A => BUF_13_Y, B => AO16_12_Y, C => BUF_44_Y, D =>
1713 XOR2_2_Y, Y => AO6_31_Y);
1714 AO6_43 : AO6
1715 port map(A => BUF_28_Y, B => AO16_11_Y, C => BUF_39_Y, D =>
1716 XOR2_17_Y, Y => AO6_43_Y);
1717 DF1_71 : DF1
1718 port map(D => E_5_net, CLK => Clock, Q => DF1_71_Q);
1719 ADD1_Mult_1_inst : ADD1
1720 port map(A => SumA_0_net, B => SumB_0_net, FCI =>
1721 FCINIT_BUFF_0_FCO, S => Mult(1), FCO => ADD1_Mult_1_FCO);
1722 AO1_4 : AO1
1723 port map(A => XOR2_19_Y, B => OR3_3_Y, C => AND3_5_Y, Y =>
1724 AO1_4_Y);
1725 DF1_77 : DF1
1726 port map(D => PP2_3_net, CLK => Clock, Q => DF1_77_Q);
1727 DF1_107 : DF1
1728 port map(D => PP3_3_net, CLK => Clock, Q => DF1_107_Q);
1729 DF1_124 : DF1
1730 port map(D => PP0_5_net, CLK => Clock, Q => DF1_124_Q);
1731 AND2_2 : AND2
1732 port map(A => XOR2_25_Y, B => BUF_29_Y, Y => AND2_2_Y);
1733 AO6_10 : AO6
1734 port map(A => BUF_8_Y, B => AO16_1_Y, C => BUF_35_Y, D =>
1735 XOR2_10_Y, Y => AO6_10_Y);
1736 DF1_12 : DF1
1737 port map(D => PP6_14_net, CLK => Clock, Q => DF1_12_Q);
1738 ADD1_Mult_17_inst : ADD1
1739 port map(A => SumA_16_net, B => SumB_16_net, FCI =>
1740 ADD1_Mult_16_FCO, S => Mult(17), FCO => ADD1_Mult_17_FCO);
1741 XOR2_PP6_15_inst : XOR2
1742 port map(A => AO6_91_Y, B => BUF_6_Y, Y => PP6_15_net);
1743 AO6_42 : AO6
1744 port map(A => BUF_15_Y, B => AO16_2_Y, C => BUF_1_Y, D =>
1745 XOR2_6_Y, Y => AO6_42_Y);
1746 AND3_2 : AND3
1747 port map(A => DataB(3), B => DataB(4), C => DataB(5), Y =>
1748 AND3_2_Y);
1749 DF1_SumB_12_inst : DF1
1750 port map(D => FA1_73_S, CLK => Clock, Q => SumB_12_net);
1751 XOR2_PP7_7_inst : XOR2
1752 port map(A => AO6_31_Y, B => BUF_22_Y, Y => PP7_7_net);
1753 DF1_32 : DF1
1754 port map(D => PP6_15_net, CLK => Clock, Q => DF1_32_Q);
1755 DF1_130 : DF1
1756 port map(D => PP1_2_net, CLK => Clock, Q => DF1_130_Q);
1757 HA1_9 : HA1
1758 port map(A => DF1_93_Q, B => DF1_83_Q, CO => HA1_9_CO, S =>
1759 HA1_9_S);
1760 FA1_11 : FA1
1761 port map(A => FA1_85_CO, B => HA1_1_S, CI => FA1_67_S,
1762 CO => FA1_11_CO, S => FA1_11_S);
1763 XOR2_12 : XOR2
1764 port map(A => AND2_7_Y, B => BUF_22_Y, Y => XOR2_12_Y);
1765 FA1_17 : FA1
1766 port map(A => FA1_36_CO, B => FA1_61_CO, CI => FA1_11_S,
1767 CO => FA1_17_CO, S => FA1_17_S);
1768 AO16_2 : AO16
1769 port map(A => DataB(9), B => DataB(10), C => BUF_41_Y, Y =>
1770 AO16_2_Y);
1771 DF1_83 : DF1
1772 port map(D => PP6_5_net, CLK => Clock, Q => DF1_83_Q);
1773 DF1_100 : DF1
1774 port map(D => PP4_14_net, CLK => Clock, Q => DF1_100_Q);
1775 AO6_53 : AO6
1776 port map(A => BUF_1_Y, B => AO16_0_Y, C => BUF_32_Y, D =>
1777 XOR2_5_Y, Y => AO6_53_Y);
1778 OR3_7 : OR3
1779 port map(A => DataB(7), B => DataB(8), C => DataB(9), Y =>
1780 OR3_7_Y);
1781 AO6_118 : AO6
1782 port map(A => BUF_35_Y, B => AO16_12_Y, C => BUF_25_Y, D =>
1783 XOR2_2_Y, Y => AO6_118_Y);
1784 HA1_12 : HA1
1785 port map(A => DF1_152_Q, B => DF1_109_Q, CO => HA1_12_CO,
1786 S => HA1_12_S);
1787 DF1_150 : DF1
1788 port map(D => PP5_3_net, CLK => Clock, Q => DF1_150_Q);
1789 BUF_37 : BUFF
1790 port map(A => DataB(9), Y => BUF_37_Y);
1791 AO6_15 : AO6
1792 port map(A => BUF_0_Y, B => AO16_7_Y, C => BUF_46_Y, D =>
1793 XOR2_28_Y, Y => AO6_15_Y);
1794 DF1_80 : DF1
1795 port map(D => PP7_4_net, CLK => Clock, Q => DF1_80_Q);
1796 XOR2_PP7_5_inst : XOR2
1797 port map(A => AO6_111_Y, B => BUF_22_Y, Y => PP7_5_net);
1798 XOR2_16 : XOR2
1799 port map(A => AND2_0_Y, B => BUF_26_Y, Y => XOR2_16_Y);
1800 FA1_41 : FA1
1801 port map(A => DF1_66_Q, B => DF1_15_Q, CI => DF1_121_Q,
1802 CO => FA1_41_CO, S => FA1_41_S);
1803 FA1_96 : FA1
1804 port map(A => FA1_54_CO, B => FA1_37_S, CI => FA1_25_S,
1805 CO => FA1_96_CO, S => FA1_96_S);
1806 DF1_135 : DF1
1807 port map(D => PP1_7_net, CLK => Clock, Q => DF1_135_Q);
1808 AO6_52 : AO6
1809 port map(A => BUF_25_Y, B => AO16_4_Y, C => BUF_4_Y, D =>
1810 XOR2_29_Y, Y => AO6_52_Y);
1811 XOR2_PP4_2_inst : XOR2
1812 port map(A => AO6_58_Y, B => BUF_37_Y, Y => PP4_2_net);
1813 DF1_SumB_21_inst : DF1
1814 port map(D => FA1_74_S, CLK => Clock, Q => SumB_21_net);
1815 XOR2_PP2_12_inst : XOR2
1816 port map(A => AO6_17_Y, B => BUF_30_Y, Y => PP2_12_net);
1817 DF1_85 : DF1
1818 port map(D => PP2_8_net, CLK => Clock, Q => DF1_85_Q);
1819 AO6_97 : AO6
1820 port map(A => BUF_8_Y, B => AO16_5_Y, C => BUF_35_Y, D =>
1821 XOR2_8_Y, Y => AO6_97_Y);
1822 FA1_81 : FA1
1823 port map(A => FA1_75_CO, B => HA1_7_S, CI => FA1_31_S,
1824 CO => FA1_81_CO, S => FA1_81_S);
1825 FA1_47 : FA1
1826 port map(A => DF1_68_Q, B => DF1_75_Q, CI => DF1_56_Q,
1827 CO => FA1_47_CO, S => FA1_47_S);
1828 FA1_94 : FA1
1829 port map(A => DF1_61_Q, B => DF1_140_Q, CI => DF1_85_Q,
1830 CO => FA1_94_CO, S => FA1_94_S);
1831 DF1_2 : DF1
1832 port map(D => PP2_0_net, CLK => Clock, Q => DF1_2_Q);
1833 DF1_79 : DF1
1834 port map(D => PP1_5_net, CLK => Clock, Q => DF1_79_Q);
1835 FA1_87 : FA1
1836 port map(A => FA1_63_CO, B => DF1_1_Q, CI => FA1_71_S,
1837 CO => FA1_87_CO, S => FA1_87_S);
1838 DF1_SumA_14_inst : DF1
1839 port map(D => FA1_96_CO, CLK => Clock, Q => SumA_14_net);
1840 DF1_105 : DF1
1841 port map(D => PP6_11_net, CLK => Clock, Q => DF1_105_Q);
1842 DF1_44 : DF1
1843 port map(D => PP5_9_net, CLK => Clock, Q => DF1_44_Q);
1844 DF1_52 : DF1
1845 port map(D => PP7_2_net, CLK => Clock, Q => DF1_52_Q);
1846 BUF_40 : BUFF
1847 port map(A => DataA(15), Y => BUF_40_Y);
1848 DF1_116 : DF1
1849 port map(D => E_7_net, CLK => Clock, Q => DF1_116_Q);
1850 AO6_98 : AO6
1851 port map(A => BUF_5_Y, B => AO16_13_Y, C => BUF_14_Y, D =>
1852 XOR2_25_Y, Y => AO6_98_Y);
1853 DF1_SumA_27_inst : DF1
1854 port map(D => FA1_91_CO, CLK => Clock, Q => SumA_27_net);
1855 FA1_58 : FA1
1856 port map(A => FA1_29_CO, B => HA1_15_CO, CI => FA1_14_S,
1857 CO => FA1_58_CO, S => FA1_58_S);
1858 FA1_52 : FA1
1859 port map(A => HA1_14_CO, B => DF1_7_Q, CI => FA1_50_CO,
1860 CO => FA1_52_CO, S => FA1_52_S);
1861 MX2_PP2_16_inst : MX2
1862 port map(A => MX2_0_Y, B => AO1_2_Y, S => AO16_9_Y, Y =>
1863 PP2_16_net);
1864 XOR2_PP0_10_inst : XOR2
1865 port map(A => AO6_48_Y, B => BUF_23_Y, Y => PP0_10_net);
1866 AO6_1 : AO6
1867 port map(A => BUF_14_Y, B => AO16_3_Y, C => BUF_10_Y, D =>
1868 XOR2_4_Y, Y => AO6_1_Y);
1869 AO6_113 : AO6
1870 port map(A => BUF_24_Y, B => AO16_3_Y, C => BUF_16_Y, D =>
1871 XOR2_4_Y, Y => AO6_113_Y);
1872 XOR2_PP6_2_inst : XOR2
1873 port map(A => AO6_64_Y, B => BUF_17_Y, Y => PP6_2_net);
1874 FA1_21 : FA1
1875 port map(A => DF1_35_Q, B => DF1_108_Q, CI => DF1_134_Q,
1876 CO => FA1_21_CO, S => FA1_21_S);
1877 BUF_42 : BUFF
1878 port map(A => DataA(11), Y => BUF_42_Y);
1879 FA1_73 : FA1
1880 port map(A => FA1_7_CO, B => FA1_9_S, CI => FA1_54_S, CO =>
1881 FA1_73_CO, S => FA1_73_S);
1882 AND2_5 : AND2
1883 port map(A => XOR2_17_Y, B => BUF_29_Y, Y => AND2_5_Y);
1884 XOR2_28 : XOR2
1885 port map(A => DataB(5), B => DataB(6), Y => XOR2_28_Y);
1886 FA1_27 : FA1
1887 port map(A => FA1_67_CO, B => HA1_1_CO, CI => FA1_86_S,
1888 CO => FA1_27_CO, S => FA1_27_S);
1889 XOR2_PP5_10_inst : XOR2
1890 port map(A => AO6_104_Y, B => BUF_41_Y, Y => PP5_10_net);
1891 DF1_SumB_10_inst : DF1
1892 port map(D => FA1_72_S, CLK => Clock, Q => SumB_10_net);
1893 AO6_47 : AO6
1894 port map(A => BUF_5_Y, B => AO16_10_Y, C => BUF_14_Y, D =>
1895 XOR2_21_Y, Y => AO6_47_Y);
1896 DF1_SumB_3_inst : DF1
1897 port map(D => FA1_84_S, CLK => Clock, Q => SumB_3_net);
1898 DF1_6 : DF1
1899 port map(D => PP4_1_net, CLK => Clock, Q => DF1_6_Q);
1900 XOR2_PP4_15_inst : XOR2
1901 port map(A => AO6_75_Y, B => BUF_33_Y, Y => PP4_15_net);
1902 XOR2_PP1_11_inst : XOR2
1903 port map(A => AO6_84_Y, B => BUF_11_Y, Y => PP1_11_net);
1904 BUF_9 : BUFF
1905 port map(A => DataA(10), Y => BUF_9_Y);
1906 XOR2_1 : XOR2
1907 port map(A => AND2_3_Y, B => BUF_17_Y, Y => XOR2_1_Y);
1908 DF1_SumB_15_inst : DF1
1909 port map(D => FA1_59_S, CLK => Clock, Q => SumB_15_net);
1910 XOR2_PP7_12_inst : XOR2
1911 port map(A => AO6_117_Y, B => BUF_20_Y, Y => PP7_12_net);
1912 AO6_48 : AO6
1913 port map(A => BUF_10_Y, B => AND2A_1_Y, C => BUF_43_Y, D =>
1914 DataB(0), Y => AO6_48_Y);
1915 XOR2_PP1_7_inst : XOR2
1916 port map(A => AO6_68_Y, B => BUF_18_Y, Y => PP1_7_net);
1917 BUF_17 : BUFF
1918 port map(A => DataB(13), Y => BUF_17_Y);
1919 XOR2_8 : XOR2
1920 port map(A => DataB(11), B => DataB(12), Y => XOR2_8_Y);
1921 BUF_27 : BUFF
1922 port map(A => DataA(2), Y => BUF_27_Y);
1923 XOR2_PP3_12_inst : XOR2
1924 port map(A => AO6_100_Y, B => BUF_3_Y, Y => PP3_12_net);
1925 FA1_31 : FA1
1926 port map(A => DF1_51_Q, B => DF1_77_Q, CI => DF1_142_Q,
1927 CO => FA1_31_CO, S => FA1_31_S);
1928 ADD1_Mult_14_inst : ADD1
1929 port map(A => SumA_13_net, B => SumB_13_net, FCI =>
1930 ADD1_Mult_13_FCO, S => Mult(14), FCO => ADD1_Mult_14_FCO);
1931 DF1_48 : DF1
1932 port map(D => PP3_15_net, CLK => Clock, Q => DF1_48_Q);
1933 ADD1_Mult_2_inst : ADD1
1934 port map(A => SumA_1_net, B => SumB_1_net, FCI =>
1935 ADD1_Mult_1_FCO, S => Mult(2), FCO => ADD1_Mult_2_FCO);
1936 XOR2_PP5_5_inst : XOR2
1937 port map(A => AO6_50_Y, B => BUF_47_Y, Y => PP5_5_net);
1938 FA1_37 : FA1
1939 port map(A => HA1_0_CO, B => DF1_86_Q, CI => FA1_26_S,
1940 CO => FA1_37_CO, S => FA1_37_S);
1941 XOR2_PP1_14_inst : XOR2
1942 port map(A => AO6_78_Y, B => BUF_11_Y, Y => PP1_14_net);
1943 AO6_57 : AO6
1944 port map(A => BUF_31_Y, B => AO16_2_Y, C => BUF_40_Y, D =>
1945 XOR2_6_Y, Y => AO6_57_Y);
1946 FA1_13 : FA1
1947 port map(A => FA1_24_CO, B => HA1_12_CO, CI => FA1_90_S,
1948 CO => FA1_13_CO, S => FA1_13_S);
1949 ADD1_Mult_19_inst : ADD1
1950 port map(A => SumA_18_net, B => SumB_18_net, FCI =>
1951 ADD1_Mult_18_FCO, S => Mult(19), FCO => ADD1_Mult_19_FCO);
1952 AO6_14 : AO6
1953 port map(A => BUF_8_Y, B => AO16_12_Y, C => BUF_35_Y, D =>
1954 XOR2_2_Y, Y => AO6_14_Y);
1955 AO1_6 : AO1
1956 port map(A => XOR2_7_Y, B => OR3_0_Y, C => AND3_3_Y, Y =>
1957 AO1_6_Y);
1958 DF1_SumA_4_inst : DF1
1959 port map(D => FA1_84_CO, CLK => Clock, Q => SumA_4_net);
1960 XOR2_PP4_5_inst : XOR2
1961 port map(A => AO6_71_Y, B => BUF_37_Y, Y => PP4_5_net);
1962 XOR2_PP3_2_inst : XOR2
1963 port map(A => AO6_108_Y, B => BUF_12_Y, Y => PP3_2_net);
1964 ADD1_Mult_11_inst : ADD1
1965 port map(A => SumA_10_net, B => SumB_10_net, FCI =>
1966 ADD1_Mult_10_FCO, S => Mult(11), FCO => ADD1_Mult_11_FCO);
1967 DF1_92 : DF1
1968 port map(D => S_4_net, CLK => Clock, Q => DF1_92_Q);
1969 FA1_61 : FA1
1970 port map(A => FA1_41_CO, B => HA1_2_S, CI => FA1_85_S,
1971 CO => FA1_61_CO, S => FA1_61_S);
1972 XOR2_PP5_7_inst : XOR2
1973 port map(A => AO6_28_Y, B => BUF_47_Y, Y => PP5_7_net);
1974 AND3_5 : AND3
1975 port map(A => DataB(9), B => DataB(10), C => DataB(11),
1976 Y => AND3_5_Y);
1977 FA1_95 : FA1
1978 port map(A => FA1_25_CO, B => FA1_34_S, CI => FA1_0_S,
1979 CO => FA1_95_CO, S => FA1_95_S);
1980 AO6_58 : AO6
1981 port map(A => BUF_35_Y, B => AO16_1_Y, C => BUF_25_Y, D =>
1982 XOR2_10_Y, Y => AO6_58_Y);
1983 DF1_121 : DF1
1984 port map(D => PP4_9_net, CLK => Clock, Q => DF1_121_Q);
1985 FA1_67 : FA1
1986 port map(A => DF1_76_Q, B => DF1_110_Q, CI => DF1_131_Q,
1987 CO => FA1_67_CO, S => FA1_67_S);
1988 DF1_1 : DF1
1989 port map(D => PP7_0_net, CLK => Clock, Q => DF1_1_Q);
1990 AO6_70 : AO6
1991 port map(A => BUF_5_Y, B => AO16_11_Y, C => BUF_14_Y, D =>
1992 XOR2_17_Y, Y => AO6_70_Y);
1993 XOR2_PP7_2_inst : XOR2
1994 port map(A => AO6_118_Y, B => BUF_22_Y, Y => PP7_2_net);
1995 BUF_41 : BUFF
1996 port map(A => DataB(11), Y => BUF_41_Y);
1997 FA1_43 : FA1
1998 port map(A => DF1_115_Q, B => DF1_23_Q, CI => DF1_24_Q,
1999 CO => FA1_43_CO, S => FA1_43_S);
2000 FA1_76 : FA1
2001 port map(A => FA1_57_CO, B => FA1_5_S, CI => FA1_7_S, CO =>
2002 FA1_76_CO, S => FA1_76_S);
2003 OR3_5 : OR3
2004 port map(A => DataB(5), B => DataB(6), C => DataB(7), Y =>
2005 OR3_5_Y);
2006 DF1_147 : DF1
2007 port map(D => PP2_10_net, CLK => Clock, Q => DF1_147_Q);
2008 XOR2_PP1_4_inst : XOR2
2009 port map(A => AO6_46_Y, B => BUF_18_Y, Y => PP1_4_net);
2010 AO6_19 : AO6
2011 port map(A => BUF_27_Y, B => AO16_10_Y, C => BUF_28_Y, D =>
2012 XOR2_21_Y, Y => AO6_19_Y);
2013 DF1_3 : DF1
2014 port map(D => PP6_1_net, CLK => Clock, Q => DF1_3_Q);
2015 DF1_128 : DF1
2016 port map(D => E_1_net, CLK => Clock, Q => DF1_128_Q);
2017 FA1_83 : FA1
2018 port map(A => DF1_13_Q, B => DF1_95_Q, CI => DF1_139_Q,
2019 CO => FA1_83_CO, S => FA1_83_S);
2020 DF1_SumB_24_inst : DF1
2021 port map(D => FA1_69_S, CLK => Clock, Q => SumB_24_net);
2022 FA1_74 : FA1
2023 port map(A => FA1_48_CO, B => FA1_18_S, CI => FA1_92_S,
2024 CO => FA1_74_CO, S => FA1_74_S);
2025 HA1_S_0_inst : HA1
2026 port map(A => XOR2_16_Y, B => DataB(1), CO => S_0_net, S =>
2027 PP0_0_net);
2028 AO6_80 : AO6
2029 port map(A => BUF_7_Y, B => AO16_10_Y, C => BUF_5_Y, D =>
2030 XOR2_21_Y, Y => AO6_80_Y);
2031 ADD1_Mult_31_inst : ADD1
2032 port map(A => SumA_30_net, B => SumB_30_net, FCI =>
2033 ADD1_Mult_30_FCO, S => Mult(31), FCO => ADD1_Mult_31_FCO);
2034 AND3_3 : AND3
2035 port map(A => DataB(11), B => DataB(12), C => DataB(13),
2036 Y => AND3_3_Y);
2037 DF1_23 : DF1
2038 port map(D => PP0_16_net, CLK => Clock, Q => DF1_23_Q);
2039 AO6_91 : AO6
2040 port map(A => BUF_31_Y, B => AO16_8_Y, C => BUF_40_Y, D =>
2041 XOR2_3_Y, Y => AO6_91_Y);
2042 AO6_112 : AO6
2043 port map(A => BUF_25_Y, B => AO16_1_Y, C => BUF_4_Y, D =>
2044 XOR2_10_Y, Y => AO6_112_Y);
2045 AO16_10 : AO16
2046 port map(A => DataB(3), B => DataB(4), C => BUF_34_Y, Y =>
2047 AO16_10_Y);
2048 ADD1_Mult_8_inst : ADD1
2049 port map(A => SumA_7_net, B => SumB_7_net, FCI =>
2050 ADD1_Mult_7_FCO, S => Mult(8), FCO => ADD1_Mult_8_FCO);
2051 AO6_117 : AO6
2052 port map(A => BUF_15_Y, B => AO16_6_Y, C => BUF_1_Y, D =>
2053 XOR2_18_Y, Y => AO6_117_Y);
2054 AOI1_E_3_inst : AOI1
2055 port map(A => XOR2_15_Y, B => OR3_5_Y, C => AND3_4_Y, Y =>
2056 E_3_net);
2057 DF1_20 : DF1
2058 port map(D => PP1_8_net, CLK => Clock, Q => DF1_20_Q);
2059 AO6_75 : AO6
2060 port map(A => BUF_31_Y, B => AO16_0_Y, C => BUF_40_Y, D =>
2061 XOR2_5_Y, Y => AO6_75_Y);
2062 AO6_63 : AO6
2063 port map(A => BUF_7_Y, B => AND2A_0_Y, C => BUF_5_Y, D =>
2064 DataB(0), Y => AO6_63_Y);
2065 DF1_140 : DF1
2066 port map(D => PP0_12_net, CLK => Clock, Q => DF1_140_Q);
2067 FA1_23 : FA1
2068 port map(A => FA1_32_CO, B => FA1_28_S, CI => FA1_58_S,
2069 CO => FA1_23_CO, S => FA1_23_S);
2070 MX2_PP4_16_inst : MX2
2071 port map(A => MX2_6_Y, B => AO1_0_Y, S => AO16_0_Y, Y =>
2072 PP4_16_net);
2073 ADD1_Mult_20_inst : ADD1
2074 port map(A => SumA_19_net, B => SumB_19_net, FCI =>
2075 ADD1_Mult_19_FCO, S => Mult(20), FCO => ADD1_Mult_20_FCO);
2076 DF1_122 : DF1
2077 port map(D => PP3_9_net, CLK => Clock, Q => DF1_122_Q);
2078 DF1_25 : DF1
2079 port map(D => PP0_2_net, CLK => Clock, Q => DF1_25_Q);
2080 AO1_5 : AO1
2081 port map(A => XOR2_13_Y, B => OR3_2_Y, C => AND3_6_Y, Y =>
2082 AO1_5_Y);
2083 DF1_SumB_19_inst : DF1
2084 port map(D => FA1_2_S, CLK => Clock, Q => SumB_19_net);
2085 DF1_113 : DF1
2086 port map(D => PP6_10_net, CLK => Clock, Q => DF1_113_Q);
2087 DF1_SumA_5_inst : DF1
2088 port map(D => FA1_82_CO, CLK => Clock, Q => SumA_5_net);
2089 DF1_84 : DF1
2090 port map(D => PP2_9_net, CLK => Clock, Q => DF1_84_Q);
2091 FA1_16 : FA1
2092 port map(A => FA1_92_CO, B => FA1_21_S, CI => FA1_45_S,
2093 CO => FA1_16_CO, S => FA1_16_S);
2094 XOR2_PP2_3_inst : XOR2
2095 port map(A => AO6_19_Y, B => BUF_34_Y, Y => PP2_3_net);
2096 ADD1_Mult_26_inst : ADD1
2097 port map(A => SumA_25_net, B => SumB_25_net, FCI =>
2098 ADD1_Mult_25_FCO, S => Mult(26), FCO => ADD1_Mult_26_FCO);
2099 DF1_139 : DF1
2100 port map(D => PP5_7_net, CLK => Clock, Q => DF1_139_Q);
2101 AO6_85 : AO6
2102 port map(A => BUF_13_Y, B => AO16_1_Y, C => BUF_44_Y, D =>
2103 XOR2_10_Y, Y => AO6_85_Y);
2104 AOI1_E_5_inst : AOI1
2105 port map(A => XOR2_19_Y, B => OR3_3_Y, C => AND3_5_Y, Y =>
2106 E_5_net);
2107 AND3_6 : AND3
2108 port map(A => DataB(1), B => DataB(2), C => DataB(3), Y =>
2109 AND3_6_Y);
2110 MX2_5 : MX2
2111 port map(A => BUF_6_Y, B => XOR2_7_Y, S => XOR2_3_Y, Y =>
2112 MX2_5_Y);
2113 AO6_62 : AO6
2114 port map(A => BUF_39_Y, B => AO16_11_Y, C => BUF_45_Y, D =>
2115 XOR2_17_Y, Y => AO6_62_Y);
2116 DF1_5 : DF1
2117 port map(D => PP4_16_net, CLK => Clock, Q => DF1_5_Q);
2118 FA1_14 : FA1
2119 port map(A => DF1_144_Q, B => DF1_20_Q, CI => DF1_41_Q,
2120 CO => FA1_14_CO, S => FA1_14_S);
2121 DF1_63 : DF1
2122 port map(D => PP0_11_net, CLK => Clock, Q => DF1_63_Q);
2123 AO6_41 : AO6
2124 port map(A => BUF_14_Y, B => AND2A_1_Y, C => BUF_10_Y, D =>
2125 DataB(0), Y => AO6_41_Y);
2126 AO6_20 : AO6
2127 port map(A => BUF_38_Y, B => AO16_0_Y, C => BUF_9_Y, D =>
2128 XOR2_5_Y, Y => AO6_20_Y);
2129 DF1_109 : DF1
2130 port map(D => PP6_3_net, CLK => Clock, Q => DF1_109_Q);
2131 BUF_35 : BUFF
2132 port map(A => DataA(1), Y => BUF_35_Y);
2133 DF1_46 : DF1
2134 port map(D => PP4_6_net, CLK => Clock, Q => DF1_46_Q);
2135 end DEF_ARCH;
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1 -- Version: 9.1 SP5 9.1.5.1
2
3 library ieee;
4 use ieee.std_logic_1164.all;
5 library Axcelerator;
6 use Axcelerator.all;
7
8 entity actram is
9 port( DI : in std_logic_vector(31 downto 0); DO : out
10 std_logic_vector(31 downto 0); WADDR : in
11 std_logic_vector(6 downto 0); RADDR : in
12 std_logic_vector(6 downto 0);WRB, RDB, WCLOCK, RCLOCK :
13 in std_logic) ;
14 end actram;
15
16
17 architecture DEF_ARCH of actram is
18
19 component INV
20 port(A : in std_logic := 'U'; Y : out std_logic) ;
21 end component;
22
23 component RAM64K36P
24 generic (MEMORYFILE:string := "");
25
26 port(WCLK, RCLK, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WEN, WW0,
27 WW1, WW2, WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6,
28 WRAD7, WRAD8, WRAD9, WRAD10, WRAD11, WRAD12, WRAD13,
29 WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6, WD7,
30 WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17,
31 WD18, WD19, WD20, WD21, WD22, WD23, WD24, WD25, WD26,
32 WD27, WD28, WD29, WD30, WD31, WD32, WD33, WD34, WD35, REN,
33 RW0, RW1, RW2, RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5,
34 RDAD6, RDAD7, RDAD8, RDAD9, RDAD10, RDAD11, RDAD12,
35 RDAD13, RDAD14, RDAD15 : in std_logic := 'U'; RD0, RD1,
36 RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12,
37 RD13, RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21,
38 RD22, RD23, RD24, RD25, RD26, RD27, RD28, RD29, RD30,
39 RD31, RD32, RD33, RD34, RD35 : out std_logic) ;
40 end component;
41
42 component VCC
43 port( Y : out std_logic);
44 end component;
45
46 component GND
47 port( Y : out std_logic);
48 end component;
49
50 signal WEP, REP, VCC_1_net, GND_1_net : std_logic ;
51 begin
52
53 VCC_2_net : VCC port map(Y => VCC_1_net);
54 GND_2_net : GND port map(Y => GND_1_net);
55 REBUBBLE : INV
56 port map(A => RDB, Y => REP);
57 WEBUBBLE : INV
58 port map(A => WRB, Y => WEP);
59 actram_R0C0 : RAM64K36P
60 port map(WCLK => WCLOCK, RCLK => RCLOCK, DEPTH0 =>
61 GND_1_net, DEPTH1 => GND_1_net, DEPTH2 => GND_1_net,
62 DEPTH3 => GND_1_net, WEN => WEP, WW0 => VCC_1_net, WW1 =>
63 GND_1_net, WW2 => VCC_1_net, WRAD0 => WADDR(0), WRAD1 =>
64 WADDR(1), WRAD2 => WADDR(2), WRAD3 => WADDR(3), WRAD4 =>
65 WADDR(4), WRAD5 => WADDR(5), WRAD6 => WADDR(6), WRAD7 =>
66 GND_1_net, WRAD8 => GND_1_net, WRAD9 => GND_1_net,
67 WRAD10 => GND_1_net, WRAD11 => GND_1_net, WRAD12 =>
68 GND_1_net, WRAD13 => GND_1_net, WRAD14 => GND_1_net,
69 WRAD15 => GND_1_net, WD0 => DI(0), WD1 => DI(1), WD2 =>
70 DI(2), WD3 => DI(3), WD4 => DI(4), WD5 => DI(5), WD6 =>
71 DI(6), WD7 => DI(7), WD8 => DI(8), WD9 => DI(9), WD10 =>
72 DI(10), WD11 => DI(11), WD12 => DI(12), WD13 => DI(13),
73 WD14 => DI(14), WD15 => DI(15), WD16 => DI(16), WD17 =>
74 DI(17), WD18 => DI(18), WD19 => DI(19), WD20 => DI(20),
75 WD21 => DI(21), WD22 => DI(22), WD23 => DI(23), WD24 =>
76 DI(24), WD25 => DI(25), WD26 => DI(26), WD27 => DI(27),
77 WD28 => DI(28), WD29 => DI(29), WD30 => DI(30), WD31 =>
78 DI(31), WD32 => GND_1_net, WD33 => GND_1_net, WD34 =>
79 GND_1_net, WD35 => GND_1_net, REN => REP, RW0 =>
80 VCC_1_net, RW1 => GND_1_net, RW2 => VCC_1_net, RDAD0 =>
81 RADDR(0), RDAD1 => RADDR(1), RDAD2 => RADDR(2), RDAD3 =>
82 RADDR(3), RDAD4 => RADDR(4), RDAD5 => RADDR(5), RDAD6 =>
83 RADDR(6), RDAD7 => GND_1_net, RDAD8 => GND_1_net,
84 RDAD9 => GND_1_net, RDAD10 => GND_1_net, RDAD11 =>
85 GND_1_net, RDAD12 => GND_1_net, RDAD13 => GND_1_net,
86 RDAD14 => GND_1_net, RDAD15 => GND_1_net, RD0 => DO(0),
87 RD1 => DO(1), RD2 => DO(2), RD3 => DO(3), RD4 => DO(4),
88 RD5 => DO(5), RD6 => DO(6), RD7 => DO(7), RD8 => DO(8),
89 RD9 => DO(9), RD10 => DO(10), RD11 => DO(11), RD12 =>
90 DO(12), RD13 => DO(13), RD14 => DO(14), RD15 => DO(15),
91 RD16 => DO(16), RD17 => DO(17), RD18 => DO(18), RD19 =>
92 DO(19), RD20 => DO(20), RD21 => DO(21), RD22 => DO(22),
93 RD23 => DO(23), RD24 => DO(24), RD25 => DO(25), RD26 =>
94 DO(26), RD27 => DO(27), RD28 => DO(28), RD29 => DO(29),
95 RD30 => DO(30), RD31 => DO(31), RD32 => OPEN , RD33 =>
96 OPEN , RD34 => OPEN , RD35 => OPEN );
97 end DEF_ARCH;
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: fftDp.vhd
10 -- Description: CoreFFT
11 -- FFT dapa path module
12 -- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
13 --
14 --
15 --------------------------------------------------------------------------------
16 -------------------------------- SWITCH -------------------------------
17 -- if (sel) straight, else cross
18 LIBRARY IEEE;
19 USE IEEE.std_logic_1164.all;
20
21 ENTITY switch IS
22 GENERIC ( DWIDTH : integer := 32 );
23 PORT (
24 clk, sel, validIn : IN std_logic;
25 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
26 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
27 validOut : OUT std_logic);
28 END ENTITY switch;
29
30 ARCHITECTURE translated OF switch IS
31 CONSTANT tscale : time := 1 ns;
32
33 SIGNAL leftQ_r, rightP_r : std_logic_vector(DWIDTH-1 DOWNTO 0);
34 SIGNAL pipe1 : std_logic;
35 SIGNAL muxP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
36 SIGNAL muxQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
37 SIGNAL temp_xhdl4 : std_logic_vector(DWIDTH-1 DOWNTO 0);
38 SIGNAL temp_xhdl5 : std_logic_vector(DWIDTH-1 DOWNTO 0);
39 SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0);
40 SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0);
41 SIGNAL validOut_xhdl3 : std_logic;
42
43 BEGIN
44 outP <= outP_xhdl1;
45 outQ <= outQ_xhdl2;
46 validOut <= validOut_xhdl3;
47 temp_xhdl4 <= leftQ_r WHEN sel = '1' ELSE inP;
48 muxP_w <= temp_xhdl4 ;
49 temp_xhdl5 <= leftQ_r WHEN NOT sel = '1' ELSE inP;
50 muxQ_w <= temp_xhdl5 ;
51
52 PROCESS (clk)
53 BEGIN
54 IF (clk'EVENT AND clk = '1') THEN
55 outP_xhdl1 <= rightP_r AFTER tscale;
56 outQ_xhdl2 <= muxQ_w AFTER tscale;
57 leftQ_r <= inQ AFTER tscale;
58 rightP_r <= muxP_w AFTER tscale;
59 validOut_xhdl3 <= pipe1 AFTER tscale;
60 pipe1 <= validIn AFTER tscale;
61 END IF;
62 END PROCESS;
63 END ARCHITECTURE translated;
64
65 ---------------------------- B U T T E R F L Y --------------------------------
66 ------------------------- Simple Round Up: 1-clk delay ----------------------V
67 ---------- Use it when it is known INBITWIDTH > OUTBITWIDTH --------------------
68 LIBRARY IEEE;
69 USE IEEE.std_logic_1164.all;
70 USE IEEE.numeric_std.all;
71
72 ENTITY kitRndUp IS
73 GENERIC (OUTBITWIDTH : integer := 12;
74 RND_MODE : integer := 0 );
75 PORT (nGrst, rst, clk, clkEn : IN std_logic;
76 inp : IN std_logic_vector(OUTBITWIDTH DOWNTO 0);
77 valInp : IN std_logic;
78 outp : OUT std_logic_vector(OUTBITWIDTH-1 DOWNTO 0);
79 valOutp : OUT std_logic);
80 END ENTITY kitRndUp;
81
82 ARCHITECTURE rtl OF kitRndUp IS
83 CONSTANT tscale : time := 1 ns;
84
85 SIGNAL int_outp : signed(OUTBITWIDTH DOWNTO 0);
86 SIGNAL int_valOutp : std_logic;
87
88 BEGIN
89 outp <= std_logic_vector(int_outp(OUTBITWIDTH DOWNTO 1));
90 valOutp <= int_valOutp;
91
92 PROCESS (clk, nGrst)
93 BEGIN
94 IF (NOT nGrst = '1') THEN
95 int_outp <= to_signed(0, OUTBITWIDTH+1);
96 int_valOutp <= '0';
97 ELSIF (clk'EVENT AND clk = '1') THEN
98 IF (rst = '1') THEN
99 int_outp <= to_signed(0, OUTBITWIDTH+1) AFTER tscale;
100 int_valOutp <= '0' AFTER 1 ns;
101 ELSIF (clkEn = '1') THEN
102 IF (valInp = '1') THEN
103 IF(RND_MODE = 1) THEN
104 int_outp <= signed(inp) + to_signed(1, OUTBITWIDTH+1) AFTER tscale;
105 ELSE int_outp <= signed(inp);
106 END IF;
107 END IF;
108 int_valOutp <= valInp AFTER tscale;
109 END IF; --rst and no rst
110 END IF; --nGrst and no nGrst
111 END PROCESS;
112 END ARCHITECTURE rtl;
113
114 -------------------------------- MULT -----------------------------V
115 library IEEE;
116 use IEEE.STD_LOGIC_1164.all;
117
118 ENTITY agen IS
119 GENERIC ( RND_MODE : integer := 0;
120 WSIZE : integer := 16;
121 DWIDTH : integer := 16;
122 TWIDTH : integer := 16 );
123 PORT ( -- synthesis syn_preserve=1
124 clk : IN std_logic;
125 a : IN std_logic_vector(WSIZE-1 DOWNTO 0);
126 t : IN std_logic_vector(TWIDTH-1 DOWNTO 0);
127 arout : OUT std_logic_vector(WSIZE-1 DOWNTO 0));
128 END ENTITY agen;
129
130 ARCHITECTURE rtl OF agen IS
131 CONSTANT tscale : time := 1 ns;
132 COMPONENT actar
133 PORT (DataA : IN std_logic_vector(WSIZE-1 DOWNTO 0);
134 DataB : IN std_logic_vector(TWIDTH-1 DOWNTO 0);
135 Mult : OUT std_logic_vector(WSIZE+TWIDTH-1 DOWNTO 0);
136 Clock : IN std_logic );
137 END COMPONENT;
138
139 COMPONENT kitRndUp
140 GENERIC (
141 OUTBITWIDTH : integer := 12;
142 RND_MODE : integer := 0 );
143 PORT (nGrst, rst, clk, clkEn : IN std_logic;
144 inp : IN std_logic_vector(OUTBITWIDTH DOWNTO 0);
145 valInp : IN std_logic;
146 outp : OUT std_logic_vector(OUTBITWIDTH-1 DOWNTO 0);
147 valOutp : OUT std_logic);
148 END COMPONENT;
149
150 SIGNAL a_r : std_logic_vector(WSIZE-1 DOWNTO 0);
151 SIGNAL t_r : std_logic_vector(TWIDTH-1 DOWNTO 0);
152 SIGNAL out1 : std_logic_vector(WSIZE DOWNTO 0);
153 SIGNAL out_w : std_logic_vector(WSIZE+TWIDTH-1 DOWNTO 0);
154 SIGNAL out_VHDL : std_logic_vector(WSIZE-1 DOWNTO 0);
155
156 BEGIN
157 arout <= out_VHDL;
158 actar_0 : actar
159 PORT MAP (DataA => a_r, DataB => t_r, Mult => out_w, Clock => clk);
160
161 kitRndUp_0: kitRndUp
162 GENERIC MAP ( OUTBITWIDTH => WSIZE, RND_MODE => RND_MODE )
163 PORT MAP (nGrst => '1', rst => '0', clk => clk, clkEn => '1',
164 inp => out1, valInp => '1', outp => out_VHDL, valOutp => open);
165
166 PROCESS (clk)
167 BEGIN
168 IF (clk'EVENT AND clk = '1') THEN
169 a_r <= a AFTER tscale;
170 t_r <= t AFTER tscale;
171
172 out1 <= out_w(DWIDTH-1 DOWNTO WSIZE-1) AFTER tscale;
173 END IF;
174 END PROCESS;
175 END ARCHITECTURE rtl;
176 -------------------------------------------------------------------------------
177
178 library IEEE;
179 use IEEE.STD_LOGIC_1164.all;
180 use IEEE.STD_LOGIC_UNSIGNED.all;
181 use IEEE.STD_LOGIC_ARITH.all;
182
183 ENTITY bfly2 IS
184 GENERIC ( RND_MODE : integer := 0;
185 WSIZE : integer := 16;
186 DWIDTH : integer := 32;
187 TWIDTH : integer := 16;
188 TDWIDTH : integer := 32 );
189 PORT (clk, validIn : IN std_logic;
190 swCrossIn : IN std_logic;
191 upScale : IN std_logic; --don't do downscaling if upScale==1
192 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
193 T : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
194 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
195 --Signals need to be delayed by the bfly latency. That's why they are here
196 validOut, swCrossOut : OUT std_logic);
197 END ENTITY bfly2;
198
199 ARCHITECTURE translated OF bfly2 IS
200 CONSTANT tscale : time := 1 ns;
201
202 COMPONENT agen
203 GENERIC ( RND_MODE : integer := 0;
204 WSIZE : integer := 16;
205 DWIDTH : integer := 16;
206 TWIDTH : integer := 16 );
207 PORT (clk : IN std_logic;
208 a : IN std_logic_vector(WSIZE-1 DOWNTO 0);
209 t : IN std_logic_vector(TWIDTH-1 DOWNTO 0);
210 arout : OUT std_logic_vector(WSIZE-1 DOWNTO 0));
211 END COMPONENT;
212
213 -- CONVENTION: real - LSBs[15:0], imag - MSBs[31:16]
214 SIGNAL inPr_w, inPi_w, inQr_w, inQi_w : std_logic_vector(WSIZE-1 DOWNTO 0);
215 SIGNAL Tr_w, Ti_w : std_logic_vector(TWIDTH-1 DOWNTO 0);
216 SIGNAL Hr_w, Hi_w, Hr, Hi : std_logic_vector(WSIZE-1 DOWNTO 0);
217 SIGNAL PrT1_r, PrT2_r, PrT3_r, PrT4_r : std_logic_vector(WSIZE-1 DOWNTO 0);
218 SIGNAL PrT5_r, PrT6_r, PiT1_r, PiT2_r : std_logic_vector(WSIZE-1 DOWNTO 0);
219 SIGNAL PiT3_r, PiT4_r, PiT5_r, PiT6_r : std_logic_vector(WSIZE-1 DOWNTO 0);
220 SIGNAL QrTr_w, QiTi_w, QiTr_w, QrTi_w : std_logic_vector(WSIZE-1 DOWNTO 0);
221 SIGNAL pipe1,pipe2,pipe3,pipe4,pipe5 : std_logic_vector(1 DOWNTO 0);
222 SIGNAL pipe6 : std_logic_vector(1 DOWNTO 0);
223 -- select either 16-bit value or sign-extended 15-bit value (downscaled one)
224 SIGNAL temp_xhdl5 : std_logic_vector(WSIZE-1 DOWNTO 0);
225 SIGNAL temp_xhdl6 : std_logic_vector(DWIDTH-1 DOWNTO WSIZE);
226 -- select either 16-bit value or left-shifted value (upscaled one)
227 SIGNAL temp_xhdl7 : std_logic_vector(WSIZE-1 DOWNTO 0);
228 SIGNAL temp_xhdl8 : std_logic_vector(WSIZE-1 DOWNTO 0);
229 SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0);
230 SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0);
231 SIGNAL validOut_xhdl3 : std_logic;
232 SIGNAL swCrossOut_xhdl4 : std_logic;
233
234 BEGIN
235 outP <= outP_xhdl1;
236 outQ <= outQ_xhdl2;
237 validOut <= validOut_xhdl3;
238 swCrossOut <= swCrossOut_xhdl4;
239 Tr_w <= T(TWIDTH-1 DOWNTO 0) ;
240 Ti_w <= T(TDWIDTH-1 DOWNTO TWIDTH) ;
241 temp_xhdl5 <= inP(WSIZE-1 DOWNTO 0) WHEN upScale = '1' ELSE inP(WSIZE-1) &
242 inP(WSIZE-1 DOWNTO 1);
243 inPr_w <= temp_xhdl5 AFTER tscale;
244 temp_xhdl6 <= inP(DWIDTH-1 DOWNTO WSIZE) WHEN upScale = '1' ELSE inP(DWIDTH-1)
245 & inP(DWIDTH-1 DOWNTO WSIZE+1);
246 inPi_w <= temp_xhdl6 AFTER tscale;
247 temp_xhdl7 <= inQ(WSIZE-2 DOWNTO 0) & '0' WHEN upScale = '1' ELSE inQ(WSIZE-1
248 DOWNTO 0);
249 inQr_w <= temp_xhdl7 AFTER tscale;
250 temp_xhdl8 <= inQ(DWIDTH-2 DOWNTO WSIZE) & '0' WHEN upScale = '1' ELSE
251 inQ(DWIDTH-1 DOWNTO WSIZE);
252 inQi_w <= temp_xhdl8 AFTER tscale;
253
254 am3QrTr : agen
255 GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE,
256 DWIDTH => DWIDTH, TWIDTH => TWIDTH)
257 PORT MAP (clk => clk, a => inQr_w, t => Tr_w, arout => QrTr_w);
258 am3QiTi : agen
259 GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE,
260 DWIDTH => DWIDTH, TWIDTH => TWIDTH)
261 PORT MAP (clk => clk, a => inQi_w, t => Ti_w, arout => QiTi_w);
262 am3QiTr : agen
263 GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE,
264 DWIDTH => DWIDTH, TWIDTH => TWIDTH)
265 PORT MAP (clk => clk, a => inQi_w, t => Tr_w, arout => QiTr_w);
266 am3QrTi : agen
267 GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE,
268 DWIDTH => DWIDTH, TWIDTH => TWIDTH)
269 PORT MAP (clk => clk, a => inQr_w, t => Ti_w, arout => QrTi_w);
270
271 Hr_w <= QrTr_w + QiTi_w AFTER tscale;
272 Hi_w <= QiTr_w - QrTi_w AFTER tscale;
273
274 PROCESS (clk)
275 BEGIN
276 IF (clk'EVENT AND clk = '1') THEN
277 outQ_xhdl2(DWIDTH-1 DOWNTO WSIZE) <= PiT6_r - Hi AFTER tscale;
278 outQ_xhdl2(WSIZE-1 DOWNTO 0) <= PrT6_r - Hr AFTER tscale;
279 outP_xhdl1(DWIDTH-1 DOWNTO WSIZE) <= PiT6_r + Hi AFTER tscale;
280 outP_xhdl1(WSIZE-1 DOWNTO 0) <= PrT6_r + Hr AFTER tscale;
281 -- pipes
282
283 PrT6_r <= PrT5_r AFTER tscale; PiT6_r <= PiT5_r AFTER tscale;
284 PrT5_r <= PrT4_r AFTER tscale; PiT5_r <= PiT4_r AFTER tscale;
285 PrT4_r <= PrT3_r AFTER tscale; PiT4_r <= PiT3_r AFTER tscale;
286 PrT3_r <= PrT2_r AFTER tscale; PiT3_r <= PiT2_r AFTER tscale;
287 PrT2_r <= PrT1_r AFTER tscale; PiT2_r <= PiT1_r AFTER tscale;
288 PrT1_r <= inPr_w AFTER tscale; PiT1_r <= inPi_w AFTER tscale;
289 Hr <= Hr_w AFTER tscale; Hi <= Hi_w AFTER tscale;
290 validOut_xhdl3 <= pipe6(0) AFTER tscale;
291 swCrossOut_xhdl4 <= pipe6(1) AFTER tscale;
292 pipe6 <= pipe5 AFTER tscale; pipe5 <= pipe4 AFTER tscale;
293 pipe4 <= pipe3 AFTER tscale; pipe3 <= pipe2 AFTER tscale;
294 pipe2 <= pipe1 AFTER tscale; pipe1(0) <= validIn AFTER tscale;
295 pipe1(1) <= swCrossIn AFTER tscale;
296 END IF;
297 END PROCESS;
298 END ARCHITECTURE translated;
299 --------------------------------------------------------------------------------
300
301 --********************************** B U F F E R *******************************
302 ----------------------------------- inBuffer ----------------------------------V
303 -- InBuf stores double complex words so that FFT engine can read two cmplx
304 -- words per clock. Thus the depth of the buffer is `LOGPTS-1
305 LIBRARY IEEE;
306 USE IEEE.std_logic_1164.all;
307
308 ENTITY inBuffer IS
309 GENERIC ( LOGPTS : integer := 8;
310 DWIDTH : integer := 32 );
311 PORT (
312 clk, clkEn : IN std_logic;
313 rA, wA_bfly, wA_load : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
314 -- new data to load, data coming from FFT engine
315 ldData, wP_bfly, wQ_bfly: IN std_logic_vector(DWIDTH-1 DOWNTO 0);
316 wEn_bfly : IN std_logic; --wEn to store FFT engine data
317 wEn_even, wEn_odd : IN std_logic; --wEn to store new data in even/odd subbuffers
318 rEn : IN std_logic; --used only by FFT engine
319 -- pipo=pong for pong buffer, =/pong for ping buffer
320 pipo : IN std_logic; --controls buffer input muxes.
321 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0)); -- output data to FFT engine
322 END ENTITY inBuffer;
323
324 ARCHITECTURE translated OF inBuffer IS
325 CONSTANT tscale : time := 1 ns;
326
327 COMPONENT wrapRam
328 GENERIC ( LOGPTS : integer := 8;
329 DWIDTH : integer := 32 );
330 PORT( clk, wEn : in std_logic;
331 wA, rA : in std_logic_vector(LOGPTS-2 downto 0);
332 D : in std_logic_vector(DWIDTH-1 downto 0);
333 Q : out std_logic_vector(DWIDTH-1 downto 0) );
334 end component;
335
336 -- internal wires, &-gates
337 SIGNAL wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
338 SIGNAL wP_w, wQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
339 SIGNAL wEn_P, wEn_Q : std_logic;
340 SIGNAL rEn_ce_w,wEnP_ce_w,wEnQ_ce_w : std_logic;
341 SIGNAL temp_xhdl3 : std_logic;
342 SIGNAL temp_xhdl4 : std_logic;
343 SIGNAL temp_xhdl5 : std_logic_vector(LOGPTS-2 DOWNTO 0);
344 SIGNAL temp_xhdl6 : std_logic_vector(DWIDTH-1 DOWNTO 0);
345 SIGNAL temp_xhdl7 : std_logic_vector(DWIDTH-1 DOWNTO 0);
346 SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0);
347 SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0);
348
349 BEGIN
350 outP <= outP_xhdl1;
351 outQ <= outQ_xhdl2;
352 rEn_ce_w <= rEn AND clkEn ;
353 wEnP_ce_w <= wEn_P AND clkEn ;
354 wEnQ_ce_w <= wEn_Q AND clkEn ;
355 temp_xhdl3 <= wEn_bfly WHEN pipo = '1' ELSE wEn_even;
356 wEn_P <= temp_xhdl3 ;
357 temp_xhdl4 <= wEn_bfly WHEN pipo = '1' ELSE wEn_odd;
358 wEn_Q <= temp_xhdl4 ;
359 temp_xhdl5 <= wA_bfly WHEN pipo = '1' ELSE wA_load;
360 wA_w <= temp_xhdl5 ;
361 temp_xhdl6 <= wP_bfly WHEN pipo = '1' ELSE ldData;
362 wP_w <= temp_xhdl6 ;
363 temp_xhdl7 <= wQ_bfly WHEN pipo = '1' ELSE ldData;
364 wQ_w <= temp_xhdl7 ;
365 -- if(~pipo) LOAD, else - RUN BFLY. Use MUX'es
366
367 -- instantiate two mem blocks `HALFPTS deep each
368 memP : wrapRam
369 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
370 PORT MAP (D => wP_w, Q => outP_xhdl1, wA => wA_w, rA => rA,
371 wEn => wEnP_ce_w, clk => clk);
372
373 memQ : wrapRam
374 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
375 PORT MAP (D => wQ_w, Q => outQ_xhdl2, wA => wA_w, rA => rA,
376 wEn => wEnQ_ce_w, clk => clk);
377 END ARCHITECTURE translated;
378 --------------------------------------------------------------------------------
379 ------------------------------- pipoBuffer ------------------------------------V
380 LIBRARY IEEE;
381 USE IEEE.std_logic_1164.all;
382
383 ENTITY pipoBuffer IS
384 GENERIC ( LOGPTS : integer := 8;
385 DWIDTH : integer := 32 );
386 PORT (
387 clk, clkEn, pong, rEn : IN std_logic;
388 rA, wA_load, wA_bfly : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
389 ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
390 wEn_bfly,wEn_even,wEn_odd : IN std_logic;
391 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) );
392 END ENTITY pipoBuffer;
393
394 ARCHITECTURE translated OF pipoBuffer IS
395 CONSTANT tscale : time := 1 ns;
396
397 COMPONENT inBuffer
398 GENERIC ( LOGPTS : integer := 8;
399 DWIDTH : integer := 32 );
400 PORT (
401 clk, clkEn, rEn, pipo : IN std_logic;
402 rA,wA_bfly,wA_load : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
403 ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
404 wEn_bfly,wEn_even,wEn_odd : IN std_logic;
405 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0));
406 END COMPONENT;
407
408 --internal signals
409 SIGNAL pi_outP, pi_outQ : std_logic_vector(DWIDTH-1 DOWNTO 0);
410 SIGNAL po_outP, po_outQ : std_logic_vector(DWIDTH-1 DOWNTO 0);
411 SIGNAL port_xhdl17 : std_logic;
412 SIGNAL temp_xhdl32 : std_logic_vector(DWIDTH-1 DOWNTO 0);
413 SIGNAL temp_xhdl33 : std_logic_vector(DWIDTH-1 DOWNTO 0);
414 SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0);
415 SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0);
416
417 BEGIN
418 outP <= outP_xhdl1;
419 outQ <= outQ_xhdl2;
420 port_xhdl17 <= NOT pong;
421 piBuf : inBuffer
422 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
423 PORT MAP (clk => clk, rA => rA, wA_bfly => wA_bfly,
424 wA_load => wA_load, ldData => ldData, wP_bfly => wP_bfly,
425 wQ_bfly => wQ_bfly, wEn_bfly => wEn_bfly,
426 wEn_even => wEn_even, wEn_odd => wEn_odd, rEn => rEn,
427 clkEn => clkEn, pipo => port_xhdl17,
428 outP => pi_outP, outQ => pi_outQ);
429
430 poBuf : inBuffer
431 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
432 PORT MAP (clk => clk, rA => rA, wA_bfly => wA_bfly,
433 wA_load => wA_load, ldData => ldData, wP_bfly => wP_bfly,
434 wQ_bfly => wQ_bfly, wEn_bfly => wEn_bfly,
435 wEn_even => wEn_even, wEn_odd => wEn_odd, rEn => rEn,
436 clkEn => clkEn, pipo => pong,
437 outP => po_outP, outQ => po_outQ);
438
439 temp_xhdl32 <= po_outP WHEN pong = '1' ELSE pi_outP;
440 outP_xhdl1 <= temp_xhdl32 ;
441 temp_xhdl33 <= po_outQ WHEN pong = '1' ELSE pi_outQ;
442 outQ_xhdl2 <= temp_xhdl33 ;
443
444 END ARCHITECTURE translated;
445 --------------------------------------------------------------------------------
446 --******************************* outBuffer *********************************V
447 LIBRARY IEEE;
448 USE IEEE.std_logic_1164.all;
449
450 ENTITY outBuff IS
451 GENERIC ( LOGPTS : integer := 8;
452 DWIDTH : integer := 32 );
453 PORT (
454 clk, clkEn, wEn : IN std_logic;
455 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
456 wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
457 rA : IN std_logic_vector(LOGPTS-1 DOWNTO 0);
458 outD : OUT std_logic_vector(DWIDTH-1 DOWNTO 0));
459 END ENTITY outBuff;
460
461 ARCHITECTURE translated OF outBuff IS
462 CONSTANT tscale : time := 1 ns;
463
464 COMPONENT wrapRam
465 GENERIC ( LOGPTS : integer := 8;
466 DWIDTH : integer := 32 );
467 PORT( clk, wEn : in std_logic;
468 wA, rA : in std_logic_vector(LOGPTS-2 downto 0);
469 D : in std_logic_vector(DWIDTH-1 downto 0);
470 Q : out std_logic_vector(DWIDTH-1 downto 0) );
471 end component;
472
473 SIGNAL wEn_r : std_logic;
474 SIGNAL inP_r, inQ_r : std_logic_vector(DWIDTH-1 DOWNTO 0);
475 SIGNAL wA_r : std_logic_vector(LOGPTS-2 DOWNTO 0);
476 SIGNAL rAmsb_r1, rAmsb_r2 : std_logic;
477 SIGNAL P_w, Q_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
478 SIGNAL outPQ : std_logic_vector(DWIDTH-1 DOWNTO 0);
479 SIGNAL temp_xhdl10 : std_logic_vector(DWIDTH-1 DOWNTO 0);
480 SIGNAL outD_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0);
481
482 BEGIN
483 outD <= outD_xhdl1;
484 outBuf_0 : wrapRam
485 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
486 PORT MAP (D => inP_r, Q => P_w, wA => wA_r,
487 rA => rA(LOGPTS-2 DOWNTO 0),
488 wEn => wEn_r, clk => clk);
489 outBuf_1 : wrapRam
490 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
491 PORT MAP (D => inQ_r, Q => Q_w, wA => wA_r,
492 rA => rA(LOGPTS-2 DOWNTO 0),
493 wEn => wEn_r, clk => clk);
494
495 temp_xhdl10 <= Q_w WHEN rAmsb_r2 = '1' ELSE P_w;
496 outPQ <= temp_xhdl10 ;
497
498 PROCESS (clk)
499 BEGIN
500 IF (clk'EVENT AND clk = '1') THEN
501 inP_r <= inP AFTER 1*tscale;
502 inQ_r <= inQ AFTER 1*tscale; -- pipes
503 wEn_r <= wEn AFTER 1*tscale;
504 wA_r <= wA AFTER 1*tscale;
505 rAmsb_r2 <= rAmsb_r1 AFTER 1*tscale;
506 rAmsb_r1 <= rA(LOGPTS-1) AFTER 1*tscale;
507 outD_xhdl1 <= outPQ AFTER 1*tscale;
508 END IF;
509 END PROCESS;
510 END ARCHITECTURE translated;
511 --------------------------------------------------------------------------------
512 --************************ T W I D D L E L U T ******************************V
513 -- RAM-block based twiddle LUT
514 LIBRARY IEEE;
515 USE IEEE.std_logic_1164.all;
516
517 ENTITY twidLUT IS
518 GENERIC ( LOGPTS : integer := 8;
519 TDWIDTH : integer := 32 );
520 PORT (
521 clk, wEn : IN std_logic;
522 wA, rA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
523 D : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
524 Q : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0));
525 END ENTITY twidLUT;
526
527 ARCHITECTURE translated OF twidLUT IS
528 CONSTANT tscale : time := 1 ns;
529
530 COMPONENT wrapRam
531 GENERIC ( LOGPTS : integer := 8;
532 DWIDTH : integer := 32 );
533 PORT( clk, wEn : in std_logic;
534 wA, rA : in std_logic_vector(LOGPTS-2 downto 0);
535 D : in std_logic_vector(TDWIDTH-1 downto 0);
536 Q : out std_logic_vector(TDWIDTH-1 downto 0) );
537 end component;
538
539 SIGNAL rA_r : std_logic_vector(LOGPTS-2 DOWNTO 0);
540 SIGNAL Q_xhdl1 : std_logic_vector(TDWIDTH-1 DOWNTO 0);
541
542 BEGIN
543 Q <= Q_xhdl1;
544 twidLUT_0 : wrapRam
545 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => TDWIDTH )
546 PORT MAP (D => D, Q => Q_xhdl1, wA => wA, rA => rA_r,
547 wEn => wEn, clk => clk);
548
549 PROCESS (clk)
550 BEGIN
551 IF (clk'EVENT AND clk = '1') THEN
552 rA_r <= rA AFTER tscale;
553 END IF;
554 END PROCESS;
555 END ARCHITECTURE translated;
556 --------------------------------------------------------------------------------
557 ------------------------- R A M -----------------------
558 LIBRARY IEEE;
559 USE IEEE.std_logic_1164.all;
560
561 ENTITY wrapRam IS
562 GENERIC ( LOGPTS : integer := 8;
563 DWIDTH : integer := 32 );
564 PORT (clk, wEn : IN std_logic;
565 D : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
566 rA, wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
567 Q : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) );
568 END ENTITY wrapRam;
569
570 ARCHITECTURE rtl OF wrapRam IS
571 CONSTANT RE : std_logic := '0';
572 COMPONENT actram
573 port(WRB, RDB, WCLOCK, RCLOCK : IN std_logic;
574 DI : in std_logic_vector(DWIDTH-1 downto 0);
575 DO : out std_logic_vector(DWIDTH-1 downto 0);
576 WADDR,RADDR : IN std_logic_vector(LOGPTS-2 downto 0) );
577 end COMPONENT;
578
579 SIGNAL nwEn : std_logic;
580
581 BEGIN
582 nwEn <= NOT wEn;
583 wrapRam_0 : actram
584 PORT MAP (DI => D, WADDR => wA, RADDR => rA, WRB => nwEn,
585 RDB => RE, RCLOCK => clk, WCLOCK => clk, DO => Q);
586 END ARCHITECTURE rtl;
587 -------------------------------------------------------------------------------V
588 LIBRARY IEEE;
589 USE IEEE.std_logic_1164.all;
590 USE work.fft_components.all;
591
592 ENTITY autoScale IS
593 GENERIC (SCALE_MODE : integer := 1 ); -- enable autoscaling
594 PORT (
595 clk, clkEn, wLastStage : IN std_logic;
596 ldRiskOV, bflyRiskOV : IN std_logic;
597 startLoad, ifo_loadOn : IN std_logic;
598 bflyOutValid, startFFT : IN std_logic;
599 wEn_even, wEn_odd : IN std_logic;
600 -- scaleMode : IN std_logic; --set 1 to turn autoscaling ON
601 upScale : OUT std_logic);
602 END ENTITY autoScale;
603
604 ARCHITECTURE translated OF autoScale IS
605 CONSTANT tscale : time := 1 ns;
606
607 SIGNAL ldMonitor, bflyMonitor, stageEnd_w : std_logic;
608 SIGNAL xhdl_5 : std_logic;
609 SIGNAL upScale_xhdl1 : std_logic;
610
611 BEGIN
612 upScale <= upScale_xhdl1;
613 xhdl_5 <= (bflyOutValid AND (NOT wLastStage));
614 fedge_0 : edgeDetect
615 GENERIC MAP (INPIPE => 0, FEDGE => 1)
616 PORT MAP (clk => clk, clkEn => clkEn, edgeIn => xhdl_5, edgeOut => stageEnd_w);
617
618 PROCESS (clk)
619 BEGIN
620 IF (clk'EVENT AND clk = '1') THEN
621 -- Initialize ldMonitor
622 IF (startLoad = '1') THEN
623 ldMonitor <= to_logic(SCALE_MODE) AFTER tscale;
624 ELSE
625 -- Monitor the data being loaded: turn down ldMonitor
626 -- if any valid input data violates the condition
627 IF ((ldRiskOV AND (wEn_even OR wEn_odd)) = '1') THEN
628 ldMonitor <= '0' AFTER tscale;
629 END IF;
630 END IF;
631 -- monitor the data being FFT'ed
632 IF ((bflyRiskOV AND bflyOutValid) = '1') THEN
633 bflyMonitor <= '0';
634 END IF;
635 --check ldMonitor on startFFT (startFFT coinsides with the next startLoad)
636 IF (startFFT = '1') THEN
637 upScale_xhdl1 <= ldMonitor AFTER tscale;
638 -- initialize bflyMonitor
639 bflyMonitor <= to_logic(SCALE_MODE) AFTER tscale;
640 ELSE
641 -- Check the bflyMonitor at a stage end except the last stage, since the
642 -- end of the last stage may come on or even after the startFFT signal
643 -- when the upScale is supposed to check the ldMonitor only
644 IF (stageEnd_w = '1') THEN
645 upScale_xhdl1 <= bflyMonitor AFTER tscale;
646 -- initialize bflyMonitor at the beginning of every stage
647 bflyMonitor <= to_logic(SCALE_MODE) AFTER tscale;
648 END IF;
649 END IF;
650 END IF;
651 END PROCESS;
652
653 END ARCHITECTURE translated;
654 --------------------------------------------------------------------------------
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: fftSm.vhd
10 -- Description: CoreFFT
11 -- FFT state machine module
12 -- Rev: 3.0 3/28/2007 4:43PM VlaD : Variable bitwidth
13 --
14 --
15 --------------------------------------------------------------------------------
16 --************************** TWIDDLE rA GENERATOR **************************
17 LIBRARY IEEE;
18 USE IEEE.std_logic_1164.all;
19 USE IEEE.std_logic_unsigned.all;
20 USE work.fft_components.all;
21
22 ENTITY twid_rA IS
23 GENERIC (LOGPTS : integer := 8;
24 LOGLOGPTS : integer := 3 );
25 PORT (clk : IN std_logic;
26 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
27 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
28 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
29 END ENTITY twid_rA;
30
31 ARCHITECTURE translated OF twid_rA IS
32 CONSTANT timescale : time := 1 ns;
33 --twiddleMask = ~(0xFFFFFFFF<<(NumberOfStages-1));
34 --addrTwiddle=reverseBits(count, NumberOfStages-1)<<(NumberOfStages-1-stage);
35 --mask out extra left bits: addrTwiddle = addrTwiddle & twiddleMask;
36 --reverse bits of the timer;
37 SIGNAL reverseBitTimer : bit_vector(LOGPTS-2 DOWNTO 0);
38 SIGNAL tA_w, tA_reg : std_logic_vector(LOGPTS-2 DOWNTO 0);
39
40 BEGIN
41 tA <= tA_reg;
42 PROCESS (timer)
43 BEGIN
44 reverseBitTimer <= reverse(timer);
45 END PROCESS;
46 -- Left shift by
47 tA_w <= To_StdLogicVector(reverseBitTimer SLL (LOGPTS-1 - to_integer(stage)) )
48 AFTER timescale;
49
50 PROCESS (clk)
51 BEGIN
52 IF (clk'EVENT AND clk = '1') THEN
53 tA_reg <= tA_w AFTER timescale;
54 END IF;
55 END PROCESS;
56 END ARCHITECTURE translated;
57 --------------------------------------------------------------------------------
58 --***************************** TIMERS & rdValid ***************************
59 -- FFT computation sequence is predefined. Once it gets started it runs for
60 -- a number of stages, `HALFPTS+ clk per stage. The following module sets the
61 -- read inBuf time sequence. Every stage takes HALFPTS + inBuf_RWDLY clk for
62 -- the inBuf to write Bfly results back in place before it starts next stage
63 LIBRARY IEEE;
64 USE IEEE.std_logic_1164.all;
65 USE work.fft_components.all;
66
67 ENTITY rdFFTtimer IS
68 GENERIC (LOGPTS : integer := 8;
69 LOGLOGPTS : integer := 3;
70 HALFPTS : integer := 128;
71 inBuf_RWDLY : integer := 12 );
72 PORT (
73 clk, cntEn, rst, nGrst : IN std_logic;
74 startFFT, fft_runs : IN std_logic;
75 timerTC, lastStage : OUT std_logic; --terminal counts of rA and stage
76 stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
77 timer : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
78 rdValid : OUT std_logic );
79 END ENTITY rdFFTtimer;
80
81 ARCHITECTURE translated OF rdFFTtimer IS
82 CONSTANT dlta : time := 1 ns;
83
84 SIGNAL preRdValid : std_logic;
85 SIGNAL pipe1, pipe2 : std_logic;
86 SIGNAL rst_comb, timerTCx1 : std_logic;
87 SIGNAL lastStage_xhdl2 : std_logic;
88 SIGNAL stage_xhdl3 : std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
89 SIGNAL timer_xhdl4 : std_logic_vector(LOGPTS-1 DOWNTO 0);
90 SIGNAL rdValid_xhdl5 : std_logic;
91
92 BEGIN
93 timerTC <= timerTCx1;
94 lastStage <= lastStage_xhdl2;
95 stage <= stage_xhdl3;
96 timer <= timer_xhdl4;
97 rdValid <= rdValid_xhdl5;
98 rst_comb <= rst OR startFFT;
99
100 rA_timer : counter
101 GENERIC MAP (WIDTH =>LOGPTS, TERMCOUNT =>HALFPTS+inBuf_RWDLY-1)
102 PORT MAP (clk => clk, nGrst => nGrst, rst => rst_comb,
103 cntEn => cntEn, tc => timerTCx1, Q => timer_xhdl4);
104 stage_timer : counter
105 GENERIC MAP (WIDTH => LOGLOGPTS, TERMCOUNT => LOGPTS-1)
106 PORT MAP (clk => clk, nGrst => nGrst, rst => rst_comb,
107 cntEn => timerTCx1, tc => lastStage_xhdl2,
108 Q => stage_xhdl3);
109
110 PROCESS (clk, nGrst)
111 BEGIN
112 IF (NOT nGrst = '1') THEN
113 preRdValid <= '0';
114 ELSIF (clk'EVENT AND clk = '1') THEN
115 IF (rst = '1') THEN
116 preRdValid <= '0' AFTER dlta;
117 ELSE
118 IF (cntEn = '1') THEN
119 IF ( to_integer(timer_xhdl4) = HALFPTS-1 ) THEN
120 preRdValid <= '0' AFTER dlta;
121 END IF;
122 -- on startFFT the valid reading session always starts
123 IF (startFFT = '1') THEN preRdValid <= '1' AFTER dlta;
124 END IF;
125 -- reading session starts on rTimerTC except after the lastStage
126 IF ((((NOT lastStage_xhdl2) AND timerTCx1) AND fft_runs) = '1') THEN
127 preRdValid <= '1' AFTER dlta;
128 END IF;
129 END IF;
130 END IF;
131 END IF;
132 END PROCESS;
133
134 PROCESS (clk)
135 BEGIN
136 IF (clk'EVENT AND clk = '1') THEN
137 rdValid_xhdl5 <= pipe2 AFTER dlta;
138 pipe2 <= pipe1 AFTER dlta;
139 pipe1 <= preRdValid AFTER dlta;
140 END IF;
141 END PROCESS;
142 END ARCHITECTURE translated;
143 --------------------------------------------------------------------------------
144 LIBRARY IEEE;
145 USE IEEE.std_logic_1164.all;
146 USE work.fft_components.all;
147
148 ENTITY wrFFTtimer IS
149 GENERIC (LOGPTS : integer := 8;
150 LOGLOGPTS : integer := 3;
151 HALFPTS : integer := 128 );
152 PORT (
153 clk, cntEn, nGrst, rst : IN std_logic;
154 rstStage, rstTime : IN std_logic;
155 timerTC, lastStage : OUT std_logic; -- terminal counts of wA and stage
156 stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
157 timer : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
158 END ENTITY wrFFTtimer;
159
160 ARCHITECTURE translated OF wrFFTtimer IS
161 CONSTANT timescale : time := 1 ns;
162
163 SIGNAL rst_VHDL,rstStage_VHDL : std_logic;
164 SIGNAL timerTC_xhdl1 : std_logic;
165 SIGNAL lastStage_xhdl2 : std_logic;
166 SIGNAL stage_xhdl3 : std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
167 SIGNAL timer_xhdl4 : std_logic_vector(LOGPTS-2 DOWNTO 0);
168
169 BEGIN
170 timerTC <= timerTC_xhdl1;
171 lastStage <= lastStage_xhdl2;
172 stage <= stage_xhdl3;
173 timer <= timer_xhdl4;
174 rst_VHDL <= rstTime OR rst;
175 wA_timer : counter
176 GENERIC MAP (WIDTH => LOGPTS-1, TERMCOUNT =>HALFPTS-1)
177 PORT MAP (clk => clk, nGrst => nGrst, rst => rst_VHDL, cntEn => cntEn,
178 tc => timerTC_xhdl1, Q => timer_xhdl4);
179 rstStage_VHDL <= rstStage OR rst;
180
181 stage_timer : counter
182 GENERIC MAP (WIDTH => LOGLOGPTS, TERMCOUNT =>LOGPTS-1)
183 PORT MAP (clk => clk, nGrst => nGrst, rst => rstStage_VHDL,
184 cntEn => timerTC_xhdl1, tc => lastStage_xhdl2,
185 Q => stage_xhdl3);
186 END ARCHITECTURE translated;
187 --------------------------------------------------------------------------------
188 --********************* inBuf LOAD ADDRESS GENERATOR *********************
189 LIBRARY IEEE;
190 USE IEEE.std_logic_1164.all;
191 USE work.fft_components.all;
192
193 ENTITY inBuf_ldA IS
194 GENERIC (PTS : integer := 256;
195 LOGPTS : integer := 8 );
196 PORT (
197 clk, clkEn, nGrst : IN std_logic;
198 --comes from topSM to reset ldA count & start another loading cycle
199 startLoad : IN std_logic;
200 ifi_dataRdy : IN std_logic; -- inData strobe
201 ifo_loadOn : OUT std_logic;-- inBuf is ready for new data
202 --tells topSM the buffer is fully loaded and ready for FFTing
203 load_done : OUT std_logic;
204 ldA : OUT std_logic_vector(LOGPTS-1 DOWNTO 1);
205 wEn_even, wEn_odd : OUT std_logic;
206 ldValid : OUT std_logic);
207 END ENTITY inBuf_ldA;
208
209 ARCHITECTURE translated OF inBuf_ldA IS
210 CONSTANT timescale : time := 1 ns;
211
212 -- just LSB of the counter below. Counts even/odd samples
213 SIGNAL ldCountLsb_w : std_logic;
214 SIGNAL closeLoad_w, cntEn_w : std_logic;
215 SIGNAL loadOver_w : std_logic;
216 SIGNAL xhdl_9 : std_logic_vector(LOGPTS-1 DOWNTO 0);
217 SIGNAL ifo_loadOn_int : std_logic;
218 SIGNAL load_done_int : std_logic;
219 SIGNAL ldA_int : std_logic_vector(LOGPTS-1 DOWNTO 1);
220 SIGNAL wEn_even_int : std_logic;
221 SIGNAL wEn_odd_int : std_logic;
222 SIGNAL ldValid_int : std_logic;
223
224 BEGIN
225 ifo_loadOn <= ifo_loadOn_int;
226 load_done <= load_done_int;
227 ldA <= ldA_int;
228 wEn_even <= wEn_even_int;
229 wEn_odd <= wEn_odd_int;
230 ldValid <= ldValid_int;
231 cntEn_w <= clkEn AND ifi_dataRdy ;
232 loadOver_w <= closeLoad_w AND wEn_odd_int ;
233 ldValid_int <= ifo_loadOn_int AND ifi_dataRdy ;
234 wEn_even_int <= NOT ldCountLsb_w AND ldValid_int ;
235 wEn_odd_int <= ldCountLsb_w AND ldValid_int ;
236 -- xhdl_9 <= ldA_int & ldCountLsb_w;
237 ldA_int <= xhdl_9(LOGPTS-1 DOWNTO 1);
238 ldCountLsb_w <= xhdl_9(0);
239 -- counts samples loaded. There is `PTS samples to load, not `PTS/2
240 ldCount : counter
241 GENERIC MAP (WIDTH =>LOGPTS, TERMCOUNT =>PTS-1)
242 PORT MAP (clk => clk, nGrst => nGrst, rst => startLoad,
243 cntEn => cntEn_w, tc => closeLoad_w, Q => xhdl_9);
244
245 -- A user can stop supplying ifi_dataRdy after loadOver gets high, thus
246 -- the loadOver can stay high indefinitely. Shorten it!
247 edge_0 : edgeDetect
248 GENERIC MAP (INPIPE => 0, FEDGE => 1)
249 PORT MAP (clk => clk, clkEn => clkEn, edgeIn => loadOver_w,
250 edgeOut => load_done_int);
251
252 PROCESS (clk, nGrst)
253 BEGIN
254 -- generate ifo_loadOn:
255 IF (NOT nGrst = '1') THEN
256 ifo_loadOn_int <= '0';
257 ELSE
258 IF (clk'EVENT AND clk = '1') THEN
259 IF (clkEn = '1') THEN
260 -- if (load_done) ifo_loadOn <= #1 0;
261 IF (loadOver_w = '1') THEN
262 ifo_loadOn_int <= '0' AFTER timescale;
263 ELSE
264 IF (startLoad = '1') THEN
265 ifo_loadOn_int <= '1' AFTER timescale;
266 END IF;
267 END IF;
268 END IF;
269 END IF;
270 END IF;
271 END PROCESS;
272 END ARCHITECTURE translated;
273 --------------------------------------------------------------------------------
274 --****************** inBuf ADDRESS GENERATOR for BFLY DATA *****************
275 -- Implements both read and write data generators. The core utilizes inPlace
276 -- algorithm thus the wA is a delayed copy of the rA
277 LIBRARY IEEE;
278 USE IEEE.std_logic_1164.all;
279 USE IEEE.STD_LOGIC_UNSIGNED.all;
280 USE work.fft_components.all;
281
282 ENTITY inBuf_fftA IS
283 GENERIC (LOGPTS : integer := 8;
284 LOGLOGPTS : integer := 3 );
285 PORT (
286 clk, clkEn :IN std_logic;
287 timer :IN std_logic_vector(LOGPTS-2 DOWNTO 0);
288 stage :IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
289 timerTC, lastStage :IN std_logic;
290 fftDone, swCross :OUT std_logic;
291 bflyA :OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
292 END ENTITY inBuf_fftA;
293
294 ARCHITECTURE translated OF inBuf_fftA IS
295 CONSTANT timescale : time := 1 ns;
296 CONSTANT offsetConst : bit_vector(LOGPTS-1 DOWNTO 0):=('1', others=>'0');
297 CONSTANT addrMask1: BIT_VECTOR(LOGPTS-1 DOWNTO 0) := ('0', OTHERS=>'1');
298 CONSTANT addrMask2: BIT_VECTOR(LOGPTS-1 DOWNTO 0) := (OTHERS=>'1');
299
300 SIGNAL fftDone_w, swCross_w: std_logic;
301 SIGNAL bflyA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
302 SIGNAL addrP_w, offsetPQ_w : std_logic_vector(LOGPTS-1 DOWNTO 0);
303 --rA takes either Paddr or Qaddr value (Qaddr=Paddr+offsetPQ) per clock.
304 --At even clk rA=Paddr, at odd clk rA=Qaddr. (Every addr holds a pair of
305 --data samples). Timer LSB controls which clk is happening now. LSB of
306 --the same timer controls switch(es).
307 SIGNAL bflyA_w_int : std_logic_vector(LOGPTS-1 DOWNTO 1);
308 SIGNAL swCross_w_int,swCross_int: std_logic;
309 SIGNAL fftDone_int : std_logic;
310 SIGNAL bflyA_int : std_logic_vector(LOGPTS-2 DOWNTO 0);
311
312 BEGIN
313 fftDone <= fftDone_int;
314 bflyA <= bflyA_int;
315 swCross <= swCross_int;
316 --addrP_w=( (timer<<1)&(~(addrMask2>>stage)) ) | (timer&(addrMask1>>stage));
317 addrP_w <= To_StdLogicVector(
318 ( (('0'& To_BitVector(timer)) SLL 1) AND (NOT (addrMask2 SRL to_integer(stage)) ) )
319 OR ( ('0'& To_BitVector(timer)) AND (addrMask1 SRL to_integer(stage)) ) );
320
321 -- address offset between P and Q offsetPQ_w= ( 1<<(`LOGPTS-1) )>>stage;
322 offsetPQ_w <= To_StdLogicVector(offsetConst SRL to_integer(stage));
323
324 -- bflyA_w = timer[0] ? (addrP_w[`LOGPTS-1:1]+offsetPQ_w[`LOGPTS-1:1]):
325 -- addrP_w[`LOGPTS-1:1];
326 bflyA_w_int <=
327 (addrP_w(LOGPTS-1 DOWNTO 1) + offsetPQ_w(LOGPTS-1 DOWNTO 1)) WHEN
328 timer(0) = '1'
329 ELSE addrP_w(LOGPTS-1 DOWNTO 1);
330
331 bflyA_w <= bflyA_w_int AFTER timescale;
332 fftDone_w <= lastStage AND timerTC AFTER timescale;
333 swCross_w_int <= '0' WHEN lastStage = '1' ELSE timer(0);
334 swCross_w <= swCross_w_int AFTER timescale;
335
336 PROCESS (clk)
337 BEGIN
338 IF (clk'EVENT AND clk = '1') THEN
339 IF (clkEn = '1') THEN
340 bflyA_int <= bflyA_w AFTER timescale;
341 swCross_int <= swCross_w AFTER timescale;
342 fftDone_int <= fftDone_w AFTER timescale;
343 END IF;
344 END IF;
345 END PROCESS;
346 END ARCHITECTURE translated;
347 --------------------------------------------------------------------------------
348 --************************** TWIDDLE wA GENERATOR ****************************
349 -- initializes Twiddle LUT on rst based on contents of twiddle.v file.
350 -- Generates trueRst when the initialization is over
351 LIBRARY IEEE;
352 USE IEEE.std_logic_1164.all;
353 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
354 USE work.fft_components.all;
355
356 ENTITY twid_wAmod IS
357 GENERIC (LOGPTS : integer := 8 );
358 PORT (
359 clk, ifiNreset : IN std_logic; -- async global reset
360 twid_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
361 twid_wEn,twidInit : OUT std_logic;
362 rstAfterInit : OUT std_logic);
363 END ENTITY twid_wAmod;
364
365 ARCHITECTURE translated OF twid_wAmod IS
366 CONSTANT timescale : time := 1 ns;
367 CONSTANT allOnes : std_logic_vector(LOGPTS+1 DOWNTO 0):=(OTHERS=>'1');
368
369 SIGNAL slowTimer_w : std_logic_vector(LOGPTS+1 DOWNTO 0);
370 SIGNAL preRstAfterInit : std_logic;
371 SIGNAL twid_wA_int : std_logic_vector(LOGPTS-2 DOWNTO 0);
372 SIGNAL twid_wEn_int : std_logic;
373 SIGNAL rstAfterInit_int : std_logic;
374 SIGNAL twidInit_int : std_logic;
375
376 BEGIN
377 twid_wA <= twid_wA_int;
378 twid_wEn <= twid_wEn_int;
379 rstAfterInit <= rstAfterInit_int;
380 twidInit <= twidInit_int;
381
382 -- slow counter not to worry about the clk rate
383 slowTimer : bcounter
384 GENERIC MAP (WIDTH => LOGPTS+2)
385 PORT MAP (clk => clk, nGrst => ifiNreset, rst => '0',
386 cntEn => twidInit_int, Q => slowTimer_w);
387 -- wEn = 2-clk wide for the RAM to have enough time
388 twid_wEn_int <= to_logic(slowTimer_w(2 DOWNTO 1) = "11");
389 twid_wA_int <= slowTimer_w(LOGPTS+1 DOWNTO 3);
390
391 PROCESS (clk, ifiNreset)
392 BEGIN
393 IF (NOT ifiNreset = '1') THEN
394 twidInit_int <= '1' AFTER timescale;
395 ELSIF (clk'EVENT AND clk = '1') THEN
396 rstAfterInit_int <= preRstAfterInit AFTER timescale;
397 IF (slowTimer_w = allOnes) THEN twidInit_int <='0' AFTER timescale;
398 END IF;
399 preRstAfterInit <= to_logic(slowTimer_w = allOnes) AFTER timescale;
400 END IF;
401 END PROCESS;
402 END ARCHITECTURE translated;
403 --------------------------------------------------------------------------------
404 ----------------------------------- outBufA ------------------------------------
405 LIBRARY IEEE;
406 USE IEEE.std_logic_1164.all;
407 USE IEEE.STD_LOGIC_UNSIGNED.all;
408 USE work.fft_components.all;
409
410 ENTITY outBufA IS
411 GENERIC (PTS : integer := 256;
412 LOGPTS : integer := 8 );
413 PORT (clk, clkEn, nGrst : IN std_logic;
414 rst, outBuf_wEn : IN std_logic;
415 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
416 -- host can slow down results reading by lowering the signal
417 rdCtl : IN std_logic;
418 wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
419 rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
420 outBuf_rEn, rdValid : OUT std_logic);
421 END ENTITY outBufA;
422
423 ARCHITECTURE translated OF outBufA IS
424 CONSTANT timescale : time := 1 ns;
425
426 SIGNAL reverseBitTimer, wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
427 SIGNAL outBufwEnFall_w : std_logic;
428 SIGNAL rA_TC_w, preOutBuf_rEn: std_logic;
429 SIGNAL pipe11, pipe12, pipe21: std_logic;
430 SIGNAL pipe22, rdCtl_reg : std_logic;
431 -- Reset a binary counter on the rear edge
432 SIGNAL rstVhdl, rdValid_int : std_logic;
433 SIGNAL wA_int : std_logic_vector(LOGPTS-2 DOWNTO 0);
434 SIGNAL rA_int : std_logic_vector(LOGPTS-1 DOWNTO 0);
435 SIGNAL outBuf_rEn_int : std_logic;
436
437 BEGIN
438 wA <= wA_int;
439 rA <= rA_int;
440 outBuf_rEn <= outBuf_rEn_int;
441 rdValid <= rdValid_int;
442
443 PROCESS (timer)
444 VARIABLE reverseBitTimer_int : std_logic_vector(LOGPTS-2 DOWNTO 0);
445 BEGIN
446 reverseBitTimer_int := reverseStd(timer);
447 reverseBitTimer <= reverseBitTimer_int;
448 END PROCESS;
449 wA_w <= reverseBitTimer AFTER timescale;
450 -- rA generator. Detect rear edge of the outBuf wEn
451 fedge_0 : edgeDetect
452 GENERIC MAP (INPIPE => 0, FEDGE => 1)
453 PORT MAP (clk => clk, clkEn => '1', edgeIn => outBuf_wEn,
454 edgeOut => outBufwEnFall_w);
455
456 rstVhdl <= rst OR outBufwEnFall_w;
457
458 outBuf_rA_0 : counter
459 GENERIC MAP (WIDTH => LOGPTS, TERMCOUNT =>PTS-1)
460 PORT MAP (clk => clk, nGrst => nGrst, rst => rstVhdl,
461 cntEn => rdCtl_reg, tc => rA_TC_w, Q => rA_int);
462
463 PROCESS (clk, nGrst)
464 BEGIN
465 -- RS FF preOutBuf_rEn
466 IF (NOT nGrst = '1') THEN
467 preOutBuf_rEn <= '0' AFTER timescale;
468 ELSE
469 IF (clk'EVENT AND clk = '1') THEN
470 IF ((rst OR outBuf_wEn OR rA_TC_w) = '1') THEN
471 preOutBuf_rEn <= '0' AFTER timescale;
472 ELSE
473 IF (outBufwEnFall_w = '1') THEN
474 preOutBuf_rEn <= '1' AFTER timescale;
475 END IF;
476 END IF;
477 END IF;
478 END IF;
479 END PROCESS;
480
481 PROCESS (clk)
482 BEGIN
483 IF (clk'EVENT AND clk = '1') THEN
484 wA_int <= wA_w AFTER timescale;
485 rdCtl_reg <= rdCtl AFTER timescale;
486 outBuf_rEn_int <= pipe12 AFTER timescale;
487 pipe12 <= pipe11 AFTER timescale;
488 pipe11 <= preOutBuf_rEn AFTER timescale;
489 rdValid_int <= pipe22 AFTER timescale;
490 pipe22 <= pipe21 AFTER timescale;
491 pipe21 <= preOutBuf_rEn AND rdCtl_reg AFTER timescale;
492 END IF;
493 END PROCESS;
494 END ARCHITECTURE translated;
495 ----------------------------------------------------------------------------------------------
496 --********************************** SM TOP ********************************
497 LIBRARY IEEE;
498 USE IEEE.std_logic_1164.all;
499 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
500 USE IEEE.std_logic_arith.all;
501 USE work.fft_components.all;
502
503 ENTITY sm_top IS
504 GENERIC ( PTS : integer := 256;
505 HALFPTS : integer := 128;
506 LOGPTS : integer := 8;
507 LOGLOGPTS : integer := 3;
508 inBuf_RWDLY : integer := 12 );
509 PORT (clk,clkEn : IN std_logic;
510 ifiStart, ifiNreset : IN std_logic; --sync and async reset
511 ifiD_valid, ifiRead_y : IN std_logic;
512 ldA, rA, wA, tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
513 twid_wA, outBuf_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
514 outBuf_rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
515 wEn_even, wEn_odd : OUT std_logic;
516 preSwCross, twid_wEn : OUT std_logic;
517 inBuf_wEn, outBuf_wEn : OUT std_logic;
518 smPong, ldValid : OUT std_logic;
519 inBuf_rdValid : OUT std_logic;
520 wLastStage : OUT std_logic;
521 smStartFFTrd : OUT std_logic;
522 smStartLoad, ifoLoad : OUT std_logic;
523 ifoY_valid, ifoY_rdy : OUT std_logic);
524 END ENTITY sm_top;
525
526 ARCHITECTURE translated OF sm_top IS
527 CONSTANT timescale : time := 1 ns;
528
529 COMPONENT inBuf_fftA
530 GENERIC (LOGPTS : integer := 8;
531 LOGLOGPTS : integer := 3 );
532 PORT (clk, clkEn : IN std_logic;
533 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
534 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
535 timerTC, lastStage : IN std_logic;
536 fftDone, swCross : OUT std_logic;
537 bflyA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0) );
538 END COMPONENT;
539
540 COMPONENT inBuf_ldA
541 GENERIC (PTS : integer := 8;
542 LOGPTS : integer := 3 );
543 PORT (
544 clk, clkEn, nGrst : IN std_logic;
545 startLoad, ifi_dataRdy : IN std_logic;
546 ifo_loadOn, load_done : OUT std_logic;
547 ldA : OUT std_logic_vector(LOGPTS-1 DOWNTO 1);
548 wEn_even, wEn_odd : OUT std_logic;
549 ldValid : OUT std_logic);
550 END COMPONENT;
551
552
553 COMPONENT outBufA
554 GENERIC (PTS : integer := 256;
555 LOGPTS : integer := 8 );
556 PORT (clk,clkEn,nGrst : IN std_logic;
557 rst, outBuf_wEn, rdCtl : IN std_logic;
558 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
559 wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
560 rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
561 outBuf_rEn, rdValid : OUT std_logic);
562 END COMPONENT;
563
564 COMPONENT rdFFTtimer
565 GENERIC (LOGPTS : integer := 8;
566 LOGLOGPTS : integer := 3;
567 HALFPTS : integer := 128;
568 inBuf_RWDLY : integer := 12 );
569 PORT (clk, cntEn, rst : IN std_logic;
570 startFFT,fft_runs,nGrst : IN std_logic;
571 timerTC, lastStage : OUT std_logic;
572 stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
573 timer : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
574 rdValid : OUT std_logic );
575 END COMPONENT;
576
577 COMPONENT twid_rA
578 GENERIC (LOGPTS : integer := 8;
579 LOGLOGPTS : integer := 3 );
580 PORT (
581 clk : IN std_logic;
582 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
583 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
584 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
585 END COMPONENT;
586
587 COMPONENT twid_wAmod
588 GENERIC (LOGPTS : integer := 8 );
589 PORT (clk, ifiNreset: IN std_logic;
590 twid_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
591 twid_wEn,twidInit : OUT std_logic;
592 rstAfterInit : OUT std_logic );
593 END COMPONENT;
594
595 COMPONENT wrFFTtimer
596 GENERIC (LOGPTS : integer := 8;
597 LOGLOGPTS : integer := 3;
598 HALFPTS : integer := 128 );
599 PORT (
600 clk, cntEn, nGrst, rst : IN std_logic;
601 rstStage, rstTime : IN std_logic;
602 timerTC, lastStage : OUT std_logic;
603 stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
604 timer : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
605 END COMPONENT;
606
607 SIGNAL rTimer_w : std_logic_vector(LOGPTS-1 DOWNTO 0);
608 SIGNAL wTimer_w, timerT1 : std_logic_vector(LOGPTS-2 DOWNTO 0);
609 SIGNAL rStage_w,wStage_w : std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
610 SIGNAL stageT1, stageT2 : std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
611 SIGNAL rLastStage_w : std_logic;
612 SIGNAL rTimerTC_w : std_logic;
613 SIGNAL wTimerTC_w : std_logic;
614 SIGNAL load_done_w : std_logic;
615 SIGNAL sync_rAwA : std_logic;
616 SIGNAL fftRd_done_w : std_logic;
617 SIGNAL preInBuf_wEn : std_logic;
618 SIGNAL preOutBuf_wEn : std_logic;
619 SIGNAL trueRst : std_logic;
620 SIGNAL smBuf_full : std_logic; -- top level SM registers
621 SIGNAL smFft_rdy : std_logic; -- top level SM registers
622 SIGNAL smFft_runs : std_logic; -- top level SM registers
623 -- Reset logic:
624 -- - On ifiNreset start loading twidLUT.
625 -- - While it is loading keep global async rst nGrst active
626 -- - Once load is over issue short rstAfterInit which is just another ifiStart
627 SIGNAL initRst, nGrst : std_logic;
628 SIGNAL rstAfterInit : std_logic;
629 SIGNAL trueRst_w : std_logic;
630 SIGNAL xhdl_27, rdTimer_cntEn : std_logic;
631 SIGNAL port_xhdl37 : std_logic_vector(LOGPTS-2 DOWNTO 0);
632 SIGNAL ldA_xhdl1 : std_logic_vector(LOGPTS-2 DOWNTO 0);
633 SIGNAL rA_xhdl2 : std_logic_vector(LOGPTS-2 DOWNTO 0);
634 SIGNAL wA_xhdl3 : std_logic_vector(LOGPTS-2 DOWNTO 0);
635 SIGNAL tA_xhdl4 : std_logic_vector(LOGPTS-2 DOWNTO 0);
636 SIGNAL twid_wA_xhdl5 : std_logic_vector(LOGPTS-2 DOWNTO 0);
637 SIGNAL outBuf_wA_xhdl6 : std_logic_vector(LOGPTS-2 DOWNTO 0);
638 SIGNAL outBuf_rA_xhdl7 : std_logic_vector(LOGPTS-1 DOWNTO 0);
639 SIGNAL wEn_even_xhdl8 : std_logic;
640 SIGNAL wEn_odd_xhdl9 : std_logic;
641 SIGNAL preSwCross_xhdl10 : std_logic;
642 SIGNAL twid_wEn_xhdl11 : std_logic;
643 SIGNAL inBuf_wEn_xhdl12 : std_logic;
644 SIGNAL outBuf_wEn_xhdl13 : std_logic;
645 SIGNAL smPong_xhdl14 : std_logic;
646 SIGNAL ldValid_xhdl15 : std_logic;
647 SIGNAL inBuf_rdValid_int : std_logic;
648 SIGNAL wLastStage_xhdl17 : std_logic;
649 SIGNAL smStartFFTrd_int : std_logic;
650 SIGNAL smStartLoad_int : std_logic;
651 SIGNAL ifoLoad_xhdl20 : std_logic;
652 SIGNAL ifoY_valid_xhdl21 : std_logic;
653 SIGNAL ifoY_rdy_xhdl22 : std_logic;
654 SIGNAL smStartLoad_w : std_logic;
655
656 BEGIN
657 ldA <= ldA_xhdl1;
658 rA <= rA_xhdl2;
659 wA <= wA_xhdl3;
660 tA <= tA_xhdl4;
661 twid_wA <= twid_wA_xhdl5;
662 outBuf_wA <= outBuf_wA_xhdl6;
663 outBuf_rA <= outBuf_rA_xhdl7;
664 wEn_even <= wEn_even_xhdl8;
665 wEn_odd <= wEn_odd_xhdl9;
666 preSwCross <= preSwCross_xhdl10;
667 twid_wEn <= twid_wEn_xhdl11;
668 inBuf_wEn <= inBuf_wEn_xhdl12;
669 outBuf_wEn <= outBuf_wEn_xhdl13;
670 smPong <= smPong_xhdl14;
671 ldValid <= ldValid_xhdl15;
672 inBuf_rdValid <= inBuf_rdValid_int;
673 wLastStage <= wLastStage_xhdl17;
674 smStartFFTrd <= smStartFFTrd_int;
675 smStartLoad <= smStartLoad_int;
676 ifoLoad <= ifoLoad_xhdl20;
677 ifoY_valid <= ifoY_valid_xhdl21;
678 ifoY_rdy <= ifoY_rdy_xhdl22;
679 nGrst <= ifiNreset AND (NOT initRst) ;
680 trueRst_w <= rstAfterInit OR ifiStart ;
681 -- Top SM outputs
682 smStartFFTrd_int <= smBuf_full AND smFft_rdy ;
683 -- Start loading on FFT start or initially on trueRst.
684 smStartLoad_w <= trueRst_w OR smStartFFTrd_int ;
685 -- To prevent fake ifoY_rdy and ifoY_valid do not let rdFFTTimer run
686 -- outside smFft_runs
687 rdTimer_cntEn <= clkEn AND (smFft_runs OR smStartFFTrd_int);
688
689 -- FFT read inBuf timer
690 rdFFTtimer_0 : rdFFTtimer
691 GENERIC MAP (LOGPTS => LOGPTS,
692 LOGLOGPTS => LOGLOGPTS,
693 HALFPTS => HALFPTS,
694 inBuf_RWDLY => inBuf_RWDLY )
695 PORT MAP (
696 clk => clk,
697 cntEn => rdTimer_cntEn,
698 nGrst => nGrst,
699 rst => trueRst,
700 startFFT => smStartFFTrd_int,
701 timer => rTimer_w,
702 timerTC => rTimerTC_w,
703 stage => rStage_w,
704 lastStage => rLastStage_w,
705 fft_runs => smFft_runs,
706 rdValid => inBuf_rdValid_int);
707
708 -- FFT write inBuf timer
709 sync_rAwA <= To_logic(rTimer_w = CONV_STD_LOGIC_VECTOR(inBuf_RWDLY, LOGPTS-1)) ;
710 xhdl_27 <= sync_rAwA OR smStartFFTrd_int;
711 wrFFTtimer_0 : wrFFTtimer
712 GENERIC MAP (LOGPTS => LOGPTS,
713 LOGLOGPTS => LOGLOGPTS,
714 HALFPTS => HALFPTS )
715 PORT MAP (
716 clk => clk,
717 rst => trueRst,
718 nGrst => nGrst,
719 rstStage => smStartFFTrd_int,
720 rstTime => xhdl_27,
721 cntEn => clkEn,
722 timer => wTimer_w,
723 timerTC => wTimerTC_w,
724 stage => wStage_w,
725 lastStage => wLastStage_xhdl17);
726
727 --inData strobe
728 --out; inBuf is ready for new data (PTS new samples)
729 --out; tells topSM the buffer is fully loaded and ready for FFTing
730 inBuf_ldA_0 : inBuf_ldA
731 GENERIC MAP (PTS => PTS,
732 LOGPTS => LOGPTS )
733 PORT MAP (
734 clk => clk,
735 clkEn => clkEn,
736 nGrst => nGrst,
737 startLoad => smStartLoad_int,
738 ifi_dataRdy => ifiD_valid,
739 ifo_loadOn => ifoLoad_xhdl20,
740 load_done => load_done_w,
741 ldA => ldA_xhdl1,
742 wEn_even => wEn_even_xhdl8,
743 wEn_odd => wEn_odd_xhdl9,
744 ldValid => ldValid_xhdl15);
745
746 port_xhdl37 <= rTimer_w(LOGPTS-2 DOWNTO 0);
747 inBuf_rA_0 : inBuf_fftA
748 GENERIC MAP (LOGPTS => LOGPTS,
749 LOGLOGPTS => LOGLOGPTS )
750 PORT MAP (
751 clk => clk,
752 clkEn => clkEn,
753 timer => port_xhdl37,
754 stage => rStage_w,
755 timerTC => rTimerTC_w,
756 lastStage => rLastStage_w,
757 fftDone => fftRd_done_w,
758 bflyA => rA_xhdl2,
759 swCross => preSwCross_xhdl10); -- out
760
761 twid_rA_0 : twid_rA
762 GENERIC MAP (LOGPTS => LOGPTS,
763 LOGLOGPTS => LOGLOGPTS )
764 PORT MAP (
765 clk => clk,
766 timer => timerT1,
767 stage => stageT2,
768 tA => tA_xhdl4);
769
770 -- Twiddle LUT initialization
771 twid_wA_0 : twid_wAmod
772 GENERIC MAP (LOGPTS => LOGPTS )
773 PORT MAP (
774 clk => clk,
775 ifiNreset => ifiNreset,
776 twid_wA => twid_wA_xhdl5,
777 twid_wEn => twid_wEn_xhdl11,
778 twidInit => initRst,
779 rstAfterInit => rstAfterInit);
780
781 -- wA generator. On the last stage the fftRd_done comes before the last
782 -- FFT results get written back to the inBuf, but it is not necessary since
783 -- the results get written into the output buffer.
784 inBuf_wA_0 : inBuf_fftA
785 GENERIC MAP (LOGPTS => LOGPTS,
786 LOGLOGPTS => LOGLOGPTS )
787 PORT MAP (
788 clk => clk,
789 clkEn => clkEn,
790 timer => wTimer_w,
791 stage => wStage_w,
792 timerTC => wTimerTC_w,
793 lastStage => wLastStage_xhdl17,
794 fftDone => open,
795 bflyA => wA_xhdl3,
796 swCross => open);
797
798 outBufA_0 : outBufA
799 GENERIC MAP (PTS => PTS,
800 LOGPTS => LOGPTS )
801 PORT MAP (
802 clk => clk,
803 clkEn => clkEn,
804 nGrst => nGrst,
805 rst => trueRst,
806 timer => wTimer_w,
807 outBuf_wEn => outBuf_wEn_xhdl13,
808 rdCtl => ifiRead_y,
809 wA => outBuf_wA_xhdl6,
810 rA => outBuf_rA_xhdl7,
811 outBuf_rEn => ifoY_rdy_xhdl22,
812 rdValid => ifoY_valid_xhdl21);
813
814 PROCESS (clk)
815 BEGIN
816 IF (clk'EVENT AND clk = '1') THEN -- pipes
817 trueRst <= trueRst_w AFTER timescale;
818 smStartLoad_int <= smStartLoad_w AFTER timescale;
819 timerT1 <= rTimer_w(LOGPTS-2 DOWNTO 0) AFTER timescale;
820 stageT1 <= rStage_w AFTER timescale;
821 stageT2 <= stageT1 AFTER timescale;
822 inBuf_wEn_xhdl12 <= preInBuf_wEn AFTER timescale;
823 outBuf_wEn_xhdl13 <= preOutBuf_wEn AFTER timescale;
824 END IF;
825 END PROCESS;
826
827 PROCESS (clk, nGrst)
828 BEGIN
829 IF (NOT nGrst = '1') THEN -- reset topSM
830 smBuf_full <= '0';
831 smFft_rdy <= '0';
832 smFft_runs <= '0';
833 smPong_xhdl14 <= '1';
834 preInBuf_wEn <= '0';
835 preOutBuf_wEn <= '0';
836 --nGrst
837 ELSIF (clk'EVENT AND clk = '1') THEN
838 --mark A
839 IF (trueRst = '1') THEN
840 -- reset topSM
841 smBuf_full <= '0' AFTER timescale;
842 smFft_rdy <= '1' AFTER timescale;
843 smFft_runs <= '0' AFTER timescale;
844 smPong_xhdl14 <= '1' AFTER timescale;
845 preInBuf_wEn <= '0' AFTER timescale;
846 preOutBuf_wEn <= '0' AFTER timescale;
847 ELSE
848 -- mark B
849 IF (load_done_w = '1') THEN
850 smBuf_full <= '1' AFTER timescale;
851 END IF;
852 IF (fftRd_done_w = '1') THEN
853 smFft_rdy <= '1' AFTER timescale;
854 smFft_runs <= '0' AFTER timescale;
855 END IF;
856 IF (smStartFFTrd_int = '1') THEN
857 smBuf_full <= '0' AFTER timescale;
858 smFft_rdy <= '0' AFTER timescale;
859 smFft_runs <= '1' AFTER timescale;
860 smPong_xhdl14 <= NOT smPong_xhdl14 AFTER timescale;
861 END IF;
862 IF (sync_rAwA = '1') THEN
863 IF (rLastStage_w = '1') THEN
864 preOutBuf_wEn <= '1' AFTER timescale;
865 ELSE
866 IF (smFft_runs = '1') THEN
867 preInBuf_wEn <= '1' AFTER timescale;
868 END IF;
869 END IF;
870 END IF;
871 IF (wTimerTC_w = '1') THEN
872 preInBuf_wEn <= '0' AFTER timescale;
873 preOutBuf_wEn <= '0' AFTER timescale;
874 END IF;
875 END IF;
876 -- mark B
877 END IF;
878 -- mark A
879 END PROCESS;
880 END ARCHITECTURE translated;
881 ------------------------------------------------------------------------------
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: fftTop.vhd
10 -- Description: CoreFFT
11 -- Top level FFT module
12 -- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
13 -- Notes: FFT In/out pins:
14 -- Input | Output | Comments
15 -- ------------+------------+------------------
16 -- clk | ifoPong |
17 -- ifiNreset | |async reset active low
18 -- start | |sync reset active high
19 -- Load Input data group |
20 -- d_im[15:0] | load |when high the inBuf is being loaded
21 -- d_re[15:0] | |
22 -- d_valid | |
23 -- Upload Output data group |
24 -- read_y | y_im[15:0] |
25 -- | y_re[15:0] |
26 -- | y_valid |marks a new output sample)
27 -- | y_rdy |when high the results are being uploaded
28 --------------------------------------------------------------------------------
29 library IEEE;
30 use IEEE.STD_LOGIC_1164.all;
31 USE work.fft_components.all;
32
33 ENTITY fftTop IS
34 GENERIC (
35 LOGPTS : integer := gLOGPTS;
36 LOGLOGPTS : integer := gLOGLOGPTS;
37 WSIZE : integer := gWSIZE;
38 TWIDTH : integer := gTWIDTH;
39 DWIDTH : integer := gDWIDTH;
40 TDWIDTH : integer := gTDWIDTH;
41 RND_MODE : integer := gRND_MODE;
42 SCALE_MODE : integer := gSCALE_MODE;
43 PTS : integer := gPTS;
44 HALFPTS : integer := gHALFPTS;
45 inBuf_RWDLY : integer := gInBuf_RWDLY );
46 PORT (
47 clk,ifiStart,ifiNreset : IN std_logic;
48 ifiD_valid, ifiRead_y : IN std_logic;
49 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
50 ifoLoad, ifoPong : OUT std_logic;
51 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
52 ifoY_valid, ifoY_rdy : OUT std_logic);
53 END ENTITY fftTop;
54
55 ARCHITECTURE translated OF fftTop IS
56
57 COMPONENT autoScale
58 GENERIC (SCALE_MODE : integer := 1 );
59 PORT (clk, clkEn, wLastStage : IN std_logic;
60 ldRiskOV, bflyRiskOV : IN std_logic;
61 startLoad, ifo_loadOn : IN std_logic;
62 bflyOutValid, startFFT : IN std_logic;
63 wEn_even, wEn_odd : IN std_logic;
64 upScale : OUT std_logic);
65 END COMPONENT;
66
67 COMPONENT bfly2
68 GENERIC ( RND_MODE : integer := 0;
69 WSIZE : integer := 16;
70 DWIDTH : integer := 32;
71 TWIDTH : integer := 16;
72 TDWIDTH : integer := 32 );
73 PORT (clk, validIn : IN std_logic;
74 swCrossIn : IN std_logic;
75 upScale : IN std_logic;
76 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
77 T : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
78 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
79 validOut, swCrossOut : OUT std_logic);
80 END COMPONENT;
81
82 COMPONENT sm_top
83 GENERIC ( PTS : integer := 256;
84 HALFPTS : integer := 128;
85 LOGPTS : integer := 8;
86 LOGLOGPTS : integer := 3;
87 inBuf_RWDLY : integer := 12 );
88 PORT (clk,clkEn : IN std_logic;
89 ifiStart, ifiNreset : IN std_logic;
90 ifiD_valid, ifiRead_y : IN std_logic;
91 ldA, rA, wA, tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
92 twid_wA, outBuf_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
93 outBuf_rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
94 wEn_even, wEn_odd : OUT std_logic;
95 preSwCross, twid_wEn : OUT std_logic;
96 inBuf_wEn, outBuf_wEn : OUT std_logic;
97 smPong, ldValid : OUT std_logic;
98 inBuf_rdValid : OUT std_logic;
99 wLastStage : OUT std_logic;
100 smStartFFTrd : OUT std_logic;
101 smStartLoad, ifoLoad : OUT std_logic;
102 ifoY_valid, ifoY_rdy : OUT std_logic);
103 END COMPONENT;
104
105 COMPONENT twiddle
106 PORT (A : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
107 T : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0));
108 END COMPONENT;
109
110 COMPONENT pipoBuffer
111 GENERIC ( LOGPTS : integer := 8;
112 DWIDTH : integer := 32 );
113 PORT (
114 clk, clkEn, pong, rEn : IN std_logic;
115 rA, wA_load, wA_bfly : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
116 ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
117 wEn_bfly,wEn_even,wEn_odd : IN std_logic;
118 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) );
119 END COMPONENT;
120
121 COMPONENT switch
122 GENERIC ( DWIDTH : integer := 16 );
123 PORT (clk, sel, validIn : IN std_logic;
124 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
125 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
126 validOut : OUT std_logic);
127 END COMPONENT;
128
129 COMPONENT twidLUT
130 GENERIC ( LOGPTS : integer := 8;
131 TDWIDTH : integer := 32 );
132 PORT (clk, wEn : IN std_logic;
133 wA, rA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
134 D : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
135 Q : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0));
136 END COMPONENT;
137
138 COMPONENT outBuff
139 GENERIC ( LOGPTS : integer := 8;
140 DWIDTH : integer := 32 );
141 PORT (clk, clkEn, wEn : IN std_logic;
142 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
143 wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
144 rA : IN std_logic_vector(LOGPTS-1 DOWNTO 0);
145 outD : OUT std_logic_vector(DWIDTH-1 DOWNTO 0));
146 END COMPONENT;
147
148 SIGNAL ldA_w, rA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
149 SIGNAL wA_w, tA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
150 SIGNAL twid_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
151 SIGNAL outBuf_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
152 SIGNAL outBuf_rA_w : std_logic_vector(LOGPTS-1 DOWNTO 0);
153 SIGNAL wEn_even_w : std_logic;
154 SIGNAL wEn_odd_w : std_logic;
155 SIGNAL inBuf_wEn_w : std_logic;
156 SIGNAL preSwCross_w : std_logic;
157 SIGNAL postSwCross_w : std_logic;
158 SIGNAL twid_wEn_w : std_logic;
159 SIGNAL outBuf_wEn_w : std_logic;
160 SIGNAL ldRiskOV_w : std_logic;
161 SIGNAL bflyRiskOV_w : std_logic;
162 SIGNAL readP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
163 SIGNAL readQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
164 SIGNAL bflyInP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
165 SIGNAL bflyInQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
166 SIGNAL bflyOutP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
167 SIGNAL bflyOutQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
168 SIGNAL T_w : std_logic_vector(TDWIDTH-1 DOWNTO 0);
169 SIGNAL twidData_w : std_logic_vector(TDWIDTH-1 DOWNTO 0);
170 SIGNAL outEven_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
171 SIGNAL outOdd_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
172 SIGNAL inBufValid_w : std_logic;
173 SIGNAL preSwValid_w : std_logic;
174 SIGNAL bflyValid_w : std_logic;
175 SIGNAL wLastStage_w : std_logic;
176 SIGNAL startFFTrd_w : std_logic;
177 SIGNAL startLoad_w : std_logic;
178 SIGNAL upScale_w : std_logic;
179 SIGNAL port_xhdl15 : std_logic;
180 SIGNAL xhdl_17 : std_logic_vector(DWIDTH-1 DOWNTO 0);
181 SIGNAL xhdl_23 : std_logic_vector(DWIDTH-1 DOWNTO 0);
182 SIGNAL clkEn_const : std_logic;
183 SIGNAL ifoLoad_xhdl1 : std_logic;
184 SIGNAL ifoY_im_xhdl2 : std_logic_vector(WSIZE-1 DOWNTO 0);
185 SIGNAL ifoY_re_xhdl3 : std_logic_vector(WSIZE-1 DOWNTO 0);
186 SIGNAL ifoPong_xhdl4 : std_logic;
187 SIGNAL ifoY_valid_xhdl5 : std_logic;
188 SIGNAL ifoY_rdy_xhdl6 : std_logic;
189 SIGNAL displayBflyOutP : std_logic;
190 SIGNAL displayBflyOutQ : std_logic;
191 SIGNAL displayInBuf_wEn : std_logic;
192 SIGNAL ldValid_w : std_logic;
193
194 BEGIN
195 ifoLoad <= ifoLoad_xhdl1;
196 ifoY_im <= ifoY_im_xhdl2;
197 ifoY_re <= ifoY_re_xhdl3;
198 ifoPong <= ifoPong_xhdl4;
199 ifoY_valid <= ifoY_valid_xhdl5;
200 ifoY_rdy <= ifoY_rdy_xhdl6;
201 -- debug only
202 displayBflyOutP <= bflyOutP_w(0) ;
203 displayBflyOutQ <= bflyOutQ_w(0) ;
204 displayInBuf_wEn <= inBuf_wEn_w ;
205 port_xhdl15 <= '1';
206
207 smTop_0 : sm_top
208 GENERIC MAP ( PTS => PTS, HALFPTS => HALFPTS,
209 LOGPTS => LOGPTS, LOGLOGPTS => LOGLOGPTS, inBuf_RWDLY => inBuf_RWDLY )
210 PORT MAP (
211 clk => clk,
212 clkEn => port_xhdl15,
213 ifiStart => ifiStart,
214 ifiNreset => ifiNreset,
215 ifiD_valid => ifiD_valid,
216 ifiRead_y => ifiRead_y,
217 ldA => ldA_w,
218 rA => rA_w,
219 wA => wA_w,
220 tA => tA_w,
221 twid_wA => twid_wA_w,
222 outBuf_wA => outBuf_wA_w,
223 outBuf_rA => outBuf_rA_w,
224 wEn_even => wEn_even_w,
225 wEn_odd => wEn_odd_w,
226 preSwCross => preSwCross_w,
227 twid_wEn => twid_wEn_w,
228 inBuf_wEn => inBuf_wEn_w,
229 outBuf_wEn => outBuf_wEn_w,
230 smPong => ifoPong_xhdl4,
231 ldValid => ldValid_w,
232 inBuf_rdValid => inBufValid_w,
233 wLastStage => wLastStage_w,
234 smStartFFTrd => startFFTrd_w,
235 smStartLoad => startLoad_w,
236 ifoLoad => ifoLoad_xhdl1,
237 ifoY_valid => ifoY_valid_xhdl5,
238 ifoY_rdy => ifoY_rdy_xhdl6);
239
240 xhdl_17 <= ifiD_im & ifiD_re;
241
242 inBuf_0 : pipoBuffer
243 GENERIC MAP ( LOGPTS => LOGPTS,
244 DWIDTH => DWIDTH )
245 PORT MAP (
246 clk => clk,
247 clkEn => '1',
248 rEn => '1',
249 rA => rA_w,
250 wA_load => ldA_w,
251 wA_bfly => wA_w,
252 ldData => xhdl_17,
253 wP_bfly => outEven_w,
254 wQ_bfly => outOdd_w,
255 wEn_bfly => inBuf_wEn_w,
256 wEn_even => wEn_even_w,
257 wEn_odd => wEn_odd_w,
258 pong => ifoPong_xhdl4,
259 outP => readP_w,
260 outQ => readQ_w);
261
262 preBflySw_0 : switch
263 GENERIC MAP ( DWIDTH => DWIDTH )
264 PORT MAP (
265 clk => clk,
266 inP => readP_w,
267 inQ => readQ_w,
268 sel => preSwCross_w,
269 outP => bflyInP_w,
270 outQ => bflyInQ_w,
271 validIn => inBufValid_w,
272 validOut => preSwValid_w);
273
274 bfly_0 : bfly2
275 GENERIC MAP (RND_MODE => RND_MODE, WSIZE => WSIZE, DWIDTH => DWIDTH,
276 TWIDTH => TWIDTH, TDWIDTH => TDWIDTH )
277 PORT MAP (
278 clk => clk,
279 upScale => upScale_w,
280 inP => bflyInP_w,
281 inQ => bflyInQ_w,
282 T => T_w,
283 outP => bflyOutP_w,
284 outQ => bflyOutQ_w,
285 validIn => preSwValid_w,
286 validOut => bflyValid_w,
287 swCrossIn => preSwCross_w,
288 swCrossOut => postSwCross_w);
289
290 lut_0 : twiddle
291 PORT MAP (A => twid_wA_w, T => twidData_w);
292
293 twidLUT_1 : twidLUT
294 GENERIC MAP ( LOGPTS => LOGPTS, TDWIDTH => TDWIDTH )
295 PORT MAP (
296 clk => clk,
297 wA => twid_wA_w,
298 wEn => twid_wEn_w,
299 rA => tA_w,
300 D => twidData_w,
301 Q => T_w);
302
303 postBflySw_0 : switch
304 GENERIC MAP ( DWIDTH => DWIDTH )
305 PORT MAP (
306 clk => clk,
307 inP => bflyOutP_w,
308 inQ => bflyOutQ_w,
309 sel => postSwCross_w,
310 outP => outEven_w,
311 outQ => outOdd_w,
312 validIn => bflyValid_w,
313 validOut => open);
314
315 ifoY_im_xhdl2 <= xhdl_23(DWIDTH-1 DOWNTO WSIZE);
316 ifoY_re_xhdl3 <= xhdl_23(WSIZE-1 DOWNTO 0);
317 outBuff_0 : outBuff
318 GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
319 PORT MAP (
320 clk => clk, clkEn => '1',
321 rA => outBuf_rA_w,
322 wA => outBuf_wA_w,
323 inP => outEven_w,
324 inQ => outOdd_w,
325 wEn => outBuf_wEn_w,
326 outD => xhdl_23);
327
328 -- Autoscaling
329 -- monitor if input data .im and .re have MSB == sign
330 ldRiskOV_w <= to_logic(
331 NOT ((ifiD_im(WSIZE-1) = ifiD_im(WSIZE-2))
332 AND (ifiD_re(WSIZE-1) = ifiD_re(WSIZE-2))) );
333
334 bflyRiskOV_w <= to_logic(
335 NOT ((((bflyOutP_w(DWIDTH-1) = bflyOutP_w(DWIDTH- 2))
336 AND (bflyOutP_w(WSIZE-1) = bflyOutP_w(WSIZE-2)))
337 AND (bflyOutQ_w(DWIDTH-1) = bflyOutQ_w(DWIDTH-2)))
338 AND (bflyOutQ_w(WSIZE-1) = bflyOutQ_w(WSIZE-2))) );
339 clkEn_const <= '1';
340 autoScale_0 : autoScale
341 GENERIC MAP (SCALE_MODE => SCALE_MODE)
342 PORT MAP (
343 clk => clk,
344 clkEn => clkEn_const,
345 ldRiskOV => ldRiskOV_w,
346 bflyRiskOV => bflyRiskOV_w,
347 startLoad => startLoad_w,
348 startFFT => startFFTrd_w,
349 bflyOutValid => bflyValid_w,
350 wLastStage => wLastStage_w,
351 wEn_even => wEn_even_w,
352 wEn_odd => wEn_odd_w,
353 ifo_loadOn => ifoLoad_xhdl1,
354 upScale => upScale_w);
355
356 END ARCHITECTURE translated;
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- Package: fft_components.vhd
10 -- Description: CoreFFT
11 -- Core package
12 -- Rev: 0.1 8/31/2005 12:54PM VD : Pre Production
13 --
14 --
15 --------------------------------------------------------------------------------
16 library IEEE;
17 use IEEE.STD_LOGIC_1164.all;
18 USE IEEE.numeric_std.all;
19 USE std.textio.all;
20 USE IEEE.STD_LOGIC_TEXTIO.all;
21
22 package FFT_COMPONENTS is
23 CONSTANT gPTS : integer:=256; --Number of FFT points
24 CONSTANT gLOGPTS : integer:=8; --Log2(PTS)
25 CONSTANT gLOGLOGPTS : integer:=3; --Stage counter width
26 -------------------------------------------------
27 CONSTANT gWSIZE : integer:=16; -- FFT bit resolution; length of a re or im sample
28 CONSTANT gTWIDTH : integer:=16; -- Twiddle, sin or cos bit resolution
29 CONSTANT gHALFPTS : integer:=gPTS/2; -- Num of FFT points (PTS) divided by 2
30 CONSTANT gDWIDTH : integer:=2*gWSIZE; -- width of a complex input word,
31 CONSTANT gTDWIDTH : integer:=2*gTWIDTH; -- width of a complex twiddle factor
32 CONSTANT gRND_MODE : integer:=1; -- enable product rounding
33 CONSTANT gSCALE_MODE : integer:=0; -- scale mode
34 CONSTANT gInBuf_RWDLY : integer:=12;
35
36 function to_logic ( x : integer) return std_logic;
37 function to_logic ( x : boolean) return std_logic;
38 FUNCTION to_integer( sig : std_logic_vector) return integer;
39 function to_integer( x : boolean) return integer;
40 function maskbar (barn, bar_enable,dma_reg_bar,dma_reg_loc : integer) return integer;
41 function anyfifo (bar0, bar1, bar2, bar3, bar4, bar5 : integer) return integer;
42 FUNCTION reverse (x : std_logic_vector) RETURN bit_vector;
43 FUNCTION reverseStd(x : std_logic_vector) RETURN std_logic_vector;
44
45 COMPONENT counter
46 GENERIC (
47 WIDTH : integer := 7;
48 TERMCOUNT : integer := 127 );
49 PORT (
50 clk, nGrst, rst, cntEn : IN std_logic;
51 tc : OUT std_logic;
52 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0));
53 END COMPONENT;
54
55 COMPONENT bcounter
56 GENERIC (
57 WIDTH : integer := 7);
58 PORT (
59 clk, nGrst, rst, cntEn : IN std_logic;
60 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
61 END COMPONENT;
62
63 COMPONENT edgeDetect
64 GENERIC (
65 INPIPE :integer := 0; --if (INPIPE==1) insert input pipeline reg
66 FEDGE :integer := 0);--If FEDGE==1 detect falling edge, else-rising edge
67 PORT (
68 clk, clkEn, edgeIn : IN std_logic;
69 edgeOut : OUT std_logic);
70 END COMPONENT;
71
72 end FFT_COMPONENTS;
73
74 package body FFT_COMPONENTS is
75
76 function to_logic ( x : integer) return std_logic is
77 variable y : std_logic;
78 begin
79 if x = 0 then
80 y := '0';
81 else
82 y := '1';
83 end if;
84 return y;
85 end to_logic;
86
87 function to_logic( x : boolean) return std_logic is
88 variable y : std_logic;
89 begin
90 if x then
91 y := '1';
92 else
93 y := '0';
94 end if;
95 return(y);
96 end to_logic;
97
98 -- added 081805
99 function to_integer(sig : std_logic_vector) return integer is
100 variable num : integer := 0; -- descending sig as integer
101 begin
102 for i in sig'range loop
103 if sig(i)='1' then
104 num := num*2+1;
105 else -- use anything other than '1' as '0'
106 num := num*2;
107 end if;
108 end loop; -- i
109 return num;
110 end function to_integer;
111
112 function to_integer( x : boolean) return integer is
113 variable y : integer;
114 begin
115 if x then
116 y := 1;
117 else
118 y := 0;
119 end if;
120 return(y);
121 end to_integer;
122
123 function maskbar (barn, bar_enable,dma_reg_bar,dma_reg_loc : integer) return integer is
124 begin
125 if ( dma_reg_loc>= 2 and barn=dma_reg_bar) then
126 return(0);
127 else
128 return(bar_enable);
129 end if;
130 end maskbar;
131
132
133 function anyfifo ( bar0, bar1, bar2, bar3, bar4, bar5 : integer) return integer is
134 begin
135 if ( bar0=2 or bar1=2 or bar2=2 or bar3=2 or bar4=2 or bar5=2) then
136 return(1);
137 else
138 return(0);
139 end if;
140 end anyfifo;
141
142 FUNCTION reverse (x :IN std_logic_vector)
143 RETURN bit_vector IS
144 VARIABLE i : integer;
145 VARIABLE reverse : bit_vector(x'HIGH DOWNTO x'LOW);
146 BEGIN
147 FOR i IN x'range LOOP
148 reverse(i) := To_bit( x(x'HIGH - i));
149 END LOOP;
150 RETURN(reverse);
151 END FUNCTION reverse;
152
153 FUNCTION reverseStd (x :IN std_logic_vector)
154 RETURN std_logic_vector IS
155 VARIABLE i : integer;
156 VARIABLE reverse : std_logic_vector(x'HIGH DOWNTO x'LOW);
157 BEGIN
158 FOR i IN x'range LOOP
159 reverse(i) := x(x'HIGH - i);
160 END LOOP;
161 RETURN(reverse);
162 END FUNCTION reverseStd;
163
164 end FFT_COMPONENTS;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 use lpp.fft_components.all;
30
31 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32
33 package lpp_fft is
34
35 component APB_FFT is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8;
42 Data_sz : integer := 16
43 );
44 port (
45 clk : in std_logic;
46 rst : in std_logic; --! Reset general du composant
47 apbi : in apb_slv_in_type;
48 apbo : out apb_slv_out_type
49 );
50 end component;
51
52
53 component APB_FFT_half is
54 generic (
55 pindex : integer := 0;
56 paddr : integer := 0;
57 pmask : integer := 16#fff#;
58 pirq : integer := 0;
59 abits : integer := 8;
60 Data_sz : integer := 16
61 );
62 port (
63 clk : in std_logic; --! Horloge du composant
64 rst : in std_logic; --! Reset general du composant
65 Ren : in std_logic;
66 ready : out std_logic;
67 valid : out std_logic;
68 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
69 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
70 OUTfill : out std_logic;
71 OUTwrite : out std_logic;
72 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
73 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
74 );
75 end component;
76
77 component FFT is
78 generic(
79 Data_sz : integer := 16;
80 NbData : integer := 256);
81 port(
82 clkm : in std_logic;
83 rstn : in std_logic;
84 FifoIN_Empty : in std_logic_vector(4 downto 0);
85 FifoIN_Data : in std_logic_vector(79 downto 0);
86 FifoOUT_Full : in std_logic_vector(4 downto 0);
87 Load : out std_logic;
88 Read : out std_logic_vector(4 downto 0);
89 Write : out std_logic_vector(4 downto 0);
90 ReUse : out std_logic_vector(4 downto 0);
91 Data : out std_logic_vector(79 downto 0)
92 );
93 end component;
94
95 component Flag_Extremum is
96 port(
97 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
98 load : in std_logic; --! Signal en provenance de CoreFFT
99 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
100 fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
101 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
102 );
103 end component;
104
105
106 component Linker_FFT is
107 generic(
108 Data_sz : integer range 1 to 32 := 16;
109 NbData : integer range 1 to 512 := 256
110 );
111 port(
112 clk : in std_logic;
113 rstn : in std_logic;
114 Ready : in std_logic;
115 Valid : in std_logic;
116 Full : in std_logic_vector(4 downto 0);
117 Data_re : in std_logic_vector(Data_sz-1 downto 0);
118 Data_im : in std_logic_vector(Data_sz-1 downto 0);
119 Read : out std_logic;
120 Write : out std_logic_vector(4 downto 0);
121 ReUse : out std_logic_vector(4 downto 0);
122 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
123 );
124 end component;
125
126
127 component Driver_FFT is
128 generic(
129 Data_sz : integer range 1 to 32 := 16;
130 NbData : integer range 1 to 512 := 256
131 );
132 port(
133 clk : in std_logic;
134 rstn : in std_logic;
135 Load : in std_logic;
136 Empty : in std_logic_vector(4 downto 0);
137 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
138 Valid : out std_logic;
139 Read : out std_logic_vector(4 downto 0);
140 Data_re : out std_logic_vector(Data_sz-1 downto 0);
141 Data_im : out std_logic_vector(Data_sz-1 downto 0)
142 );
143 end component;
144
145 component FFTamont is
146 generic(
147 Data_sz : integer range 1 to 32 := 16;
148 NbData : integer range 1 to 512 := 256
149 );
150 port(
151 clk : in std_logic;
152 rstn : in std_logic;
153 Load : in std_logic;
154 Empty : in std_logic;
155 DATA : in std_logic_vector(Data_sz-1 downto 0);
156 Valid : out std_logic;
157 Read : out std_logic;
158 Data_re : out std_logic_vector(Data_sz-1 downto 0);
159 Data_im : out std_logic_vector(Data_sz-1 downto 0)
160 );
161 end component;
162
163 component FFTaval is
164 generic(
165 Data_sz : integer range 1 to 32 := 8;
166 NbData : integer range 1 to 512 := 256
167 );
168 port(
169 clk : in std_logic;
170 rstn : in std_logic;
171 Ready : in std_logic;
172 Valid : in std_logic;
173 Full : in std_logic;
174 Data_re : in std_logic_vector(Data_sz-1 downto 0);
175 Data_im : in std_logic_vector(Data_sz-1 downto 0);
176 Read : out std_logic;
177 Write : out std_logic;
178 ReUse : out std_logic;
179 DATA : out std_logic_vector(Data_sz-1 downto 0)
180 );
181 end component;
182 --==============================================================|
183 --================== IP VHDL de la FFT actel ===================|
184 --================ non partag� dans la VHD_Lib =================|
185 --==============================================================|
186
187 component CoreFFT IS
188 GENERIC (
189 LOGPTS : integer := gLOGPTS;
190 LOGLOGPTS : integer := gLOGLOGPTS;
191 WSIZE : integer := gWSIZE;
192 TWIDTH : integer := gTWIDTH;
193 DWIDTH : integer := gDWIDTH;
194 TDWIDTH : integer := gTDWIDTH;
195 RND_MODE : integer := gRND_MODE;
196 SCALE_MODE : integer := gSCALE_MODE;
197 PTS : integer := gPTS;
198 HALFPTS : integer := gHALFPTS;
199 inBuf_RWDLY : integer := gInBuf_RWDLY );
200 PORT (
201 clk,ifiStart,ifiNreset : IN std_logic;
202 ifiD_valid, ifiRead_y : IN std_logic;
203 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
204 ifoLoad, ifoPong : OUT std_logic;
205 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
206 ifoY_valid, ifoY_rdy : OUT std_logic);
207 END component;
208
209
210 component actar is
211 port( DataA : in std_logic_vector(15 downto 0); DataB : in
212 std_logic_vector(15 downto 0); Mult : out
213 std_logic_vector(31 downto 0);Clock : in std_logic) ;
214 end component;
215
216 component actram is
217 port( DI : in std_logic_vector(31 downto 0); DO : out
218 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
219 WADDR : in std_logic_vector(6 downto 0); RADDR : in
220 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
221 std_logic) ;
222 end component;
223
224 component switch IS
225 GENERIC ( DWIDTH : integer := 32 );
226 PORT (
227 clk, sel, validIn : IN std_logic;
228 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
229 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
230 validOut : OUT std_logic);
231 END component;
232
233 component twid_rA IS
234 GENERIC (LOGPTS : integer := 8;
235 LOGLOGPTS : integer := 3 );
236 PORT (clk : IN std_logic;
237 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
238 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
239 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
240 END component;
241
242 component counter IS
243 GENERIC (
244 WIDTH : integer := 7;
245 TERMCOUNT : integer := 127 );
246 PORT (
247 clk, nGrst, rst, cntEn : IN std_logic;
248 tc : OUT std_logic;
249 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
250 END component;
251
252
253 component twiddle IS
254 PORT (
255 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
256 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
257 END component;
258
259
260 end; No newline at end of file
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: primitives.vhd
10 -- Description: CoreFFT
11 -- FFT primitives module
12 -- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
13 --
14 --
15 --------------------------------------------------------------------------------
16 -- counts up to TERMCOUNT, then jumps to 0.
17 -- Generates tc signal on count==TERMCOUNT-1
18 LIBRARY IEEE;
19 USE IEEE.std_logic_1164.all;
20 USE IEEE.numeric_std.all;
21 USE work.fft_components.all;
22
23 ENTITY counter IS
24 GENERIC (
25 WIDTH : integer := 7;
26 TERMCOUNT : integer := 127 );
27 PORT (
28 clk, nGrst, rst, cntEn : IN std_logic;
29 tc : OUT std_logic;
30 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
31 END ENTITY counter;
32
33 ARCHITECTURE translated OF counter IS
34 SIGNAL tc_out : std_logic;
35 SIGNAL Q_out : unsigned(WIDTH-1 DOWNTO 0);
36
37 BEGIN
38 tc <= tc_out;
39 Q <= std_logic_vector(Q_out);
40 PROCESS (clk, nGrst)
41 BEGIN
42 IF (nGrst = '0') THEN
43 Q_out <= (OTHERS => '0');
44 tc_out <= '0';
45 ELSIF (clk'EVENT AND clk = '1') THEN -- nGrst!=0
46 IF (rst = '1') THEN
47 Q_out <= (OTHERS => '0');
48 tc_out <= '0';
49 ELSE
50 IF (cntEn = '1') THEN -- start cntEn
51 tc_out <= to_logic( Q_out = to_unsigned((TERMCOUNT-1),WIDTH));
52 IF (Q_out = to_unsigned(TERMCOUNT, WIDTH)) THEN
53 Q_out <= (OTHERS => '0');
54 ELSE
55 Q_out <= unsigned(Q_out) + to_unsigned(1, WIDTH);
56 END IF;
57 END IF; -- end cntEn
58 END IF; -- end rst
59 END IF; -- end nGrst
60 END PROCESS;
61 END ARCHITECTURE translated;
62
63 --------------------------------------------------------------------------
64 -- binary counter with no feedback. Counts up to 2^WIDTH - 1
65 LIBRARY IEEE;
66 USE IEEE.std_logic_1164.all;
67 USE IEEE.numeric_std.all;
68
69 ENTITY bcounter IS
70 GENERIC (WIDTH : integer:=7 );
71 PORT (clk, nGrst, rst, cntEn : IN std_logic;
72 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0));
73 END ENTITY bcounter;
74
75 ARCHITECTURE translated OF bcounter IS
76 SIGNAL Q_out : unsigned(WIDTH-1 DOWNTO 0);
77
78 BEGIN
79 Q <= std_logic_vector(Q_out);
80 PROCESS (clk, nGrst)
81 BEGIN
82 IF (nGrst = '0') THEN
83 Q_out <= (OTHERS => '0');
84 ELSIF (clk'EVENT AND clk = '1') THEN
85 IF (cntEn = '1') THEN
86 IF (rst = '1') THEN
87 Q_out <= (OTHERS => '0');
88 ELSE
89 Q_out <= unsigned(Q_out) + to_unsigned(1, WIDTH);
90 END IF;
91 END IF;
92 END IF;
93 END PROCESS;
94 END ARCHITECTURE translated;
95 --------------------------------------------------------------------------
96 -- rising-falling edge detector
97 LIBRARY IEEE;
98 USE IEEE.std_logic_1164.all;
99
100 ENTITY edgeDetect IS
101 GENERIC (
102 INPIPE :integer := 0; --if (INPIPE==1) insert input pipeline reg
103 FEDGE :integer := 0);--If FEDGE==1 detect falling edge, else-rising edge
104 PORT (
105 clk, clkEn, edgeIn : IN std_logic;
106 edgeOut : OUT std_logic);
107 END ENTITY edgeDetect;
108
109 ARCHITECTURE translated OF edgeDetect IS
110 SIGNAL in_pipe, in_t1 : std_logic; -- regs
111 SIGNAL temp_input : std_logic;
112 SIGNAL in_w : std_logic;
113 SIGNAL temp_output : std_logic;
114 SIGNAL out_w : std_logic;
115 SIGNAL output_reg : std_logic;
116
117 BEGIN
118 edgeOut <= output_reg;
119 temp_input <= (in_pipe) WHEN INPIPE /= 0 ELSE edgeIn;
120 in_w <= temp_input ;
121 temp_output<=
122 ((NOT in_w) AND in_t1) WHEN FEDGE /= 0 ELSE (in_w AND (NOT in_t1));
123 out_w <= temp_output ;
124
125 PROCESS (clk)
126 BEGIN
127 IF (clk'EVENT AND clk = '1') THEN
128 in_pipe <= edgeIn;
129 in_t1 <= in_w;
130 output_reg <= out_w;
131 END IF;
132 END PROCESS;
133 END ARCHITECTURE translated;
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1 --------------------------------------------------------------------------------
2 -- Copyright 2007 Actel Corporation. All rights reserved.
3
4 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
5 -- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
6 -- IN ADVANCE IN WRITING.
7
8 -- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
9 -- File: twiddle.v
10 --
11 -- Description: CoreFFT
12 -- Twiddle factor table
13 --
14 -- Rev: 0.1 5/10/2005 8:36AM VD : Pre Production
15 -- History: 5/10/2005 8:36AM - created
16 --
17 --------------------------------------------------------------------------------
18 LIBRARY IEEE;
19 USE IEEE.std_logic_1164.all;
20 USE work.fft_components.all;
21
22 ENTITY twiddle IS
23 PORT (
24 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
25 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
26 END ENTITY twiddle;
27
28 ARCHITECTURE translated OF twiddle IS
29 SIGNAL T_int : std_logic_vector(gTDWIDTH-1 DOWNTO 0);
30
31 BEGIN
32 T <= T_int;
33
34 PROCESS (A)
35 VARIABLE T_int1 : std_logic_vector(gTDWIDTH-1 DOWNTO 0);
36 BEGIN
37 CASE A IS -- synopsys parallel_case
38 WHEN "0000000" => T_int1 := "00000000000000000111111111111111"; -- X0000 X7fff
39 WHEN "0000001" => T_int1 := "00000011001001000111111111110101"; -- X0324 X7ff5
40 WHEN "0000010" => T_int1 := "00000110010010000111111111011000"; -- X0648 X7fd8
41 WHEN "0000011" => T_int1 := "00001001011010100111111110100110"; -- X096a X7fa6
42 WHEN "0000100" => T_int1 := "00001100100011000111111101100001"; -- X0c8c X7f61
43 WHEN "0000101" => T_int1 := "00001111101010110111111100001001"; -- X0fab X7f09
44 WHEN "0000110" => T_int1 := "00010010110010000111111010011100"; -- X12c8 X7e9c
45 WHEN "0000111" => T_int1 := "00010101111000100111111000011101"; -- X15e2 X7e1d
46 WHEN "0001000" => T_int1 := "00011000111110010111110110001001"; -- X18f9 X7d89
47 WHEN "0001001" => T_int1 := "00011100000010110111110011100011"; -- X1c0b X7ce3
48 WHEN "0001010" => T_int1 := "00011111000110100111110000101001"; -- X1f1a X7c29
49 WHEN "0001011" => T_int1 := "00100010001000110111101101011100"; -- X2223 X7b5c
50 WHEN "0001100" => T_int1 := "00100101001010000111101001111100"; -- X2528 X7a7c
51 WHEN "0001101" => T_int1 := "00101000001001100111100110001001"; -- X2826 X7989
52 WHEN "0001110" => T_int1 := "00101011000111110111100010000100"; -- X2b1f X7884
53 WHEN "0001111" => T_int1 := "00101110000100010111011101101011"; -- X2e11 X776b
54 WHEN "0010000" => T_int1 := "00110000111110110111011001000001"; -- X30fb X7641
55 WHEN "0010001" => T_int1 := "00110011110111110111010100000100"; -- X33df X7504
56 WHEN "0010010" => T_int1 := "00110110101110100111001110110101"; -- X36ba X73b5
57 WHEN "0010011" => T_int1 := "00111001100011000111001001010100"; -- X398c X7254
58 WHEN "0010100" => T_int1 := "00111100010101100111000011100010"; -- X3c56 X70e2
59 WHEN "0010101" => T_int1 := "00111111000101110110111101011110"; -- X3f17 X6f5e
60 WHEN "0010110" => T_int1 := "01000001110011100110110111001001"; -- X41ce X6dc9
61 WHEN "0010111" => T_int1 := "01000100011110100110110000100011"; -- X447a X6c23
62 WHEN "0011000" => T_int1 := "01000111000111000110101001101101"; -- X471c X6a6d
63 WHEN "0011001" => T_int1 := "01001001101101000110100010100110"; -- X49b4 X68a6
64 WHEN "0011010" => T_int1 := "01001100001111110110011011001111"; -- X4c3f X66cf
65 WHEN "0011011" => T_int1 := "01001110101111110110010011101000"; -- X4ebf X64e8
66 WHEN "0011100" => T_int1 := "01010001001100110110001011110001"; -- X5133 X62f1
67 WHEN "0011101" => T_int1 := "01010011100110110110000011101011"; -- X539b X60eb
68 WHEN "0011110" => T_int1 := "01010101111101010101111011010111"; -- X55f5 X5ed7
69 WHEN "0011111" => T_int1 := "01011000010000100101110010110011"; -- X5842 X5cb3
70 WHEN "0100000" => T_int1 := "01011010100000100101101010000010"; -- X5a82 X5a82
71 WHEN "0100001" => T_int1 := "01011100101100110101100001000010"; -- X5cb3 X5842
72 WHEN "0100010" => T_int1 := "01011110110101110101010111110101"; -- X5ed7 X55f5
73 WHEN "0100011" => T_int1 := "01100000111010110101001110011011"; -- X60eb X539b
74 WHEN "0100100" => T_int1 := "01100010111100010101000100110011"; -- X62f1 X5133
75 WHEN "0100101" => T_int1 := "01100100111010000100111010111111"; -- X64e8 X4ebf
76 WHEN "0100110" => T_int1 := "01100110110011110100110000111111"; -- X66cf X4c3f
77 WHEN "0100111" => T_int1 := "01101000101001100100100110110100"; -- X68a6 X49b4
78 WHEN "0101000" => T_int1 := "01101010011011010100011100011100"; -- X6a6d X471c
79 WHEN "0101001" => T_int1 := "01101100001000110100010001111010"; -- X6c23 X447a
80 WHEN "0101010" => T_int1 := "01101101110010010100000111001110"; -- X6dc9 X41ce
81 WHEN "0101011" => T_int1 := "01101111010111100011111100010111"; -- X6f5e X3f17
82 WHEN "0101100" => T_int1 := "01110000111000100011110001010110"; -- X70e2 X3c56
83 WHEN "0101101" => T_int1 := "01110010010101000011100110001100"; -- X7254 X398c
84 WHEN "0101110" => T_int1 := "01110011101101010011011010111010"; -- X73b5 X36ba
85 WHEN "0101111" => T_int1 := "01110101000001000011001111011111"; -- X7504 X33df
86 WHEN "0110000" => T_int1 := "01110110010000010011000011111011"; -- X7641 X30fb
87 WHEN "0110001" => T_int1 := "01110111011010110010111000010001"; -- X776b X2e11
88 WHEN "0110010" => T_int1 := "01111000100001000010101100011111"; -- X7884 X2b1f
89 WHEN "0110011" => T_int1 := "01111001100010010010100000100110"; -- X7989 X2826
90 WHEN "0110100" => T_int1 := "01111010011111000010010100101000"; -- X7a7c X2528
91 WHEN "0110101" => T_int1 := "01111011010111000010001000100011"; -- X7b5c X2223
92 WHEN "0110110" => T_int1 := "01111100001010010001111100011010"; -- X7c29 X1f1a
93 WHEN "0110111" => T_int1 := "01111100111000110001110000001011"; -- X7ce3 X1c0b
94 WHEN "0111000" => T_int1 := "01111101100010010001100011111001"; -- X7d89 X18f9
95 WHEN "0111001" => T_int1 := "01111110000111010001010111100010"; -- X7e1d X15e2
96 WHEN "0111010" => T_int1 := "01111110100111000001001011001000"; -- X7e9c X12c8
97 WHEN "0111011" => T_int1 := "01111111000010010000111110101011"; -- X7f09 X0fab
98 WHEN "0111100" => T_int1 := "01111111011000010000110010001100"; -- X7f61 X0c8c
99 WHEN "0111101" => T_int1 := "01111111101001100000100101101010"; -- X7fa6 X096a
100 WHEN "0111110" => T_int1 := "01111111110110000000011001001000"; -- X7fd8 X0648
101 WHEN "0111111" => T_int1 := "01111111111101010000001100100100"; -- X7ff5 X0324
102 WHEN "1000000" => T_int1 := "01111111111111110000000000000000"; -- X7fff X0000
103 WHEN "1000001" => T_int1 := "01111111111101011111110011011100"; -- X7ff5 Xfcdc
104 WHEN "1000010" => T_int1 := "01111111110110001111100110111000"; -- X7fd8 Xf9b8
105 WHEN "1000011" => T_int1 := "01111111101001101111011010010110"; -- X7fa6 Xf696
106 WHEN "1000100" => T_int1 := "01111111011000011111001101110100"; -- X7f61 Xf374
107 WHEN "1000101" => T_int1 := "01111111000010011111000001010101"; -- X7f09 Xf055
108 WHEN "1000110" => T_int1 := "01111110100111001110110100111000"; -- X7e9c Xed38
109 WHEN "1000111" => T_int1 := "01111110000111011110101000011110"; -- X7e1d Xea1e
110 WHEN "1001000" => T_int1 := "01111101100010011110011100000111"; -- X7d89 Xe707
111 WHEN "1001001" => T_int1 := "01111100111000111110001111110101"; -- X7ce3 Xe3f5
112 WHEN "1001010" => T_int1 := "01111100001010011110000011100110"; -- X7c29 Xe0e6
113 WHEN "1001011" => T_int1 := "01111011010111001101110111011101"; -- X7b5c Xdddd
114 WHEN "1001100" => T_int1 := "01111010011111001101101011011000"; -- X7a7c Xdad8
115 WHEN "1001101" => T_int1 := "01111001100010011101011111011010"; -- X7989 Xd7da
116 WHEN "1001110" => T_int1 := "01111000100001001101010011100001"; -- X7884 Xd4e1
117 WHEN "1001111" => T_int1 := "01110111011010111101000111101111"; -- X776b Xd1ef
118 WHEN "1010000" => T_int1 := "01110110010000011100111100000101"; -- X7641 Xcf05
119 WHEN "1010001" => T_int1 := "01110101000001001100110000100001"; -- X7504 Xcc21
120 WHEN "1010010" => T_int1 := "01110011101101011100100101000110"; -- X73b5 Xc946
121 WHEN "1010011" => T_int1 := "01110010010101001100011001110100"; -- X7254 Xc674
122 WHEN "1010100" => T_int1 := "01110000111000101100001110101010"; -- X70e2 Xc3aa
123 WHEN "1010101" => T_int1 := "01101111010111101100000011101001"; -- X6f5e Xc0e9
124 WHEN "1010110" => T_int1 := "01101101110010011011111000110010"; -- X6dc9 Xbe32
125 WHEN "1010111" => T_int1 := "01101100001000111011101110000110"; -- X6c23 Xbb86
126 WHEN "1011000" => T_int1 := "01101010011011011011100011100100"; -- X6a6d Xb8e4
127 WHEN "1011001" => T_int1 := "01101000101001101011011001001100"; -- X68a6 Xb64c
128 WHEN "1011010" => T_int1 := "01100110110011111011001111000001"; -- X66cf Xb3c1
129 WHEN "1011011" => T_int1 := "01100100111010001011000101000001"; -- X64e8 Xb141
130 WHEN "1011100" => T_int1 := "01100010111100011010111011001101"; -- X62f1 Xaecd
131 WHEN "1011101" => T_int1 := "01100000111010111010110001100101"; -- X60eb Xac65
132 WHEN "1011110" => T_int1 := "01011110110101111010101000001011"; -- X5ed7 Xaa0b
133 WHEN "1011111" => T_int1 := "01011100101100111010011110111110"; -- X5cb3 Xa7be
134 WHEN "1100000" => T_int1 := "01011010100000101010010101111110"; -- X5a82 Xa57e
135 WHEN "1100001" => T_int1 := "01011000010000101010001101001101"; -- X5842 Xa34d
136 WHEN "1100010" => T_int1 := "01010101111101011010000100101001"; -- X55f5 Xa129
137 WHEN "1100011" => T_int1 := "01010011100110111001111100010101"; -- X539b X9f15
138 WHEN "1100100" => T_int1 := "01010001001100111001110100001111"; -- X5133 X9d0f
139 WHEN "1100101" => T_int1 := "01001110101111111001101100011000"; -- X4ebf X9b18
140 WHEN "1100110" => T_int1 := "01001100001111111001100100110001"; -- X4c3f X9931
141 WHEN "1100111" => T_int1 := "01001001101101001001011101011010"; -- X49b4 X975a
142 WHEN "1101000" => T_int1 := "01000111000111001001010110010011"; -- X471c X9593
143 WHEN "1101001" => T_int1 := "01000100011110101001001111011101"; -- X447a X93dd
144 WHEN "1101010" => T_int1 := "01000001110011101001001000110111"; -- X41ce X9237
145 WHEN "1101011" => T_int1 := "00111111000101111001000010100010"; -- X3f17 X90a2
146 WHEN "1101100" => T_int1 := "00111100010101101000111100011110"; -- X3c56 X8f1e
147 WHEN "1101101" => T_int1 := "00111001100011001000110110101100"; -- X398c X8dac
148 WHEN "1101110" => T_int1 := "00110110101110101000110001001011"; -- X36ba X8c4b
149 WHEN "1101111" => T_int1 := "00110011110111111000101011111100"; -- X33df X8afc
150 WHEN "1110000" => T_int1 := "00110000111110111000100110111111"; -- X30fb X89bf
151 WHEN "1110001" => T_int1 := "00101110000100011000100010010101"; -- X2e11 X8895
152 WHEN "1110010" => T_int1 := "00101011000111111000011101111100"; -- X2b1f X877c
153 WHEN "1110011" => T_int1 := "00101000001001101000011001110111"; -- X2826 X8677
154 WHEN "1110100" => T_int1 := "00100101001010001000010110000100"; -- X2528 X8584
155 WHEN "1110101" => T_int1 := "00100010001000111000010010100100"; -- X2223 X84a4
156 WHEN "1110110" => T_int1 := "00011111000110101000001111010111"; -- X1f1a X83d7
157 WHEN "1110111" => T_int1 := "00011100000010111000001100011101"; -- X1c0b X831d
158 WHEN "1111000" => T_int1 := "00011000111110011000001001110111"; -- X18f9 X8277
159 WHEN "1111001" => T_int1 := "00010101111000101000000111100011"; -- X15e2 X81e3
160 WHEN "1111010" => T_int1 := "00010010110010001000000101100100"; -- X12c8 X8164
161 WHEN "1111011" => T_int1 := "00001111101010111000000011110111"; -- X0fab X80f7
162 WHEN "1111100" => T_int1 := "00001100100011001000000010011111"; -- X0c8c X809f
163 WHEN "1111101" => T_int1 := "00001001011010101000000001011010"; -- X096a X805a
164 WHEN "1111110" => T_int1 := "00000110010010001000000000101000"; -- X0648 X8028
165 WHEN "1111111" => T_int1 := "00000011001001001000000000001011"; -- X0324 X800b
166 WHEN OTHERS => NULL;
167 END CASE;
168 T_int <= T_int1;
169 END PROCESS;
170
171 END ARCHITECTURE translated;
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1 NO CONTENT: new file 100644
NO CONTENT: new file 100644
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@@ -0,0 +1,16
1 fft_components.vhd
2 lpp_fft.vhd
3 actar.vhd
4 actram.vhd
5 CoreFFT.vhd
6 fftDp.vhd
7 fftSm.vhd
8 primitives.vhd
9 twiddle.vhd
10 APB_FFT.vhd
11 Driver_FFT.vhd
12 FFT.vhd
13 FFTamont.vhd
14 FFTaval.vhd
15 Flag_Extremum.vhd
16 Linker_FFT.vhd
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@@ -514,7 +514,7 BEGIN -- beh
514 pirq_ms => 6,
514 pirq_ms => 6,
515 pirq_wfp => 14,
515 pirq_wfp => 14,
516 hindex => 2,
516 hindex => 2,
517 top_lfr_version => X"000154") -- aa.bb.cc version
517 top_lfr_version => X"000159") -- aa.bb.cc version
518 PORT MAP (
518 PORT MAP (
519 clk => clk_25,
519 clk => clk_25,
520 rstn => LFR_rstn,
520 rstn => LFR_rstn,
@@ -653,4 +653,4 BEGIN -- beh
653 END GENERATE ahbo_m_ext_not_used;
653 END GENERATE ahbo_m_ext_not_used;
654 END GENERATE all_ahbo_m_ext;
654 END GENERATE all_ahbo_m_ext;
655
655
656 END beh; No newline at end of file
656 END beh;
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@@ -16,23 +16,23 nb_point = 256
16 t = np.arange(nb_point)
16 t = np.arange(nb_point)
17
17
18 ## f0
18 ## f0
19 ampl_f0_0 = pow(2,14)
19 ampl_f0_0 = pow(2,16)-1
20 freq_f0_0 = float(16)/256
20 freq_f0_0 = float(16)/256
21 phi_f0_0 = 0
21 phi_f0_0 = 0
22
22
23 ampl_f0_1 = pow(2,13)
23 ampl_f0_1 = pow(2,15)-1
24 freq_f0_1 = float(16)/256
24 freq_f0_1 = float(16)/256
25 phi_f0_1 = 0
25 phi_f0_1 = 0
26
26
27 ampl_f0_2 = pow(2,12)
27 ampl_f0_2 = pow(2,14)-1
28 freq_f0_2 = float(16)/256
28 freq_f0_2 = float(16)/256
29 phi_f0_2 = 0
29 phi_f0_2 = 0
30
30
31 ampl_f0_3 = pow(2,11)
31 ampl_f0_3 = pow(2,13)-1
32 freq_f0_3 = float(16)/256
32 freq_f0_3 = float(16)/256
33 phi_f0_3 = 0
33 phi_f0_3 = 0
34
34
35 ampl_f0_4 = pow(2,10)
35 ampl_f0_4 = pow(2,10)-1
36 freq_f0_4 = float(16)/256
36 freq_f0_4 = float(16)/256
37 phi_f0_4 = 0
37 phi_f0_4 = 0
38
38
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