diff --git a/designs/LFR-RTAX_keypoint/LFR-EQM.vhd b/designs/LFR-RTAX_keypoint/LFR-EQM.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR-RTAX_keypoint/LFR-EQM.vhd @@ -0,0 +1,605 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +USE techmap.axcomp.ALL; + +LIBRARY gaisler; +USE gaisler.sim.ALL; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; +LIBRARY esa; +USE esa.memoryctrl.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib +USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_management.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; + +--library proasic3l; +--use proasic3l.all; + +ENTITY LFR_EQM IS + GENERIC ( + Mem_use : INTEGER := use_RAM; + USE_BOOTLOADER : INTEGER := 0; + USE_ADCDRIVER : INTEGER := 1; + tech : INTEGER := inferred; + tech_leon : INTEGER := inferred; + DEBUG_FORCE_DATA_DMA : INTEGER := 0; + USE_DEBUG_VECTOR : INTEGER := 0 + ); + + PORT ( + clk50MHz : IN STD_ULOGIC; + clk49_152MHz : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + + TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); + + -- TAG -------------------------------------------------------------------- + --TAG1 : IN STD_ULOGIC; -- DSU rx data + --TAG3 : OUT STD_ULOGIC; -- DSU tx data + -- UART APB --------------------------------------------------------------- + --TAG2 : IN STD_ULOGIC; -- UART1 rx data + --TAG4 : OUT STD_ULOGIC; -- UART1 tx data + -- RAM -------------------------------------------------------------------- + address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + nSRAM_MBE : INOUT STD_LOGIC; -- new + nSRAM_E1 : OUT STD_LOGIC; -- new + nSRAM_E2 : OUT STD_LOGIC; -- new +-- nSRAM_SCRUB : OUT STD_LOGIC; -- new + nSRAM_W : OUT STD_LOGIC; -- new + nSRAM_G : OUT STD_LOGIC; -- new + nSRAM_BUSY : IN STD_LOGIC; -- new + -- SPW -------------------------------------------------------------------- + spw1_en : OUT STD_LOGIC; -- new + spw1_din : IN STD_LOGIC; + spw1_sin : IN STD_LOGIC; + spw1_dout : OUT STD_LOGIC; + spw1_sout : OUT STD_LOGIC; + spw2_en : OUT STD_LOGIC; -- new + spw2_din : IN STD_LOGIC; + spw2_sin : IN STD_LOGIC; + spw2_dout : OUT STD_LOGIC; + spw2_sout : OUT STD_LOGIC; + -- ADC -------------------------------------------------------------------- + bias_fail_sw : OUT STD_LOGIC; + ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ADC_smpclk : OUT STD_LOGIC; + ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + -- DAC -------------------------------------------------------------------- + DAC_SDO : OUT STD_LOGIC; + DAC_SCK : OUT STD_LOGIC; + DAC_SYNC : OUT STD_LOGIC; + DAC_CAL_EN : OUT STD_LOGIC; + -- HK --------------------------------------------------------------------- + HK_smpclk : OUT STD_LOGIC; + ADC_OEB_bar_HK : OUT STD_LOGIC; + HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + +END LFR_EQM; + + +ARCHITECTURE beh OF LFR_EQM IS + + SIGNAL clk_25_int : STD_LOGIC := '0'; + SIGNAL clk_25 : STD_LOGIC := '0'; + SIGNAL clk_24 : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + + -- CONSTANTS + CONSTANT CFG_PADTECH : INTEGER := inferred; + CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f + CONSTANT NB_AHB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker + + SIGNAL apbi_ext : apb_slv_in_type; + SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); + SIGNAL ahbi_s_ext : ahb_slv_in_type; + SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); + SIGNAL ahbi_m_ext : AHB_Mst_In_Type; + SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL swni : grspw_in_type; + SIGNAL swno : grspw_out_type; + +--GPIO + SIGNAL gpioi : gpio_in_type; + SIGNAL gpioo : gpio_out_type; + +-- AD Converter ADS7886 + SIGNAL sample : Samples14v(8 DOWNTO 0); + SIGNAL sample_s : Samples(8 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL LFR_rstn_int : STD_LOGIC := '0'; + SIGNAL rstn_25_int : STD_LOGIC := '0'; + SIGNAL rstn_25 : STD_LOGIC; + SIGNAL rstn_24 : STD_LOGIC; + + SIGNAL LFR_soft_rstn : STD_LOGIC; + SIGNAL LFR_rstn : STD_LOGIC; + + SIGNAL ADC_smpclk_s : STD_LOGIC; + + SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL clk50MHz_int : STD_LOGIC := '0'; + + component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; + + SIGNAL rstn_50 : STD_LOGIC; + SIGNAL clk_lock : STD_LOGIC; + SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL nSRAM_BUSY_reg : STD_LOGIC; + + SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL ahbrxd: STD_LOGIC; + SIGNAL ahbtxd: STD_LOGIC; + SIGNAL urxd1 : STD_LOGIC; + SIGNAL utxd1 : STD_LOGIC; +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- CLK_LOCK + ----------------------------------------------------------------------------- + rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); + + PROCESS (clk50MHz_int, rstn_50) + BEGIN -- PROCESS + IF rstn_50 = '0' THEN -- asynchronous reset (active low) + clk_lock <= '0'; + clk_busy_counter <= (OTHERS => '0'); + nSRAM_BUSY_reg <= '0'; + ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge + nSRAM_BUSY_reg <= nSRAM_BUSY; + IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN + IF clk_busy_counter = "1111" THEN + clk_lock <= '1'; + ELSE + clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); + END IF; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- CLK + ----------------------------------------------------------------------------- + rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25_int, OPEN); + rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); + + rstn_pad_25 : clkint port map (A => rstn_25_int, Y => rstn_25 ); + + --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); + clk50MHz_int <= clk50MHz; + + PROCESS(clk50MHz_int) + BEGIN + IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN + clk_25_int <= NOT clk_25_int; + --clk_25 <= NOT clk_25; + END IF; + END PROCESS; + clk_pad_25 : hclkint port map (A => clk_25_int, Y => clk_25 ); + + PROCESS(clk49_152MHz) + BEGIN + IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN + clk_24 <= NOT clk_24; + END IF; + END PROCESS; +-- clk_49 <= clk49_152MHz; + + ----------------------------------------------------------------------------- + leon3_soc_1 : leon3_soc + GENERIC MAP ( + fabtech => axcel,--inferred,--axdsp, + memtech => axcel,--inferred,--tech_leon, + padtech => axcel,--inferred, + clktech => axcel,--inferred, + disas => 0, + dbguart => 0, + pclow => 2, + clk_freq => 25000, + IS_RADHARD => 1, + NB_CPU => 1, + ENABLE_FPU => 1, + FPU_NETLIST => 0, + ENABLE_DSU => 1, + ENABLE_AHB_UART => 0, + ENABLE_APB_UART => 1, + ENABLE_IRQMP => 1, + ENABLE_GPT => 1, + NB_AHB_MASTER => NB_AHB_MASTER, + NB_AHB_SLAVE => NB_AHB_SLAVE, + NB_APB_SLAVE => NB_APB_SLAVE, + ADDRESS_SIZE => 19, + USES_IAP_MEMCTRLR => 1, + BYPASS_EDAC_MEMCTRLR => '0', + SRBANKSZ => 8) + PORT MAP ( + clk => clk_25, + reset => rstn_25, + errorn => OPEN, + + ahbrxd => ahbrxd, -- INPUT + ahbtxd => ahbtxd, -- OUTPUT + urxd1 => urxd1, -- INPUT + utxd1 => utxd1, -- OUTPUT + + address => address, + data => data, + nSRAM_BE0 => OPEN, + nSRAM_BE1 => OPEN, + nSRAM_BE2 => OPEN, + nSRAM_BE3 => OPEN, + nSRAM_WE => nSRAM_W, + nSRAM_CE => nSRAM_CE, + nSRAM_OE => nSRAM_G, + nSRAM_READY => nSRAM_BUSY, + SRAM_MBE => nSRAM_MBE, + + apbi_ext => apbi_ext, + apbo_ext => apbo_ext, + ahbi_s_ext => ahbi_s_ext, + ahbo_s_ext => ahbo_s_ext, + ahbi_m_ext => ahbi_m_ext, + ahbo_m_ext => ahbo_m_ext); + + + nSRAM_E1 <= nSRAM_CE(0); + nSRAM_E2 <= nSRAM_CE(1); + +------------------------------------------------------------------------------- +-- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_management_1 : apb_lfr_management + GENERIC MAP ( + tech => tech, + pindex => 6, + paddr => 6, + pmask => 16#fff#, + --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 + NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set + PORT MAP ( + clk25MHz => clk_25, + resetn_25MHz => rstn_25, -- TODO + --clk24_576MHz => clk_24, -- 49.152MHz/2 + --resetn_24_576MHz => rstn_24, -- TODO + + grspw_tick => swno.tickout, + apbi => apbi_ext, + apbo => apbo_ext(6), + + HK_sample => sample_s(8), + HK_val => sample_val, + HK_sel => HK_SEL, + + DAC_SDO => DAC_SDO, + DAC_SCK => DAC_SCK, + DAC_SYNC => DAC_SYNC, + DAC_CAL_EN => DAC_CAL_EN, + + coarse_time => coarse_time, + fine_time => fine_time, + LFR_soft_rstn => LFR_soft_rstn + ); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + ------------------------------------------------------------------------------ + -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ + ------------------------------------------------------------------------------ + spw1_en <= '1'; + spw2_en <= '1'; + ------------------------------------------------------------------------------ + -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ + ------------------------------------------------------------------------------ + + --spw_clk <= clk50MHz; + --spw_rxtxclk <= spw_clk; + --spw_rxclkn <= NOT spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (spw1_din, dtmp(0)); + spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (spw1_sin, stmp(0)); + spw1_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (spw1_dout, swno.d(0)); + spw1_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (spw1_sout, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (spw2_din, dtmp(1)); + spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (spw2_sin, stmp(1)); + spw2_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (spw2_dout, swno.d(1)); + spw2_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (spw2_sout, swno.s(1)); + + -- GRSPW PHY + --spw1_input: if CFG_SPW_GRSPW = 1 generate + spw_inputloop : FOR j IN 0 TO 1 GENERATE + spw_phy0 : grspw_phy + GENERIC MAP( + tech => axcel,-- inferred,--axdsp,--tech_leon, + rxclkbuftype => 1, + scantest => 0) + PORT MAP( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 DOWNTO j*5), + dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); + END GENERATE spw_inputloop; + + -- SPW core + sw0 : grspwm GENERIC MAP( + tech => axcel,--inferred,--axdsp,--tech_leon, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 1, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => axcel,--inferred,--tech_leon, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + PORT MAP(rstn_25, clk_25, spw_rxclk(0), + spw_rxclk(1), + clk50MHz_int, + clk50MHz_int, +-- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, + ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (OTHERS => '0'); + swni.dcrstval <= (OTHERS => '0'); + swni.timerrstval <= (OTHERS => '0'); + +------------------------------------------------------------------------------- +-- LFR ------------------------------------------------------------------------ +------------------------------------------------------------------------------- + --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN); + LFR_rstn_int <= LFR_soft_rstn AND rstn_25_int; + + rstn_pad_lfr : clkint port map (A => LFR_rstn_int, Y => LFR_rstn ); + + lpp_lfr_1 : lpp_lfr + GENERIC MAP ( + Mem_use => Mem_use, + tech => inferred,--tech, + nb_data_by_buffer_size => 32, + --nb_word_by_buffer_size => 30, + nb_snapshot_param_size => 32, + delta_vector_size => 32, + delta_vector_size_f0_2 => 7, -- log2(96) + pindex => 15, + paddr => 15, + pmask => 16#fff#, + pirq_ms => 6, + pirq_wfp => 14, + hindex => 2, + top_lfr_version => X"020159", -- aa.bb.cc version + -- AA : BOARD NUMBER + -- 0 => MINI_LFR + -- 1 => EM + -- 2 => EQM (with A3PE3000) + DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA, + RTL_DESIGN_LIGHT =>0, + WINDOWS_HAANNING_PARAM_SIZE => 15) + PORT MAP ( + clk => clk_25, + rstn => LFR_rstn, + sample_B => sample_s(2 DOWNTO 0), + sample_E => sample_s(7 DOWNTO 3), + sample_val => sample_val, + apbi => apbi_ext, + apbo => apbo_ext(15), + ahbi => ahbi_m_ext, + ahbo => ahbo_m_ext(2), + coarse_time => coarse_time, + fine_time => fine_time, + data_shaping_BW => bias_fail_sw, + debug_vector => debug_vector, + debug_vector_ms => OPEN); --, + --observation_vector_0 => OPEN, + --observation_vector_1 => OPEN, + --observation_reg => observation_reg); + + + all_sample : FOR I IN 7 DOWNTO 0 GENERATE + sample_s(I) <= sample(I) & '0' & '0'; + END GENERATE all_sample; + sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE + top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter + GENERIC MAP ( + ChanelCount => 9, + ncycle_cnv_high => 12, + ncycle_cnv => 25, + FILTER_ENABLED => 16#FF#) + PORT MAP ( + cnv_clk => clk_24, + cnv_rstn => rstn_24, + cnv => ADC_smpclk_s, + clk => clk_25, + rstn => rstn_25, + ADC_data => ADC_data, + ADC_nOE => ADC_OEB_bar_CH_s, + sample => sample, + sample_val => sample_val); + + END GENERATE USE_ADCDRIVER_true; + + USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE + top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter + GENERIC MAP ( + ChanelCount => 9, + ncycle_cnv_high => 25, + ncycle_cnv => 50, + FILTER_ENABLED => 16#FF#) + PORT MAP ( + cnv_clk => clk_24, + cnv_rstn => rstn_24, + cnv => ADC_smpclk_s, + clk => clk_25, + rstn => rstn_25, + ADC_data => ADC_data, + ADC_nOE => OPEN, + sample => OPEN, + sample_val => sample_val); + + ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); + + all_sample: FOR I IN 8 DOWNTO 0 GENERATE + ramp_generator_1: ramp_generator + GENERIC MAP ( + DATA_SIZE => 14, + VALUE_UNSIGNED_INIT => 2**I, + VALUE_UNSIGNED_INCR => 0, + VALUE_UNSIGNED_MASK => 16#3FFF#) + PORT MAP ( + clk => clk_25, + rstn => rstn_25, + new_data => sample_val, + output_data => sample(I) ); + END GENERATE all_sample; + + + END GENERATE USE_ADCDRIVER_false; + + + + + ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); + + ADC_smpclk <= ADC_smpclk_s; + HK_smpclk <= ADC_smpclk_s; + + + ----------------------------------------------------------------------------- + -- HK + ----------------------------------------------------------------------------- + ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE + -- lpp_bootloader_1: lpp_bootloader + -- GENERIC MAP ( + -- pindex => 13, + -- paddr => 13, + -- pmask => 16#fff#, + -- hindex => 3, + -- haddr => 0, + -- hmask => 16#fff#) + -- PORT MAP ( + -- HCLK => clk_25, + -- HRESETn => rstn_25, + -- apbi => apbi_ext, + -- apbo => apbo_ext(13), + -- ahbsi => ahbi_s_ext, + -- ahbso => ahbo_s_ext(3)); + --END GENERATE inst_bootloader; + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE + PROCESS (clk_25, rstn_25) + BEGIN -- PROCESS + IF rstn_25 = '0' THEN -- asynchronous reset (active low) + TAG <= (OTHERS => '0'); + ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge + TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); + END IF; + END PROCESS; + + + END GENERATE USE_DEBUG_VECTOR_IF; + + USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE + --ahbrxd <= TAG(1); -- AHB UART + --TAG(3) <= ahbtxd; + + urxd1 <= TAG(2); -- APB UART + TAG(4) <= utxd1; + --TAG(8) <= nSRAM_BUSY; + END GENERATE USE_DEBUG_VECTOR_IF2; + +END beh; \ No newline at end of file diff --git a/designs/LFR-RTAX_keypoint/Makefile b/designs/LFR-RTAX_keypoint/Makefile new file mode 100644 --- /dev/null +++ b/designs/LFR-RTAX_keypoint/Makefile @@ -0,0 +1,55 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) + +TOP=LFR_EQM +BOARD=LFR-EQM + +include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc + +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= + +VHDLSYNFILES=LFR-EQM.vhd +VHDLSIMFILES=testbench.vhd + +PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc +SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc + +BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = axcelerator + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./dsp/lpp_fft \ + ./lpp_uart \ + ./lpp_usb \ + ./lpp_sim/CY7C1061DV33 \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd\ + CoreFFT_simu.vhd \ + lpp_lfr_apbreg_simu.vhd \ + sgmii.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -514,7 +514,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000154") -- aa.bb.cc version + top_lfr_version => X"000159") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, @@ -653,4 +653,4 @@ BEGIN -- beh END GENERATE ahbo_m_ext_not_used; END GENERATE all_ahbo_m_ext; -END beh; \ No newline at end of file +END beh; diff --git a/designs/Validation_MS_auto/data_file/test/test_gen_data.py b/designs/Validation_MS_auto/data_file/test/test_gen_data.py --- a/designs/Validation_MS_auto/data_file/test/test_gen_data.py +++ b/designs/Validation_MS_auto/data_file/test/test_gen_data.py @@ -16,23 +16,23 @@ nb_point = 256 t = np.arange(nb_point) ## f0 -ampl_f0_0 = pow(2,14) +ampl_f0_0 = pow(2,16)-1 freq_f0_0 = float(16)/256 phi_f0_0 = 0 -ampl_f0_1 = pow(2,13) +ampl_f0_1 = pow(2,15)-1 freq_f0_1 = float(16)/256 phi_f0_1 = 0 -ampl_f0_2 = pow(2,12) +ampl_f0_2 = pow(2,14)-1 freq_f0_2 = float(16)/256 phi_f0_2 = 0 -ampl_f0_3 = pow(2,11) +ampl_f0_3 = pow(2,13)-1 freq_f0_3 = float(16)/256 phi_f0_3 = 0 -ampl_f0_4 = pow(2,10) +ampl_f0_4 = pow(2,10)-1 freq_f0_4 = float(16)/256 phi_f0_4 = 0 diff --git a/lib/lpp/dsp/lpp_fft_rtax/CoreFFT.vhd b/lib/lpp/dsp/lpp_fft_rtax/CoreFFT.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/CoreFFT.vhd @@ -0,0 +1,356 @@ +-------------------------------------------------------------------------------- +-- Copyright 2007 Actel Corporation. All rights reserved. + +-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN +-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED +-- IN ADVANCE IN WRITING. + +-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release +-- File: CoreFFT.vhd +-- Description: CoreFFT +-- Top level FFT module +-- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production +-- Notes: FFT In/out pins: +-- Input | Output | Comments +-- ------------+------------+------------------ +-- clk | ifoPong | +-- ifiNreset | |async reset active low +-- start | |sync reset active high +-- Load Input data group | +-- d_im[15:0] | load |when high the inBuf is being loaded +-- d_re[15:0] | | +-- d_valid | | +-- Upload Output data group | +-- read_y | y_im[15:0] | +-- | y_re[15:0] | +-- | y_valid |marks a new output sample) +-- | y_rdy |when high the results are being uploaded +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +USE work.fft_components.all; + +ENTITY CoreFFT IS + GENERIC ( + LOGPTS : integer := gLOGPTS; + LOGLOGPTS : integer := gLOGLOGPTS; + WSIZE : integer := gWSIZE; + TWIDTH : integer := gTWIDTH; + DWIDTH : integer := gDWIDTH; + TDWIDTH : integer := gTDWIDTH; + RND_MODE : integer := gRND_MODE; + SCALE_MODE : integer := gSCALE_MODE; + PTS : integer := gPTS; + HALFPTS : integer := gHALFPTS; + inBuf_RWDLY : integer := gInBuf_RWDLY ); + PORT ( + clk,ifiStart,ifiNreset : IN std_logic; + ifiD_valid, ifiRead_y : IN std_logic; + ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0); + ifoLoad, ifoPong : OUT std_logic; + ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0); + ifoY_valid, ifoY_rdy : OUT std_logic); +END ENTITY CoreFFT; + +ARCHITECTURE translated OF CoreFFT IS + + COMPONENT autoScale + GENERIC (SCALE_MODE : integer := 1 ); + PORT (clk, clkEn, wLastStage : IN std_logic; + ldRiskOV, bflyRiskOV : IN std_logic; + startLoad, ifo_loadOn : IN std_logic; + bflyOutValid, startFFT : IN std_logic; + wEn_even, wEn_odd : IN std_logic; + upScale : OUT std_logic); + END COMPONENT; + + COMPONENT bfly2 + GENERIC ( RND_MODE : integer := 0; + WSIZE : integer := 16; + DWIDTH : integer := 32; + TWIDTH : integer := 16; + TDWIDTH : integer := 32 ); + PORT (clk, validIn : IN std_logic; + swCrossIn : IN std_logic; + upScale : IN std_logic; + inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + T : IN std_logic_vector(TDWIDTH-1 DOWNTO 0); + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0); + validOut, swCrossOut : OUT std_logic); + END COMPONENT; + + COMPONENT sm_top + GENERIC ( PTS : integer := 256; + HALFPTS : integer := 128; + LOGPTS : integer := 8; + LOGLOGPTS : integer := 3; + inBuf_RWDLY : integer := 12 ); + PORT (clk,clkEn : IN std_logic; + ifiStart, ifiNreset : IN std_logic; + ifiD_valid, ifiRead_y : IN std_logic; + ldA, rA, wA, tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0); + twid_wA, outBuf_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0); + outBuf_rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0); + wEn_even, wEn_odd : OUT std_logic; + preSwCross, twid_wEn : OUT std_logic; + inBuf_wEn, outBuf_wEn : OUT std_logic; + smPong, ldValid : OUT std_logic; + inBuf_rdValid : OUT std_logic; + wLastStage : OUT std_logic; + smStartFFTrd : OUT std_logic; + smStartLoad, ifoLoad : OUT std_logic; + ifoY_valid, ifoY_rdy : OUT std_logic); + END COMPONENT; + + COMPONENT twiddle + PORT (A : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + T : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT pipoBuffer + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT ( + clk, clkEn, pong, rEn : IN std_logic; + rA, wA_load, wA_bfly : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + wEn_bfly,wEn_even,wEn_odd : IN std_logic; + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) ); + END COMPONENT; + + COMPONENT switch + GENERIC ( DWIDTH : integer := 16 ); + PORT (clk, sel, validIn : IN std_logic; + inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0); + validOut : OUT std_logic); + END COMPONENT; + + COMPONENT twidLUT + GENERIC ( LOGPTS : integer := 8; + TDWIDTH : integer := 32 ); + PORT (clk, wEn : IN std_logic; + wA, rA : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + D : IN std_logic_vector(TDWIDTH-1 DOWNTO 0); + Q : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT outBuff + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT (clk, clkEn, wEn : IN std_logic; + inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + rA : IN std_logic_vector(LOGPTS-1 DOWNTO 0); + outD : OUT std_logic_vector(DWIDTH-1 DOWNTO 0)); + END COMPONENT; + + SIGNAL ldA_w, rA_w : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL wA_w, tA_w : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL twid_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL outBuf_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL outBuf_rA_w : std_logic_vector(LOGPTS-1 DOWNTO 0); + SIGNAL wEn_even_w : std_logic; + SIGNAL wEn_odd_w : std_logic; + SIGNAL inBuf_wEn_w : std_logic; + SIGNAL preSwCross_w : std_logic; + SIGNAL postSwCross_w : std_logic; + SIGNAL twid_wEn_w : std_logic; + SIGNAL outBuf_wEn_w : std_logic; + SIGNAL ldRiskOV_w : std_logic; + SIGNAL bflyRiskOV_w : std_logic; + SIGNAL readP_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL readQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL bflyInP_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL bflyInQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL bflyOutP_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL bflyOutQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL T_w : std_logic_vector(TDWIDTH-1 DOWNTO 0); + SIGNAL twidData_w : std_logic_vector(TDWIDTH-1 DOWNTO 0); + SIGNAL outEven_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL outOdd_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL inBufValid_w : std_logic; + SIGNAL preSwValid_w : std_logic; + SIGNAL bflyValid_w : std_logic; + SIGNAL wLastStage_w : std_logic; + SIGNAL startFFTrd_w : std_logic; + SIGNAL startLoad_w : std_logic; + SIGNAL upScale_w : std_logic; + SIGNAL port_xhdl15 : std_logic; + SIGNAL xhdl_17 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL xhdl_23 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL clkEn_const : std_logic; + SIGNAL ifoLoad_xhdl1 : std_logic; + SIGNAL ifoY_im_xhdl2 : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL ifoY_re_xhdl3 : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL ifoPong_xhdl4 : std_logic; + SIGNAL ifoY_valid_xhdl5 : std_logic; + SIGNAL ifoY_rdy_xhdl6 : std_logic; + SIGNAL displayBflyOutP : std_logic; + SIGNAL displayBflyOutQ : std_logic; + SIGNAL displayInBuf_wEn : std_logic; + SIGNAL ldValid_w : std_logic; + +BEGIN + ifoLoad <= ifoLoad_xhdl1; + ifoY_im <= ifoY_im_xhdl2; + ifoY_re <= ifoY_re_xhdl3; + ifoPong <= ifoPong_xhdl4; + ifoY_valid <= ifoY_valid_xhdl5; + ifoY_rdy <= ifoY_rdy_xhdl6; + -- debug only + displayBflyOutP <= bflyOutP_w(0) ; + displayBflyOutQ <= bflyOutQ_w(0) ; + displayInBuf_wEn <= inBuf_wEn_w ; + port_xhdl15 <= '1'; + + smTop_0 : sm_top + GENERIC MAP ( PTS => PTS, HALFPTS => HALFPTS, + LOGPTS => LOGPTS, LOGLOGPTS => LOGLOGPTS, inBuf_RWDLY => inBuf_RWDLY ) + PORT MAP ( + clk => clk, + clkEn => port_xhdl15, + ifiStart => ifiStart, + ifiNreset => ifiNreset, + ifiD_valid => ifiD_valid, + ifiRead_y => ifiRead_y, + ldA => ldA_w, + rA => rA_w, + wA => wA_w, + tA => tA_w, + twid_wA => twid_wA_w, + outBuf_wA => outBuf_wA_w, + outBuf_rA => outBuf_rA_w, + wEn_even => wEn_even_w, + wEn_odd => wEn_odd_w, + preSwCross => preSwCross_w, + twid_wEn => twid_wEn_w, + inBuf_wEn => inBuf_wEn_w, + outBuf_wEn => outBuf_wEn_w, + smPong => ifoPong_xhdl4, + ldValid => ldValid_w, + inBuf_rdValid => inBufValid_w, + wLastStage => wLastStage_w, + smStartFFTrd => startFFTrd_w, + smStartLoad => startLoad_w, + ifoLoad => ifoLoad_xhdl1, + ifoY_valid => ifoY_valid_xhdl5, + ifoY_rdy => ifoY_rdy_xhdl6); + + xhdl_17 <= ifiD_im & ifiD_re; + + inBuf_0 : pipoBuffer + GENERIC MAP ( LOGPTS => LOGPTS, + DWIDTH => DWIDTH ) + PORT MAP ( + clk => clk, + clkEn => '1', + rEn => '1', + rA => rA_w, + wA_load => ldA_w, + wA_bfly => wA_w, + ldData => xhdl_17, + wP_bfly => outEven_w, + wQ_bfly => outOdd_w, + wEn_bfly => inBuf_wEn_w, + wEn_even => wEn_even_w, + wEn_odd => wEn_odd_w, + pong => ifoPong_xhdl4, + outP => readP_w, + outQ => readQ_w); + + preBflySw_0 : switch + GENERIC MAP ( DWIDTH => DWIDTH ) + PORT MAP ( + clk => clk, + inP => readP_w, + inQ => readQ_w, + sel => preSwCross_w, + outP => bflyInP_w, + outQ => bflyInQ_w, + validIn => inBufValid_w, + validOut => preSwValid_w); + + bfly_0 : bfly2 + GENERIC MAP (RND_MODE => RND_MODE, WSIZE => WSIZE, DWIDTH => DWIDTH, + TWIDTH => TWIDTH, TDWIDTH => TDWIDTH ) + PORT MAP ( + clk => clk, + upScale => upScale_w, + inP => bflyInP_w, + inQ => bflyInQ_w, + T => T_w, + outP => bflyOutP_w, + outQ => bflyOutQ_w, + validIn => preSwValid_w, + validOut => bflyValid_w, + swCrossIn => preSwCross_w, + swCrossOut => postSwCross_w); + + lut_0 : twiddle + PORT MAP (A => twid_wA_w, T => twidData_w); + + twidLUT_1 : twidLUT + GENERIC MAP ( LOGPTS => LOGPTS, TDWIDTH => TDWIDTH ) + PORT MAP ( + clk => clk, + wA => twid_wA_w, + wEn => twid_wEn_w, + rA => tA_w, + D => twidData_w, + Q => T_w); + + postBflySw_0 : switch + GENERIC MAP ( DWIDTH => DWIDTH ) + PORT MAP ( + clk => clk, + inP => bflyOutP_w, + inQ => bflyOutQ_w, + sel => postSwCross_w, + outP => outEven_w, + outQ => outOdd_w, + validIn => bflyValid_w, + validOut => open); + + ifoY_im_xhdl2 <= xhdl_23(DWIDTH-1 DOWNTO WSIZE); + ifoY_re_xhdl3 <= xhdl_23(WSIZE-1 DOWNTO 0); + outBuff_0 : outBuff + GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH ) + PORT MAP ( + clk => clk, clkEn => '1', + rA => outBuf_rA_w, + wA => outBuf_wA_w, + inP => outEven_w, + inQ => outOdd_w, + wEn => outBuf_wEn_w, + outD => xhdl_23); + + -- Autoscaling + -- monitor if input data .im and .re have MSB == sign + ldRiskOV_w <= to_logic( + NOT ((ifiD_im(WSIZE-1) = ifiD_im(WSIZE-2)) + AND (ifiD_re(WSIZE-1) = ifiD_re(WSIZE-2))) ); + + bflyRiskOV_w <= to_logic( + NOT ((((bflyOutP_w(DWIDTH-1) = bflyOutP_w(DWIDTH- 2)) + AND (bflyOutP_w(WSIZE-1) = bflyOutP_w(WSIZE-2))) + AND (bflyOutQ_w(DWIDTH-1) = bflyOutQ_w(DWIDTH-2))) + AND (bflyOutQ_w(WSIZE-1) = bflyOutQ_w(WSIZE-2))) ); + clkEn_const <= '1'; + autoScale_0 : autoScale + GENERIC MAP (SCALE_MODE => SCALE_MODE) + PORT MAP ( + clk => clk, + clkEn => clkEn_const, + ldRiskOV => ldRiskOV_w, + bflyRiskOV => bflyRiskOV_w, + startLoad => startLoad_w, + startFFT => startFFTrd_w, + bflyOutValid => bflyValid_w, + wLastStage => wLastStage_w, + wEn_even => wEn_even_w, + wEn_odd => wEn_odd_w, + ifo_loadOn => ifoLoad_xhdl1, + upScale => upScale_w); + +END ARCHITECTURE translated; \ No newline at end of file diff --git a/lib/lpp/dsp/lpp_fft_rtax/CoreFFT_simu.vhd b/lib/lpp/dsp/lpp_fft_rtax/CoreFFT_simu.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/CoreFFT_simu.vhd @@ -0,0 +1,288 @@ +-------------------------------------------------------------------------------- +-- Copyright 2007 Actel Corporation. All rights reserved. + +-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN +-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED +-- IN ADVANCE IN WRITING. + +-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release +-- File: CoreFFT.vhd +-- Description: CoreFFT +-- Top level FFT module +-- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production +-- Notes: FFT In/out pins: +-- Input | Output | Comments +-- ------------+------------+------------------ +-- clk | ifoPong | +-- ifiNreset | |async reset active low +-- start | |sync reset active high +-- Load Input data group | +-- d_im[15:0] | load |when high the inBuf is being loaded +-- d_re[15:0] | | +-- d_valid | | +-- Upload Output data group | +-- read_y | y_im[15:0] | +-- | y_re[15:0] | +-- | y_valid |marks a new output sample) +-- | y_rdy |when high the results are being uploaded +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.numeric_std.ALL; +USE work.fft_components.ALL; + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; + +ENTITY CoreFFT IS + GENERIC ( + LOGPTS : INTEGER := gLOGPTS; + LOGLOGPTS : INTEGER := gLOGLOGPTS; + WSIZE : INTEGER := gWSIZE; + TWIDTH : INTEGER := gTWIDTH; + DWIDTH : INTEGER := gDWIDTH; + TDWIDTH : INTEGER := gTDWIDTH; + RND_MODE : INTEGER := gRND_MODE; + SCALE_MODE : INTEGER := gSCALE_MODE; + PTS : INTEGER := gPTS; + HALFPTS : INTEGER := gHALFPTS; + inBuf_RWDLY : INTEGER := gInBuf_RWDLY); + PORT ( + clk : IN STD_LOGIC; + ifiStart : IN STD_LOGIC; -- start -- cste + ifiNreset : IN STD_LOGIC; + ifiD_valid : IN STD_LOGIC; -- d_valid + ifiRead_y : IN STD_LOGIC; -- read_y + ifiD_im, ifiD_re : IN STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0); + ifoLoad : OUT STD_LOGIC; -- load + ifoPong : OUT STD_LOGIC; -- pong -- UNUSED + ifoY_im, ifoY_re : OUT STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0); + ifoY_valid : OUT STD_LOGIC; -- y_valid + ifoY_rdy : OUT STD_LOGIC); -- y_rdy +END ENTITY CoreFFT; + +ARCHITECTURE translated OF CoreFFT IS + SIGNAL fft_ongoing : STD_LOGIC; + SIGNAL fft_done : STD_LOGIC; + SIGNAL counter : INTEGER; + SIGNAL counter_out : INTEGER; + SIGNAL counter_wait : INTEGER; + SIGNAL fft_ongoing_ok : STD_LOGIC; + SIGNAL fft_ongoing_ok_1 : STD_LOGIC; + SIGNAL fft_ongoing_ok_2 : STD_LOGIC; + SIGNAL fft_ongoing_ok_3 : STD_LOGIC; + SIGNAL fft_ongoing_ok_4 : STD_LOGIC; + -- + SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL ren : STD_LOGIC; + SIGNAL wen : STD_LOGIC; + -- + SIGNAL ifoLoad_s : STD_LOGIC; -- load + SIGNAL ifoY_rdy_s : STD_LOGIC; -- y_rdy + SIGNAL ifoY_rdy_s2 : STD_LOGIC; -- y_rdy + SIGNAL ifoY_rdy_s3 : STD_LOGIC; -- y_rdy + SIGNAL ifoY_valid_s : STD_LOGIC; -- y_valid + SIGNAL ifoPong_s : STD_LOGIC; -- pong -- UNUSED + SIGNAL ifoPong_first : STD_LOGIC; -- pong -- UNUSED + + ----------------------------------------------------------------------------- + SIGNAL ifoY_im_counter : INTEGER; +BEGIN + + ----------------------------------------------------------------------------- + -- INPUT INTERFACE + ----------------------------------------------------------------------------- + -- in ifiD_valid + -- in (internal) fft_done + + -- out(internal) fft_ongoing + -- out ifoLoad_s + PROCESS (clk, ifiNreset) + BEGIN + IF ifiNreset = '0' THEN + counter <= 0; + fft_ongoing <= '0'; + ifoLoad_s <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + IF fft_ongoing = '0' THEN + ifoLoad_s <= '1'; + fft_ongoing <= '0'; + IF ifiD_valid = '1' THEN + ifoLoad_s <= '1'; + IF counter = 255 THEN + ifoLoad_s <= '0'; + fft_ongoing <= '1'; + counter <= 0; + ELSE + counter <= counter + 1; + END IF; + END IF; + ELSIF fft_ongoing_ok = '1' THEN--fft_done + fft_ongoing <= '0'; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- WAIT PROCESS + ----------------------------------------------------------------------------- + PROCESS (clk, ifiNreset) + BEGIN + IF ifiNreset = '0' THEN +-- fft_done <= '0'; + + counter_wait <= 0; + fft_ongoing_ok <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + fft_done <= '0'; + fft_ongoing_ok <= '0'; + IF fft_ongoing = '0' THEN +-- fft_done <= '1'; + counter_wait <= 1140;--1000;--1140;--855;--936; + ELSE + IF counter_wait > 0 THEN + counter_wait <= counter_wait -1; + IF counter_wait = 1 THEN + fft_ongoing_ok <= '1'; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- OUTPUT INTERFACE + ----------------------------------------------------------------------------- + PROCESS (clk, ifiNreset) + BEGIN -- PROCESS + IF ifiNreset = '0' THEN -- asynchronous reset (active low) + fft_ongoing_ok_1 <= '0'; + fft_ongoing_ok_2 <= '0'; + fft_ongoing_ok_3 <= '0'; + fft_ongoing_ok_4 <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + fft_ongoing_ok_1 <= fft_ongoing_ok; + fft_ongoing_ok_2 <= fft_ongoing_ok_1; + fft_ongoing_ok_3 <= fft_ongoing_ok_2; + fft_ongoing_ok_4 <= fft_ongoing_ok_3; + + END IF; + END PROCESS; + + + -- in ifiRead_y + -- in(internal) fft_ongoing_ok + + -- out (internal) fft_done + -- out ifoY_im + -- out ifoY_re + -- out ifoY_valid_s + -- out ifoY_rdy_s + PROCESS (clk, ifiNreset) + BEGIN + IF ifiNreset = '0' THEN + -- fft_done <= '0'; + --ifoY_im <= (OTHERS => '0'); + --ifoY_re <= (OTHERS => '0'); + ifoY_valid_s <= '0'; + ifoY_rdy_s <= '0'; + counter_out <= 0; + ELSIF clk'EVENT AND clk = '1' THEN +-- fft_done <= '0'; + + IF fft_ongoing_ok_4 = '1' THEN + counter_out <= 256; + END IF; + + ifoY_valid_s <= '0'; + ifoY_rdy_s <= '0'; + IF counter_out > 0 THEN + ifoY_valid_s <= '1'; + ifoY_rdy_s <= '1'; + IF ifiRead_y = '1' THEN + counter_out <= counter_out - 1; + --IF counter_out = 1 THEN + -- fft_done <= '1'; + --END IF; + END IF; + END IF; + + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- DATA + ----------------------------------------------------------------------------- + lpp_fifo_1: lpp_fifo + GENERIC MAP ( + tech => 0, + Mem_use => use_CEL, + DataSz => 32, + AddrSz => 7) + PORT MAP ( + clk => clk, + rstn => ifiNreset, + + ReUse => '0', + + wen => wen, + wdata => wdata, + + ren => ren, + rdata => rdata, + + empty => OPEN, + full => OPEN, + almost_full => OPEN); + + wen <= '0' WHEN ifoLoad_s = '1' AND ifiD_valid = '1' ELSE '1'; + wdata <= ifiD_im & ifiD_re; + + + ren <= '0' WHEN ifoY_rdy_s = '1' AND ifiRead_y = '1' ELSE '1'; + ifoY_im <= STD_LOGIC_VECTOR(to_unsigned(ifoY_im_counter,16));--rdata(31 DOWNTO 16); + ifoY_re <= rdata(15 DOWNTO 0); + + PROCESS (clk, ifiNreset) + BEGIN + IF ifiNreset = '0' THEN + ifoY_im_counter <= 0; + ELSIF clk'event AND clk = '1' THEN + IF ifoY_rdy_s = '1' AND ifiRead_y = '1' THEN + ifoY_im_counter <= ifoY_im_counter + 1; + END IF; + END IF; + END PROCESS; + + + + ifoLoad <= ifoLoad_s; + ifoY_rdy <= ifoY_rdy_s OR ifoY_rdy_s2 OR ifoY_rdy_s3; + + + PROCESS (clk, ifiNreset) + BEGIN + IF ifiNreset = '0' THEN + ifoY_valid <= '0'; + ifoY_rdy_s2 <= '0'; + ifoY_rdy_s3 <= '0'; + ifoPong_s <= '0'; + ifoPong_first <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + ifoY_valid <= ifoY_valid_s; + ifoY_rdy_s2 <= ifoY_rdy_s; + ifoY_rdy_s3 <= ifoY_rdy_s2; + IF fft_ongoing_ok = '1' THEN + IF ifoPong_first = '1' THEN + ifoPong_s <= NOT ifoPong_s; + END IF; + ifoPong_first <= '1'; + END IF; + END IF; + END PROCESS; + + ifoPong <= ifoPong_s; + +END ARCHITECTURE translated; diff --git a/lib/lpp/dsp/lpp_fft_rtax/CoreFFT_simu_light.vhd b/lib/lpp/dsp/lpp_fft_rtax/CoreFFT_simu_light.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/CoreFFT_simu_light.vhd @@ -0,0 +1,386 @@ +-------------------------------------------------------------------------------- +-- Copyright 2007 Actel Corporation. All rights reserved. + +-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN +-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED +-- IN ADVANCE IN WRITING. + +-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release +-- File: CoreFFT.vhd +-- Description: CoreFFT +-- Top level FFT module +-- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production +-- Notes: FFT In/out pins: +-- Input | Output | Comments +-- ------------+------------+------------------ +-- clk | ifoPong | +-- ifiNreset | |async reset active low +-- start | |sync reset active high +-- Load Input data group | +-- d_im[15:0] | load |when high the inBuf is being loaded +-- d_re[15:0] | | +-- d_valid | | +-- Upload Output data group | +-- read_y | y_im[15:0] | +-- | y_re[15:0] | +-- | y_valid |marks a new output sample) +-- | y_rdy |when high the results are being uploaded +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.numeric_std.ALL; +USE work.fft_components.ALL; + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; + +ENTITY CoreFFT IS + GENERIC ( + LOGPTS : INTEGER := gLOGPTS; + LOGLOGPTS : INTEGER := gLOGLOGPTS; + WSIZE : INTEGER := gWSIZE; + TWIDTH : INTEGER := gTWIDTH; + DWIDTH : INTEGER := gDWIDTH; + TDWIDTH : INTEGER := gTDWIDTH; + RND_MODE : INTEGER := gRND_MODE; + SCALE_MODE : INTEGER := gSCALE_MODE; + PTS : INTEGER := gPTS; + HALFPTS : INTEGER := gHALFPTS; + inBuf_RWDLY : INTEGER := gInBuf_RWDLY); + PORT ( + clk : IN STD_LOGIC; + ifiStart : IN STD_LOGIC; -- start -- cste + ifiNreset : IN STD_LOGIC; + ifiD_valid : IN STD_LOGIC; -- d_valid + ifiRead_y : IN STD_LOGIC; -- read_y + ifiD_im, ifiD_re : IN STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0); + ifoLoad : OUT STD_LOGIC; -- load + ifoPong : OUT STD_LOGIC; -- pong -- UNUSED + ifoY_im, ifoY_re : OUT STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0); + ifoY_valid : OUT STD_LOGIC; -- y_valid + ifoY_rdy : OUT STD_LOGIC); -- y_rdy +END ENTITY CoreFFT; + +ARCHITECTURE translated OF CoreFFT IS + + + SIGNAL fft_ongoing : STD_LOGIC; + SIGNAL fft_done : STD_LOGIC; + SIGNAL counter : INTEGER; + SIGNAL counter_out : INTEGER; + SIGNAL counter_wait : INTEGER; + SIGNAL fft_ongoing_ok : STD_LOGIC; + SIGNAL fft_ongoing_ok_1 : STD_LOGIC; + SIGNAL fft_ongoing_ok_2 : STD_LOGIC; + SIGNAL fft_ongoing_ok_3 : STD_LOGIC; + SIGNAL fft_ongoing_ok_4 : STD_LOGIC; + -- + SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL ren : STD_LOGIC; + SIGNAL wen : STD_LOGIC; + -- + SIGNAL ifoLoad_s : STD_LOGIC; -- load + SIGNAL ifoY_rdy_s : STD_LOGIC; -- y_rdy + SIGNAL ifoY_rdy_s2 : STD_LOGIC; -- y_rdy + SIGNAL ifoY_rdy_s3 : STD_LOGIC; -- y_rdy + SIGNAL ifoY_valid_s : STD_LOGIC; -- y_valid + SIGNAL ifoPong_s : STD_LOGIC; -- pong -- UNUSED + SIGNAL ifoPong_first : STD_LOGIC; -- pong -- UNUSED + + ----------------------------------------------------------------------------- + SIGNAL ifoY_im_counter : INTEGER; + + + + SIGNAL counter_in : INTEGER; + SIGNAL fft_start : STD_LOGIC; + SIGNAL fft_done : STD_LOGIC; + + SIGNAL ifoLoad_s : STD_LOGIC; + SIGNAL ifoLoad_s2 : STD_LOGIC; +BEGIN + + --clk : IN STD_LOGIC; + --ifiNreset : IN STD_LOGIC; + ----------------------------------------------------------------------------- + --INPUT INTERFACE + --ifoLoad : OUT STD_LOGIC; -- load + --ifiD_valid : IN STD_LOGIC; -- d_valid + --ifiD_im, ifiD_re : IN STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0); + + ifoLoad <= ifoLoad_s; + + PROCESS (clk, ifiNreset) + BEGIN -- PROCESS + IF ifiNreset = '0' THEN -- asynchronous reset (active low) + counter_in <= 0; + fft_start <= '0'; + ifoLoad_s <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF counter_in < 256 AND ifoLoad_s = '1'THEN + IF ifiD_valid = '1' THEN + counter_in <= counter_in + 1; + IF counter_in = 255 THEN + ifoLoad_s <= '0'; + fft_start <= '1'; + END IF; + END IF; + ELSE + ifoLoad_s <= fft_done AND (NOT fft_start); + counter_in <= 0; + fft_start <= '0'; + END IF; + END IF; + END PROCESS; + + PROCESS (clk, ifiNreset) + BEGIN -- PROCESS + IF ifiNreset = '0' THEN -- asynchronous reset (active low) + fft_done <= '1'; + counter_wait <= 0; + output_start <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + output_start <= '0'; + IF counter_wait > 0 THEN + IF output_done = '1' THEN + counter_wait <= counter_wait - 1; + IF counter_wait = 1 THEN + output_start <= '1'; + END IF; + END IF; + ELSE + fft_done <= '1'; + IF fft_start = '1' THEN + counter_wait <= 855; + fft_done <= '0'; + END IF; + counter_wait <= 0; + END IF; + END IF; + END PROCESS; + + PROCESS (clk, ifiNreset) + BEGIN -- PROCESS + IF ifiNreset = '0' THEN -- asynchronous reset (active low) + output_done <= '1'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF output_start = '1' THEN + output_done <= '0'; + counter_output <= 0; + ELSE + + END IF; + + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + ifiStart : IN STD_LOGIC; -- start -- cste + + ifiRead_y : IN STD_LOGIC; -- read_y + + + ifoPong : OUT STD_LOGIC; -- pong -- UNUSED + ifoY_im, ifoY_re : OUT STD_LOGIC_VECTOR(WSIZE-1 DOWNTO 0); + ifoY_valid : OUT STD_LOGIC; -- y_valid + ifoY_rdy : OUT STD_LOGIC); -- y_rdy + + + + ----------------------------------------------------------------------------- + -- INPUT INTERFACE + ----------------------------------------------------------------------------- + -- in ifiD_valid + -- in (internal) fft_done + + -- out(internal) fft_ongoing + -- out ifoLoad_s + PROCESS (clk, ifiNreset) + BEGIN + IF ifiNreset = '0' THEN + counter <= 0; + fft_ongoing <= '0'; + ifoLoad_s <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + IF fft_ongoing = '0' THEN + ifoLoad_s <= '1'; + fft_ongoing <= '0'; + IF ifiD_valid = '1' THEN + ifoLoad_s <= '1'; + IF counter = 255 THEN + ifoLoad_s <= '0'; + fft_ongoing <= '1'; + counter <= 0; + ELSE + counter <= counter + 1; + END IF; + END IF; + ELSIF fft_ongoing_ok = '1' THEN--fft_done + fft_ongoing <= '0'; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- WAIT PROCESS + ----------------------------------------------------------------------------- + PROCESS (clk, ifiNreset) + BEGIN + IF ifiNreset = '0' THEN +-- fft_done <= '0'; + + counter_wait <= 0; + fft_ongoing_ok <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + fft_done <= '0'; + fft_ongoing_ok <= '0'; + IF fft_ongoing = '0' THEN +-- fft_done <= '1'; + counter_wait <= 855;--936;--1000;--1140;--936; + ELSE + IF counter_wait > 0 THEN + counter_wait <= counter_wait -1; + IF counter_wait = 1 THEN + fft_ongoing_ok <= '1'; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- OUTPUT INTERFACE + ----------------------------------------------------------------------------- + PROCESS (clk, ifiNreset) + BEGIN -- PROCESS + IF ifiNreset = '0' THEN -- asynchronous reset (active low) + fft_ongoing_ok_1 <= '0'; + fft_ongoing_ok_2 <= '0'; + fft_ongoing_ok_3 <= '0'; + fft_ongoing_ok_4 <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + fft_ongoing_ok_1 <= fft_ongoing_ok; + fft_ongoing_ok_2 <= fft_ongoing_ok_1; + fft_ongoing_ok_3 <= fft_ongoing_ok_2; + fft_ongoing_ok_4 <= fft_ongoing_ok_3; + + END IF; + END PROCESS; + + + -- in ifiRead_y + -- in(internal) fft_ongoing_ok + + -- out (internal) fft_done + -- out ifoY_im + -- out ifoY_re + -- out ifoY_valid_s + -- out ifoY_rdy_s + PROCESS (clk, ifiNreset) + BEGIN + IF ifiNreset = '0' THEN + -- fft_done <= '0'; + --ifoY_im <= (OTHERS => '0'); + --ifoY_re <= (OTHERS => '0'); + ifoY_valid_s <= '0'; + ifoY_rdy_s <= '0'; + counter_out <= 0; + ELSIF clk'EVENT AND clk = '1' THEN +-- fft_done <= '0'; + + IF fft_ongoing_ok_4 = '1' THEN + counter_out <= 256; + END IF; + + ifoY_valid_s <= '0'; + ifoY_rdy_s <= '0'; + IF counter_out > 0 THEN + ifoY_valid_s <= '1'; + ifoY_rdy_s <= '1'; + IF ifiRead_y = '1' THEN + counter_out <= counter_out - 1; + --IF counter_out = 1 THEN + -- fft_done <= '1'; + --END IF; + END IF; + END IF; + + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- DATA + ----------------------------------------------------------------------------- + lpp_fifo_1: lpp_fifo + GENERIC MAP ( + tech => 0, + Mem_use => use_CEL, + DataSz => 32, + AddrSz => 7) + PORT MAP ( + clk => clk, + rstn => ifiNreset, + + ReUse => '0', + + wen => wen, + wdata => wdata, + + ren => ren, + rdata => rdata, + + empty => OPEN, + full => OPEN, + almost_full => OPEN); + + wen <= '0' WHEN ifoLoad_s = '1' AND ifiD_valid = '1' ELSE '1'; + wdata <= ifiD_im & ifiD_re; + + + ren <= '0' WHEN ifoY_rdy_s = '1' AND ifiRead_y = '1' ELSE '1'; + ifoY_im <= STD_LOGIC_VECTOR(to_unsigned(ifoY_im_counter,16));--rdata(31 DOWNTO 16); + ifoY_re <= rdata(15 DOWNTO 0); + + PROCESS (clk, ifiNreset) + BEGIN + IF ifiNreset = '0' THEN + ifoY_im_counter <= 0; + ELSIF clk'event AND clk = '1' THEN + IF ifoY_rdy_s = '1' AND ifiRead_y = '1' THEN + ifoY_im_counter <= ifoY_im_counter + 1; + END IF; + END IF; + END PROCESS; + + + + ifoLoad <= ifoLoad_s; + ifoY_rdy <= ifoY_rdy_s OR ifoY_rdy_s2 OR ifoY_rdy_s3; + + + PROCESS (clk, ifiNreset) + BEGIN + IF ifiNreset = '0' THEN + ifoY_valid <= '0'; + ifoY_rdy_s2 <= '0'; + ifoY_rdy_s3 <= '0'; + ifoPong_s <= '0'; + ifoPong_first <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + ifoY_valid <= ifoY_valid_s; + ifoY_rdy_s2 <= ifoY_rdy_s; + ifoY_rdy_s3 <= ifoY_rdy_s2; + IF fft_ongoing_ok = '1' THEN + IF ifoPong_first = '1' THEN + ifoPong_s <= NOT ifoPong_s; + END IF; + ifoPong_first <= '1'; + END IF; + END IF; + END PROCESS; + + ifoPong <= ifoPong_s; + +END ARCHITECTURE translated; diff --git a/lib/lpp/dsp/lpp_fft_rtax/Driver_FFT.vhd b/lib/lpp/dsp/lpp_fft_rtax/Driver_FFT.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/Driver_FFT.vhd @@ -0,0 +1,122 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY Driver_FFT IS + GENERIC( + Data_sz : INTEGER RANGE 1 TO 32 := 16; + NbData : INTEGER RANGE 1 TO 512 := 256 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + Load : IN STD_LOGIC; -- (CoreFFT) FFT_Load + -- Load + Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- FifoIN_Empty + DATA : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); -- FifoIN_Data + Valid : OUT STD_LOGIC; --(CoreFFT) Drive_write + Read : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- Read + Data_re : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --(CoreFFT) Drive_DataRE + Data_im : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0) --(CoreFFT) Drive_DataIM + ); +END ENTITY; + + +ARCHITECTURE ar_Driver OF Driver_FFT IS + + TYPE etat IS (eX, e0, e1, e2); + SIGNAL ect : etat; + + SIGNAL DataCount : INTEGER RANGE 0 TO 255 := 0; + SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0; + + SIGNAL sLoad : STD_LOGIC; + +BEGIN + + PROCESS(clk, rstn) + BEGIN + IF(rstn = '0')then + ect <= e0; + Read <= (OTHERS => '1'); + Valid <= '0'; + Data_re <= (OTHERS => '0'); + Data_im <= (OTHERS => '0'); + DataCount <= 0; + FifoCpt <= 0; + sLoad <= '0'; + + ELSIF(clk'EVENT AND clk = '1')then + sLoad <= Load; + + IF(sLoad = '1' and Load = '0')THEN + IF(FifoCpt = 4)THEN + FifoCpt <= 0; + ELSE + FifoCpt <= FifoCpt + 1; + END IF; + END IF; + + CASE ect IS + + WHEN e0 => + IF(Load = '1' and Empty(FifoCpt) = '0')THEN + Read(FifoCpt) <= '0'; + ect <= e1; + END IF; + + WHEN e1 => + Valid <= '0'; + Read(FifoCpt) <= '1'; + ect <= e2; + + WHEN e2 => + Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)); + Data_im <= (OTHERS => '0'); + Valid <= '1'; + IF(DataCount = NbData-1)THEN + DataCount <= 0; + ect <= eX; + ELSE + DataCount <= DataCount + 1; + IF(Load = '1' and Empty(FifoCpt) = '0')THEN + Read(FifoCpt) <= '0'; + ect <= e1; + ELSE + ect <= eX; + END IF; + END IF; + + WHEN eX => + Valid <= '0'; + ect <= e0; + + WHEN OTHERS => + NULL; + + END CASE; + END IF; + END PROCESS; + +END ARCHITECTURE; diff --git a/lib/lpp/dsp/lpp_fft_rtax/FFT.vhd b/lib/lpp/dsp/lpp_fft_rtax/FFT.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/FFT.vhd @@ -0,0 +1,105 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_fft.all; +use lpp.fft_components.all; + +-- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "créneau" + +entity FFT is + generic( + Data_sz : integer := 16; + NbData : integer := 256); + port( + clkm : in std_logic; + rstn : in std_logic; + FifoIN_Empty : in std_logic_vector(4 downto 0); + FifoIN_Data : in std_logic_vector(79 downto 0); + FifoOUT_Full : in std_logic_vector(4 downto 0); + Load : out std_logic; + Read : out std_logic_vector(4 downto 0); + Write : out std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + Data : out std_logic_vector(79 downto 0) + ); +end entity; + + +architecture ar_FFT of FFT is + +signal Drive_Write : std_logic; +signal Drive_DataRE : std_logic_vector(15 downto 0); +signal Drive_DataIM : std_logic_vector(15 downto 0); + +signal Start : std_logic; +signal FFT_Load : std_logic; +signal FFT_Ready : std_logic; +signal FFT_Valid : std_logic; +signal FFT_DataRE : std_logic_vector(15 downto 0); +signal FFT_DataIM : std_logic_vector(15 downto 0); + +signal Link_Read : std_logic; + +begin + +Start <= '0'; +Load <= FFT_Load; + + DRIVE : Driver_FFT + generic map(Data_sz,NbData) + port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM); + + FFT0 : CoreFFT + generic map( + LOGPTS => gLOGPTS, + LOGLOGPTS => gLOGLOGPTS, + WSIZE => gWSIZE, + TWIDTH => gTWIDTH, + DWIDTH => gDWIDTH, + TDWIDTH => gTDWIDTH, + RND_MODE => gRND_MODE, + SCALE_MODE => gSCALE_MODE, + PTS => gPTS, + HALFPTS => gHALFPTS, + inBuf_RWDLY => gInBuf_RWDLY) + port map(clkm,start,rstn, + Drive_Write, -- ifiD_valid + Link_Read, -- ifiRead_y + Drive_DataIM, -- ifiD_im + Drive_DataRE, -- ifiD_re + FFT_Load, -- ifoLoad + open, -- ifoPong + FFT_DataIM, -- ifoY_im + FFT_DataRE, -- ifoY_re + FFT_Valid, -- ifiY_valid + FFT_Ready); -- ifiY_rdy + + + LINK : Linker_FFT + generic map(Data_sz,NbData) + port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); + + +end architecture; diff --git a/lib/lpp/dsp/lpp_fft_rtax/Linker_FFT.vhd b/lib/lpp/dsp/lpp_fft_rtax/Linker_FFT.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/Linker_FFT.vhd @@ -0,0 +1,113 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY Linker_FFT IS + GENERIC( + Data_sz : INTEGER RANGE 1 TO 32 := 16; + NbData : INTEGER RANGE 1 TO 512 := 256 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + Ready : IN STD_LOGIC; -- + Valid : IN STD_LOGIC; -- + Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- + Data_re : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); -- + Data_im : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); -- + + Read : OUT STD_LOGIC; -- Link_Read + Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- + ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + DATA : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_Linker OF Linker_FFT IS + + TYPE etat IS (eX, e0, e1, e2); + SIGNAL ect : etat; + + SIGNAL DataTmp : STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); + + SIGNAL sRead : STD_LOGIC; + SIGNAL sReady : STD_LOGIC; + + SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0; + +BEGIN + + PROCESS(clk, rstn) + BEGIN + IF(rstn = '0')then + ect <= e0; + sRead <= '0'; + sReady <= '0'; + Write <= (OTHERS => '1'); + Reuse <= (OTHERS => '0'); + FifoCpt <= 0; + + ELSIF(clk'EVENT AND clk = '1')then + sReady <= Ready; + + IF(sReady = '1' and Ready = '0')THEN + IF(FifoCpt = 4)THEN + FifoCpt <= 0; + ELSE + FifoCpt <= FifoCpt + 1; + END IF; + ELSIF(Ready = '1')then + sRead <= NOT sRead; + ELSE + sRead <= '0'; + END IF; + + CASE ect IS + + WHEN e0 => + Write(FifoCpt) <= '1'; + IF(Valid = '1' and Full(FifoCpt) = '0')THEN + DataTmp <= Data_im; + DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= Data_re; + Write(FifoCpt) <= '0'; + ect <= e1; + ELSIF(Full(FifoCpt) = '1')then + ReUse(FifoCpt) <= '1'; + END IF; + + WHEN e1 => + DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= DataTmp; + ect <= e0; + + WHEN OTHERS => + NULL; + + END CASE; + END IF; + END PROCESS; + + Read <= sRead; + +END ARCHITECTURE; diff --git a/lib/lpp/dsp/lpp_fft_rtax/actar.vhd b/lib/lpp/dsp/lpp_fft_rtax/actar.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/actar.vhd @@ -0,0 +1,2135 @@ +-- Version: 9.1 SP5 9.1.5.1 + +library ieee; +use ieee.std_logic_1164.all; +library Axcelerator; +use Axcelerator.all; + +entity actar is + port( DataA : in std_logic_vector(15 downto 0); DataB : in + std_logic_vector(15 downto 0); Mult : out + std_logic_vector(31 downto 0);Clock : in std_logic) ; +end actar; + + +architecture DEF_ARCH of actar is + + component DF1 + port(D, CLK : in std_logic := 'U'; Q : out std_logic) ; + end component; + + component XOR2 + port(A, B : in std_logic := 'U'; Y : out std_logic) ; + end component; + + component AO6 + port(A, B, C, D : in std_logic := 'U'; Y : out std_logic + ) ; + end component; + + component FA1 + port(A, B, CI : in std_logic := 'U'; CO, S : out + std_logic) ; + end component; + + component MX2 + port(A, B, S : in std_logic := 'U'; Y : out std_logic) ; + end component; + + component ADD1 + port(A, B, FCI : in std_logic := 'U'; S, FCO : out + std_logic) ; + end component; + + component BUFF + port(A : in std_logic := 'U'; Y : out std_logic) ; + end component; + + component HA1 + port(A, B : in std_logic := 'U'; CO, S : out std_logic) ; + end component; + + component OR3 + port(A, B, C : in std_logic := 'U'; Y : out std_logic) ; + end component; + + component AND3 + port(A, B, C : in std_logic := 'U'; Y : out std_logic) ; + end component; + + component AO16 + port(A, B, C : in std_logic := 'U'; Y : out std_logic) ; + end component; + + component AO1 + port(A, B, C : in std_logic := 'U'; Y : out std_logic) ; + end component; + + component AND2 + port(A, B : in std_logic := 'U'; Y : out std_logic) ; + end component; + + component FCINIT_BUFF + port(A : in std_logic := 'U'; FCO : out std_logic) ; + end component; + + component AND2A + port(A, B : in std_logic := 'U'; Y : out std_logic) ; + end component; + + component AOI1 + port(A, B, C : in std_logic := 'U'; Y : out std_logic) ; + end component; + + component FCEND_BUFF + port(FCI : in std_logic := 'U'; CO : out std_logic) ; + end component; + + component VCC + port( Y : out std_logic); + end component; + + component GND + port( Y : out std_logic); + end component; + + signal S_0_net, S_1_net, S_2_net, S_3_net, S_4_net, S_5_net, + S_6_net, S_7_net, E_0_net, E_1_net, E_2_net, E_3_net, + E_4_net, E_5_net, E_6_net, E_7_net, EBAR, PP0_0_net, + PP0_1_net, PP0_2_net, PP0_3_net, PP0_4_net, PP0_5_net, + PP0_6_net, PP0_7_net, PP0_8_net, PP0_9_net, PP0_10_net, + PP0_11_net, PP0_12_net, PP0_13_net, PP0_14_net, + PP0_15_net, PP0_16_net, PP1_0_net, PP1_1_net, PP1_2_net, + PP1_3_net, PP1_4_net, PP1_5_net, PP1_6_net, PP1_7_net, + PP1_8_net, PP1_9_net, PP1_10_net, PP1_11_net, PP1_12_net, + PP1_13_net, PP1_14_net, PP1_15_net, PP1_16_net, PP2_0_net, + PP2_1_net, PP2_2_net, PP2_3_net, PP2_4_net, PP2_5_net, + PP2_6_net, PP2_7_net, PP2_8_net, PP2_9_net, PP2_10_net, + PP2_11_net, PP2_12_net, PP2_13_net, PP2_14_net, + PP2_15_net, PP2_16_net, PP3_0_net, PP3_1_net, PP3_2_net, + PP3_3_net, PP3_4_net, PP3_5_net, PP3_6_net, PP3_7_net, + PP3_8_net, PP3_9_net, PP3_10_net, PP3_11_net, PP3_12_net, + PP3_13_net, PP3_14_net, PP3_15_net, PP3_16_net, PP4_0_net, + PP4_1_net, PP4_2_net, PP4_3_net, PP4_4_net, PP4_5_net, + PP4_6_net, PP4_7_net, PP4_8_net, PP4_9_net, PP4_10_net, + PP4_11_net, PP4_12_net, PP4_13_net, PP4_14_net, + PP4_15_net, PP4_16_net, PP5_0_net, PP5_1_net, PP5_2_net, + PP5_3_net, PP5_4_net, PP5_5_net, PP5_6_net, PP5_7_net, + PP5_8_net, PP5_9_net, PP5_10_net, PP5_11_net, PP5_12_net, + PP5_13_net, PP5_14_net, PP5_15_net, PP5_16_net, PP6_0_net, + PP6_1_net, PP6_2_net, PP6_3_net, PP6_4_net, PP6_5_net, + PP6_6_net, PP6_7_net, PP6_8_net, PP6_9_net, PP6_10_net, + PP6_11_net, PP6_12_net, PP6_13_net, PP6_14_net, + PP6_15_net, PP6_16_net, PP7_0_net, PP7_1_net, PP7_2_net, + PP7_3_net, PP7_4_net, PP7_5_net, PP7_6_net, PP7_7_net, + PP7_8_net, PP7_9_net, PP7_10_net, PP7_11_net, PP7_12_net, + PP7_13_net, PP7_14_net, PP7_15_net, PP7_16_net, + SumA_0_net, SumA_1_net, SumA_2_net, SumA_3_net, + SumA_4_net, SumA_5_net, SumA_6_net, SumA_7_net, + SumA_8_net, SumA_9_net, SumA_10_net, SumA_11_net, + SumA_12_net, SumA_13_net, SumA_14_net, SumA_15_net, + SumA_16_net, SumA_17_net, SumA_18_net, SumA_19_net, + SumA_20_net, SumA_21_net, SumA_22_net, SumA_23_net, + SumA_24_net, SumA_25_net, SumA_26_net, SumA_27_net, + SumA_28_net, SumA_29_net, SumA_30_net, SumB_0_net, + SumB_1_net, SumB_2_net, SumB_3_net, SumB_4_net, + SumB_5_net, SumB_6_net, SumB_7_net, SumB_8_net, + SumB_9_net, SumB_10_net, SumB_11_net, SumB_12_net, + SumB_13_net, SumB_14_net, SumB_15_net, SumB_16_net, + SumB_17_net, SumB_18_net, SumB_19_net, SumB_20_net, + SumB_21_net, SumB_22_net, SumB_23_net, SumB_24_net, + SumB_25_net, SumB_26_net, SumB_27_net, SumB_28_net, + SumB_29_net, SumB_30_net, DF1_117_Q, DF1_114_Q, DF1_25_Q, + DF1_111_Q, DF1_143_Q, DF1_124_Q, DF1_18_Q, DF1_30_Q, + DF1_97_Q, DF1_90_Q, DF1_102_Q, DF1_63_Q, DF1_140_Q, + DF1_137_Q, DF1_45_Q, DF1_73_Q, DF1_23_Q, DF1_120_Q, + DF1_36_Q, DF1_130_Q, DF1_42_Q, DF1_8_Q, DF1_79_Q, + DF1_78_Q, DF1_135_Q, DF1_20_Q, DF1_112_Q, DF1_61_Q, + DF1_123_Q, DF1_70_Q, DF1_55_Q, DF1_28_Q, DF1_95_Q, + DF1_94_Q, DF1_2_Q, DF1_34_Q, DF1_125_Q, DF1_77_Q, + DF1_145_Q, DF1_88_Q, DF1_49_Q, DF1_17_Q, DF1_85_Q, + DF1_84_Q, DF1_147_Q, DF1_27_Q, DF1_115_Q, DF1_66_Q, + DF1_133_Q, DF1_76_Q, DF1_10_Q, DF1_127_Q, DF1_51_Q, + DF1_50_Q, DF1_107_Q, DF1_144_Q, DF1_81_Q, DF1_33_Q, + DF1_98_Q, DF1_43_Q, DF1_122_Q, DF1_96_Q, DF1_13_Q, + DF1_11_Q, DF1_67_Q, DF1_106_Q, DF1_48_Q, DF1_151_Q, + DF1_58_Q, DF1_6_Q, DF1_103_Q, DF1_64_Q, DF1_141_Q, + DF1_138_Q, DF1_46_Q, DF1_74_Q, DF1_24_Q, DF1_121_Q, + DF1_37_Q, DF1_131_Q, DF1_59_Q, DF1_31_Q, DF1_100_Q, + DF1_99_Q, DF1_5_Q, DF1_41_Q, DF1_132_Q, DF1_82_Q, + DF1_150_Q, DF1_91_Q, DF1_101_Q, DF1_62_Q, DF1_139_Q, + DF1_136_Q, DF1_44_Q, DF1_72_Q, DF1_22_Q, DF1_119_Q, + DF1_35_Q, DF1_129_Q, DF1_68_Q, DF1_118_Q, DF1_16_Q, + DF1_3_Q, DF1_86_Q, DF1_109_Q, DF1_60_Q, DF1_83_Q, + DF1_54_Q, DF1_53_Q, DF1_19_Q, DF1_69_Q, DF1_113_Q, + DF1_105_Q, DF1_38_Q, DF1_56_Q, DF1_12_Q, DF1_32_Q, + DF1_4_Q, DF1_1_Q, DF1_152_Q, DF1_52_Q, DF1_93_Q, DF1_80_Q, + DF1_14_Q, DF1_39_Q, DF1_146_Q, DF1_9_Q, DF1_134_Q, + DF1_126_Q, DF1_7_Q, DF1_57_Q, DF1_104_Q, DF1_89_Q, + DF1_26_Q, DF1_47_Q, DF1_0_Q, DF1_21_Q, DF1_148_Q, + DF1_142_Q, DF1_92_Q, DF1_149_Q, DF1_40_Q, DF1_29_Q, + DF1_110_Q, DF1_128_Q, DF1_87_Q, DF1_108_Q, DF1_75_Q, + DF1_71_Q, DF1_65_Q, DF1_116_Q, DF1_15_Q, HA1_13_S, + HA1_13_CO, FA1_94_S, FA1_94_CO, FA1_63_S, FA1_63_CO, + HA1_0_S, HA1_0_CO, FA1_71_S, FA1_71_CO, FA1_26_S, + FA1_26_CO, FA1_42_S, FA1_42_CO, FA1_24_S, FA1_24_CO, + HA1_12_S, HA1_12_CO, FA1_43_S, FA1_43_CO, FA1_90_S, + FA1_90_CO, HA1_6_S, HA1_6_CO, FA1_41_S, FA1_41_CO, + FA1_83_S, FA1_83_CO, HA1_9_S, HA1_9_CO, FA1_85_S, + FA1_85_CO, FA1_10_S, FA1_10_CO, HA1_2_S, HA1_2_CO, + FA1_67_S, FA1_67_CO, FA1_6_S, FA1_6_CO, HA1_1_S, HA1_1_CO, + FA1_86_S, FA1_86_CO, FA1_55_S, FA1_55_CO, FA1_3_S, + FA1_3_CO, HA1_8_S, HA1_8_CO, HA1_7_S, HA1_7_CO, FA1_30_S, + FA1_30_CO, FA1_29_S, FA1_29_CO, HA1_15_S, HA1_15_CO, + FA1_28_S, FA1_28_CO, FA1_14_S, FA1_14_CO, FA1_89_S, + FA1_89_CO, FA1_62_S, FA1_62_CO, FA1_5_S, FA1_5_CO, + FA1_12_S, FA1_12_CO, FA1_9_S, FA1_9_CO, FA1_38_S, + FA1_38_CO, FA1_37_S, FA1_37_CO, FA1_87_S, FA1_87_CO, + FA1_34_S, FA1_34_CO, FA1_44_S, FA1_44_CO, FA1_13_S, + FA1_13_CO, FA1_77_S, FA1_77_CO, FA1_33_S, FA1_33_CO, + FA1_40_S, FA1_40_CO, FA1_36_S, FA1_36_CO, FA1_61_S, + FA1_61_CO, FA1_60_S, FA1_60_CO, FA1_11_S, FA1_11_CO, + FA1_56_S, FA1_56_CO, FA1_27_S, FA1_27_CO, FA1_1_S, + FA1_1_CO, FA1_68_S, FA1_68_CO, FA1_18_S, FA1_18_CO, + FA1_22_S, FA1_22_CO, FA1_21_S, FA1_21_CO, FA1_51_S, + FA1_51_CO, FA1_50_S, FA1_50_CO, HA1_14_S, HA1_14_CO, + FA1_47_S, FA1_47_CO, HA1_10_S, HA1_10_CO, HA1_11_S, + HA1_11_CO, FA1_75_S, FA1_75_CO, FA1_31_S, FA1_31_CO, + FA1_35_S, FA1_35_CO, FA1_32_S, FA1_32_CO, FA1_58_S, + FA1_58_CO, FA1_57_S, FA1_57_CO, FA1_7_S, FA1_7_CO, + FA1_54_S, FA1_54_CO, FA1_25_S, FA1_25_CO, FA1_0_S, + FA1_0_CO, FA1_66_S, FA1_66_CO, FA1_15_S, FA1_15_CO, + FA1_20_S, FA1_20_CO, FA1_17_S, FA1_17_CO, FA1_49_S, + FA1_49_CO, FA1_48_S, FA1_48_CO, FA1_92_S, FA1_92_CO, + FA1_45_S, FA1_45_CO, FA1_70_S, FA1_70_CO, FA1_52_S, + FA1_52_CO, FA1_8_S, FA1_8_CO, FA1_65_S, FA1_65_CO, + HA1_5_S, HA1_5_CO, FA1_74_CO, FA1_74_S, HA1_3_CO, HA1_3_S, + FA1_78_CO, FA1_78_S, FA1_72_CO, FA1_72_S, HA1_4_CO, + HA1_4_S, FA1_73_CO, FA1_73_S, FA1_39_CO, FA1_39_S, + FA1_81_CO, FA1_81_S, FA1_2_CO, FA1_2_S, FA1_16_CO, + FA1_16_S, FA1_91_CO, FA1_91_S, FA1_93_CO, FA1_93_S, + FA1_88_CO, FA1_88_S, FA1_76_CO, FA1_76_S, FA1_82_CO, + FA1_82_S, FA1_95_CO, FA1_95_S, FA1_84_CO, FA1_84_S, + FA1_4_CO, FA1_4_S, FA1_46_CO, FA1_46_S, FA1_96_CO, + FA1_96_S, FA1_59_CO, FA1_59_S, FA1_80_CO, FA1_80_S, + FA1_69_CO, FA1_69_S, FA1_53_CO, FA1_53_S, FA1_79_CO, + FA1_79_S, FA1_64_CO, FA1_64_S, FA1_23_CO, FA1_23_S, + FA1_19_CO, FA1_19_S, BUF_29_Y, BUF_8_Y, BUF_21_Y, + BUF_35_Y, BUF_27_Y, BUF_25_Y, BUF_28_Y, BUF_4_Y, BUF_39_Y, + BUF_2_Y, BUF_45_Y, BUF_36_Y, BUF_7_Y, BUF_13_Y, BUF_5_Y, + BUF_44_Y, BUF_14_Y, BUF_19_Y, BUF_10_Y, BUF_38_Y, + BUF_43_Y, BUF_9_Y, BUF_42_Y, BUF_15_Y, BUF_24_Y, BUF_1_Y, + BUF_16_Y, BUF_32_Y, BUF_0_Y, BUF_31_Y, BUF_46_Y, BUF_40_Y, + BUF_47_Y, BUF_41_Y, XOR2_24_Y, XOR2_19_Y, AO1_4_Y, + XOR2_6_Y, AO16_2_Y, AO6_57_Y, AO6_107_Y, AO6_104_Y, + AO6_82_Y, MX2_3_Y, AO6_115_Y, AO6_13_Y, AO6_42_Y, + XOR2_29_Y, AO16_4_Y, AO6_25_Y, AO6_36_Y, AO6_65_Y, + AND2_6_Y, AO6_28_Y, AO6_50_Y, AO6_72_Y, AO6_60_Y, + AO6_52_Y, OR3_3_Y, AND3_5_Y, BUF_17_Y, BUF_6_Y, XOR2_1_Y, + XOR2_7_Y, AO1_6_Y, XOR2_3_Y, AO16_8_Y, AO6_91_Y, AO6_93_Y, + AO6_56_Y, AO6_54_Y, MX2_5_Y, AO6_74_Y, AO6_102_Y, AO6_3_Y, + XOR2_8_Y, AO16_5_Y, AO6_44_Y, AO6_0_Y, AO6_97_Y, AND2_3_Y, + AO6_40_Y, AO6_67_Y, AO6_64_Y, AO6_90_Y, AO6_55_Y, OR3_0_Y, + AND3_3_Y, BUF_18_Y, BUF_11_Y, XOR2_27_Y, XOR2_13_Y, + AO1_5_Y, XOR2_4_Y, AO16_3_Y, AO6_23_Y, AO6_113_Y, + AO6_22_Y, AO6_1_Y, MX2_1_Y, AO6_78_Y, AO6_84_Y, AO6_33_Y, + XOR2_25_Y, AO16_13_Y, AO6_105_Y, AO6_46_Y, AO6_61_Y, + AND2_2_Y, AO6_68_Y, AO6_35_Y, AO6_29_Y, AO6_98_Y, + AO6_66_Y, OR3_2_Y, AND3_6_Y, BUF_26_Y, BUF_23_Y, + XOR2_16_Y, XOR2_26_Y, AND2A_1_Y, AO6_88_Y, AO6_51_Y, + AO6_48_Y, AO6_41_Y, MX2_2_Y, AO6_30_Y, AO6_92_Y, AO6_11_Y, + AND2A_0_Y, AO6_76_Y, AO6_73_Y, AO6_114_Y, AND2_0_Y, + AO6_63_Y, AO6_32_Y, AO6_45_Y, AO6_38_Y, AO6_4_Y, OR3_1_Y, + AND3_1_Y, BUF_22_Y, BUF_20_Y, XOR2_12_Y, XOR2_11_Y, + AO1_3_Y, XOR2_18_Y, AO16_6_Y, AO6_69_Y, AO6_21_Y, + AO6_34_Y, AO6_6_Y, MX2_4_Y, AO6_95_Y, AO6_101_Y, + AO6_117_Y, XOR2_2_Y, AO16_12_Y, AO6_109_Y, AO6_7_Y, + AO6_14_Y, AND2_7_Y, AO6_31_Y, AO6_111_Y, AO6_118_Y, + AO6_2_Y, AO6_96_Y, OR3_4_Y, AND3_7_Y, BUF_37_Y, BUF_33_Y, + XOR2_0_Y, XOR2_20_Y, AO1_0_Y, XOR2_5_Y, AO16_0_Y, + AO6_75_Y, AO6_53_Y, AO6_20_Y, AO6_49_Y, MX2_6_Y, AO6_94_Y, + AO6_87_Y, AO6_37_Y, XOR2_10_Y, AO16_1_Y, AO6_89_Y, + AO6_83_Y, AO6_10_Y, AND2_4_Y, AO6_85_Y, AO6_71_Y, + AO6_58_Y, AO6_26_Y, AO6_112_Y, OR3_7_Y, AND3_0_Y, + BUF_12_Y, BUF_3_Y, XOR2_14_Y, XOR2_15_Y, AO1_1_Y, + XOR2_28_Y, AO16_7_Y, AO6_15_Y, AO6_59_Y, AO6_12_Y, + AO6_86_Y, MX2_7_Y, AO6_8_Y, AO6_99_Y, AO6_100_Y, + XOR2_17_Y, AO16_11_Y, AO6_103_Y, AO6_43_Y, AO6_16_Y, + AND2_5_Y, AO6_110_Y, AO6_62_Y, AO6_108_Y, AO6_70_Y, + AO6_18_Y, OR3_5_Y, AND3_4_Y, BUF_34_Y, BUF_30_Y, XOR2_9_Y, + XOR2_22_Y, AO1_2_Y, XOR2_23_Y, AO16_9_Y, AO6_79_Y, + AO6_5_Y, AO6_119_Y, AO6_116_Y, MX2_0_Y, AO6_39_Y, + AO6_81_Y, AO6_17_Y, XOR2_21_Y, AO16_10_Y, AO6_9_Y, + AO6_77_Y, AO6_24_Y, AND2_1_Y, AO6_80_Y, AO6_27_Y, + AO6_106_Y, AO6_47_Y, AO6_19_Y, OR3_6_Y, AND3_2_Y, + FCEND_BUFF_0_CO, FCINIT_BUFF_0_FCO, ADD1_Mult_1_FCO, + ADD1_Mult_2_FCO, ADD1_Mult_3_FCO, ADD1_Mult_4_FCO, + ADD1_Mult_5_FCO, ADD1_Mult_6_FCO, ADD1_Mult_7_FCO, + ADD1_Mult_8_FCO, ADD1_Mult_9_FCO, ADD1_Mult_10_FCO, + ADD1_Mult_11_FCO, ADD1_Mult_12_FCO, ADD1_Mult_13_FCO, + ADD1_Mult_14_FCO, ADD1_Mult_15_FCO, ADD1_Mult_16_FCO, + ADD1_Mult_17_FCO, ADD1_Mult_18_FCO, ADD1_Mult_19_FCO, + ADD1_Mult_20_FCO, ADD1_Mult_21_FCO, ADD1_Mult_22_FCO, + ADD1_Mult_23_FCO, ADD1_Mult_24_FCO, ADD1_Mult_25_FCO, + ADD1_Mult_26_FCO, ADD1_Mult_27_FCO, ADD1_Mult_28_FCO, + ADD1_Mult_29_FCO, ADD1_Mult_30_FCO, ADD1_Mult_31_FCO, + VCC_1_net, GND_1_net : std_logic ; + begin + + VCC_2_net : VCC port map(Y => VCC_1_net); + GND_2_net : GND port map(Y => GND_1_net); + DF1_SumB_0_inst : DF1 + port map(D => DF1_0_Q, CLK => Clock, Q => SumB_0_net); + XOR2_PP7_9_inst : XOR2 + port map(A => AO6_6_Y, B => BUF_20_Y, Y => PP7_9_net); + DF1_145 : DF1 + port map(D => PP2_4_net, CLK => Clock, Q => DF1_145_Q); + DF1_SumA_17_inst : DF1 + port map(D => FA1_93_CO, CLK => Clock, Q => SumA_17_net); + AO6_7 : AO6 + port map(A => BUF_4_Y, B => AO16_12_Y, C => BUF_2_Y, D => + XOR2_2_Y, Y => AO6_7_Y); + DF1_60 : DF1 + port map(D => PP6_4_net, CLK => Clock, Q => DF1_60_Q); + FA1_33 : FA1 + port map(A => FA1_90_CO, B => HA1_6_CO, CI => FA1_83_S, + CO => FA1_33_CO, S => FA1_33_S); + FA1_46 : FA1 + port map(A => HA1_11_CO, B => DF1_127_Q, CI => FA1_75_S, + CO => FA1_46_CO, S => FA1_46_S); + DF1_SumA_6_inst : DF1 + port map(D => FA1_46_CO, CLK => Clock, Q => SumA_6_net); + MX2_PP1_16_inst : MX2 + port map(A => MX2_1_Y, B => AO1_5_Y, S => AO16_3_Y, Y => + PP1_16_net); + DF1_65 : DF1 + port map(D => E_6_net, CLK => Clock, Q => DF1_65_Q); + ADD1_Mult_23_inst : ADD1 + port map(A => SumA_22_net, B => SumB_22_net, FCI => + ADD1_Mult_22_FCO, S => Mult(23), FCO => ADD1_Mult_23_FCO); + DF1_SumB_6_inst : DF1 + port map(D => FA1_81_S, CLK => Clock, Q => SumB_6_net); + FA1_86 : FA1 + port map(A => DF1_106_Q, B => VCC_1_net, CI => DF1_72_Q, + CO => FA1_86_CO, S => FA1_86_S); + DF1_SumB_13_inst : DF1 + port map(D => FA1_96_S, CLK => Clock, Q => SumB_13_net); + FA1_44 : FA1 + port map(A => FA1_71_CO, B => HA1_12_S, CI => FA1_42_S, + CO => FA1_44_CO, S => FA1_44_S); + FA1_9 : FA1 + port map(A => DF1_40_Q, B => DF1_150_Q, CI => FA1_94_CO, + CO => FA1_9_CO, S => FA1_9_S); + FA1_90 : FA1 + port map(A => DF1_96_Q, B => DF1_28_Q, CI => DF1_62_Q, + CO => FA1_90_CO, S => FA1_90_S); + DF1_SumA_22_inst : DF1 + port map(D => FA1_74_CO, CLK => Clock, Q => SumA_22_net); + BUF_36 : BUFF + port map(A => DataA(5), Y => BUF_36_Y); + AO6_30 : AO6 + port map(A => BUF_16_Y, B => AND2A_1_Y, C => BUF_0_Y, D => + DataB(0), Y => AO6_30_Y); + DF1_SumB_4_inst : DF1 + port map(D => FA1_82_S, CLK => Clock, Q => SumB_4_net); + XOR2_PP0_13_inst : XOR2 + port map(A => AO6_51_Y, B => BUF_23_Y, Y => PP0_13_net); + XOR2_PP5_4_inst : XOR2 + port map(A => AO6_36_Y, B => BUF_47_Y, Y => PP5_4_net); + AO6_8 : AO6 + port map(A => BUF_16_Y, B => AO16_7_Y, C => BUF_0_Y, D => + XOR2_28_Y, Y => AO6_8_Y); + FA1_84 : FA1 + port map(A => DF1_130_Q, B => DF1_143_Q, CI => DF1_2_Q, + CO => FA1_84_CO, S => FA1_84_S); + HA1_11 : HA1 + port map(A => DF1_42_Q, B => DF1_124_Q, CO => HA1_11_CO, + S => HA1_11_S); + XOR2_PP6_6_inst : XOR2 + port map(A => AO6_44_Y, B => BUF_17_Y, Y => PP6_6_net); + AO6_25 : AO6 + port map(A => BUF_36_Y, B => AO16_4_Y, C => BUF_13_Y, D => + XOR2_29_Y, Y => AO6_25_Y); + FA1_63 : FA1 + port map(A => DF1_123_Q, B => DF1_137_Q, CI => DF1_84_Q, + CO => FA1_63_CO, S => FA1_63_S); + AO6_51 : AO6 + port map(A => BUF_24_Y, B => AND2A_1_Y, C => BUF_16_Y, D => + DataB(0), Y => AO6_51_Y); + FA1_75 : FA1 + port map(A => DF1_8_Q, B => DF1_18_Q, CI => DF1_125_Q, + CO => FA1_75_CO, S => FA1_75_S); + AO6_16 : AO6 + port map(A => BUF_29_Y, B => AO16_11_Y, C => BUF_21_Y, D => + XOR2_17_Y, Y => AO6_16_Y); + XOR2_PP6_4_inst : XOR2 + port map(A => AO6_0_Y, B => BUF_17_Y, Y => PP6_4_net); + XOR2_PP6_10_inst : XOR2 + port map(A => AO6_56_Y, B => BUF_6_Y, Y => PP6_10_net); + XOR2_PP5_13_inst : XOR2 + port map(A => AO6_107_Y, B => BUF_41_Y, Y => PP5_13_net); + DF1_SumA_30_inst : DF1 + port map(D => DF1_116_Q, CLK => Clock, Q => SumA_30_net); + DF1_88 : DF1 + port map(D => PP2_5_net, CLK => Clock, Q => DF1_88_Q); + OR3_6 : OR3 + port map(A => DataB(3), B => DataB(4), C => DataB(5), Y => + OR3_6_Y); + DF1_SumB_5_inst : DF1 + port map(D => FA1_46_S, CLK => Clock, Q => SumB_5_net); + FA1_26 : FA1 + port map(A => DF1_43_Q, B => DF1_70_Q, CI => DF1_91_Q, + CO => FA1_26_CO, S => FA1_26_S); + BUF_43 : BUFF + port map(A => DataA(10), Y => BUF_43_Y); + DF1_134 : DF1 + port map(D => PP7_9_net, CLK => Clock, Q => DF1_134_Q); + DF1_13 : DF1 + port map(D => PP3_11_net, CLK => Clock, Q => DF1_13_Q); + ADD1_Mult_28_inst : ADD1 + port map(A => SumA_27_net, B => SumB_27_net, FCI => + ADD1_Mult_27_FCO, S => Mult(28), FCO => ADD1_Mult_28_FCO); + XOR2_PP2_4_inst : XOR2 + port map(A => AO6_77_Y, B => BUF_34_Y, Y => PP2_4_net); + FA1_24 : FA1 + port map(A => DF1_122_Q, B => DF1_55_Q, CI => DF1_101_Q, + CO => FA1_24_CO, S => FA1_24_S); + MX2_1 : MX2 + port map(A => BUF_11_Y, B => XOR2_13_Y, S => XOR2_4_Y, Y => + MX2_1_Y); + ADD1_Mult_6_inst : ADD1 + port map(A => SumA_5_net, B => SumB_5_net, FCI => + ADD1_Mult_5_FCO, S => Mult(6), FCO => ADD1_Mult_6_FCO); + AO6_35 : AO6 + port map(A => BUF_39_Y, B => AO16_13_Y, C => BUF_45_Y, D => + XOR2_25_Y, Y => AO6_35_Y); + AO6_74 : AO6 + port map(A => BUF_32_Y, B => AO16_8_Y, C => BUF_31_Y, D => + XOR2_3_Y, Y => AO6_74_Y); + DF1_104 : DF1 + port map(D => PP7_13_net, CLK => Clock, Q => DF1_104_Q); + XOR2_PP2_11_inst : XOR2 + port map(A => AO6_81_Y, B => BUF_30_Y, Y => PP2_11_net); + DF1_10 : DF1 + port map(D => PP2_16_net, CLK => Clock, Q => DF1_10_Q); + DF1_33 : DF1 + port map(D => PP3_6_net, CLK => Clock, Q => DF1_33_Q); + AO6_108 : AO6 + port map(A => BUF_21_Y, B => AO16_11_Y, C => BUF_27_Y, D => + XOR2_17_Y, Y => AO6_108_Y); + FA1_51 : FA1 + port map(A => DF1_105_Q, B => DF1_99_Q, CI => HA1_8_CO, + CO => FA1_51_CO, S => FA1_51_S); + XOR2_PP1_15_inst : XOR2 + port map(A => AO6_23_Y, B => BUF_11_Y, Y => PP1_15_net); + DF1_0 : DF1 + port map(D => S_0_net, CLK => Clock, Q => DF1_0_Q); + DF1_9 : DF1 + port map(D => PP7_8_net, CLK => Clock, Q => DF1_9_Q); + AO6_67 : AO6 + port map(A => BUF_2_Y, B => AO16_5_Y, C => BUF_36_Y, D => + XOR2_8_Y, Y => AO6_67_Y); + BUF_15 : BUFF + port map(A => DataA(11), Y => BUF_15_Y); + AO6_2 : AO6 + port map(A => BUF_44_Y, B => AO16_12_Y, C => BUF_19_Y, D => + XOR2_2_Y, Y => AO6_2_Y); + DF1_15 : DF1 + port map(D => EBAR, CLK => Clock, Q => DF1_15_Q); + DF1_72 : DF1 + port map(D => PP5_10_net, CLK => Clock, Q => DF1_72_Q); + DF1_41 : DF1 + port map(D => PP5_0_net, CLK => Clock, Q => DF1_41_Q); + FA1_57 : FA1 + port map(A => FA1_28_CO, B => FA1_14_CO, CI => FA1_62_S, + CO => FA1_57_CO, S => FA1_57_S); + BUF_25 : BUFF + port map(A => DataA(2), Y => BUF_25_Y); + DF1_30 : DF1 + port map(D => PP0_7_net, CLK => Clock, Q => DF1_30_Q); + XOR2_PP4_7_inst : XOR2 + port map(A => AO6_85_Y, B => BUF_37_Y, Y => PP4_7_net); + AO6_84 : AO6 + port map(A => BUF_43_Y, B => AO16_3_Y, C => BUF_42_Y, D => + XOR2_4_Y, Y => AO6_84_Y); + FA1_0 : FA1 + port map(A => FA1_37_CO, B => FA1_87_CO, CI => FA1_44_S, + CO => FA1_0_CO, S => FA1_0_S); + DF1_47 : DF1 + port map(D => PP7_16_net, CLK => Clock, Q => DF1_47_Q); + FA1_15 : FA1 + port map(A => FA1_13_CO, B => FA1_77_CO, CI => FA1_40_S, + CO => FA1_15_CO, S => FA1_15_S); + FA1_36 : FA1 + port map(A => FA1_83_CO, B => HA1_9_CO, CI => FA1_10_S, + CO => FA1_36_CO, S => FA1_36_S); + XOR2_24 : XOR2 + port map(A => AND2_6_Y, B => BUF_47_Y, Y => XOR2_24_Y); + DF1_35 : DF1 + port map(D => PP5_13_net, CLK => Clock, Q => DF1_35_Q); + AO6_68 : AO6 + port map(A => BUF_7_Y, B => AO16_13_Y, C => BUF_5_Y, D => + XOR2_25_Y, Y => AO6_68_Y); + XOR2_PP2_14_inst : XOR2 + port map(A => AO6_39_Y, B => BUF_30_Y, Y => PP2_14_net); + FA1_34 : FA1 + port map(A => FA1_26_CO, B => DF1_29_Q, CI => FA1_24_S, + CO => FA1_34_CO, S => FA1_34_S); + AO6_79 : AO6 + port map(A => BUF_0_Y, B => AO16_9_Y, C => BUF_46_Y, D => + XOR2_23_Y, Y => AO6_79_Y); + BUF_16 : BUFF + port map(A => DataA(13), Y => BUF_16_Y); + DF1_SumA_7_inst : DF1 + port map(D => FA1_81_CO, CLK => Clock, Q => SumA_7_net); + OR3_4 : OR3 + port map(A => DataB(13), B => DataB(14), C => DataB(15), + Y => OR3_4_Y); + MX2_0 : MX2 + port map(A => BUF_30_Y, B => XOR2_22_Y, S => XOR2_23_Y, + Y => MX2_0_Y); + AO6_3 : AO6 + port map(A => BUF_15_Y, B => AO16_8_Y, C => BUF_1_Y, D => + XOR2_3_Y, Y => AO6_3_Y); + BUF_26 : BUFF + port map(A => DataB(1), Y => BUF_26_Y); + DF1_SumA_20_inst : DF1 + port map(D => FA1_2_CO, CLK => Clock, Q => SumA_20_net); + AO6_115 : AO6 + port map(A => BUF_32_Y, B => AO16_2_Y, C => BUF_31_Y, D => + XOR2_6_Y, Y => AO6_115_Y); + FA1_66 : FA1 + port map(A => FA1_34_CO, B => FA1_44_CO, CI => FA1_77_S, + CO => FA1_66_CO, S => FA1_66_S); + FA1_45 : FA1 + port map(A => FA1_18_CO, B => FA1_22_CO, CI => FA1_51_S, + CO => FA1_45_CO, S => FA1_45_S); + AO6_103 : AO6 + port map(A => BUF_45_Y, B => AO16_11_Y, C => BUF_7_Y, D => + XOR2_17_Y, Y => AO6_103_Y); + AO6_89 : AO6 + port map(A => BUF_36_Y, B => AO16_1_Y, C => BUF_13_Y, D => + XOR2_10_Y, Y => AO6_89_Y); + DF1_SumB_27_inst : DF1 + port map(D => FA1_19_S, CLK => Clock, Q => SumB_27_net); + DF1_53 : DF1 + port map(D => PP6_7_net, CLK => Clock, Q => DF1_53_Q); + HA1_8 : HA1 + port map(A => DF1_151_Q, B => VCC_1_net, CO => HA1_8_CO, + S => HA1_8_S); + DF1_SumA_25_inst : DF1 + port map(D => FA1_69_CO, CLK => Clock, Q => SumA_25_net); + FA1_85 : FA1 + port map(A => DF1_133_Q, B => DF1_15_Q, CI => DF1_37_Q, + CO => FA1_85_CO, S => FA1_85_S); + FA1_64 : FA1 + port map(A => FA1_35_CO, B => FA1_29_S, CI => FA1_32_S, + CO => FA1_64_CO, S => FA1_64_S); + XOR2_PP7_11_inst : XOR2 + port map(A => AO6_101_Y, B => BUF_20_Y, Y => PP7_11_net); + XOR2_PP5_1_inst : XOR2 + port map(A => AO6_65_Y, B => BUF_47_Y, Y => PP5_1_net); + DF1_50 : DF1 + port map(D => PP3_2_net, CLK => Clock, Q => DF1_50_Q); + XOR2_PP4_10_inst : XOR2 + port map(A => AO6_20_Y, B => BUF_33_Y, Y => PP4_10_net); + AO6_24 : AO6 + port map(A => BUF_29_Y, B => AO16_10_Y, C => BUF_21_Y, D => + XOR2_21_Y, Y => AO6_24_Y); + XOR2_PP3_11_inst : XOR2 + port map(A => AO6_99_Y, B => BUF_3_Y, Y => PP3_11_net); + XOR2_9 : XOR2 + port map(A => AND2_1_Y, B => BUF_34_Y, Y => XOR2_9_Y); + XOR2_25 : XOR2 + port map(A => DataB(1), B => DataB(2), Y => XOR2_25_Y); + DF1_24 : DF1 + port map(D => PP4_8_net, CLK => Clock, Q => DF1_24_Q); + DF1_55 : DF1 + port map(D => PP1_13_net, CLK => Clock, Q => DF1_55_Q); + FA1_7 : FA1 + port map(A => FA1_89_CO, B => FA1_62_CO, CI => FA1_12_S, + CO => FA1_7_CO, S => FA1_7_S); + AND3_0 : AND3 + port map(A => DataB(7), B => DataB(8), C => DataB(9), Y => + AND3_0_Y); + FA1_70 : FA1 + port map(A => FA1_51_CO, B => HA1_14_S, CI => FA1_21_CO, + CO => FA1_70_CO, S => FA1_70_S); + XOR2_PP1_1_inst : XOR2 + port map(A => AO6_61_Y, B => BUF_18_Y, Y => PP1_1_net); + AO16_4 : AO16 + port map(A => DataB(9), B => DataB(10), C => BUF_47_Y, Y => + AO16_4_Y); + DF1_49 : DF1 + port map(D => PP2_6_net, CLK => Clock, Q => DF1_49_Q); + MX2_7 : MX2 + port map(A => BUF_3_Y, B => XOR2_15_Y, S => XOR2_28_Y, Y => + MX2_7_Y); + DF1_SumB_16_inst : DF1 + port map(D => FA1_93_S, CLK => Clock, Q => SumB_16_net); + HA1_13 : HA1 + port map(A => DF1_112_Q, B => DF1_63_Q, CO => HA1_13_CO, + S => HA1_13_S); + FA1_25 : FA1 + port map(A => FA1_9_CO, B => FA1_38_CO, CI => FA1_87_S, + CO => FA1_25_CO, S => FA1_25_S); + XOR2_PP7_14_inst : XOR2 + port map(A => AO6_95_Y, B => BUF_20_Y, Y => PP7_14_net); + DF1_86 : DF1 + port map(D => PP6_2_net, CLK => Clock, Q => DF1_86_Q); + AO1_3 : AO1 + port map(A => XOR2_11_Y, B => OR3_4_Y, C => AND3_7_Y, Y => + AO1_3_Y); + AND3_7 : AND3 + port map(A => DataB(13), B => DataB(14), C => DataB(15), + Y => AND3_7_Y); + DF1_126 : DF1 + port map(D => PP7_10_net, CLK => Clock, Q => DF1_126_Q); + OR3_0 : OR3 + port map(A => DataB(11), B => DataB(12), C => DataB(13), + Y => OR3_0_Y); + MX2_6 : MX2 + port map(A => BUF_33_Y, B => XOR2_20_Y, S => XOR2_5_Y, Y => + MX2_6_Y); + AO6_34 : AO6 + port map(A => BUF_38_Y, B => AO16_6_Y, C => BUF_9_Y, D => + XOR2_18_Y, Y => AO6_34_Y); + XOR2_PP3_14_inst : XOR2 + port map(A => AO6_8_Y, B => BUF_3_Y, Y => PP3_14_net); + AO16_1 : AO16 + port map(A => DataB(7), B => DataB(8), C => BUF_37_Y, Y => + AO16_1_Y); + ADD1_Mult_10_inst : ADD1 + port map(A => SumA_9_net, B => SumB_9_net, FCI => + ADD1_Mult_9_FCO, S => Mult(10), FCO => ADD1_Mult_10_FCO); + AO6_29 : AO6 + port map(A => BUF_21_Y, B => AO16_13_Y, C => BUF_27_Y, D => + XOR2_25_Y, Y => AO6_29_Y); + XOR2_PP0_12_inst : XOR2 + port map(A => AO6_11_Y, B => BUF_23_Y, Y => PP0_12_net); + DF1_SumB_18_inst : DF1 + port map(D => FA1_79_S, CLK => Clock, Q => SumB_18_net); + AO1_0 : AO1 + port map(A => XOR2_20_Y, B => OR3_7_Y, C => AND3_0_Y, Y => + AO1_0_Y); + DF1_SumB_7_inst : DF1 + port map(D => FA1_80_S, CLK => Clock, Q => SumB_7_net); + DF1_149 : DF1 + port map(D => S_5_net, CLK => Clock, Q => DF1_149_Q); + DF1_SumB_8_inst : DF1 + port map(D => FA1_64_S, CLK => Clock, Q => SumB_8_net); + ADD1_Mult_16_inst : ADD1 + port map(A => SumA_15_net, B => SumB_15_net, FCI => + ADD1_Mult_15_FCO, S => Mult(16), FCO => ADD1_Mult_16_FCO); + AO16_7 : AO16 + port map(A => DataB(5), B => DataB(6), C => BUF_3_Y, Y => + AO16_7_Y); + DF1_64 : DF1 + port map(D => PP4_3_net, CLK => Clock, Q => DF1_64_Q); + XOR2_18 : XOR2 + port map(A => DataB(13), B => DataB(14), Y => XOR2_18_Y); + XOR2_PP5_12_inst : XOR2 + port map(A => AO6_42_Y, B => BUF_41_Y, Y => PP5_12_net); + DF1_117 : DF1 + port map(D => PP0_0_net, CLK => Clock, Q => DF1_117_Q); + XOR2_20 : XOR2 + port map(A => BUF_40_Y, B => DataB(9), Y => XOR2_20_Y); + DF1_SumA_12_inst : DF1 + port map(D => FA1_76_CO, CLK => Clock, Q => SumA_12_net); + FA1_1 : FA1 + port map(A => DF1_146_Q, B => DF1_22_Q, CI => FA1_86_CO, + CO => FA1_1_CO, S => FA1_1_S); + FA1_35 : FA1 + port map(A => DF1_58_Q, B => DF1_50_Q, CI => HA1_7_CO, + CO => FA1_35_CO, S => FA1_35_S); + FA1_53 : FA1 + port map(A => FA1_49_CO, B => FA1_1_S, CI => FA1_48_S, + CO => FA1_53_CO, S => FA1_53_S); + MX2_PP3_16_inst : MX2 + port map(A => MX2_7_Y, B => AO1_1_Y, S => AO16_7_Y, Y => + PP3_16_net); + FA1_10 : FA1 + port map(A => DF1_11_Q, B => DF1_94_Q, CI => DF1_136_Q, + CO => FA1_10_CO, S => FA1_10_S); + AO6_39 : AO6 + port map(A => BUF_16_Y, B => AO16_9_Y, C => BUF_0_Y, D => + XOR2_23_Y, Y => AO6_39_Y); + ADD1_Mult_30_inst : ADD1 + port map(A => SumA_29_net, B => SumB_29_net, FCI => + ADD1_Mult_29_FCO, S => Mult(30), FCO => ADD1_Mult_30_FCO); + AO6_76 : AO6 + port map(A => BUF_45_Y, B => AND2A_0_Y, C => BUF_7_Y, D => + DataB(0), Y => AO6_76_Y); + BUF_44 : BUFF + port map(A => DataA(7), Y => BUF_44_Y); + HA1_S_6_inst : HA1 + port map(A => XOR2_1_Y, B => DataB(13), CO => S_6_net, S => + PP6_0_net); + DF1_28 : DF1 + port map(D => PP1_14_net, CLK => Clock, Q => DF1_28_Q); + DF1_93 : DF1 + port map(D => PP7_3_net, CLK => Clock, Q => DF1_93_Q); + AND2_4 : AND2 + port map(A => XOR2_10_Y, B => BUF_8_Y, Y => AND2_4_Y); + AO6_61 : AO6 + port map(A => BUF_29_Y, B => AO16_13_Y, C => BUF_21_Y, D => + XOR2_25_Y, Y => AO6_61_Y); + DF1_131 : DF1 + port map(D => PP4_11_net, CLK => Clock, Q => DF1_131_Q); + MX2_PP6_16_inst : MX2 + port map(A => MX2_5_Y, B => AO1_6_Y, S => AO16_8_Y, Y => + PP6_16_net); + XOR2_PP7_8_inst : XOR2 + port map(A => AO6_2_Y, B => BUF_22_Y, Y => PP7_8_net); + ADD1_Mult_13_inst : ADD1 + port map(A => SumA_12_net, B => SumB_12_net, FCI => + ADD1_Mult_12_FCO, S => Mult(13), FCO => ADD1_Mult_13_FCO); + AND2_0 : AND2 + port map(A => DataB(0), B => BUF_29_Y, Y => AND2_0_Y); + DF1_90 : DF1 + port map(D => PP0_9_net, CLK => Clock, Q => DF1_90_Q); + AO6_86 : AO6 + port map(A => BUF_14_Y, B => AO16_7_Y, C => BUF_10_Y, D => + XOR2_28_Y, Y => AO6_86_Y); + DF1_110 : DF1 + port map(D => E_0_net, CLK => Clock, Q => DF1_110_Q); + FA1_65 : FA1 + port map(A => DF1_32_Q, B => DF1_71_Q, CI => DF1_104_Q, + CO => FA1_65_CO, S => FA1_65_S); + BUF_38 : BUFF + port map(A => DataA(9), Y => BUF_38_Y); + FA1_4 : FA1 + port map(A => FA1_15_CO, B => FA1_36_S, CI => FA1_20_S, + CO => FA1_4_CO, S => FA1_4_S); + AO6_90 : AO6 + port map(A => BUF_44_Y, B => AO16_5_Y, C => BUF_19_Y, D => + XOR2_8_Y, Y => AO6_90_Y); + AND2_6 : AND2 + port map(A => XOR2_29_Y, B => BUF_8_Y, Y => AND2_6_Y); + XOR2_PP6_13_inst : XOR2 + port map(A => AO6_93_Y, B => BUF_6_Y, Y => PP6_13_net); + DF1_101 : DF1 + port map(D => PP5_5_net, CLK => Clock, Q => DF1_101_Q); + FA1_40 : FA1 + port map(A => FA1_43_CO, B => HA1_9_S, CI => FA1_41_S, + CO => FA1_40_CO, S => FA1_40_S); + AO6_102 : AO6 + port map(A => BUF_9_Y, B => AO16_8_Y, C => BUF_15_Y, D => + XOR2_3_Y, Y => AO6_102_Y); + DF1_95 : DF1 + port map(D => PP1_15_net, CLK => Clock, Q => DF1_95_Q); + DF1_138 : DF1 + port map(D => PP4_5_net, CLK => Clock, Q => DF1_138_Q); + DF1_SumA_29_inst : DF1 + port map(D => HA1_4_S, CLK => Clock, Q => SumA_29_net); + AO6_107 : AO6 + port map(A => BUF_1_Y, B => AO16_2_Y, C => BUF_32_Y, D => + XOR2_6_Y, Y => AO6_107_Y); + FA1_8 : FA1 + port map(A => DF1_57_Q, B => DF1_12_Q, CI => HA1_10_S, + CO => FA1_8_CO, S => FA1_8_S); + FA1_80 : FA1 + port map(A => FA1_31_CO, B => FA1_30_S, CI => FA1_35_S, + CO => FA1_80_CO, S => FA1_80_S); + DF1_81 : DF1 + port map(D => PP3_5_net, CLK => Clock, Q => DF1_81_Q); + DF1_151 : DF1 + port map(D => PP3_16_net, CLK => Clock, Q => DF1_151_Q); + XOR2_PP0_5_inst : XOR2 + port map(A => AO6_32_Y, B => BUF_26_Y, Y => PP0_5_net); + HA1_5 : HA1 + port map(A => DF1_4_Q, B => VCC_1_net, CO => HA1_5_CO, S => + HA1_5_S); + DF1_7 : DF1 + port map(D => PP7_11_net, CLK => Clock, Q => DF1_7_Q); + DF1_87 : DF1 + port map(D => E_2_net, CLK => Clock, Q => DF1_87_Q); + BUF_5 : BUFF + port map(A => DataA(7), Y => BUF_5_Y); + DF1_144 : DF1 + port map(D => PP3_4_net, CLK => Clock, Q => DF1_144_Q); + DF1_108 : DF1 + port map(D => E_3_net, CLK => Clock, Q => DF1_108_Q); + HA1_14 : HA1 + port map(A => DF1_126_Q, B => DF1_38_Q, CO => HA1_14_CO, + S => HA1_14_S); + DF1_14 : DF1 + port map(D => PP7_5_net, CLK => Clock, Q => DF1_14_Q); + DF1_68 : DF1 + port map(D => PP5_15_net, CLK => Clock, Q => DF1_68_Q); + OR3_2 : OR3 + port map(A => DataB(1), B => DataB(2), C => DataB(3), Y => + OR3_2_Y); + BUF_30 : BUFF + port map(A => DataB(5), Y => BUF_30_Y); + ADD1_Mult_18_inst : ADD1 + port map(A => SumA_17_net, B => SumB_17_net, FCI => + ADD1_Mult_17_FCO, S => Mult(18), FCO => ADD1_Mult_18_FCO); + XOR2_PP2_8_inst : XOR2 + port map(A => AO6_47_Y, B => BUF_34_Y, Y => PP2_8_net); + XOR2_7 : XOR2 + port map(A => BUF_40_Y, B => DataB(13), Y => XOR2_7_Y); + DF1_115 : DF1 + port map(D => PP2_12_net, CLK => Clock, Q => DF1_115_Q); + BUF_0 : BUFF + port map(A => DataA(14), Y => BUF_0_Y); + DF1_34 : DF1 + port map(D => PP2_1_net, CLK => Clock, Q => DF1_34_Q); + FA1_2 : FA1 + port map(A => FA1_17_CO, B => FA1_56_S, CI => FA1_49_S, + CO => FA1_2_CO, S => FA1_2_S); + FA1_20 : FA1 + port map(A => FA1_33_CO, B => FA1_40_CO, CI => FA1_61_S, + CO => FA1_20_CO, S => FA1_20_S); + DF1_132 : DF1 + port map(D => PP5_1_net, CLK => Clock, Q => DF1_132_Q); + AO6_95 : AO6 + port map(A => BUF_32_Y, B => AO16_6_Y, C => BUF_31_Y, D => + XOR2_18_Y, Y => AO6_95_Y); + BUF_32 : BUFF + port map(A => DataA(13), Y => BUF_32_Y); + AO6_40 : AO6 + port map(A => BUF_13_Y, B => AO16_5_Y, C => BUF_44_Y, D => + XOR2_8_Y, Y => AO6_40_Y); + XOR2_23 : XOR2 + port map(A => DataB(3), B => DataB(4), Y => XOR2_23_Y); + XOR2_PP5_2_inst : XOR2 + port map(A => AO6_72_Y, B => BUF_47_Y, Y => PP5_2_net); + AO6_26 : AO6 + port map(A => BUF_44_Y, B => AO16_1_Y, C => BUF_19_Y, D => + XOR2_10_Y, Y => AO6_26_Y); + DF1_SumA_23_inst : DF1 + port map(D => FA1_16_CO, CLK => Clock, Q => SumA_23_net); + XOR2_PP2_15_inst : XOR2 + port map(A => AO6_79_Y, B => BUF_30_Y, Y => PP2_15_net); + XOR2_29 : XOR2 + port map(A => DataB(9), B => DataB(10), Y => XOR2_29_Y); + FA1_56 : FA1 + port map(A => FA1_6_CO, B => DF1_39_Q, CI => FA1_55_S, + CO => FA1_56_CO, S => FA1_56_S); + DF1_102 : DF1 + port map(D => PP0_10_net, CLK => Clock, Q => DF1_102_Q); + DF1_SumA_10_inst : DF1 + port map(D => FA1_23_CO, CLK => Clock, Q => SumA_10_net); + XOR2_PP3_5_inst : XOR2 + port map(A => AO6_62_Y, B => BUF_12_Y, Y => PP3_5_net); + XOR2_PP0_9_inst : XOR2 + port map(A => AO6_41_Y, B => BUF_23_Y, Y => PP0_9_net); + XOR2_PP2_6_inst : XOR2 + port map(A => AO6_9_Y, B => BUF_34_Y, Y => PP2_6_net); + FA1_54 : FA1 + port map(A => FA1_5_CO, B => FA1_12_CO, CI => FA1_38_S, + CO => FA1_54_CO, S => FA1_54_S); + DF1_152 : DF1 + port map(D => PP7_1_net, CLK => Clock, Q => DF1_152_Q); + DF1_SumA_15_inst : DF1 + port map(D => FA1_95_CO, CLK => Clock, Q => SumA_15_net); + XOR2_27 : XOR2 + port map(A => AND2_2_Y, B => BUF_18_Y, Y => XOR2_27_Y); + DF1_SumA_3_inst : DF1 + port map(D => HA1_3_CO, CLK => Clock, Q => SumA_3_net); + XOR2_6 : XOR2 + port map(A => DataB(9), B => DataB(10), Y => XOR2_6_Y); + BUF_7 : BUFF + port map(A => DataA(6), Y => BUF_7_Y); + FCINIT_BUFF_0 : FCINIT_BUFF + port map(A => GND_1_net, FCO => FCINIT_BUFF_0_FCO); + AO6_36 : AO6 + port map(A => BUF_4_Y, B => AO16_4_Y, C => BUF_2_Y, D => + XOR2_29_Y, Y => AO6_36_Y); + BUF_4 : BUFF + port map(A => DataA(3), Y => BUF_4_Y); + FA1_3 : FA1 + port map(A => DF1_48_Q, B => DF1_87_Q, CI => DF1_31_Q, + CO => FA1_3_CO, S => FA1_3_S); + BUF_18 : BUFF + port map(A => DataB(3), Y => BUF_18_Y); + FA1_30 : FA1 + port map(A => DF1_78_Q, B => DF1_97_Q, CI => DF1_145_Q, + CO => FA1_30_CO, S => FA1_30_S); + DF1_123 : DF1 + port map(D => PP1_11_net, CLK => Clock, Q => DF1_123_Q); + BUF_28 : BUFF + port map(A => DataA(3), Y => BUF_28_Y); + DF1_89 : DF1 + port map(D => PP7_14_net, CLK => Clock, Q => DF1_89_Q); + MX2_PP0_16_inst : MX2 + port map(A => MX2_2_Y, B => EBAR, S => AND2A_1_Y, Y => + PP0_16_net); + AO6_9 : AO6 + port map(A => BUF_45_Y, B => AO16_10_Y, C => BUF_7_Y, D => + XOR2_21_Y, Y => AO6_9_Y); + DF1_18 : DF1 + port map(D => PP0_6_net, CLK => Clock, Q => DF1_18_Q); + DF1_SumB_30_inst : DF1 + port map(D => HA1_4_CO, CLK => Clock, Q => SumB_30_net); + DF1_SumB_22_inst : DF1 + port map(D => FA1_16_S, CLK => Clock, Q => SumB_22_net); + AO6_45 : AO6 + port map(A => BUF_21_Y, B => AND2A_0_Y, C => BUF_27_Y, D => + DataB(0), Y => AO6_45_Y); + AO6_13 : AO6 + port map(A => BUF_9_Y, B => AO16_2_Y, C => BUF_15_Y, D => + XOR2_6_Y, Y => AO6_13_Y); + AO6_50 : AO6 + port map(A => BUF_2_Y, B => AO16_4_Y, C => BUF_36_Y, D => + XOR2_29_Y, Y => AO6_50_Y); + DF1_54 : DF1 + port map(D => PP6_6_net, CLK => Clock, Q => DF1_54_Q); + AND2A_1 : AND2A + port map(A => DataB(0), B => BUF_23_Y, Y => AND2A_1_Y); + XOR2_PP6_5_inst : XOR2 + port map(A => AO6_67_Y, B => BUF_17_Y, Y => PP6_5_net); + XOR2_PP6_8_inst : XOR2 + port map(A => AO6_90_Y, B => BUF_17_Y, Y => PP6_8_net); + DF1_26 : DF1 + port map(D => PP7_15_net, CLK => Clock, Q => DF1_26_Q); + DF1_38 : DF1 + port map(D => PP6_12_net, CLK => Clock, Q => DF1_38_Q); + XOR2_PP4_13_inst : XOR2 + port map(A => AO6_53_Y, B => BUF_33_Y, Y => PP4_13_net); + XOR2_PP4_3_inst : XOR2 + port map(A => AO6_112_Y, B => BUF_37_Y, Y => PP4_3_net); + ADD1_Mult_9_inst : ADD1 + port map(A => SumA_8_net, B => SumB_8_net, FCI => + ADD1_Mult_8_FCO, S => Mult(9), FCO => ADD1_Mult_9_FCO); + BUF_10 : BUFF + port map(A => DataA(9), Y => BUF_10_Y); + AO6_12 : AO6 + port map(A => BUF_10_Y, B => AO16_7_Y, C => BUF_43_Y, D => + XOR2_28_Y, Y => AO6_12_Y); + FA1_6 : FA1 + port map(A => DF1_67_Q, B => DF1_128_Q, CI => DF1_44_Q, + CO => FA1_6_CO, S => FA1_6_S); + ADD1_Mult_5_inst : ADD1 + port map(A => SumA_4_net, B => SumB_4_net, FCI => + ADD1_Mult_4_FCO, S => Mult(5), FCO => ADD1_Mult_5_FCO); + FA1_60 : FA1 + port map(A => FA1_10_CO, B => HA1_2_CO, CI => FA1_6_S, + CO => FA1_60_CO, S => FA1_60_S); + BUF_20 : BUFF + port map(A => DataB(15), Y => BUF_20_Y); + XOR2_PP7_15_inst : XOR2 + port map(A => AO6_69_Y, B => BUF_20_Y, Y => PP7_15_net); + DF1_SumB_11_inst : DF1 + port map(D => FA1_76_S, CLK => Clock, Q => SumB_11_net); + XOR2_PP6_9_inst : XOR2 + port map(A => AO6_54_Y, B => BUF_6_Y, Y => PP6_9_net); + XOR2_PP1_2_inst : XOR2 + port map(A => AO6_29_Y, B => BUF_18_Y, Y => PP1_2_net); + HA1_15 : HA1 + port map(A => DF1_6_Q, B => DF1_107_Q, CO => HA1_15_CO, + S => HA1_15_S); + BUF_12 : BUFF + port map(A => DataB(7), Y => BUF_12_Y); + AOI1_E_0_inst : AOI1 + port map(A => XOR2_26_Y, B => OR3_1_Y, C => AND3_1_Y, Y => + E_0_net); + XOR2_PP1_10_inst : XOR2 + port map(A => AO6_22_Y, B => BUF_11_Y, Y => PP1_10_net); + XOR2_PP3_15_inst : XOR2 + port map(A => AO6_15_Y, B => BUF_3_Y, Y => PP3_15_net); + MX2_PP5_16_inst : MX2 + port map(A => MX2_3_Y, B => AO1_4_Y, S => AO16_2_Y, Y => + PP5_16_net); + BUF_22 : BUFF + port map(A => DataB(15), Y => BUF_22_Y); + AO6_4 : AO6 + port map(A => BUF_27_Y, B => AND2A_0_Y, C => BUF_28_Y, D => + DataB(0), Y => AO6_4_Y); + BUF_31 : BUFF + port map(A => DataA(14), Y => BUF_31_Y); + AO6_55 : AO6 + port map(A => BUF_25_Y, B => AO16_5_Y, C => BUF_4_Y, D => + XOR2_8_Y, Y => AO6_55_Y); + XOR2_PP5_9_inst : XOR2 + port map(A => AO6_82_Y, B => BUF_41_Y, Y => PP5_9_net); + AO6_114 : AO6 + port map(A => BUF_29_Y, B => AND2A_0_Y, C => BUF_21_Y, D => + DataB(0), Y => AO6_114_Y); + DF1_66 : DF1 + port map(D => PP2_13_net, CLK => Clock, Q => DF1_66_Q); + XOR2_0 : XOR2 + port map(A => AND2_4_Y, B => BUF_37_Y, Y => XOR2_0_Y); + DF1_SumA_9_inst : DF1 + port map(D => FA1_64_CO, CLK => Clock, Q => SumA_9_net); + HA1_S_5_inst : HA1 + port map(A => XOR2_24_Y, B => DataB(11), CO => S_5_net, + S => PP5_0_net); + AO6_94 : AO6 + port map(A => BUF_32_Y, B => AO16_0_Y, C => BUF_31_Y, D => + XOR2_5_Y, Y => AO6_94_Y); + AO6_116 : AO6 + port map(A => BUF_14_Y, B => AO16_9_Y, C => BUF_10_Y, D => + XOR2_23_Y, Y => AO6_116_Y); + DF1_73 : DF1 + port map(D => PP0_15_net, CLK => Clock, Q => DF1_73_Q); + XOR2_PP6_12_inst : XOR2 + port map(A => AO6_3_Y, B => BUF_6_Y, Y => PP6_12_net); + DF1_58 : DF1 + port map(D => PP4_0_net, CLK => Clock, Q => DF1_58_Q); + XOR2_PP0_1_inst : XOR2 + port map(A => AO6_114_Y, B => BUF_26_Y, Y => PP0_1_net); + XOR2_PP4_1_inst : XOR2 + port map(A => AO6_10_Y, B => BUF_37_Y, Y => PP4_1_net); + XOR2_PP5_3_inst : XOR2 + port map(A => AO6_52_Y, B => BUF_47_Y, Y => PP5_3_net); + FA1_55 : FA1 + port map(A => DF1_59_Q, B => DF1_10_Q, CI => DF1_19_Q, + CO => FA1_55_CO, S => FA1_55_S); + DF1_70 : DF1 + port map(D => PP1_12_net, CLK => Clock, Q => DF1_70_Q); + AO6_105 : AO6 + port map(A => BUF_45_Y, B => AO16_13_Y, C => BUF_7_Y, D => + XOR2_25_Y, Y => AO6_105_Y); + AOI1_E_2_inst : AOI1 + port map(A => XOR2_22_Y, B => OR3_6_Y, C => AND3_2_Y, Y => + E_2_net); + AO6_5 : AO6 + port map(A => BUF_24_Y, B => AO16_9_Y, C => BUF_16_Y, D => + XOR2_23_Y, Y => AO6_5_Y); + DF1_75 : DF1 + port map(D => E_4_net, CLK => Clock, Q => DF1_75_Q); + DF1_SumB_20_inst : DF1 + port map(D => FA1_53_S, CLK => Clock, Q => SumB_20_net); + DF1_21 : DF1 + port map(D => S_1_net, CLK => Clock, Q => DF1_21_Q); + DF1_94 : DF1 + port map(D => PP1_16_net, CLK => Clock, Q => DF1_94_Q); + AO6_99 : AO6 + port map(A => BUF_43_Y, B => AO16_7_Y, C => BUF_42_Y, D => + XOR2_28_Y, Y => AO6_99_Y); + DF1_SumA_19_inst : DF1 + port map(D => FA1_79_CO, CLK => Clock, Q => SumA_19_net); + DF1_27 : DF1 + port map(D => PP2_11_net, CLK => Clock, Q => DF1_27_Q); + DF1_141 : DF1 + port map(D => PP4_4_net, CLK => Clock, Q => DF1_141_Q); + DF1_SumA_26_inst : DF1 + port map(D => FA1_39_CO, CLK => Clock, Q => SumA_26_net); + ADD1_Mult_7_inst : ADD1 + port map(A => SumA_6_net, B => SumB_6_net, FCI => + ADD1_Mult_6_FCO, S => Mult(7), FCO => ADD1_Mult_7_FCO); + DF1_42 : DF1 + port map(D => PP1_3_net, CLK => Clock, Q => DF1_42_Q); + AO6_44 : AO6 + port map(A => BUF_36_Y, B => AO16_5_Y, C => BUF_13_Y, D => + XOR2_8_Y, Y => AO6_44_Y); + DF1_SumB_25_inst : DF1 + port map(D => FA1_39_S, CLK => Clock, Q => SumB_25_net); + AOI1_E_7_inst : AOI1 + port map(A => XOR2_11_Y, B => OR3_4_Y, C => AND3_7_Y, Y => + E_7_net); + XOR2_21 : XOR2 + port map(A => DataB(3), B => DataB(4), Y => XOR2_21_Y); + AO6_17 : AO6 + port map(A => BUF_42_Y, B => AO16_9_Y, C => BUF_24_Y, D => + XOR2_23_Y, Y => AO6_17_Y); + XOR2_PP0_2_inst : XOR2 + port map(A => AO6_45_Y, B => BUF_26_Y, Y => PP0_2_net); + XOR2_PP6_3_inst : XOR2 + port map(A => AO6_55_Y, B => BUF_17_Y, Y => PP6_3_net); + DF1_16 : DF1 + port map(D => PP6_0_net, CLK => Clock, Q => DF1_16_Q); + DF1_148 : DF1 + port map(D => S_2_net, CLK => Clock, Q => DF1_148_Q); + DF1_SumA_28_inst : DF1 + port map(D => FA1_19_CO, CLK => Clock, Q => SumA_28_net); + XOR2_PP0_11_inst : XOR2 + port map(A => AO6_92_Y, B => BUF_23_Y, Y => PP0_11_net); + XOR2_14 : XOR2 + port map(A => AND2_5_Y, B => BUF_12_Y, Y => XOR2_14_Y); + AO1_EBAR : AO1 + port map(A => XOR2_26_Y, B => OR3_1_Y, C => AND3_1_Y, Y => + EBAR); + BUF_11 : BUFF + port map(A => DataB(3), Y => BUF_11_Y); + DF1_119 : DF1 + port map(D => PP5_12_net, CLK => Clock, Q => DF1_119_Q); + BUF_21 : BUFF + port map(A => DataA(1), Y => BUF_21_Y); + FA1_79 : FA1 + port map(A => FA1_20_CO, B => FA1_60_S, CI => FA1_17_S, + CO => FA1_79_CO, S => FA1_79_S); + DF1_36 : DF1 + port map(D => PP1_1_net, CLK => Clock, Q => DF1_36_Q); + FA1_92 : FA1 + port map(A => FA1_1_CO, B => FA1_68_CO, CI => FA1_22_S, + CO => FA1_92_CO, S => FA1_92_S); + AO6_18 : AO6 + port map(A => BUF_27_Y, B => AO16_11_Y, C => BUF_28_Y, D => + XOR2_17_Y, Y => AO6_18_Y); + DF1_61 : DF1 + port map(D => PP1_10_net, CLK => Clock, Q => DF1_61_Q); + XOR2_PP5_11_inst : XOR2 + port map(A => AO6_13_Y, B => BUF_41_Y, Y => PP5_11_net); + XOR2_4 : XOR2 + port map(A => DataB(1), B => DataB(2), Y => XOR2_4_Y); + AO6_49 : AO6 + port map(A => BUF_19_Y, B => AO16_0_Y, C => BUF_38_Y, D => + XOR2_5_Y, Y => AO6_49_Y); + DF1_SumA_13_inst : DF1 + port map(D => FA1_73_CO, CLK => Clock, Q => SumA_13_net); + XOR2_PP1_9_inst : XOR2 + port map(A => AO6_1_Y, B => BUF_11_Y, Y => PP1_9_net); + DF1_67 : DF1 + port map(D => PP3_13_net, CLK => Clock, Q => DF1_67_Q); + AO6_0 : AO6 + port map(A => BUF_4_Y, B => AO16_5_Y, C => BUF_2_Y, D => + XOR2_8_Y, Y => AO6_0_Y); + BUF_47 : BUFF + port map(A => DataB(11), Y => BUF_47_Y); + HA1_1 : HA1 + port map(A => DF1_14_Q, B => DF1_53_Q, CO => HA1_1_CO, S => + HA1_1_S); + HA1_10 : HA1 + port map(A => DF1_118_Q, B => VCC_1_net, CO => HA1_10_CO, + S => HA1_10_S); + XOR2_PP5_6_inst : XOR2 + port map(A => AO6_25_Y, B => BUF_47_Y, Y => PP5_6_net); + AO6_54 : AO6 + port map(A => BUF_19_Y, B => AO16_8_Y, C => BUF_38_Y, D => + XOR2_3_Y, Y => AO6_54_Y); + DF1_136 : DF1 + port map(D => PP5_8_net, CLK => Clock, Q => DF1_136_Q); + XOR2_PP0_14_inst : XOR2 + port map(A => AO6_30_Y, B => BUF_23_Y, Y => PP0_14_net); + ADD1_Mult_4_inst : ADD1 + port map(A => SumA_3_net, B => SumB_3_net, FCI => + ADD1_Mult_3_FCO, S => Mult(4), FCO => ADD1_Mult_4_FCO); + DF1_142 : DF1 + port map(D => S_3_net, CLK => Clock, Q => DF1_142_Q); + DF1_98 : DF1 + port map(D => PP3_7_net, CLK => Clock, Q => DF1_98_Q); + DF1_SumA_8_inst : DF1 + port map(D => FA1_80_CO, CLK => Clock, Q => SumA_8_net); + AO6_110 : AO6 + port map(A => BUF_7_Y, B => AO16_11_Y, C => BUF_5_Y, D => + XOR2_17_Y, Y => AO6_110_Y); + AND2_1 : AND2 + port map(A => XOR2_21_Y, B => BUF_29_Y, Y => AND2_1_Y); + OR3_3 : OR3 + port map(A => DataB(9), B => DataB(10), C => DataB(11), + Y => OR3_3_Y); + DF1_29 : DF1 + port map(D => S_7_net, CLK => Clock, Q => DF1_29_Q); + DF1_SumB_14_inst : DF1 + port map(D => FA1_95_S, CLK => Clock, Q => SumB_14_net); + DF1_SumB_2_inst : DF1 + port map(D => HA1_3_S, CLK => Clock, Q => SumB_2_net); + XOR2_PP4_12_inst : XOR2 + port map(A => AO6_37_Y, B => BUF_33_Y, Y => PP4_12_net); + HA1_S_4_inst : HA1 + port map(A => XOR2_0_Y, B => DataB(9), CO => S_4_net, S => + PP4_0_net); + DF1_106 : DF1 + port map(D => PP3_14_net, CLK => Clock, Q => DF1_106_Q); + AND2_7 : AND2 + port map(A => XOR2_2_Y, B => BUF_8_Y, Y => AND2_7_Y); + XOR2_PP5_14_inst : XOR2 + port map(A => AO6_115_Y, B => BUF_41_Y, Y => PP5_14_net); + BUF_33 : BUFF + port map(A => DataB(9), Y => BUF_33_Y); + AO6_73 : AO6 + port map(A => BUF_28_Y, B => AND2A_0_Y, C => BUF_39_Y, D => + DataB(0), Y => AO6_73_Y); + XOR2_PP0_6_inst : XOR2 + port map(A => AO6_76_Y, B => BUF_26_Y, Y => PP0_6_net); + XOR2_PP3_1_inst : XOR2 + port map(A => AO6_16_Y, B => BUF_12_Y, Y => PP3_1_net); + XOR2_15 : XOR2 + port map(A => BUF_46_Y, B => DataB(7), Y => XOR2_15_Y); + HA1_6 : HA1 + port map(A => DF1_52_Q, B => DF1_60_Q, CO => HA1_6_CO, S => + HA1_6_S); + FCEND_BUFF_0 : FCEND_BUFF + port map(FCI => ADD1_Mult_31_FCO, CO => FCEND_BUFF_0_CO); + AO6_111 : AO6 + port map(A => BUF_2_Y, B => AO16_12_Y, C => BUF_36_Y, D => + XOR2_2_Y, Y => AO6_111_Y); + FA1_19 : FA1 + port map(A => HA1_5_S, B => DF1_89_Q, CI => FA1_65_CO, + CO => FA1_19_CO, S => FA1_19_S); + MX2_4 : MX2 + port map(A => BUF_20_Y, B => XOR2_11_Y, S => XOR2_18_Y, + Y => MX2_4_Y); + AO6_59 : AO6 + port map(A => BUF_24_Y, B => AO16_7_Y, C => BUF_16_Y, D => + XOR2_28_Y, Y => AO6_59_Y); + AO6_60 : AO6 + port map(A => BUF_44_Y, B => AO16_4_Y, C => BUF_19_Y, D => + XOR2_29_Y, Y => AO6_60_Y); + DF1_56 : DF1 + port map(D => PP6_13_net, CLK => Clock, Q => DF1_56_Q); + FA1_5 : FA1 + port map(A => DF1_82_Q, B => DF1_33_Q, CI => HA1_13_CO, + CO => FA1_5_CO, S => FA1_5_S); + AND3_4 : AND3 + port map(A => DataB(5), B => DataB(6), C => DataB(7), Y => + AND3_4_Y); + XOR2_PP2_2_inst : XOR2 + port map(A => AO6_106_Y, B => BUF_34_Y, Y => PP2_2_net); + AO6_72 : AO6 + port map(A => BUF_35_Y, B => AO16_4_Y, C => BUF_25_Y, D => + XOR2_29_Y, Y => AO6_72_Y); + FA1_50 : FA1 + port map(A => DF1_5_Q, B => VCC_1_net, CI => DF1_129_Q, + CO => FA1_50_CO, S => FA1_50_S); + AO6_83 : AO6 + port map(A => BUF_4_Y, B => AO16_1_Y, C => BUF_2_Y, D => + XOR2_10_Y, Y => AO6_83_Y); + DF1_114 : DF1 + port map(D => PP0_1_net, CLK => Clock, Q => DF1_114_Q); + DF1_11 : DF1 + port map(D => PP3_12_net, CLK => Clock, Q => DF1_11_Q); + BUF_8 : BUFF + port map(A => DataA(0), Y => BUF_8_Y); + AO6_96 : AO6 + port map(A => BUF_25_Y, B => AO16_12_Y, C => BUF_4_Y, D => + XOR2_2_Y, Y => AO6_96_Y); + HA1_3 : HA1 + port map(A => DF1_36_Q, B => DF1_111_Q, CO => HA1_3_CO, + S => HA1_3_S); + DF1_17 : DF1 + port map(D => PP2_7_net, CLK => Clock, Q => DF1_17_Q); + AOI1_E_4_inst : AOI1 + port map(A => XOR2_20_Y, B => OR3_7_Y, C => AND3_0_Y, Y => + E_4_net); + DF1_69 : DF1 + port map(D => PP6_9_net, CLK => Clock, Q => DF1_69_Q); + AO6_82 : AO6 + port map(A => BUF_19_Y, B => AO16_2_Y, C => BUF_38_Y, D => + XOR2_6_Y, Y => AO6_82_Y); + AND3_1 : AND3 + port map(A => GND_1_net, B => DataB(0), C => DataB(1), Y => + AND3_1_Y); + XOR2_22 : XOR2 + port map(A => BUF_46_Y, B => DataB(5), Y => XOR2_22_Y); + DF1_31 : DF1 + port map(D => PP4_13_net, CLK => Clock, Q => DF1_31_Q); + FA1_49 : FA1 + port map(A => FA1_60_CO, B => FA1_11_CO, CI => FA1_27_S, + CO => FA1_49_CO, S => FA1_49_S); + DF1_SumB_29_inst : DF1 + port map(D => FA1_88_CO, CLK => Clock, Q => SumB_29_net); + AO16_13 : AO16 + port map(A => DataB(1), B => DataB(2), C => BUF_18_Y, Y => + AO16_13_Y); + DF1_127 : DF1 + port map(D => PP3_0_net, CLK => Clock, Q => DF1_127_Q); + DF1_37 : DF1 + port map(D => PP4_10_net, CLK => Clock, Q => DF1_37_Q); + XOR2_PP6_1_inst : XOR2 + port map(A => AO6_97_Y, B => BUF_17_Y, Y => PP6_1_net); + AO6_119 : AO6 + port map(A => BUF_10_Y, B => AO16_9_Y, C => BUF_43_Y, D => + XOR2_23_Y, Y => AO6_119_Y); + FA1_89 : FA1 + port map(A => DF1_64_Q, B => DF1_17_Q, CI => DF1_149_Q, + CO => FA1_89_CO, S => FA1_89_S); + XOR2_10 : XOR2 + port map(A => DataB(7), B => DataB(8), Y => XOR2_10_Y); + XOR2_PP3_6_inst : XOR2 + port map(A => AO6_103_Y, B => BUF_12_Y, Y => PP3_6_net); + AO6_65 : AO6 + port map(A => BUF_8_Y, B => AO16_4_Y, C => BUF_35_Y, D => + XOR2_29_Y, Y => AO6_65_Y); + XOR2_PP1_13_inst : XOR2 + port map(A => AO6_113_Y, B => BUF_11_Y, Y => PP1_13_net); + ADD1_Mult_22_inst : ADD1 + port map(A => SumA_21_net, B => SumB_21_net, FCI => + ADD1_Mult_21_FCO, S => Mult(22), FCO => ADD1_Mult_22_FCO); + XOR2_26 : XOR2 + port map(A => BUF_46_Y, B => DataB(1), Y => XOR2_26_Y); + HA1_S_7_inst : HA1 + port map(A => XOR2_12_Y, B => DataB(15), CO => S_7_net, + S => PP7_0_net); + AO6_23 : AO6 + port map(A => BUF_0_Y, B => AO16_3_Y, C => BUF_46_Y, D => + XOR2_4_Y, Y => AO6_23_Y); + XOR2_PP2_1_inst : XOR2 + port map(A => AO6_24_Y, B => BUF_34_Y, Y => PP2_1_net); + AO6_46 : AO6 + port map(A => BUF_28_Y, B => AO16_13_Y, C => BUF_39_Y, D => + XOR2_25_Y, Y => AO6_46_Y); + XOR2_PP2_10_inst : XOR2 + port map(A => AO6_119_Y, B => BUF_30_Y, Y => PP2_10_net); + BUF_13 : BUFF + port map(A => DataA(6), Y => BUF_13_Y); + DF1_120 : DF1 + port map(D => PP1_0_net, CLK => Clock, Q => DF1_120_Q); + FA1_29 : FA1 + port map(A => DF1_135_Q, B => DF1_90_Q, CI => DF1_88_Q, + CO => FA1_29_CO, S => FA1_29_S); + AO6_11 : AO6 + port map(A => BUF_42_Y, B => AND2A_1_Y, C => BUF_24_Y, D => + DataB(0), Y => AO6_11_Y); + AND2_3 : AND2 + port map(A => XOR2_8_Y, B => BUF_8_Y, Y => AND2_3_Y); + BUF_23 : BUFF + port map(A => DataB(1), Y => BUF_23_Y); + XOR2_PP1_6_inst : XOR2 + port map(A => AO6_105_Y, B => BUF_18_Y, Y => PP1_6_net); + FA1_78 : FA1 + port map(A => FA1_45_CO, B => FA1_50_S, CI => FA1_70_S, + CO => FA1_78_CO, S => FA1_78_S); + DF1_SumB_23_inst : DF1 + port map(D => FA1_78_S, CLK => Clock, Q => SumB_23_net); + FA1_72 : FA1 + port map(A => FA1_58_CO, B => FA1_89_S, CI => FA1_57_S, + CO => FA1_72_CO, S => FA1_72_S); + XOR2_PP7_3_inst : XOR2 + port map(A => AO6_96_Y, B => BUF_22_Y, Y => PP7_3_net); + AO6_22 : AO6 + port map(A => BUF_10_Y, B => AO16_3_Y, C => BUF_43_Y, D => + XOR2_4_Y, Y => AO6_22_Y); + MX2_PP7_16_inst : MX2 + port map(A => MX2_4_Y, B => AO1_3_Y, S => AO16_6_Y, Y => + PP7_16_net); + DF1_74 : DF1 + port map(D => PP4_7_net, CLK => Clock, Q => DF1_74_Q); + DF1_82 : DF1 + port map(D => PP5_2_net, CLK => Clock, Q => DF1_82_Q); + DF1_51 : DF1 + port map(D => PP3_1_net, CLK => Clock, Q => DF1_51_Q); + BUF_39 : BUFF + port map(A => DataA(4), Y => BUF_39_Y); + XOR2_PP3_4_inst : XOR2 + port map(A => AO6_43_Y, B => BUF_12_Y, Y => PP3_4_net); + AO6_6 : AO6 + port map(A => BUF_19_Y, B => AO16_6_Y, C => BUF_38_Y, D => + XOR2_18_Y, Y => AO6_6_Y); + DF1_4 : DF1 + port map(D => PP6_16_net, CLK => Clock, Q => DF1_4_Q); + DF1_19 : DF1 + port map(D => PP6_8_net, CLK => Clock, Q => DF1_19_Q); + AO6_33 : AO6 + port map(A => BUF_42_Y, B => AO16_3_Y, C => BUF_24_Y, D => + XOR2_4_Y, Y => AO6_33_Y); + DF1_96 : DF1 + port map(D => PP3_10_net, CLK => Clock, Q => DF1_96_Q); + DF1_57 : DF1 + port map(D => PP7_12_net, CLK => Clock, Q => DF1_57_Q); + DF1_SumA_16_inst : DF1 + port map(D => FA1_59_CO, CLK => Clock, Q => SumA_16_net); + AO6_77 : AO6 + port map(A => BUF_28_Y, B => AO16_10_Y, C => BUF_39_Y, D => + XOR2_21_Y, Y => AO6_77_Y); + AND2A_0 : AND2A + port map(A => DataB(0), B => BUF_26_Y, Y => AND2A_0_Y); + DF1_39 : DF1 + port map(D => PP7_6_net, CLK => Clock, Q => DF1_39_Q); + DF1_SumA_1_inst : DF1 + port map(D => DF1_25_Q, CLK => Clock, Q => SumA_1_net); + DF1_125 : DF1 + port map(D => PP2_2_net, CLK => Clock, Q => DF1_125_Q); + XOR2_PP4_8_inst : XOR2 + port map(A => AO6_26_Y, B => BUF_37_Y, Y => PP4_8_net); + AO6_56 : AO6 + port map(A => BUF_38_Y, B => AO16_8_Y, C => BUF_9_Y, D => + XOR2_3_Y, Y => AO6_56_Y); + FA1_39 : FA1 + port map(A => FA1_52_CO, B => FA1_47_CO, CI => FA1_8_S, + CO => FA1_39_CO, S => FA1_39_S); + AO6_32 : AO6 + port map(A => BUF_39_Y, B => AND2A_0_Y, C => BUF_45_Y, D => + DataB(0), Y => AO6_32_Y); + DF1_SumA_21_inst : DF1 + port map(D => FA1_53_CO, CLK => Clock, Q => SumA_21_net); + ADD1_Mult_25_inst : ADD1 + port map(A => SumA_24_net, B => SumB_24_net, FCI => + ADD1_Mult_24_FCO, S => Mult(25), FCO => ADD1_Mult_25_FCO); + AO16_8 : AO16 + port map(A => DataB(11), B => DataB(12), C => BUF_6_Y, Y => + AO16_8_Y); + DF1_SumA_18_inst : DF1 + port map(D => FA1_4_CO, CLK => Clock, Q => SumA_18_net); + AO6_78 : AO6 + port map(A => BUF_16_Y, B => AO16_3_Y, C => BUF_0_Y, D => + XOR2_4_Y, Y => AO6_78_Y); + DF1_133 : DF1 + port map(D => PP2_14_net, CLK => Clock, Q => DF1_133_Q); + AO6_87 : AO6 + port map(A => BUF_9_Y, B => AO16_0_Y, C => BUF_15_Y, D => + XOR2_5_Y, Y => AO6_87_Y); + XOR2_13 : XOR2 + port map(A => BUF_46_Y, B => DataB(3), Y => XOR2_13_Y); + XOR2_2 : XOR2 + port map(A => DataB(13), B => DataB(14), Y => XOR2_2_Y); + XOR2_3 : XOR2 + port map(A => DataB(11), B => DataB(12), Y => XOR2_3_Y); + FA1_18 : FA1 + port map(A => DF1_113_Q, B => DF1_100_Q, CI => HA1_8_S, + CO => FA1_18_CO, S => FA1_18_S); + XOR2_PP7_10_inst : XOR2 + port map(A => AO6_34_Y, B => BUF_20_Y, Y => PP7_10_net); + FA1_12 : FA1 + port map(A => DF1_16_Q, B => DF1_141_Q, CI => FA1_94_S, + CO => FA1_12_CO, S => FA1_12_S); + XOR2_19 : XOR2 + port map(A => BUF_40_Y, B => DataB(11), Y => XOR2_19_Y); + HA1_7 : HA1 + port map(A => DF1_79_Q, B => DF1_30_Q, CO => HA1_7_CO, S => + HA1_7_S); + AO1_2 : AO1 + port map(A => XOR2_22_Y, B => OR3_6_Y, C => AND3_2_Y, Y => + AO1_2_Y); + XOR2_PP3_7_inst : XOR2 + port map(A => AO6_110_Y, B => BUF_12_Y, Y => PP3_7_net); + HA1_S_1_inst : HA1 + port map(A => XOR2_27_Y, B => DataB(3), CO => S_1_net, S => + PP1_0_net); + DF1_103 : DF1 + port map(D => PP4_2_net, CLK => Clock, Q => DF1_103_Q); + XOR2_PP0_4_inst : XOR2 + port map(A => AO6_73_Y, B => BUF_26_Y, Y => PP0_4_net); + AO6_88 : AO6 + port map(A => BUF_0_Y, B => AND2A_1_Y, C => BUF_46_Y, D => + DataB(0), Y => AO6_88_Y); + XOR2_PP3_10_inst : XOR2 + port map(A => AO6_12_Y, B => BUF_3_Y, Y => PP3_10_net); + FA1_69 : FA1 + port map(A => FA1_70_CO, B => FA1_47_S, CI => FA1_52_S, + CO => FA1_69_CO, S => FA1_69_S); + XOR2_PP1_8_inst : XOR2 + port map(A => AO6_98_Y, B => BUF_18_Y, Y => PP1_8_net); + XOR2_PP7_4_inst : XOR2 + port map(A => AO6_7_Y, B => BUF_22_Y, Y => PP7_4_net); + BUF_34 : BUFF + port map(A => DataB(5), Y => BUF_34_Y); + HA1_2 : HA1 + port map(A => DF1_80_Q, B => DF1_54_Q, CO => HA1_2_CO, S => + HA1_2_S); + DF1_78 : DF1 + port map(D => PP1_6_net, CLK => Clock, Q => DF1_78_Q); + XOR2_PP3_9_inst : XOR2 + port map(A => AO6_86_Y, B => BUF_3_Y, Y => PP3_9_net); + XOR2_PP6_11_inst : XOR2 + port map(A => AO6_102_Y, B => BUF_6_Y, Y => PP6_11_net); + DF1_SumB_9_inst : DF1 + port map(D => FA1_23_S, CLK => Clock, Q => SumB_9_net); + AO6_64 : AO6 + port map(A => BUF_35_Y, B => AO16_5_Y, C => BUF_25_Y, D => + XOR2_8_Y, Y => AO6_64_Y); + XOR2_17 : XOR2 + port map(A => DataB(5), B => DataB(6), Y => XOR2_17_Y); + AO6_104 : AO6 + port map(A => BUF_38_Y, B => AO16_2_Y, C => BUF_9_Y, D => + XOR2_6_Y, Y => AO6_104_Y); + XOR2_PP0_15_inst : XOR2 + port map(A => AO6_88_Y, B => BUF_23_Y, Y => PP0_15_net); + ADD1_Mult_27_inst : ADD1 + port map(A => SumA_26_net, B => SumB_26_net, FCI => + ADD1_Mult_26_FCO, S => Mult(27), FCO => ADD1_Mult_27_FCO); + DF1_59 : DF1 + port map(D => PP4_12_net, CLK => Clock, Q => DF1_59_Q); + FA1_48 : FA1 + port map(A => FA1_56_CO, B => FA1_27_CO, CI => FA1_68_S, + CO => FA1_48_CO, S => FA1_48_S); + OR3_1 : OR3 + port map(A => GND_1_net, B => DataB(0), C => DataB(1), Y => + OR3_1_Y); + FA1_42 : FA1 + port map(A => DF1_27_Q, B => DF1_73_Q, CI => DF1_74_Q, + CO => FA1_42_CO, S => FA1_42_S); + DF1_SumB_1_inst : DF1 + port map(D => DF1_120_Q, CLK => Clock, Q => SumB_1_net); + XOR2_PP5_8_inst : XOR2 + port map(A => AO6_60_Y, B => BUF_47_Y, Y => PP5_8_net); + BUF_19 : BUFF + port map(A => DataA(8), Y => BUF_19_Y); + XOR2_PP6_7_inst : XOR2 + port map(A => AO6_40_Y, B => BUF_17_Y, Y => PP6_7_net); + AO6_106 : AO6 + port map(A => BUF_21_Y, B => AO16_10_Y, C => BUF_27_Y, D => + XOR2_21_Y, Y => AO6_106_Y); + FA1_88 : FA1 + port map(A => DF1_26_Q, B => DF1_65_Q, CI => HA1_5_CO, + CO => FA1_88_CO, S => FA1_88_S); + BUF_45 : BUFF + port map(A => DataA(5), Y => BUF_45_Y); + DF1_146 : DF1 + port map(D => PP7_7_net, CLK => Clock, Q => DF1_146_Q); + FA1_82 : FA1 + port map(A => DF1_148_Q, B => DF1_34_Q, CI => HA1_11_S, + CO => FA1_82_CO, S => FA1_82_S); + DF1_SumB_17_inst : DF1 + port map(D => FA1_4_S, CLK => Clock, Q => SumB_17_net); + XOR2_PP5_15_inst : XOR2 + port map(A => AO6_57_Y, B => BUF_41_Y, Y => PP5_15_net); + BUF_29 : BUFF + port map(A => DataA(0), Y => BUF_29_Y); + DF1_91 : DF1 + port map(D => PP5_4_net, CLK => Clock, Q => DF1_91_Q); + AO6_27 : AO6 + port map(A => BUF_39_Y, B => AO16_10_Y, C => BUF_45_Y, D => + XOR2_21_Y, Y => AO6_27_Y); + XOR2_PP1_5_inst : XOR2 + port map(A => AO6_35_Y, B => BUF_18_Y, Y => PP1_5_net); + XOR2_PP6_14_inst : XOR2 + port map(A => AO6_74_Y, B => BUF_6_Y, Y => PP6_14_net); + DF1_97 : DF1 + port map(D => PP0_8_net, CLK => Clock, Q => DF1_97_Q); + DF1_111 : DF1 + port map(D => PP0_3_net, CLK => Clock, Q => DF1_111_Q); + XOR2_PP1_3_inst : XOR2 + port map(A => AO6_66_Y, B => BUF_18_Y, Y => PP1_3_net); + XOR2_PP2_5_inst : XOR2 + port map(A => AO6_27_Y, B => BUF_34_Y, Y => PP2_5_net); + AO6_69 : AO6 + port map(A => BUF_31_Y, B => AO16_6_Y, C => BUF_40_Y, D => + XOR2_18_Y, Y => AO6_69_Y); + XOR2_PP2_7_inst : XOR2 + port map(A => AO6_80_Y, B => BUF_34_Y, Y => PP2_7_net); + XOR2_PP4_4_inst : XOR2 + port map(A => AO6_83_Y, B => BUF_37_Y, Y => PP4_4_net); + AO6_28 : AO6 + port map(A => BUF_13_Y, B => AO16_4_Y, C => BUF_44_Y, D => + XOR2_29_Y, Y => AO6_28_Y); + BUF_46 : BUFF + port map(A => DataA(15), Y => BUF_46_Y); + FA1_91 : FA1 + port map(A => FA1_8_CO, B => HA1_10_CO, CI => FA1_65_S, + CO => FA1_91_CO, S => FA1_91_S); + AO16_3 : AO16 + port map(A => DataB(1), B => DataB(2), C => BUF_11_Y, Y => + AO16_3_Y); + HA1_S_2_inst : HA1 + port map(A => XOR2_9_Y, B => DataB(5), CO => S_2_net, S => + PP2_0_net); + XOR2_PP2_9_inst : XOR2 + port map(A => AO6_116_Y, B => BUF_30_Y, Y => PP2_9_net); + FA1_28 : FA1 + port map(A => DF1_49_Q, B => DF1_102_Q, CI => DF1_103_Q, + CO => FA1_28_CO, S => FA1_28_S); + DF1_118 : DF1 + port map(D => PP5_16_net, CLK => Clock, Q => DF1_118_Q); + FA1_22 : FA1 + port map(A => DF1_9_Q, B => DF1_119_Q, CI => FA1_3_CO, + CO => FA1_22_CO, S => FA1_22_S); + XOR2_PP1_12_inst : XOR2 + port map(A => AO6_33_Y, B => BUF_11_Y, Y => PP1_12_net); + HA1_S_3_inst : HA1 + port map(A => XOR2_14_Y, B => DataB(7), CO => S_3_net, S => + PP3_0_net); + AO6_37 : AO6 + port map(A => BUF_15_Y, B => AO16_0_Y, C => BUF_1_Y, D => + XOR2_5_Y, Y => AO6_37_Y); + DF1_SumB_26_inst : DF1 + port map(D => FA1_91_S, CLK => Clock, Q => SumB_26_net); + DF1_Mult_0_inst : DF1 + port map(D => DF1_117_Q, CLK => Clock, Q => Mult(0)); + DF1_SumA_0_inst : DF1 + port map(D => DF1_114_Q, CLK => Clock, Q => SumA_0_net); + AOI1_E_6_inst : AOI1 + port map(A => XOR2_7_Y, B => OR3_0_Y, C => AND3_3_Y, Y => + E_6_net); + AO6_38 : AO6 + port map(A => BUF_5_Y, B => AND2A_0_Y, C => BUF_14_Y, D => + DataB(0), Y => AO6_38_Y); + BUF_14 : BUFF + port map(A => DataA(8), Y => BUF_14_Y); + DF1_SumA_2_inst : DF1 + port map(D => DF1_21_Q, CLK => Clock, Q => SumA_2_net); + DF1_43 : DF1 + port map(D => PP3_8_net, CLK => Clock, Q => DF1_43_Q); + AO16_5 : AO16 + port map(A => DataB(11), B => DataB(12), C => BUF_17_Y, + Y => AO16_5_Y); + BUF_24 : BUFF + port map(A => DataA(12), Y => BUF_24_Y); + DF1_SumB_28_inst : DF1 + port map(D => FA1_88_S, CLK => Clock, Q => SumB_28_net); + DF1_112 : DF1 + port map(D => PP1_9_net, CLK => Clock, Q => DF1_112_Q); + FA1_38 : FA1 + port map(A => HA1_0_S, B => DF1_3_Q, CI => FA1_63_S, CO => + FA1_38_CO, S => FA1_38_S); + DF1_40 : DF1 + port map(D => S_6_net, CLK => Clock, Q => DF1_40_Q); + FA1_32 : FA1 + port map(A => HA1_15_S, B => DF1_92_Q, CI => FA1_30_CO, + CO => FA1_32_CO, S => FA1_32_S); + AO6_71 : AO6 + port map(A => BUF_2_Y, B => AO16_1_Y, C => BUF_36_Y, D => + XOR2_10_Y, Y => AO6_71_Y); + AO16_0 : AO16 + port map(A => DataB(7), B => DataB(8), C => BUF_33_Y, Y => + AO16_0_Y); + AO1_1 : AO1 + port map(A => XOR2_15_Y, B => OR3_5_Y, C => AND3_4_Y, Y => + AO1_1_Y); + BUF_6 : BUFF + port map(A => DataB(13), Y => BUF_6_Y); + XOR2_PP4_11_inst : XOR2 + port map(A => AO6_87_Y, B => BUF_33_Y, Y => PP4_11_net); + DF1_SumA_24_inst : DF1 + port map(D => FA1_78_CO, CLK => Clock, Q => SumA_24_net); + XOR2_PP7_1_inst : XOR2 + port map(A => AO6_14_Y, B => BUF_22_Y, Y => PP7_1_net); + DF1_99 : DF1 + port map(D => PP4_15_net, CLK => Clock, Q => DF1_99_Q); + BUF_3 : BUFF + port map(A => DataB(7), Y => BUF_3_Y); + DF1_22 : DF1 + port map(D => PP5_11_net, CLK => Clock, Q => DF1_22_Q); + DF1_45 : DF1 + port map(D => PP0_14_net, CLK => Clock, Q => DF1_45_Q); + DF1_8 : DF1 + port map(D => PP1_4_net, CLK => Clock, Q => DF1_8_Q); + ADD1_Mult_12_inst : ADD1 + port map(A => SumA_11_net, B => SumB_11_net, FCI => + ADD1_Mult_11_FCO, S => Mult(12), FCO => ADD1_Mult_12_FCO); + MX2_2 : MX2 + port map(A => BUF_23_Y, B => XOR2_26_Y, S => DataB(0), Y => + MX2_2_Y); + XOR2_PP4_9_inst : XOR2 + port map(A => AO6_49_Y, B => BUF_33_Y, Y => PP4_9_net); + XOR2_PP2_13_inst : XOR2 + port map(A => AO6_5_Y, B => BUF_30_Y, Y => PP2_13_net); + AO6_81 : AO6 + port map(A => BUF_43_Y, B => AO16_9_Y, C => BUF_42_Y, D => + XOR2_23_Y, Y => AO6_81_Y); + DF1_76 : DF1 + port map(D => PP2_15_net, CLK => Clock, Q => DF1_76_Q); + AO6_100 : AO6 + port map(A => BUF_42_Y, B => AO16_7_Y, C => BUF_24_Y, D => + XOR2_28_Y, Y => AO6_100_Y); + FA1_68 : FA1 + port map(A => FA1_55_CO, B => DF1_69_Q, CI => FA1_3_S, + CO => FA1_68_CO, S => FA1_68_S); + FA1_62 : FA1 + port map(A => DF1_132_Q, B => DF1_81_Q, CI => HA1_13_S, + CO => FA1_62_CO, S => FA1_62_S); + AO16_9 : AO16 + port map(A => DataB(3), B => DataB(4), C => BUF_30_Y, Y => + AO16_9_Y); + XOR2_11 : XOR2 + port map(A => BUF_40_Y, B => DataB(15), Y => XOR2_11_Y); + XOR2_PP4_14_inst : XOR2 + port map(A => AO6_94_Y, B => BUF_33_Y, Y => PP4_14_net); + AO16_12 : AO16 + port map(A => DataB(13), B => DataB(14), C => BUF_22_Y, + Y => AO16_12_Y); + AO6_101 : AO6 + port map(A => BUF_9_Y, B => AO16_6_Y, C => BUF_15_Y, D => + XOR2_18_Y, Y => AO6_101_Y); + XOR2_PP3_3_inst : XOR2 + port map(A => AO6_18_Y, B => BUF_12_Y, Y => PP3_3_net); + ADD1_Mult_24_inst : ADD1 + port map(A => SumA_23_net, B => SumB_23_net, FCI => + ADD1_Mult_23_FCO, S => Mult(24), FCO => ADD1_Mult_24_FCO); + DF1_129 : DF1 + port map(D => PP5_14_net, CLK => Clock, Q => DF1_129_Q); + HA1_0 : HA1 + port map(A => DF1_138_Q, B => DF1_98_Q, CO => HA1_0_CO, + S => HA1_0_S); + XOR2_PP3_8_inst : XOR2 + port map(A => AO6_70_Y, B => BUF_12_Y, Y => PP3_8_net); + AOI1_E_1_inst : AOI1 + port map(A => XOR2_13_Y, B => OR3_2_Y, C => AND3_6_Y, Y => + E_1_net); + XOR2_PP0_3_inst : XOR2 + port map(A => AO6_4_Y, B => BUF_26_Y, Y => PP0_3_net); + AO6_66 : AO6 + port map(A => BUF_27_Y, B => AO16_13_Y, C => BUF_28_Y, D => + XOR2_25_Y, Y => AO6_66_Y); + DF1_SumA_11_inst : DF1 + port map(D => FA1_72_CO, CLK => Clock, Q => SumA_11_net); + DF1_62 : DF1 + port map(D => PP5_6_net, CLK => Clock, Q => DF1_62_Q); + AO16_11 : AO16 + port map(A => DataB(5), B => DataB(6), C => BUF_12_Y, Y => + AO16_11_Y); + XOR2_5 : XOR2 + port map(A => DataB(7), B => DataB(8), Y => XOR2_5_Y); + HA1_4 : HA1 + port map(A => DF1_47_Q, B => VCC_1_net, CO => HA1_4_CO, + S => HA1_4_S); + XOR2_PP4_6_inst : XOR2 + port map(A => AO6_89_Y, B => BUF_37_Y, Y => PP4_6_net); + XOR2_PP0_8_inst : XOR2 + port map(A => AO6_38_Y, B => BUF_26_Y, Y => PP0_8_net); + ADD1_Mult_29_inst : ADD1 + port map(A => SumA_28_net, B => SumB_28_net, FCI => + ADD1_Mult_28_FCO, S => Mult(29), FCO => ADD1_Mult_29_FCO); + AO6_93 : AO6 + port map(A => BUF_1_Y, B => AO16_8_Y, C => BUF_32_Y, D => + XOR2_3_Y, Y => AO6_93_Y); + FA1_59 : FA1 + port map(A => FA1_0_CO, B => FA1_13_S, CI => FA1_66_S, + CO => FA1_59_CO, S => FA1_59_S); + ADD1_Mult_21_inst : ADD1 + port map(A => SumA_20_net, B => SumB_20_net, FCI => + ADD1_Mult_20_FCO, S => Mult(21), FCO => ADD1_Mult_21_FCO); + AO6_21 : AO6 + port map(A => BUF_1_Y, B => AO16_6_Y, C => BUF_32_Y, D => + XOR2_18_Y, Y => AO6_21_Y); + XOR2_PP0_7_inst : XOR2 + port map(A => AO6_63_Y, B => BUF_26_Y, Y => PP0_7_net); + ADD1_Mult_15_inst : ADD1 + port map(A => SumA_14_net, B => SumB_14_net, FCI => + ADD1_Mult_14_FCO, S => Mult(15), FCO => ADD1_Mult_15_FCO); + DF1_143 : DF1 + port map(D => PP0_4_net, CLK => Clock, Q => DF1_143_Q); + AO6_92 : AO6 + port map(A => BUF_43_Y, B => AND2A_1_Y, C => BUF_42_Y, D => + DataB(0), Y => AO6_92_Y); + FA1_71 : FA1 + port map(A => DF1_147_Q, B => DF1_45_Q, CI => DF1_46_Q, + CO => FA1_71_CO, S => FA1_71_S); + FA1_93 : FA1 + port map(A => FA1_66_CO, B => FA1_33_S, CI => FA1_15_S, + CO => FA1_93_CO, S => FA1_93_S); + XOR2_PP7_13_inst : XOR2 + port map(A => AO6_21_Y, B => BUF_20_Y, Y => PP7_13_net); + AO6_109 : AO6 + port map(A => BUF_36_Y, B => AO16_12_Y, C => BUF_13_Y, D => + XOR2_2_Y, Y => AO6_109_Y); + AO16_6 : AO16 + port map(A => DataB(13), B => DataB(14), C => BUF_20_Y, + Y => AO16_6_Y); + BUF_1 : BUFF + port map(A => DataA(12), Y => BUF_1_Y); + FA1_77 : FA1 + port map(A => FA1_42_CO, B => HA1_6_S, CI => FA1_43_S, + CO => FA1_77_CO, S => FA1_77_S); + BUF_2 : BUFF + port map(A => DataA(4), Y => BUF_2_Y); + XOR2_PP3_13_inst : XOR2 + port map(A => AO6_59_Y, B => BUF_3_Y, Y => PP3_13_net); + MX2_3 : MX2 + port map(A => BUF_41_Y, B => XOR2_19_Y, S => XOR2_6_Y, Y => + MX2_3_Y); + DF1_137 : DF1 + port map(D => PP0_13_net, CLK => Clock, Q => DF1_137_Q); + ADD1_Mult_3_inst : ADD1 + port map(A => SumA_2_net, B => SumB_2_net, FCI => + ADD1_Mult_2_FCO, S => Mult(3), FCO => ADD1_Mult_3_FCO); + XOR2_PP7_6_inst : XOR2 + port map(A => AO6_109_Y, B => BUF_22_Y, Y => PP7_6_net); + AO6_31 : AO6 + port map(A => BUF_13_Y, B => AO16_12_Y, C => BUF_44_Y, D => + XOR2_2_Y, Y => AO6_31_Y); + AO6_43 : AO6 + port map(A => BUF_28_Y, B => AO16_11_Y, C => BUF_39_Y, D => + XOR2_17_Y, Y => AO6_43_Y); + DF1_71 : DF1 + port map(D => E_5_net, CLK => Clock, Q => DF1_71_Q); + ADD1_Mult_1_inst : ADD1 + port map(A => SumA_0_net, B => SumB_0_net, FCI => + FCINIT_BUFF_0_FCO, S => Mult(1), FCO => ADD1_Mult_1_FCO); + AO1_4 : AO1 + port map(A => XOR2_19_Y, B => OR3_3_Y, C => AND3_5_Y, Y => + AO1_4_Y); + DF1_77 : DF1 + port map(D => PP2_3_net, CLK => Clock, Q => DF1_77_Q); + DF1_107 : DF1 + port map(D => PP3_3_net, CLK => Clock, Q => DF1_107_Q); + DF1_124 : DF1 + port map(D => PP0_5_net, CLK => Clock, Q => DF1_124_Q); + AND2_2 : AND2 + port map(A => XOR2_25_Y, B => BUF_29_Y, Y => AND2_2_Y); + AO6_10 : AO6 + port map(A => BUF_8_Y, B => AO16_1_Y, C => BUF_35_Y, D => + XOR2_10_Y, Y => AO6_10_Y); + DF1_12 : DF1 + port map(D => PP6_14_net, CLK => Clock, Q => DF1_12_Q); + ADD1_Mult_17_inst : ADD1 + port map(A => SumA_16_net, B => SumB_16_net, FCI => + ADD1_Mult_16_FCO, S => Mult(17), FCO => ADD1_Mult_17_FCO); + XOR2_PP6_15_inst : XOR2 + port map(A => AO6_91_Y, B => BUF_6_Y, Y => PP6_15_net); + AO6_42 : AO6 + port map(A => BUF_15_Y, B => AO16_2_Y, C => BUF_1_Y, D => + XOR2_6_Y, Y => AO6_42_Y); + AND3_2 : AND3 + port map(A => DataB(3), B => DataB(4), C => DataB(5), Y => + AND3_2_Y); + DF1_SumB_12_inst : DF1 + port map(D => FA1_73_S, CLK => Clock, Q => SumB_12_net); + XOR2_PP7_7_inst : XOR2 + port map(A => AO6_31_Y, B => BUF_22_Y, Y => PP7_7_net); + DF1_32 : DF1 + port map(D => PP6_15_net, CLK => Clock, Q => DF1_32_Q); + DF1_130 : DF1 + port map(D => PP1_2_net, CLK => Clock, Q => DF1_130_Q); + HA1_9 : HA1 + port map(A => DF1_93_Q, B => DF1_83_Q, CO => HA1_9_CO, S => + HA1_9_S); + FA1_11 : FA1 + port map(A => FA1_85_CO, B => HA1_1_S, CI => FA1_67_S, + CO => FA1_11_CO, S => FA1_11_S); + XOR2_12 : XOR2 + port map(A => AND2_7_Y, B => BUF_22_Y, Y => XOR2_12_Y); + FA1_17 : FA1 + port map(A => FA1_36_CO, B => FA1_61_CO, CI => FA1_11_S, + CO => FA1_17_CO, S => FA1_17_S); + AO16_2 : AO16 + port map(A => DataB(9), B => DataB(10), C => BUF_41_Y, Y => + AO16_2_Y); + DF1_83 : DF1 + port map(D => PP6_5_net, CLK => Clock, Q => DF1_83_Q); + DF1_100 : DF1 + port map(D => PP4_14_net, CLK => Clock, Q => DF1_100_Q); + AO6_53 : AO6 + port map(A => BUF_1_Y, B => AO16_0_Y, C => BUF_32_Y, D => + XOR2_5_Y, Y => AO6_53_Y); + OR3_7 : OR3 + port map(A => DataB(7), B => DataB(8), C => DataB(9), Y => + OR3_7_Y); + AO6_118 : AO6 + port map(A => BUF_35_Y, B => AO16_12_Y, C => BUF_25_Y, D => + XOR2_2_Y, Y => AO6_118_Y); + HA1_12 : HA1 + port map(A => DF1_152_Q, B => DF1_109_Q, CO => HA1_12_CO, + S => HA1_12_S); + DF1_150 : DF1 + port map(D => PP5_3_net, CLK => Clock, Q => DF1_150_Q); + BUF_37 : BUFF + port map(A => DataB(9), Y => BUF_37_Y); + AO6_15 : AO6 + port map(A => BUF_0_Y, B => AO16_7_Y, C => BUF_46_Y, D => + XOR2_28_Y, Y => AO6_15_Y); + DF1_80 : DF1 + port map(D => PP7_4_net, CLK => Clock, Q => DF1_80_Q); + XOR2_PP7_5_inst : XOR2 + port map(A => AO6_111_Y, B => BUF_22_Y, Y => PP7_5_net); + XOR2_16 : XOR2 + port map(A => AND2_0_Y, B => BUF_26_Y, Y => XOR2_16_Y); + FA1_41 : FA1 + port map(A => DF1_66_Q, B => DF1_15_Q, CI => DF1_121_Q, + CO => FA1_41_CO, S => FA1_41_S); + FA1_96 : FA1 + port map(A => FA1_54_CO, B => FA1_37_S, CI => FA1_25_S, + CO => FA1_96_CO, S => FA1_96_S); + DF1_135 : DF1 + port map(D => PP1_7_net, CLK => Clock, Q => DF1_135_Q); + AO6_52 : AO6 + port map(A => BUF_25_Y, B => AO16_4_Y, C => BUF_4_Y, D => + XOR2_29_Y, Y => AO6_52_Y); + XOR2_PP4_2_inst : XOR2 + port map(A => AO6_58_Y, B => BUF_37_Y, Y => PP4_2_net); + DF1_SumB_21_inst : DF1 + port map(D => FA1_74_S, CLK => Clock, Q => SumB_21_net); + XOR2_PP2_12_inst : XOR2 + port map(A => AO6_17_Y, B => BUF_30_Y, Y => PP2_12_net); + DF1_85 : DF1 + port map(D => PP2_8_net, CLK => Clock, Q => DF1_85_Q); + AO6_97 : AO6 + port map(A => BUF_8_Y, B => AO16_5_Y, C => BUF_35_Y, D => + XOR2_8_Y, Y => AO6_97_Y); + FA1_81 : FA1 + port map(A => FA1_75_CO, B => HA1_7_S, CI => FA1_31_S, + CO => FA1_81_CO, S => FA1_81_S); + FA1_47 : FA1 + port map(A => DF1_68_Q, B => DF1_75_Q, CI => DF1_56_Q, + CO => FA1_47_CO, S => FA1_47_S); + FA1_94 : FA1 + port map(A => DF1_61_Q, B => DF1_140_Q, CI => DF1_85_Q, + CO => FA1_94_CO, S => FA1_94_S); + DF1_2 : DF1 + port map(D => PP2_0_net, CLK => Clock, Q => DF1_2_Q); + DF1_79 : DF1 + port map(D => PP1_5_net, CLK => Clock, Q => DF1_79_Q); + FA1_87 : FA1 + port map(A => FA1_63_CO, B => DF1_1_Q, CI => FA1_71_S, + CO => FA1_87_CO, S => FA1_87_S); + DF1_SumA_14_inst : DF1 + port map(D => FA1_96_CO, CLK => Clock, Q => SumA_14_net); + DF1_105 : DF1 + port map(D => PP6_11_net, CLK => Clock, Q => DF1_105_Q); + DF1_44 : DF1 + port map(D => PP5_9_net, CLK => Clock, Q => DF1_44_Q); + DF1_52 : DF1 + port map(D => PP7_2_net, CLK => Clock, Q => DF1_52_Q); + BUF_40 : BUFF + port map(A => DataA(15), Y => BUF_40_Y); + DF1_116 : DF1 + port map(D => E_7_net, CLK => Clock, Q => DF1_116_Q); + AO6_98 : AO6 + port map(A => BUF_5_Y, B => AO16_13_Y, C => BUF_14_Y, D => + XOR2_25_Y, Y => AO6_98_Y); + DF1_SumA_27_inst : DF1 + port map(D => FA1_91_CO, CLK => Clock, Q => SumA_27_net); + FA1_58 : FA1 + port map(A => FA1_29_CO, B => HA1_15_CO, CI => FA1_14_S, + CO => FA1_58_CO, S => FA1_58_S); + FA1_52 : FA1 + port map(A => HA1_14_CO, B => DF1_7_Q, CI => FA1_50_CO, + CO => FA1_52_CO, S => FA1_52_S); + MX2_PP2_16_inst : MX2 + port map(A => MX2_0_Y, B => AO1_2_Y, S => AO16_9_Y, Y => + PP2_16_net); + XOR2_PP0_10_inst : XOR2 + port map(A => AO6_48_Y, B => BUF_23_Y, Y => PP0_10_net); + AO6_1 : AO6 + port map(A => BUF_14_Y, B => AO16_3_Y, C => BUF_10_Y, D => + XOR2_4_Y, Y => AO6_1_Y); + AO6_113 : AO6 + port map(A => BUF_24_Y, B => AO16_3_Y, C => BUF_16_Y, D => + XOR2_4_Y, Y => AO6_113_Y); + XOR2_PP6_2_inst : XOR2 + port map(A => AO6_64_Y, B => BUF_17_Y, Y => PP6_2_net); + FA1_21 : FA1 + port map(A => DF1_35_Q, B => DF1_108_Q, CI => DF1_134_Q, + CO => FA1_21_CO, S => FA1_21_S); + BUF_42 : BUFF + port map(A => DataA(11), Y => BUF_42_Y); + FA1_73 : FA1 + port map(A => FA1_7_CO, B => FA1_9_S, CI => FA1_54_S, CO => + FA1_73_CO, S => FA1_73_S); + AND2_5 : AND2 + port map(A => XOR2_17_Y, B => BUF_29_Y, Y => AND2_5_Y); + XOR2_28 : XOR2 + port map(A => DataB(5), B => DataB(6), Y => XOR2_28_Y); + FA1_27 : FA1 + port map(A => FA1_67_CO, B => HA1_1_CO, CI => FA1_86_S, + CO => FA1_27_CO, S => FA1_27_S); + XOR2_PP5_10_inst : XOR2 + port map(A => AO6_104_Y, B => BUF_41_Y, Y => PP5_10_net); + DF1_SumB_10_inst : DF1 + port map(D => FA1_72_S, CLK => Clock, Q => SumB_10_net); + AO6_47 : AO6 + port map(A => BUF_5_Y, B => AO16_10_Y, C => BUF_14_Y, D => + XOR2_21_Y, Y => AO6_47_Y); + DF1_SumB_3_inst : DF1 + port map(D => FA1_84_S, CLK => Clock, Q => SumB_3_net); + DF1_6 : DF1 + port map(D => PP4_1_net, CLK => Clock, Q => DF1_6_Q); + XOR2_PP4_15_inst : XOR2 + port map(A => AO6_75_Y, B => BUF_33_Y, Y => PP4_15_net); + XOR2_PP1_11_inst : XOR2 + port map(A => AO6_84_Y, B => BUF_11_Y, Y => PP1_11_net); + BUF_9 : BUFF + port map(A => DataA(10), Y => BUF_9_Y); + XOR2_1 : XOR2 + port map(A => AND2_3_Y, B => BUF_17_Y, Y => XOR2_1_Y); + DF1_SumB_15_inst : DF1 + port map(D => FA1_59_S, CLK => Clock, Q => SumB_15_net); + XOR2_PP7_12_inst : XOR2 + port map(A => AO6_117_Y, B => BUF_20_Y, Y => PP7_12_net); + AO6_48 : AO6 + port map(A => BUF_10_Y, B => AND2A_1_Y, C => BUF_43_Y, D => + DataB(0), Y => AO6_48_Y); + XOR2_PP1_7_inst : XOR2 + port map(A => AO6_68_Y, B => BUF_18_Y, Y => PP1_7_net); + BUF_17 : BUFF + port map(A => DataB(13), Y => BUF_17_Y); + XOR2_8 : XOR2 + port map(A => DataB(11), B => DataB(12), Y => XOR2_8_Y); + BUF_27 : BUFF + port map(A => DataA(2), Y => BUF_27_Y); + XOR2_PP3_12_inst : XOR2 + port map(A => AO6_100_Y, B => BUF_3_Y, Y => PP3_12_net); + FA1_31 : FA1 + port map(A => DF1_51_Q, B => DF1_77_Q, CI => DF1_142_Q, + CO => FA1_31_CO, S => FA1_31_S); + ADD1_Mult_14_inst : ADD1 + port map(A => SumA_13_net, B => SumB_13_net, FCI => + ADD1_Mult_13_FCO, S => Mult(14), FCO => ADD1_Mult_14_FCO); + DF1_48 : DF1 + port map(D => PP3_15_net, CLK => Clock, Q => DF1_48_Q); + ADD1_Mult_2_inst : ADD1 + port map(A => SumA_1_net, B => SumB_1_net, FCI => + ADD1_Mult_1_FCO, S => Mult(2), FCO => ADD1_Mult_2_FCO); + XOR2_PP5_5_inst : XOR2 + port map(A => AO6_50_Y, B => BUF_47_Y, Y => PP5_5_net); + FA1_37 : FA1 + port map(A => HA1_0_CO, B => DF1_86_Q, CI => FA1_26_S, + CO => FA1_37_CO, S => FA1_37_S); + XOR2_PP1_14_inst : XOR2 + port map(A => AO6_78_Y, B => BUF_11_Y, Y => PP1_14_net); + AO6_57 : AO6 + port map(A => BUF_31_Y, B => AO16_2_Y, C => BUF_40_Y, D => + XOR2_6_Y, Y => AO6_57_Y); + FA1_13 : FA1 + port map(A => FA1_24_CO, B => HA1_12_CO, CI => FA1_90_S, + CO => FA1_13_CO, S => FA1_13_S); + ADD1_Mult_19_inst : ADD1 + port map(A => SumA_18_net, B => SumB_18_net, FCI => + ADD1_Mult_18_FCO, S => Mult(19), FCO => ADD1_Mult_19_FCO); + AO6_14 : AO6 + port map(A => BUF_8_Y, B => AO16_12_Y, C => BUF_35_Y, D => + XOR2_2_Y, Y => AO6_14_Y); + AO1_6 : AO1 + port map(A => XOR2_7_Y, B => OR3_0_Y, C => AND3_3_Y, Y => + AO1_6_Y); + DF1_SumA_4_inst : DF1 + port map(D => FA1_84_CO, CLK => Clock, Q => SumA_4_net); + XOR2_PP4_5_inst : XOR2 + port map(A => AO6_71_Y, B => BUF_37_Y, Y => PP4_5_net); + XOR2_PP3_2_inst : XOR2 + port map(A => AO6_108_Y, B => BUF_12_Y, Y => PP3_2_net); + ADD1_Mult_11_inst : ADD1 + port map(A => SumA_10_net, B => SumB_10_net, FCI => + ADD1_Mult_10_FCO, S => Mult(11), FCO => ADD1_Mult_11_FCO); + DF1_92 : DF1 + port map(D => S_4_net, CLK => Clock, Q => DF1_92_Q); + FA1_61 : FA1 + port map(A => FA1_41_CO, B => HA1_2_S, CI => FA1_85_S, + CO => FA1_61_CO, S => FA1_61_S); + XOR2_PP5_7_inst : XOR2 + port map(A => AO6_28_Y, B => BUF_47_Y, Y => PP5_7_net); + AND3_5 : AND3 + port map(A => DataB(9), B => DataB(10), C => DataB(11), + Y => AND3_5_Y); + FA1_95 : FA1 + port map(A => FA1_25_CO, B => FA1_34_S, CI => FA1_0_S, + CO => FA1_95_CO, S => FA1_95_S); + AO6_58 : AO6 + port map(A => BUF_35_Y, B => AO16_1_Y, C => BUF_25_Y, D => + XOR2_10_Y, Y => AO6_58_Y); + DF1_121 : DF1 + port map(D => PP4_9_net, CLK => Clock, Q => DF1_121_Q); + FA1_67 : FA1 + port map(A => DF1_76_Q, B => DF1_110_Q, CI => DF1_131_Q, + CO => FA1_67_CO, S => FA1_67_S); + DF1_1 : DF1 + port map(D => PP7_0_net, CLK => Clock, Q => DF1_1_Q); + AO6_70 : AO6 + port map(A => BUF_5_Y, B => AO16_11_Y, C => BUF_14_Y, D => + XOR2_17_Y, Y => AO6_70_Y); + XOR2_PP7_2_inst : XOR2 + port map(A => AO6_118_Y, B => BUF_22_Y, Y => PP7_2_net); + BUF_41 : BUFF + port map(A => DataB(11), Y => BUF_41_Y); + FA1_43 : FA1 + port map(A => DF1_115_Q, B => DF1_23_Q, CI => DF1_24_Q, + CO => FA1_43_CO, S => FA1_43_S); + FA1_76 : FA1 + port map(A => FA1_57_CO, B => FA1_5_S, CI => FA1_7_S, CO => + FA1_76_CO, S => FA1_76_S); + OR3_5 : OR3 + port map(A => DataB(5), B => DataB(6), C => DataB(7), Y => + OR3_5_Y); + DF1_147 : DF1 + port map(D => PP2_10_net, CLK => Clock, Q => DF1_147_Q); + XOR2_PP1_4_inst : XOR2 + port map(A => AO6_46_Y, B => BUF_18_Y, Y => PP1_4_net); + AO6_19 : AO6 + port map(A => BUF_27_Y, B => AO16_10_Y, C => BUF_28_Y, D => + XOR2_21_Y, Y => AO6_19_Y); + DF1_3 : DF1 + port map(D => PP6_1_net, CLK => Clock, Q => DF1_3_Q); + DF1_128 : DF1 + port map(D => E_1_net, CLK => Clock, Q => DF1_128_Q); + FA1_83 : FA1 + port map(A => DF1_13_Q, B => DF1_95_Q, CI => DF1_139_Q, + CO => FA1_83_CO, S => FA1_83_S); + DF1_SumB_24_inst : DF1 + port map(D => FA1_69_S, CLK => Clock, Q => SumB_24_net); + FA1_74 : FA1 + port map(A => FA1_48_CO, B => FA1_18_S, CI => FA1_92_S, + CO => FA1_74_CO, S => FA1_74_S); + HA1_S_0_inst : HA1 + port map(A => XOR2_16_Y, B => DataB(1), CO => S_0_net, S => + PP0_0_net); + AO6_80 : AO6 + port map(A => BUF_7_Y, B => AO16_10_Y, C => BUF_5_Y, D => + XOR2_21_Y, Y => AO6_80_Y); + ADD1_Mult_31_inst : ADD1 + port map(A => SumA_30_net, B => SumB_30_net, FCI => + ADD1_Mult_30_FCO, S => Mult(31), FCO => ADD1_Mult_31_FCO); + AND3_3 : AND3 + port map(A => DataB(11), B => DataB(12), C => DataB(13), + Y => AND3_3_Y); + DF1_23 : DF1 + port map(D => PP0_16_net, CLK => Clock, Q => DF1_23_Q); + AO6_91 : AO6 + port map(A => BUF_31_Y, B => AO16_8_Y, C => BUF_40_Y, D => + XOR2_3_Y, Y => AO6_91_Y); + AO6_112 : AO6 + port map(A => BUF_25_Y, B => AO16_1_Y, C => BUF_4_Y, D => + XOR2_10_Y, Y => AO6_112_Y); + AO16_10 : AO16 + port map(A => DataB(3), B => DataB(4), C => BUF_34_Y, Y => + AO16_10_Y); + ADD1_Mult_8_inst : ADD1 + port map(A => SumA_7_net, B => SumB_7_net, FCI => + ADD1_Mult_7_FCO, S => Mult(8), FCO => ADD1_Mult_8_FCO); + AO6_117 : AO6 + port map(A => BUF_15_Y, B => AO16_6_Y, C => BUF_1_Y, D => + XOR2_18_Y, Y => AO6_117_Y); + AOI1_E_3_inst : AOI1 + port map(A => XOR2_15_Y, B => OR3_5_Y, C => AND3_4_Y, Y => + E_3_net); + DF1_20 : DF1 + port map(D => PP1_8_net, CLK => Clock, Q => DF1_20_Q); + AO6_75 : AO6 + port map(A => BUF_31_Y, B => AO16_0_Y, C => BUF_40_Y, D => + XOR2_5_Y, Y => AO6_75_Y); + AO6_63 : AO6 + port map(A => BUF_7_Y, B => AND2A_0_Y, C => BUF_5_Y, D => + DataB(0), Y => AO6_63_Y); + DF1_140 : DF1 + port map(D => PP0_12_net, CLK => Clock, Q => DF1_140_Q); + FA1_23 : FA1 + port map(A => FA1_32_CO, B => FA1_28_S, CI => FA1_58_S, + CO => FA1_23_CO, S => FA1_23_S); + MX2_PP4_16_inst : MX2 + port map(A => MX2_6_Y, B => AO1_0_Y, S => AO16_0_Y, Y => + PP4_16_net); + ADD1_Mult_20_inst : ADD1 + port map(A => SumA_19_net, B => SumB_19_net, FCI => + ADD1_Mult_19_FCO, S => Mult(20), FCO => ADD1_Mult_20_FCO); + DF1_122 : DF1 + port map(D => PP3_9_net, CLK => Clock, Q => DF1_122_Q); + DF1_25 : DF1 + port map(D => PP0_2_net, CLK => Clock, Q => DF1_25_Q); + AO1_5 : AO1 + port map(A => XOR2_13_Y, B => OR3_2_Y, C => AND3_6_Y, Y => + AO1_5_Y); + DF1_SumB_19_inst : DF1 + port map(D => FA1_2_S, CLK => Clock, Q => SumB_19_net); + DF1_113 : DF1 + port map(D => PP6_10_net, CLK => Clock, Q => DF1_113_Q); + DF1_SumA_5_inst : DF1 + port map(D => FA1_82_CO, CLK => Clock, Q => SumA_5_net); + DF1_84 : DF1 + port map(D => PP2_9_net, CLK => Clock, Q => DF1_84_Q); + FA1_16 : FA1 + port map(A => FA1_92_CO, B => FA1_21_S, CI => FA1_45_S, + CO => FA1_16_CO, S => FA1_16_S); + XOR2_PP2_3_inst : XOR2 + port map(A => AO6_19_Y, B => BUF_34_Y, Y => PP2_3_net); + ADD1_Mult_26_inst : ADD1 + port map(A => SumA_25_net, B => SumB_25_net, FCI => + ADD1_Mult_25_FCO, S => Mult(26), FCO => ADD1_Mult_26_FCO); + DF1_139 : DF1 + port map(D => PP5_7_net, CLK => Clock, Q => DF1_139_Q); + AO6_85 : AO6 + port map(A => BUF_13_Y, B => AO16_1_Y, C => BUF_44_Y, D => + XOR2_10_Y, Y => AO6_85_Y); + AOI1_E_5_inst : AOI1 + port map(A => XOR2_19_Y, B => OR3_3_Y, C => AND3_5_Y, Y => + E_5_net); + AND3_6 : AND3 + port map(A => DataB(1), B => DataB(2), C => DataB(3), Y => + AND3_6_Y); + MX2_5 : MX2 + port map(A => BUF_6_Y, B => XOR2_7_Y, S => XOR2_3_Y, Y => + MX2_5_Y); + AO6_62 : AO6 + port map(A => BUF_39_Y, B => AO16_11_Y, C => BUF_45_Y, D => + XOR2_17_Y, Y => AO6_62_Y); + DF1_5 : DF1 + port map(D => PP4_16_net, CLK => Clock, Q => DF1_5_Q); + FA1_14 : FA1 + port map(A => DF1_144_Q, B => DF1_20_Q, CI => DF1_41_Q, + CO => FA1_14_CO, S => FA1_14_S); + DF1_63 : DF1 + port map(D => PP0_11_net, CLK => Clock, Q => DF1_63_Q); + AO6_41 : AO6 + port map(A => BUF_14_Y, B => AND2A_1_Y, C => BUF_10_Y, D => + DataB(0), Y => AO6_41_Y); + AO6_20 : AO6 + port map(A => BUF_38_Y, B => AO16_0_Y, C => BUF_9_Y, D => + XOR2_5_Y, Y => AO6_20_Y); + DF1_109 : DF1 + port map(D => PP6_3_net, CLK => Clock, Q => DF1_109_Q); + BUF_35 : BUFF + port map(A => DataA(1), Y => BUF_35_Y); + DF1_46 : DF1 + port map(D => PP4_6_net, CLK => Clock, Q => DF1_46_Q); +end DEF_ARCH; diff --git a/lib/lpp/dsp/lpp_fft_rtax/actram.vhd b/lib/lpp/dsp/lpp_fft_rtax/actram.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/actram.vhd @@ -0,0 +1,97 @@ +-- Version: 9.1 SP5 9.1.5.1 + +library ieee; +use ieee.std_logic_1164.all; +library Axcelerator; +use Axcelerator.all; + +entity actram is + port( DI : in std_logic_vector(31 downto 0); DO : out + std_logic_vector(31 downto 0); WADDR : in + std_logic_vector(6 downto 0); RADDR : in + std_logic_vector(6 downto 0);WRB, RDB, WCLOCK, RCLOCK : + in std_logic) ; +end actram; + + +architecture DEF_ARCH of actram is + + component INV + port(A : in std_logic := 'U'; Y : out std_logic) ; + end component; + + component RAM64K36P + generic (MEMORYFILE:string := ""); + + port(WCLK, RCLK, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WEN, WW0, + WW1, WW2, WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, + WRAD7, WRAD8, WRAD9, WRAD10, WRAD11, WRAD12, WRAD13, + WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6, WD7, + WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, + WD18, WD19, WD20, WD21, WD22, WD23, WD24, WD25, WD26, + WD27, WD28, WD29, WD30, WD31, WD32, WD33, WD34, WD35, REN, + RW0, RW1, RW2, RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, + RDAD6, RDAD7, RDAD8, RDAD9, RDAD10, RDAD11, RDAD12, + RDAD13, RDAD14, RDAD15 : in std_logic := 'U'; RD0, RD1, + RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, + RD13, RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, + RD22, RD23, RD24, RD25, RD26, RD27, RD28, RD29, RD30, + RD31, RD32, RD33, RD34, RD35 : out std_logic) ; + end component; + + component VCC + port( Y : out std_logic); + end component; + + component GND + port( Y : out std_logic); + end component; + + signal WEP, REP, VCC_1_net, GND_1_net : std_logic ; + begin + + VCC_2_net : VCC port map(Y => VCC_1_net); + GND_2_net : GND port map(Y => GND_1_net); + REBUBBLE : INV + port map(A => RDB, Y => REP); + WEBUBBLE : INV + port map(A => WRB, Y => WEP); + actram_R0C0 : RAM64K36P + port map(WCLK => WCLOCK, RCLK => RCLOCK, DEPTH0 => + GND_1_net, DEPTH1 => GND_1_net, DEPTH2 => GND_1_net, + DEPTH3 => GND_1_net, WEN => WEP, WW0 => VCC_1_net, WW1 => + GND_1_net, WW2 => VCC_1_net, WRAD0 => WADDR(0), WRAD1 => + WADDR(1), WRAD2 => WADDR(2), WRAD3 => WADDR(3), WRAD4 => + WADDR(4), WRAD5 => WADDR(5), WRAD6 => WADDR(6), WRAD7 => + GND_1_net, WRAD8 => GND_1_net, WRAD9 => GND_1_net, + WRAD10 => GND_1_net, WRAD11 => GND_1_net, WRAD12 => + GND_1_net, WRAD13 => GND_1_net, WRAD14 => GND_1_net, + WRAD15 => GND_1_net, WD0 => DI(0), WD1 => DI(1), WD2 => + DI(2), WD3 => DI(3), WD4 => DI(4), WD5 => DI(5), WD6 => + DI(6), WD7 => DI(7), WD8 => DI(8), WD9 => DI(9), WD10 => + DI(10), WD11 => DI(11), WD12 => DI(12), WD13 => DI(13), + WD14 => DI(14), WD15 => DI(15), WD16 => DI(16), WD17 => + DI(17), WD18 => DI(18), WD19 => DI(19), WD20 => DI(20), + WD21 => DI(21), WD22 => DI(22), WD23 => DI(23), WD24 => + DI(24), WD25 => DI(25), WD26 => DI(26), WD27 => DI(27), + WD28 => DI(28), WD29 => DI(29), WD30 => DI(30), WD31 => + DI(31), WD32 => GND_1_net, WD33 => GND_1_net, WD34 => + GND_1_net, WD35 => GND_1_net, REN => REP, RW0 => + VCC_1_net, RW1 => GND_1_net, RW2 => VCC_1_net, RDAD0 => + RADDR(0), RDAD1 => RADDR(1), RDAD2 => RADDR(2), RDAD3 => + RADDR(3), RDAD4 => RADDR(4), RDAD5 => RADDR(5), RDAD6 => + RADDR(6), RDAD7 => GND_1_net, RDAD8 => GND_1_net, + RDAD9 => GND_1_net, RDAD10 => GND_1_net, RDAD11 => + GND_1_net, RDAD12 => GND_1_net, RDAD13 => GND_1_net, + RDAD14 => GND_1_net, RDAD15 => GND_1_net, RD0 => DO(0), + RD1 => DO(1), RD2 => DO(2), RD3 => DO(3), RD4 => DO(4), + RD5 => DO(5), RD6 => DO(6), RD7 => DO(7), RD8 => DO(8), + RD9 => DO(9), RD10 => DO(10), RD11 => DO(11), RD12 => + DO(12), RD13 => DO(13), RD14 => DO(14), RD15 => DO(15), + RD16 => DO(16), RD17 => DO(17), RD18 => DO(18), RD19 => + DO(19), RD20 => DO(20), RD21 => DO(21), RD22 => DO(22), + RD23 => DO(23), RD24 => DO(24), RD25 => DO(25), RD26 => + DO(26), RD27 => DO(27), RD28 => DO(28), RD29 => DO(29), + RD30 => DO(30), RD31 => DO(31), RD32 => OPEN , RD33 => + OPEN , RD34 => OPEN , RD35 => OPEN ); +end DEF_ARCH; diff --git a/lib/lpp/dsp/lpp_fft_rtax/fftDp.vhd b/lib/lpp/dsp/lpp_fft_rtax/fftDp.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/fftDp.vhd @@ -0,0 +1,654 @@ +-------------------------------------------------------------------------------- +-- Copyright 2007 Actel Corporation. All rights reserved. + +-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN +-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED +-- IN ADVANCE IN WRITING. + +-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release +-- File: fftDp.vhd +-- Description: CoreFFT +-- FFT dapa path module +-- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production +-- +-- +-------------------------------------------------------------------------------- +-------------------------------- SWITCH ------------------------------- +-- if (sel) straight, else cross +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY switch IS + GENERIC ( DWIDTH : integer := 32 ); + PORT ( + clk, sel, validIn : IN std_logic; + inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0); + validOut : OUT std_logic); +END ENTITY switch; + +ARCHITECTURE translated OF switch IS + CONSTANT tscale : time := 1 ns; + + SIGNAL leftQ_r, rightP_r : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL pipe1 : std_logic; + SIGNAL muxP_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL muxQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL temp_xhdl4 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL temp_xhdl5 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL validOut_xhdl3 : std_logic; + +BEGIN + outP <= outP_xhdl1; + outQ <= outQ_xhdl2; + validOut <= validOut_xhdl3; + temp_xhdl4 <= leftQ_r WHEN sel = '1' ELSE inP; + muxP_w <= temp_xhdl4 ; + temp_xhdl5 <= leftQ_r WHEN NOT sel = '1' ELSE inP; + muxQ_w <= temp_xhdl5 ; + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN + outP_xhdl1 <= rightP_r AFTER tscale; + outQ_xhdl2 <= muxQ_w AFTER tscale; + leftQ_r <= inQ AFTER tscale; + rightP_r <= muxP_w AFTER tscale; + validOut_xhdl3 <= pipe1 AFTER tscale; + pipe1 <= validIn AFTER tscale; + END IF; + END PROCESS; +END ARCHITECTURE translated; + +---------------------------- B U T T E R F L Y -------------------------------- +------------------------- Simple Round Up: 1-clk delay ----------------------V +---------- Use it when it is known INBITWIDTH > OUTBITWIDTH -------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.numeric_std.all; + +ENTITY kitRndUp IS + GENERIC (OUTBITWIDTH : integer := 12; + RND_MODE : integer := 0 ); + PORT (nGrst, rst, clk, clkEn : IN std_logic; + inp : IN std_logic_vector(OUTBITWIDTH DOWNTO 0); + valInp : IN std_logic; + outp : OUT std_logic_vector(OUTBITWIDTH-1 DOWNTO 0); + valOutp : OUT std_logic); +END ENTITY kitRndUp; + +ARCHITECTURE rtl OF kitRndUp IS + CONSTANT tscale : time := 1 ns; + + SIGNAL int_outp : signed(OUTBITWIDTH DOWNTO 0); + SIGNAL int_valOutp : std_logic; + +BEGIN + outp <= std_logic_vector(int_outp(OUTBITWIDTH DOWNTO 1)); + valOutp <= int_valOutp; + + PROCESS (clk, nGrst) + BEGIN + IF (NOT nGrst = '1') THEN + int_outp <= to_signed(0, OUTBITWIDTH+1); + int_valOutp <= '0'; + ELSIF (clk'EVENT AND clk = '1') THEN + IF (rst = '1') THEN + int_outp <= to_signed(0, OUTBITWIDTH+1) AFTER tscale; + int_valOutp <= '0' AFTER 1 ns; + ELSIF (clkEn = '1') THEN + IF (valInp = '1') THEN + IF(RND_MODE = 1) THEN + int_outp <= signed(inp) + to_signed(1, OUTBITWIDTH+1) AFTER tscale; + ELSE int_outp <= signed(inp); + END IF; + END IF; + int_valOutp <= valInp AFTER tscale; + END IF; --rst and no rst + END IF; --nGrst and no nGrst + END PROCESS; +END ARCHITECTURE rtl; + +-------------------------------- MULT -----------------------------V +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +ENTITY agen IS + GENERIC ( RND_MODE : integer := 0; + WSIZE : integer := 16; + DWIDTH : integer := 16; + TWIDTH : integer := 16 ); + PORT ( -- synthesis syn_preserve=1 + clk : IN std_logic; + a : IN std_logic_vector(WSIZE-1 DOWNTO 0); + t : IN std_logic_vector(TWIDTH-1 DOWNTO 0); + arout : OUT std_logic_vector(WSIZE-1 DOWNTO 0)); +END ENTITY agen; + +ARCHITECTURE rtl OF agen IS + CONSTANT tscale : time := 1 ns; + COMPONENT actar + PORT (DataA : IN std_logic_vector(WSIZE-1 DOWNTO 0); + DataB : IN std_logic_vector(TWIDTH-1 DOWNTO 0); + Mult : OUT std_logic_vector(WSIZE+TWIDTH-1 DOWNTO 0); + Clock : IN std_logic ); + END COMPONENT; + + COMPONENT kitRndUp + GENERIC ( + OUTBITWIDTH : integer := 12; + RND_MODE : integer := 0 ); + PORT (nGrst, rst, clk, clkEn : IN std_logic; + inp : IN std_logic_vector(OUTBITWIDTH DOWNTO 0); + valInp : IN std_logic; + outp : OUT std_logic_vector(OUTBITWIDTH-1 DOWNTO 0); + valOutp : OUT std_logic); + END COMPONENT; + + SIGNAL a_r : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL t_r : std_logic_vector(TWIDTH-1 DOWNTO 0); + SIGNAL out1 : std_logic_vector(WSIZE DOWNTO 0); + SIGNAL out_w : std_logic_vector(WSIZE+TWIDTH-1 DOWNTO 0); + SIGNAL out_VHDL : std_logic_vector(WSIZE-1 DOWNTO 0); + +BEGIN + arout <= out_VHDL; + actar_0 : actar + PORT MAP (DataA => a_r, DataB => t_r, Mult => out_w, Clock => clk); + + kitRndUp_0: kitRndUp + GENERIC MAP ( OUTBITWIDTH => WSIZE, RND_MODE => RND_MODE ) + PORT MAP (nGrst => '1', rst => '0', clk => clk, clkEn => '1', + inp => out1, valInp => '1', outp => out_VHDL, valOutp => open); + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN + a_r <= a AFTER tscale; + t_r <= t AFTER tscale; + + out1 <= out_w(DWIDTH-1 DOWNTO WSIZE-1) AFTER tscale; + END IF; + END PROCESS; +END ARCHITECTURE rtl; +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.STD_LOGIC_ARITH.all; + +ENTITY bfly2 IS + GENERIC ( RND_MODE : integer := 0; + WSIZE : integer := 16; + DWIDTH : integer := 32; + TWIDTH : integer := 16; + TDWIDTH : integer := 32 ); + PORT (clk, validIn : IN std_logic; + swCrossIn : IN std_logic; + upScale : IN std_logic; --don't do downscaling if upScale==1 + inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + T : IN std_logic_vector(TDWIDTH-1 DOWNTO 0); + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0); + --Signals need to be delayed by the bfly latency. That's why they are here + validOut, swCrossOut : OUT std_logic); +END ENTITY bfly2; + +ARCHITECTURE translated OF bfly2 IS + CONSTANT tscale : time := 1 ns; + + COMPONENT agen + GENERIC ( RND_MODE : integer := 0; + WSIZE : integer := 16; + DWIDTH : integer := 16; + TWIDTH : integer := 16 ); + PORT (clk : IN std_logic; + a : IN std_logic_vector(WSIZE-1 DOWNTO 0); + t : IN std_logic_vector(TWIDTH-1 DOWNTO 0); + arout : OUT std_logic_vector(WSIZE-1 DOWNTO 0)); + END COMPONENT; + + -- CONVENTION: real - LSBs[15:0], imag - MSBs[31:16] + SIGNAL inPr_w, inPi_w, inQr_w, inQi_w : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL Tr_w, Ti_w : std_logic_vector(TWIDTH-1 DOWNTO 0); + SIGNAL Hr_w, Hi_w, Hr, Hi : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL PrT1_r, PrT2_r, PrT3_r, PrT4_r : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL PrT5_r, PrT6_r, PiT1_r, PiT2_r : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL PiT3_r, PiT4_r, PiT5_r, PiT6_r : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL QrTr_w, QiTi_w, QiTr_w, QrTi_w : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL pipe1,pipe2,pipe3,pipe4,pipe5 : std_logic_vector(1 DOWNTO 0); + SIGNAL pipe6 : std_logic_vector(1 DOWNTO 0); + -- select either 16-bit value or sign-extended 15-bit value (downscaled one) + SIGNAL temp_xhdl5 : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL temp_xhdl6 : std_logic_vector(DWIDTH-1 DOWNTO WSIZE); + -- select either 16-bit value or left-shifted value (upscaled one) + SIGNAL temp_xhdl7 : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL temp_xhdl8 : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL validOut_xhdl3 : std_logic; + SIGNAL swCrossOut_xhdl4 : std_logic; + +BEGIN + outP <= outP_xhdl1; + outQ <= outQ_xhdl2; + validOut <= validOut_xhdl3; + swCrossOut <= swCrossOut_xhdl4; + Tr_w <= T(TWIDTH-1 DOWNTO 0) ; + Ti_w <= T(TDWIDTH-1 DOWNTO TWIDTH) ; + temp_xhdl5 <= inP(WSIZE-1 DOWNTO 0) WHEN upScale = '1' ELSE inP(WSIZE-1) & + inP(WSIZE-1 DOWNTO 1); + inPr_w <= temp_xhdl5 AFTER tscale; + temp_xhdl6 <= inP(DWIDTH-1 DOWNTO WSIZE) WHEN upScale = '1' ELSE inP(DWIDTH-1) + & inP(DWIDTH-1 DOWNTO WSIZE+1); + inPi_w <= temp_xhdl6 AFTER tscale; + temp_xhdl7 <= inQ(WSIZE-2 DOWNTO 0) & '0' WHEN upScale = '1' ELSE inQ(WSIZE-1 + DOWNTO 0); + inQr_w <= temp_xhdl7 AFTER tscale; + temp_xhdl8 <= inQ(DWIDTH-2 DOWNTO WSIZE) & '0' WHEN upScale = '1' ELSE + inQ(DWIDTH-1 DOWNTO WSIZE); + inQi_w <= temp_xhdl8 AFTER tscale; + + am3QrTr : agen + GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE, + DWIDTH => DWIDTH, TWIDTH => TWIDTH) + PORT MAP (clk => clk, a => inQr_w, t => Tr_w, arout => QrTr_w); + am3QiTi : agen + GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE, + DWIDTH => DWIDTH, TWIDTH => TWIDTH) + PORT MAP (clk => clk, a => inQi_w, t => Ti_w, arout => QiTi_w); + am3QiTr : agen + GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE, + DWIDTH => DWIDTH, TWIDTH => TWIDTH) + PORT MAP (clk => clk, a => inQi_w, t => Tr_w, arout => QiTr_w); + am3QrTi : agen + GENERIC MAP ( RND_MODE => RND_MODE, WSIZE => WSIZE, + DWIDTH => DWIDTH, TWIDTH => TWIDTH) + PORT MAP (clk => clk, a => inQr_w, t => Ti_w, arout => QrTi_w); + + Hr_w <= QrTr_w + QiTi_w AFTER tscale; + Hi_w <= QiTr_w - QrTi_w AFTER tscale; + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN + outQ_xhdl2(DWIDTH-1 DOWNTO WSIZE) <= PiT6_r - Hi AFTER tscale; + outQ_xhdl2(WSIZE-1 DOWNTO 0) <= PrT6_r - Hr AFTER tscale; + outP_xhdl1(DWIDTH-1 DOWNTO WSIZE) <= PiT6_r + Hi AFTER tscale; + outP_xhdl1(WSIZE-1 DOWNTO 0) <= PrT6_r + Hr AFTER tscale; + -- pipes + + PrT6_r <= PrT5_r AFTER tscale; PiT6_r <= PiT5_r AFTER tscale; + PrT5_r <= PrT4_r AFTER tscale; PiT5_r <= PiT4_r AFTER tscale; + PrT4_r <= PrT3_r AFTER tscale; PiT4_r <= PiT3_r AFTER tscale; + PrT3_r <= PrT2_r AFTER tscale; PiT3_r <= PiT2_r AFTER tscale; + PrT2_r <= PrT1_r AFTER tscale; PiT2_r <= PiT1_r AFTER tscale; + PrT1_r <= inPr_w AFTER tscale; PiT1_r <= inPi_w AFTER tscale; + Hr <= Hr_w AFTER tscale; Hi <= Hi_w AFTER tscale; + validOut_xhdl3 <= pipe6(0) AFTER tscale; + swCrossOut_xhdl4 <= pipe6(1) AFTER tscale; + pipe6 <= pipe5 AFTER tscale; pipe5 <= pipe4 AFTER tscale; + pipe4 <= pipe3 AFTER tscale; pipe3 <= pipe2 AFTER tscale; + pipe2 <= pipe1 AFTER tscale; pipe1(0) <= validIn AFTER tscale; + pipe1(1) <= swCrossIn AFTER tscale; + END IF; + END PROCESS; +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- + +--********************************** B U F F E R ******************************* +----------------------------------- inBuffer ----------------------------------V +-- InBuf stores double complex words so that FFT engine can read two cmplx +-- words per clock. Thus the depth of the buffer is `LOGPTS-1 +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY inBuffer IS + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT ( + clk, clkEn : IN std_logic; + rA, wA_bfly, wA_load : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + -- new data to load, data coming from FFT engine + ldData, wP_bfly, wQ_bfly: IN std_logic_vector(DWIDTH-1 DOWNTO 0); + wEn_bfly : IN std_logic; --wEn to store FFT engine data + wEn_even, wEn_odd : IN std_logic; --wEn to store new data in even/odd subbuffers + rEn : IN std_logic; --used only by FFT engine + -- pipo=pong for pong buffer, =/pong for ping buffer + pipo : IN std_logic; --controls buffer input muxes. + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0)); -- output data to FFT engine +END ENTITY inBuffer; + +ARCHITECTURE translated OF inBuffer IS + CONSTANT tscale : time := 1 ns; + + COMPONENT wrapRam + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT( clk, wEn : in std_logic; + wA, rA : in std_logic_vector(LOGPTS-2 downto 0); + D : in std_logic_vector(DWIDTH-1 downto 0); + Q : out std_logic_vector(DWIDTH-1 downto 0) ); + end component; + + -- internal wires, &-gates + SIGNAL wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL wP_w, wQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL wEn_P, wEn_Q : std_logic; + SIGNAL rEn_ce_w,wEnP_ce_w,wEnQ_ce_w : std_logic; + SIGNAL temp_xhdl3 : std_logic; + SIGNAL temp_xhdl4 : std_logic; + SIGNAL temp_xhdl5 : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL temp_xhdl6 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL temp_xhdl7 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0); + +BEGIN + outP <= outP_xhdl1; + outQ <= outQ_xhdl2; + rEn_ce_w <= rEn AND clkEn ; + wEnP_ce_w <= wEn_P AND clkEn ; + wEnQ_ce_w <= wEn_Q AND clkEn ; + temp_xhdl3 <= wEn_bfly WHEN pipo = '1' ELSE wEn_even; + wEn_P <= temp_xhdl3 ; + temp_xhdl4 <= wEn_bfly WHEN pipo = '1' ELSE wEn_odd; + wEn_Q <= temp_xhdl4 ; + temp_xhdl5 <= wA_bfly WHEN pipo = '1' ELSE wA_load; + wA_w <= temp_xhdl5 ; + temp_xhdl6 <= wP_bfly WHEN pipo = '1' ELSE ldData; + wP_w <= temp_xhdl6 ; + temp_xhdl7 <= wQ_bfly WHEN pipo = '1' ELSE ldData; + wQ_w <= temp_xhdl7 ; + -- if(~pipo) LOAD, else - RUN BFLY. Use MUX'es + + -- instantiate two mem blocks `HALFPTS deep each + memP : wrapRam + GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH ) + PORT MAP (D => wP_w, Q => outP_xhdl1, wA => wA_w, rA => rA, + wEn => wEnP_ce_w, clk => clk); + + memQ : wrapRam + GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH ) + PORT MAP (D => wQ_w, Q => outQ_xhdl2, wA => wA_w, rA => rA, + wEn => wEnQ_ce_w, clk => clk); +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- +------------------------------- pipoBuffer ------------------------------------V +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY pipoBuffer IS + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT ( + clk, clkEn, pong, rEn : IN std_logic; + rA, wA_load, wA_bfly : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + wEn_bfly,wEn_even,wEn_odd : IN std_logic; + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) ); +END ENTITY pipoBuffer; + +ARCHITECTURE translated OF pipoBuffer IS + CONSTANT tscale : time := 1 ns; + + COMPONENT inBuffer + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT ( + clk, clkEn, rEn, pipo : IN std_logic; + rA,wA_bfly,wA_load : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + wEn_bfly,wEn_even,wEn_odd : IN std_logic; + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0)); + END COMPONENT; + + --internal signals + SIGNAL pi_outP, pi_outQ : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL po_outP, po_outQ : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL port_xhdl17 : std_logic; + SIGNAL temp_xhdl32 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL temp_xhdl33 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL outP_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL outQ_xhdl2 : std_logic_vector(DWIDTH-1 DOWNTO 0); + +BEGIN + outP <= outP_xhdl1; + outQ <= outQ_xhdl2; + port_xhdl17 <= NOT pong; + piBuf : inBuffer + GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH ) + PORT MAP (clk => clk, rA => rA, wA_bfly => wA_bfly, + wA_load => wA_load, ldData => ldData, wP_bfly => wP_bfly, + wQ_bfly => wQ_bfly, wEn_bfly => wEn_bfly, + wEn_even => wEn_even, wEn_odd => wEn_odd, rEn => rEn, + clkEn => clkEn, pipo => port_xhdl17, + outP => pi_outP, outQ => pi_outQ); + + poBuf : inBuffer + GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH ) + PORT MAP (clk => clk, rA => rA, wA_bfly => wA_bfly, + wA_load => wA_load, ldData => ldData, wP_bfly => wP_bfly, + wQ_bfly => wQ_bfly, wEn_bfly => wEn_bfly, + wEn_even => wEn_even, wEn_odd => wEn_odd, rEn => rEn, + clkEn => clkEn, pipo => pong, + outP => po_outP, outQ => po_outQ); + + temp_xhdl32 <= po_outP WHEN pong = '1' ELSE pi_outP; + outP_xhdl1 <= temp_xhdl32 ; + temp_xhdl33 <= po_outQ WHEN pong = '1' ELSE pi_outQ; + outQ_xhdl2 <= temp_xhdl33 ; + +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- +--******************************* outBuffer *********************************V +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY outBuff IS + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT ( + clk, clkEn, wEn : IN std_logic; + inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + rA : IN std_logic_vector(LOGPTS-1 DOWNTO 0); + outD : OUT std_logic_vector(DWIDTH-1 DOWNTO 0)); +END ENTITY outBuff; + +ARCHITECTURE translated OF outBuff IS + CONSTANT tscale : time := 1 ns; + + COMPONENT wrapRam + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT( clk, wEn : in std_logic; + wA, rA : in std_logic_vector(LOGPTS-2 downto 0); + D : in std_logic_vector(DWIDTH-1 downto 0); + Q : out std_logic_vector(DWIDTH-1 downto 0) ); + end component; + + SIGNAL wEn_r : std_logic; + SIGNAL inP_r, inQ_r : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL wA_r : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL rAmsb_r1, rAmsb_r2 : std_logic; + SIGNAL P_w, Q_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL outPQ : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL temp_xhdl10 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL outD_xhdl1 : std_logic_vector(DWIDTH-1 DOWNTO 0); + +BEGIN + outD <= outD_xhdl1; + outBuf_0 : wrapRam + GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH ) + PORT MAP (D => inP_r, Q => P_w, wA => wA_r, + rA => rA(LOGPTS-2 DOWNTO 0), + wEn => wEn_r, clk => clk); + outBuf_1 : wrapRam + GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH ) + PORT MAP (D => inQ_r, Q => Q_w, wA => wA_r, + rA => rA(LOGPTS-2 DOWNTO 0), + wEn => wEn_r, clk => clk); + + temp_xhdl10 <= Q_w WHEN rAmsb_r2 = '1' ELSE P_w; + outPQ <= temp_xhdl10 ; + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN + inP_r <= inP AFTER 1*tscale; + inQ_r <= inQ AFTER 1*tscale; -- pipes + wEn_r <= wEn AFTER 1*tscale; + wA_r <= wA AFTER 1*tscale; + rAmsb_r2 <= rAmsb_r1 AFTER 1*tscale; + rAmsb_r1 <= rA(LOGPTS-1) AFTER 1*tscale; + outD_xhdl1 <= outPQ AFTER 1*tscale; + END IF; + END PROCESS; +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- +--************************ T W I D D L E L U T ******************************V +-- RAM-block based twiddle LUT +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY twidLUT IS + GENERIC ( LOGPTS : integer := 8; + TDWIDTH : integer := 32 ); + PORT ( + clk, wEn : IN std_logic; + wA, rA : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + D : IN std_logic_vector(TDWIDTH-1 DOWNTO 0); + Q : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0)); +END ENTITY twidLUT; + +ARCHITECTURE translated OF twidLUT IS + CONSTANT tscale : time := 1 ns; + + COMPONENT wrapRam + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT( clk, wEn : in std_logic; + wA, rA : in std_logic_vector(LOGPTS-2 downto 0); + D : in std_logic_vector(TDWIDTH-1 downto 0); + Q : out std_logic_vector(TDWIDTH-1 downto 0) ); + end component; + + SIGNAL rA_r : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL Q_xhdl1 : std_logic_vector(TDWIDTH-1 DOWNTO 0); + +BEGIN + Q <= Q_xhdl1; + twidLUT_0 : wrapRam + GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => TDWIDTH ) + PORT MAP (D => D, Q => Q_xhdl1, wA => wA, rA => rA_r, + wEn => wEn, clk => clk); + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN + rA_r <= rA AFTER tscale; + END IF; + END PROCESS; +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- +------------------------- R A M ----------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY wrapRam IS + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT (clk, wEn : IN std_logic; + D : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + rA, wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + Q : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) ); +END ENTITY wrapRam; + +ARCHITECTURE rtl OF wrapRam IS + CONSTANT RE : std_logic := '0'; + COMPONENT actram + port(WRB, RDB, WCLOCK, RCLOCK : IN std_logic; + DI : in std_logic_vector(DWIDTH-1 downto 0); + DO : out std_logic_vector(DWIDTH-1 downto 0); + WADDR,RADDR : IN std_logic_vector(LOGPTS-2 downto 0) ); + end COMPONENT; + + SIGNAL nwEn : std_logic; + +BEGIN + nwEn <= NOT wEn; + wrapRam_0 : actram + PORT MAP (DI => D, WADDR => wA, RADDR => rA, WRB => nwEn, + RDB => RE, RCLOCK => clk, WCLOCK => clk, DO => Q); +END ARCHITECTURE rtl; +-------------------------------------------------------------------------------V +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE work.fft_components.all; + +ENTITY autoScale IS + GENERIC (SCALE_MODE : integer := 1 ); -- enable autoscaling + PORT ( + clk, clkEn, wLastStage : IN std_logic; + ldRiskOV, bflyRiskOV : IN std_logic; + startLoad, ifo_loadOn : IN std_logic; + bflyOutValid, startFFT : IN std_logic; + wEn_even, wEn_odd : IN std_logic; +-- scaleMode : IN std_logic; --set 1 to turn autoscaling ON + upScale : OUT std_logic); +END ENTITY autoScale; + +ARCHITECTURE translated OF autoScale IS + CONSTANT tscale : time := 1 ns; + + SIGNAL ldMonitor, bflyMonitor, stageEnd_w : std_logic; + SIGNAL xhdl_5 : std_logic; + SIGNAL upScale_xhdl1 : std_logic; + +BEGIN + upScale <= upScale_xhdl1; + xhdl_5 <= (bflyOutValid AND (NOT wLastStage)); + fedge_0 : edgeDetect + GENERIC MAP (INPIPE => 0, FEDGE => 1) + PORT MAP (clk => clk, clkEn => clkEn, edgeIn => xhdl_5, edgeOut => stageEnd_w); + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN + -- Initialize ldMonitor + IF (startLoad = '1') THEN + ldMonitor <= to_logic(SCALE_MODE) AFTER tscale; + ELSE + -- Monitor the data being loaded: turn down ldMonitor + -- if any valid input data violates the condition + IF ((ldRiskOV AND (wEn_even OR wEn_odd)) = '1') THEN + ldMonitor <= '0' AFTER tscale; + END IF; + END IF; + -- monitor the data being FFT'ed + IF ((bflyRiskOV AND bflyOutValid) = '1') THEN + bflyMonitor <= '0'; + END IF; + --check ldMonitor on startFFT (startFFT coinsides with the next startLoad) + IF (startFFT = '1') THEN + upScale_xhdl1 <= ldMonitor AFTER tscale; + -- initialize bflyMonitor + bflyMonitor <= to_logic(SCALE_MODE) AFTER tscale; + ELSE + -- Check the bflyMonitor at a stage end except the last stage, since the + -- end of the last stage may come on or even after the startFFT signal + -- when the upScale is supposed to check the ldMonitor only + IF (stageEnd_w = '1') THEN + upScale_xhdl1 <= bflyMonitor AFTER tscale; + -- initialize bflyMonitor at the beginning of every stage + bflyMonitor <= to_logic(SCALE_MODE) AFTER tscale; + END IF; + END IF; + END IF; + END PROCESS; + +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- diff --git a/lib/lpp/dsp/lpp_fft_rtax/fftSm.vhd b/lib/lpp/dsp/lpp_fft_rtax/fftSm.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/fftSm.vhd @@ -0,0 +1,881 @@ +-------------------------------------------------------------------------------- +-- Copyright 2007 Actel Corporation. All rights reserved. + +-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN +-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED +-- IN ADVANCE IN WRITING. + +-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release +-- File: fftSm.vhd +-- Description: CoreFFT +-- FFT state machine module +-- Rev: 3.0 3/28/2007 4:43PM VlaD : Variable bitwidth +-- +-- +-------------------------------------------------------------------------------- +--************************** TWIDDLE rA GENERATOR ************************** +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.std_logic_unsigned.all; +USE work.fft_components.all; + +ENTITY twid_rA IS + GENERIC (LOGPTS : integer := 8; + LOGLOGPTS : integer := 3 ); + PORT (clk : IN std_logic; + timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0)); +END ENTITY twid_rA; + +ARCHITECTURE translated OF twid_rA IS + CONSTANT timescale : time := 1 ns; + --twiddleMask = ~(0xFFFFFFFF<<(NumberOfStages-1)); + --addrTwiddle=reverseBits(count, NumberOfStages-1)<<(NumberOfStages-1-stage); + --mask out extra left bits: addrTwiddle = addrTwiddle & twiddleMask; + --reverse bits of the timer; + SIGNAL reverseBitTimer : bit_vector(LOGPTS-2 DOWNTO 0); + SIGNAL tA_w, tA_reg : std_logic_vector(LOGPTS-2 DOWNTO 0); + +BEGIN + tA <= tA_reg; + PROCESS (timer) + BEGIN + reverseBitTimer <= reverse(timer); + END PROCESS; + -- Left shift by + tA_w <= To_StdLogicVector(reverseBitTimer SLL (LOGPTS-1 - to_integer(stage)) ) + AFTER timescale; + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN + tA_reg <= tA_w AFTER timescale; + END IF; + END PROCESS; +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- +--***************************** TIMERS & rdValid *************************** +-- FFT computation sequence is predefined. Once it gets started it runs for +-- a number of stages, `HALFPTS+ clk per stage. The following module sets the +-- read inBuf time sequence. Every stage takes HALFPTS + inBuf_RWDLY clk for +-- the inBuf to write Bfly results back in place before it starts next stage +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE work.fft_components.all; + +ENTITY rdFFTtimer IS + GENERIC (LOGPTS : integer := 8; + LOGLOGPTS : integer := 3; + HALFPTS : integer := 128; + inBuf_RWDLY : integer := 12 ); + PORT ( + clk, cntEn, rst, nGrst : IN std_logic; + startFFT, fft_runs : IN std_logic; + timerTC, lastStage : OUT std_logic; --terminal counts of rA and stage + stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + timer : OUT std_logic_vector(LOGPTS-1 DOWNTO 0); + rdValid : OUT std_logic ); +END ENTITY rdFFTtimer; + +ARCHITECTURE translated OF rdFFTtimer IS + CONSTANT dlta : time := 1 ns; + + SIGNAL preRdValid : std_logic; + SIGNAL pipe1, pipe2 : std_logic; + SIGNAL rst_comb, timerTCx1 : std_logic; + SIGNAL lastStage_xhdl2 : std_logic; + SIGNAL stage_xhdl3 : std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + SIGNAL timer_xhdl4 : std_logic_vector(LOGPTS-1 DOWNTO 0); + SIGNAL rdValid_xhdl5 : std_logic; + +BEGIN + timerTC <= timerTCx1; + lastStage <= lastStage_xhdl2; + stage <= stage_xhdl3; + timer <= timer_xhdl4; + rdValid <= rdValid_xhdl5; + rst_comb <= rst OR startFFT; + + rA_timer : counter + GENERIC MAP (WIDTH =>LOGPTS, TERMCOUNT =>HALFPTS+inBuf_RWDLY-1) + PORT MAP (clk => clk, nGrst => nGrst, rst => rst_comb, + cntEn => cntEn, tc => timerTCx1, Q => timer_xhdl4); + stage_timer : counter + GENERIC MAP (WIDTH => LOGLOGPTS, TERMCOUNT => LOGPTS-1) + PORT MAP (clk => clk, nGrst => nGrst, rst => rst_comb, + cntEn => timerTCx1, tc => lastStage_xhdl2, + Q => stage_xhdl3); + + PROCESS (clk, nGrst) + BEGIN + IF (NOT nGrst = '1') THEN + preRdValid <= '0'; + ELSIF (clk'EVENT AND clk = '1') THEN + IF (rst = '1') THEN + preRdValid <= '0' AFTER dlta; + ELSE + IF (cntEn = '1') THEN + IF ( to_integer(timer_xhdl4) = HALFPTS-1 ) THEN + preRdValid <= '0' AFTER dlta; + END IF; + -- on startFFT the valid reading session always starts + IF (startFFT = '1') THEN preRdValid <= '1' AFTER dlta; + END IF; + -- reading session starts on rTimerTC except after the lastStage + IF ((((NOT lastStage_xhdl2) AND timerTCx1) AND fft_runs) = '1') THEN + preRdValid <= '1' AFTER dlta; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN + rdValid_xhdl5 <= pipe2 AFTER dlta; + pipe2 <= pipe1 AFTER dlta; + pipe1 <= preRdValid AFTER dlta; + END IF; + END PROCESS; +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE work.fft_components.all; + +ENTITY wrFFTtimer IS + GENERIC (LOGPTS : integer := 8; + LOGLOGPTS : integer := 3; + HALFPTS : integer := 128 ); + PORT ( + clk, cntEn, nGrst, rst : IN std_logic; + rstStage, rstTime : IN std_logic; + timerTC, lastStage : OUT std_logic; -- terminal counts of wA and stage + stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + timer : OUT std_logic_vector(LOGPTS-2 DOWNTO 0)); +END ENTITY wrFFTtimer; + +ARCHITECTURE translated OF wrFFTtimer IS + CONSTANT timescale : time := 1 ns; + + SIGNAL rst_VHDL,rstStage_VHDL : std_logic; + SIGNAL timerTC_xhdl1 : std_logic; + SIGNAL lastStage_xhdl2 : std_logic; + SIGNAL stage_xhdl3 : std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + SIGNAL timer_xhdl4 : std_logic_vector(LOGPTS-2 DOWNTO 0); + +BEGIN + timerTC <= timerTC_xhdl1; + lastStage <= lastStage_xhdl2; + stage <= stage_xhdl3; + timer <= timer_xhdl4; + rst_VHDL <= rstTime OR rst; + wA_timer : counter + GENERIC MAP (WIDTH => LOGPTS-1, TERMCOUNT =>HALFPTS-1) + PORT MAP (clk => clk, nGrst => nGrst, rst => rst_VHDL, cntEn => cntEn, + tc => timerTC_xhdl1, Q => timer_xhdl4); + rstStage_VHDL <= rstStage OR rst; + + stage_timer : counter + GENERIC MAP (WIDTH => LOGLOGPTS, TERMCOUNT =>LOGPTS-1) + PORT MAP (clk => clk, nGrst => nGrst, rst => rstStage_VHDL, + cntEn => timerTC_xhdl1, tc => lastStage_xhdl2, + Q => stage_xhdl3); +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- +--********************* inBuf LOAD ADDRESS GENERATOR ********************* +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE work.fft_components.all; + +ENTITY inBuf_ldA IS + GENERIC (PTS : integer := 256; + LOGPTS : integer := 8 ); + PORT ( + clk, clkEn, nGrst : IN std_logic; + --comes from topSM to reset ldA count & start another loading cycle + startLoad : IN std_logic; + ifi_dataRdy : IN std_logic; -- inData strobe + ifo_loadOn : OUT std_logic;-- inBuf is ready for new data + --tells topSM the buffer is fully loaded and ready for FFTing + load_done : OUT std_logic; + ldA : OUT std_logic_vector(LOGPTS-1 DOWNTO 1); + wEn_even, wEn_odd : OUT std_logic; + ldValid : OUT std_logic); +END ENTITY inBuf_ldA; + +ARCHITECTURE translated OF inBuf_ldA IS + CONSTANT timescale : time := 1 ns; + + -- just LSB of the counter below. Counts even/odd samples + SIGNAL ldCountLsb_w : std_logic; + SIGNAL closeLoad_w, cntEn_w : std_logic; + SIGNAL loadOver_w : std_logic; + SIGNAL xhdl_9 : std_logic_vector(LOGPTS-1 DOWNTO 0); + SIGNAL ifo_loadOn_int : std_logic; + SIGNAL load_done_int : std_logic; + SIGNAL ldA_int : std_logic_vector(LOGPTS-1 DOWNTO 1); + SIGNAL wEn_even_int : std_logic; + SIGNAL wEn_odd_int : std_logic; + SIGNAL ldValid_int : std_logic; + +BEGIN + ifo_loadOn <= ifo_loadOn_int; + load_done <= load_done_int; + ldA <= ldA_int; + wEn_even <= wEn_even_int; + wEn_odd <= wEn_odd_int; + ldValid <= ldValid_int; + cntEn_w <= clkEn AND ifi_dataRdy ; + loadOver_w <= closeLoad_w AND wEn_odd_int ; + ldValid_int <= ifo_loadOn_int AND ifi_dataRdy ; + wEn_even_int <= NOT ldCountLsb_w AND ldValid_int ; + wEn_odd_int <= ldCountLsb_w AND ldValid_int ; +-- xhdl_9 <= ldA_int & ldCountLsb_w; + ldA_int <= xhdl_9(LOGPTS-1 DOWNTO 1); + ldCountLsb_w <= xhdl_9(0); + -- counts samples loaded. There is `PTS samples to load, not `PTS/2 + ldCount : counter + GENERIC MAP (WIDTH =>LOGPTS, TERMCOUNT =>PTS-1) + PORT MAP (clk => clk, nGrst => nGrst, rst => startLoad, + cntEn => cntEn_w, tc => closeLoad_w, Q => xhdl_9); + + -- A user can stop supplying ifi_dataRdy after loadOver gets high, thus + -- the loadOver can stay high indefinitely. Shorten it! + edge_0 : edgeDetect + GENERIC MAP (INPIPE => 0, FEDGE => 1) + PORT MAP (clk => clk, clkEn => clkEn, edgeIn => loadOver_w, + edgeOut => load_done_int); + + PROCESS (clk, nGrst) + BEGIN + -- generate ifo_loadOn: + IF (NOT nGrst = '1') THEN + ifo_loadOn_int <= '0'; + ELSE + IF (clk'EVENT AND clk = '1') THEN + IF (clkEn = '1') THEN + -- if (load_done) ifo_loadOn <= #1 0; + IF (loadOver_w = '1') THEN + ifo_loadOn_int <= '0' AFTER timescale; + ELSE + IF (startLoad = '1') THEN + ifo_loadOn_int <= '1' AFTER timescale; + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS; +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- +--****************** inBuf ADDRESS GENERATOR for BFLY DATA ***************** +-- Implements both read and write data generators. The core utilizes inPlace +-- algorithm thus the wA is a delayed copy of the rA +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.STD_LOGIC_UNSIGNED.all; +USE work.fft_components.all; + +ENTITY inBuf_fftA IS + GENERIC (LOGPTS : integer := 8; + LOGLOGPTS : integer := 3 ); + PORT ( + clk, clkEn :IN std_logic; + timer :IN std_logic_vector(LOGPTS-2 DOWNTO 0); + stage :IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + timerTC, lastStage :IN std_logic; + fftDone, swCross :OUT std_logic; + bflyA :OUT std_logic_vector(LOGPTS-2 DOWNTO 0)); +END ENTITY inBuf_fftA; + +ARCHITECTURE translated OF inBuf_fftA IS + CONSTANT timescale : time := 1 ns; + CONSTANT offsetConst : bit_vector(LOGPTS-1 DOWNTO 0):=('1', others=>'0'); + CONSTANT addrMask1: BIT_VECTOR(LOGPTS-1 DOWNTO 0) := ('0', OTHERS=>'1'); + CONSTANT addrMask2: BIT_VECTOR(LOGPTS-1 DOWNTO 0) := (OTHERS=>'1'); + + SIGNAL fftDone_w, swCross_w: std_logic; + SIGNAL bflyA_w : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL addrP_w, offsetPQ_w : std_logic_vector(LOGPTS-1 DOWNTO 0); + --rA takes either Paddr or Qaddr value (Qaddr=Paddr+offsetPQ) per clock. + --At even clk rA=Paddr, at odd clk rA=Qaddr. (Every addr holds a pair of + --data samples). Timer LSB controls which clk is happening now. LSB of + --the same timer controls switch(es). + SIGNAL bflyA_w_int : std_logic_vector(LOGPTS-1 DOWNTO 1); + SIGNAL swCross_w_int,swCross_int: std_logic; + SIGNAL fftDone_int : std_logic; + SIGNAL bflyA_int : std_logic_vector(LOGPTS-2 DOWNTO 0); + +BEGIN + fftDone <= fftDone_int; + bflyA <= bflyA_int; + swCross <= swCross_int; + --addrP_w=( (timer<<1)&(~(addrMask2>>stage)) ) | (timer&(addrMask1>>stage)); + addrP_w <= To_StdLogicVector( + ( (('0'& To_BitVector(timer)) SLL 1) AND (NOT (addrMask2 SRL to_integer(stage)) ) ) + OR ( ('0'& To_BitVector(timer)) AND (addrMask1 SRL to_integer(stage)) ) ); + + -- address offset between P and Q offsetPQ_w= ( 1<<(`LOGPTS-1) )>>stage; + offsetPQ_w <= To_StdLogicVector(offsetConst SRL to_integer(stage)); + + -- bflyA_w = timer[0] ? (addrP_w[`LOGPTS-1:1]+offsetPQ_w[`LOGPTS-1:1]): + -- addrP_w[`LOGPTS-1:1]; + bflyA_w_int <= + (addrP_w(LOGPTS-1 DOWNTO 1) + offsetPQ_w(LOGPTS-1 DOWNTO 1)) WHEN + timer(0) = '1' + ELSE addrP_w(LOGPTS-1 DOWNTO 1); + + bflyA_w <= bflyA_w_int AFTER timescale; + fftDone_w <= lastStage AND timerTC AFTER timescale; + swCross_w_int <= '0' WHEN lastStage = '1' ELSE timer(0); + swCross_w <= swCross_w_int AFTER timescale; + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN + IF (clkEn = '1') THEN + bflyA_int <= bflyA_w AFTER timescale; + swCross_int <= swCross_w AFTER timescale; + fftDone_int <= fftDone_w AFTER timescale; + END IF; + END IF; + END PROCESS; +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- +--************************** TWIDDLE wA GENERATOR **************************** +-- initializes Twiddle LUT on rst based on contents of twiddle.v file. +-- Generates trueRst when the initialization is over +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE work.fft_components.all; + +ENTITY twid_wAmod IS + GENERIC (LOGPTS : integer := 8 ); + PORT ( + clk, ifiNreset : IN std_logic; -- async global reset + twid_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0); + twid_wEn,twidInit : OUT std_logic; + rstAfterInit : OUT std_logic); +END ENTITY twid_wAmod; + +ARCHITECTURE translated OF twid_wAmod IS + CONSTANT timescale : time := 1 ns; + CONSTANT allOnes : std_logic_vector(LOGPTS+1 DOWNTO 0):=(OTHERS=>'1'); + + SIGNAL slowTimer_w : std_logic_vector(LOGPTS+1 DOWNTO 0); + SIGNAL preRstAfterInit : std_logic; + SIGNAL twid_wA_int : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL twid_wEn_int : std_logic; + SIGNAL rstAfterInit_int : std_logic; + SIGNAL twidInit_int : std_logic; + +BEGIN + twid_wA <= twid_wA_int; + twid_wEn <= twid_wEn_int; + rstAfterInit <= rstAfterInit_int; + twidInit <= twidInit_int; + + -- slow counter not to worry about the clk rate + slowTimer : bcounter + GENERIC MAP (WIDTH => LOGPTS+2) + PORT MAP (clk => clk, nGrst => ifiNreset, rst => '0', + cntEn => twidInit_int, Q => slowTimer_w); + -- wEn = 2-clk wide for the RAM to have enough time + twid_wEn_int <= to_logic(slowTimer_w(2 DOWNTO 1) = "11"); + twid_wA_int <= slowTimer_w(LOGPTS+1 DOWNTO 3); + + PROCESS (clk, ifiNreset) + BEGIN + IF (NOT ifiNreset = '1') THEN + twidInit_int <= '1' AFTER timescale; + ELSIF (clk'EVENT AND clk = '1') THEN + rstAfterInit_int <= preRstAfterInit AFTER timescale; + IF (slowTimer_w = allOnes) THEN twidInit_int <='0' AFTER timescale; + END IF; + preRstAfterInit <= to_logic(slowTimer_w = allOnes) AFTER timescale; + END IF; + END PROCESS; +END ARCHITECTURE translated; +-------------------------------------------------------------------------------- +----------------------------------- outBufA ------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.STD_LOGIC_UNSIGNED.all; +USE work.fft_components.all; + +ENTITY outBufA IS + GENERIC (PTS : integer := 256; + LOGPTS : integer := 8 ); + PORT (clk, clkEn, nGrst : IN std_logic; + rst, outBuf_wEn : IN std_logic; + timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + -- host can slow down results reading by lowering the signal + rdCtl : IN std_logic; + wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0); + rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0); + outBuf_rEn, rdValid : OUT std_logic); +END ENTITY outBufA; + +ARCHITECTURE translated OF outBufA IS + CONSTANT timescale : time := 1 ns; + + SIGNAL reverseBitTimer, wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL outBufwEnFall_w : std_logic; + SIGNAL rA_TC_w, preOutBuf_rEn: std_logic; + SIGNAL pipe11, pipe12, pipe21: std_logic; + SIGNAL pipe22, rdCtl_reg : std_logic; + -- Reset a binary counter on the rear edge + SIGNAL rstVhdl, rdValid_int : std_logic; + SIGNAL wA_int : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL rA_int : std_logic_vector(LOGPTS-1 DOWNTO 0); + SIGNAL outBuf_rEn_int : std_logic; + +BEGIN + wA <= wA_int; + rA <= rA_int; + outBuf_rEn <= outBuf_rEn_int; + rdValid <= rdValid_int; + + PROCESS (timer) + VARIABLE reverseBitTimer_int : std_logic_vector(LOGPTS-2 DOWNTO 0); + BEGIN + reverseBitTimer_int := reverseStd(timer); + reverseBitTimer <= reverseBitTimer_int; + END PROCESS; + wA_w <= reverseBitTimer AFTER timescale; + -- rA generator. Detect rear edge of the outBuf wEn + fedge_0 : edgeDetect + GENERIC MAP (INPIPE => 0, FEDGE => 1) + PORT MAP (clk => clk, clkEn => '1', edgeIn => outBuf_wEn, + edgeOut => outBufwEnFall_w); + + rstVhdl <= rst OR outBufwEnFall_w; + + outBuf_rA_0 : counter + GENERIC MAP (WIDTH => LOGPTS, TERMCOUNT =>PTS-1) + PORT MAP (clk => clk, nGrst => nGrst, rst => rstVhdl, + cntEn => rdCtl_reg, tc => rA_TC_w, Q => rA_int); + + PROCESS (clk, nGrst) + BEGIN + -- RS FF preOutBuf_rEn + IF (NOT nGrst = '1') THEN + preOutBuf_rEn <= '0' AFTER timescale; + ELSE + IF (clk'EVENT AND clk = '1') THEN + IF ((rst OR outBuf_wEn OR rA_TC_w) = '1') THEN + preOutBuf_rEn <= '0' AFTER timescale; + ELSE + IF (outBufwEnFall_w = '1') THEN + preOutBuf_rEn <= '1' AFTER timescale; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN + wA_int <= wA_w AFTER timescale; + rdCtl_reg <= rdCtl AFTER timescale; + outBuf_rEn_int <= pipe12 AFTER timescale; + pipe12 <= pipe11 AFTER timescale; + pipe11 <= preOutBuf_rEn AFTER timescale; + rdValid_int <= pipe22 AFTER timescale; + pipe22 <= pipe21 AFTER timescale; + pipe21 <= preOutBuf_rEn AND rdCtl_reg AFTER timescale; + END IF; + END PROCESS; +END ARCHITECTURE translated; +---------------------------------------------------------------------------------------------- +--********************************** SM TOP ******************************** +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.std_logic_arith.all; +USE work.fft_components.all; + +ENTITY sm_top IS + GENERIC ( PTS : integer := 256; + HALFPTS : integer := 128; + LOGPTS : integer := 8; + LOGLOGPTS : integer := 3; + inBuf_RWDLY : integer := 12 ); + PORT (clk,clkEn : IN std_logic; + ifiStart, ifiNreset : IN std_logic; --sync and async reset + ifiD_valid, ifiRead_y : IN std_logic; + ldA, rA, wA, tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0); + twid_wA, outBuf_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0); + outBuf_rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0); + wEn_even, wEn_odd : OUT std_logic; + preSwCross, twid_wEn : OUT std_logic; + inBuf_wEn, outBuf_wEn : OUT std_logic; + smPong, ldValid : OUT std_logic; + inBuf_rdValid : OUT std_logic; + wLastStage : OUT std_logic; + smStartFFTrd : OUT std_logic; + smStartLoad, ifoLoad : OUT std_logic; + ifoY_valid, ifoY_rdy : OUT std_logic); +END ENTITY sm_top; + +ARCHITECTURE translated OF sm_top IS + CONSTANT timescale : time := 1 ns; + + COMPONENT inBuf_fftA + GENERIC (LOGPTS : integer := 8; + LOGLOGPTS : integer := 3 ); + PORT (clk, clkEn : IN std_logic; + timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + timerTC, lastStage : IN std_logic; + fftDone, swCross : OUT std_logic; + bflyA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0) ); + END COMPONENT; + + COMPONENT inBuf_ldA + GENERIC (PTS : integer := 8; + LOGPTS : integer := 3 ); + PORT ( + clk, clkEn, nGrst : IN std_logic; + startLoad, ifi_dataRdy : IN std_logic; + ifo_loadOn, load_done : OUT std_logic; + ldA : OUT std_logic_vector(LOGPTS-1 DOWNTO 1); + wEn_even, wEn_odd : OUT std_logic; + ldValid : OUT std_logic); + END COMPONENT; + + + COMPONENT outBufA + GENERIC (PTS : integer := 256; + LOGPTS : integer := 8 ); + PORT (clk,clkEn,nGrst : IN std_logic; + rst, outBuf_wEn, rdCtl : IN std_logic; + timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0); + rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0); + outBuf_rEn, rdValid : OUT std_logic); + END COMPONENT; + + COMPONENT rdFFTtimer + GENERIC (LOGPTS : integer := 8; + LOGLOGPTS : integer := 3; + HALFPTS : integer := 128; + inBuf_RWDLY : integer := 12 ); + PORT (clk, cntEn, rst : IN std_logic; + startFFT,fft_runs,nGrst : IN std_logic; + timerTC, lastStage : OUT std_logic; + stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + timer : OUT std_logic_vector(LOGPTS-1 DOWNTO 0); + rdValid : OUT std_logic ); + END COMPONENT; + + COMPONENT twid_rA + GENERIC (LOGPTS : integer := 8; + LOGLOGPTS : integer := 3 ); + PORT ( + clk : IN std_logic; + timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0)); + END COMPONENT; + + COMPONENT twid_wAmod + GENERIC (LOGPTS : integer := 8 ); + PORT (clk, ifiNreset: IN std_logic; + twid_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0); + twid_wEn,twidInit : OUT std_logic; + rstAfterInit : OUT std_logic ); + END COMPONENT; + + COMPONENT wrFFTtimer + GENERIC (LOGPTS : integer := 8; + LOGLOGPTS : integer := 3; + HALFPTS : integer := 128 ); + PORT ( + clk, cntEn, nGrst, rst : IN std_logic; + rstStage, rstTime : IN std_logic; + timerTC, lastStage : OUT std_logic; + stage : OUT std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + timer : OUT std_logic_vector(LOGPTS-2 DOWNTO 0)); + END COMPONENT; + + SIGNAL rTimer_w : std_logic_vector(LOGPTS-1 DOWNTO 0); + SIGNAL wTimer_w, timerT1 : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL rStage_w,wStage_w : std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + SIGNAL stageT1, stageT2 : std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + SIGNAL rLastStage_w : std_logic; + SIGNAL rTimerTC_w : std_logic; + SIGNAL wTimerTC_w : std_logic; + SIGNAL load_done_w : std_logic; + SIGNAL sync_rAwA : std_logic; + SIGNAL fftRd_done_w : std_logic; + SIGNAL preInBuf_wEn : std_logic; + SIGNAL preOutBuf_wEn : std_logic; + SIGNAL trueRst : std_logic; + SIGNAL smBuf_full : std_logic; -- top level SM registers + SIGNAL smFft_rdy : std_logic; -- top level SM registers + SIGNAL smFft_runs : std_logic; -- top level SM registers + -- Reset logic: + -- - On ifiNreset start loading twidLUT. + -- - While it is loading keep global async rst nGrst active + -- - Once load is over issue short rstAfterInit which is just another ifiStart + SIGNAL initRst, nGrst : std_logic; + SIGNAL rstAfterInit : std_logic; + SIGNAL trueRst_w : std_logic; + SIGNAL xhdl_27, rdTimer_cntEn : std_logic; + SIGNAL port_xhdl37 : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL ldA_xhdl1 : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL rA_xhdl2 : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL wA_xhdl3 : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL tA_xhdl4 : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL twid_wA_xhdl5 : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL outBuf_wA_xhdl6 : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL outBuf_rA_xhdl7 : std_logic_vector(LOGPTS-1 DOWNTO 0); + SIGNAL wEn_even_xhdl8 : std_logic; + SIGNAL wEn_odd_xhdl9 : std_logic; + SIGNAL preSwCross_xhdl10 : std_logic; + SIGNAL twid_wEn_xhdl11 : std_logic; + SIGNAL inBuf_wEn_xhdl12 : std_logic; + SIGNAL outBuf_wEn_xhdl13 : std_logic; + SIGNAL smPong_xhdl14 : std_logic; + SIGNAL ldValid_xhdl15 : std_logic; + SIGNAL inBuf_rdValid_int : std_logic; + SIGNAL wLastStage_xhdl17 : std_logic; + SIGNAL smStartFFTrd_int : std_logic; + SIGNAL smStartLoad_int : std_logic; + SIGNAL ifoLoad_xhdl20 : std_logic; + SIGNAL ifoY_valid_xhdl21 : std_logic; + SIGNAL ifoY_rdy_xhdl22 : std_logic; + SIGNAL smStartLoad_w : std_logic; + +BEGIN + ldA <= ldA_xhdl1; + rA <= rA_xhdl2; + wA <= wA_xhdl3; + tA <= tA_xhdl4; + twid_wA <= twid_wA_xhdl5; + outBuf_wA <= outBuf_wA_xhdl6; + outBuf_rA <= outBuf_rA_xhdl7; + wEn_even <= wEn_even_xhdl8; + wEn_odd <= wEn_odd_xhdl9; + preSwCross <= preSwCross_xhdl10; + twid_wEn <= twid_wEn_xhdl11; + inBuf_wEn <= inBuf_wEn_xhdl12; + outBuf_wEn <= outBuf_wEn_xhdl13; + smPong <= smPong_xhdl14; + ldValid <= ldValid_xhdl15; + inBuf_rdValid <= inBuf_rdValid_int; + wLastStage <= wLastStage_xhdl17; + smStartFFTrd <= smStartFFTrd_int; + smStartLoad <= smStartLoad_int; + ifoLoad <= ifoLoad_xhdl20; + ifoY_valid <= ifoY_valid_xhdl21; + ifoY_rdy <= ifoY_rdy_xhdl22; + nGrst <= ifiNreset AND (NOT initRst) ; + trueRst_w <= rstAfterInit OR ifiStart ; + -- Top SM outputs + smStartFFTrd_int <= smBuf_full AND smFft_rdy ; + -- Start loading on FFT start or initially on trueRst. + smStartLoad_w <= trueRst_w OR smStartFFTrd_int ; + -- To prevent fake ifoY_rdy and ifoY_valid do not let rdFFTTimer run + -- outside smFft_runs + rdTimer_cntEn <= clkEn AND (smFft_runs OR smStartFFTrd_int); + + -- FFT read inBuf timer + rdFFTtimer_0 : rdFFTtimer + GENERIC MAP (LOGPTS => LOGPTS, + LOGLOGPTS => LOGLOGPTS, + HALFPTS => HALFPTS, + inBuf_RWDLY => inBuf_RWDLY ) + PORT MAP ( + clk => clk, + cntEn => rdTimer_cntEn, + nGrst => nGrst, + rst => trueRst, + startFFT => smStartFFTrd_int, + timer => rTimer_w, + timerTC => rTimerTC_w, + stage => rStage_w, + lastStage => rLastStage_w, + fft_runs => smFft_runs, + rdValid => inBuf_rdValid_int); + + -- FFT write inBuf timer + sync_rAwA <= To_logic(rTimer_w = CONV_STD_LOGIC_VECTOR(inBuf_RWDLY, LOGPTS-1)) ; + xhdl_27 <= sync_rAwA OR smStartFFTrd_int; + wrFFTtimer_0 : wrFFTtimer + GENERIC MAP (LOGPTS => LOGPTS, + LOGLOGPTS => LOGLOGPTS, + HALFPTS => HALFPTS ) + PORT MAP ( + clk => clk, + rst => trueRst, + nGrst => nGrst, + rstStage => smStartFFTrd_int, + rstTime => xhdl_27, + cntEn => clkEn, + timer => wTimer_w, + timerTC => wTimerTC_w, + stage => wStage_w, + lastStage => wLastStage_xhdl17); + + --inData strobe + --out; inBuf is ready for new data (PTS new samples) + --out; tells topSM the buffer is fully loaded and ready for FFTing + inBuf_ldA_0 : inBuf_ldA + GENERIC MAP (PTS => PTS, + LOGPTS => LOGPTS ) + PORT MAP ( + clk => clk, + clkEn => clkEn, + nGrst => nGrst, + startLoad => smStartLoad_int, + ifi_dataRdy => ifiD_valid, + ifo_loadOn => ifoLoad_xhdl20, + load_done => load_done_w, + ldA => ldA_xhdl1, + wEn_even => wEn_even_xhdl8, + wEn_odd => wEn_odd_xhdl9, + ldValid => ldValid_xhdl15); + + port_xhdl37 <= rTimer_w(LOGPTS-2 DOWNTO 0); + inBuf_rA_0 : inBuf_fftA + GENERIC MAP (LOGPTS => LOGPTS, + LOGLOGPTS => LOGLOGPTS ) + PORT MAP ( + clk => clk, + clkEn => clkEn, + timer => port_xhdl37, + stage => rStage_w, + timerTC => rTimerTC_w, + lastStage => rLastStage_w, + fftDone => fftRd_done_w, + bflyA => rA_xhdl2, + swCross => preSwCross_xhdl10); -- out + + twid_rA_0 : twid_rA + GENERIC MAP (LOGPTS => LOGPTS, + LOGLOGPTS => LOGLOGPTS ) + PORT MAP ( + clk => clk, + timer => timerT1, + stage => stageT2, + tA => tA_xhdl4); + + -- Twiddle LUT initialization + twid_wA_0 : twid_wAmod + GENERIC MAP (LOGPTS => LOGPTS ) + PORT MAP ( + clk => clk, + ifiNreset => ifiNreset, + twid_wA => twid_wA_xhdl5, + twid_wEn => twid_wEn_xhdl11, + twidInit => initRst, + rstAfterInit => rstAfterInit); + + -- wA generator. On the last stage the fftRd_done comes before the last + -- FFT results get written back to the inBuf, but it is not necessary since + -- the results get written into the output buffer. + inBuf_wA_0 : inBuf_fftA + GENERIC MAP (LOGPTS => LOGPTS, + LOGLOGPTS => LOGLOGPTS ) + PORT MAP ( + clk => clk, + clkEn => clkEn, + timer => wTimer_w, + stage => wStage_w, + timerTC => wTimerTC_w, + lastStage => wLastStage_xhdl17, + fftDone => open, + bflyA => wA_xhdl3, + swCross => open); + + outBufA_0 : outBufA + GENERIC MAP (PTS => PTS, + LOGPTS => LOGPTS ) + PORT MAP ( + clk => clk, + clkEn => clkEn, + nGrst => nGrst, + rst => trueRst, + timer => wTimer_w, + outBuf_wEn => outBuf_wEn_xhdl13, + rdCtl => ifiRead_y, + wA => outBuf_wA_xhdl6, + rA => outBuf_rA_xhdl7, + outBuf_rEn => ifoY_rdy_xhdl22, + rdValid => ifoY_valid_xhdl21); + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN -- pipes + trueRst <= trueRst_w AFTER timescale; + smStartLoad_int <= smStartLoad_w AFTER timescale; + timerT1 <= rTimer_w(LOGPTS-2 DOWNTO 0) AFTER timescale; + stageT1 <= rStage_w AFTER timescale; + stageT2 <= stageT1 AFTER timescale; + inBuf_wEn_xhdl12 <= preInBuf_wEn AFTER timescale; + outBuf_wEn_xhdl13 <= preOutBuf_wEn AFTER timescale; + END IF; + END PROCESS; + + PROCESS (clk, nGrst) + BEGIN + IF (NOT nGrst = '1') THEN -- reset topSM + smBuf_full <= '0'; + smFft_rdy <= '0'; + smFft_runs <= '0'; + smPong_xhdl14 <= '1'; + preInBuf_wEn <= '0'; + preOutBuf_wEn <= '0'; + --nGrst + ELSIF (clk'EVENT AND clk = '1') THEN + --mark A + IF (trueRst = '1') THEN + -- reset topSM + smBuf_full <= '0' AFTER timescale; + smFft_rdy <= '1' AFTER timescale; + smFft_runs <= '0' AFTER timescale; + smPong_xhdl14 <= '1' AFTER timescale; + preInBuf_wEn <= '0' AFTER timescale; + preOutBuf_wEn <= '0' AFTER timescale; + ELSE + -- mark B + IF (load_done_w = '1') THEN + smBuf_full <= '1' AFTER timescale; + END IF; + IF (fftRd_done_w = '1') THEN + smFft_rdy <= '1' AFTER timescale; + smFft_runs <= '0' AFTER timescale; + END IF; + IF (smStartFFTrd_int = '1') THEN + smBuf_full <= '0' AFTER timescale; + smFft_rdy <= '0' AFTER timescale; + smFft_runs <= '1' AFTER timescale; + smPong_xhdl14 <= NOT smPong_xhdl14 AFTER timescale; + END IF; + IF (sync_rAwA = '1') THEN + IF (rLastStage_w = '1') THEN + preOutBuf_wEn <= '1' AFTER timescale; + ELSE + IF (smFft_runs = '1') THEN + preInBuf_wEn <= '1' AFTER timescale; + END IF; + END IF; + END IF; + IF (wTimerTC_w = '1') THEN + preInBuf_wEn <= '0' AFTER timescale; + preOutBuf_wEn <= '0' AFTER timescale; + END IF; + END IF; + -- mark B + END IF; + -- mark A + END PROCESS; +END ARCHITECTURE translated; +------------------------------------------------------------------------------ diff --git a/lib/lpp/dsp/lpp_fft_rtax/fftTop.vhd b/lib/lpp/dsp/lpp_fft_rtax/fftTop.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/fftTop.vhd @@ -0,0 +1,356 @@ +-------------------------------------------------------------------------------- +-- Copyright 2007 Actel Corporation. All rights reserved. + +-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN +-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED +-- IN ADVANCE IN WRITING. + +-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release +-- File: fftTop.vhd +-- Description: CoreFFT +-- Top level FFT module +-- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production +-- Notes: FFT In/out pins: +-- Input | Output | Comments +-- ------------+------------+------------------ +-- clk | ifoPong | +-- ifiNreset | |async reset active low +-- start | |sync reset active high +-- Load Input data group | +-- d_im[15:0] | load |when high the inBuf is being loaded +-- d_re[15:0] | | +-- d_valid | | +-- Upload Output data group | +-- read_y | y_im[15:0] | +-- | y_re[15:0] | +-- | y_valid |marks a new output sample) +-- | y_rdy |when high the results are being uploaded +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +USE work.fft_components.all; + +ENTITY fftTop IS + GENERIC ( + LOGPTS : integer := gLOGPTS; + LOGLOGPTS : integer := gLOGLOGPTS; + WSIZE : integer := gWSIZE; + TWIDTH : integer := gTWIDTH; + DWIDTH : integer := gDWIDTH; + TDWIDTH : integer := gTDWIDTH; + RND_MODE : integer := gRND_MODE; + SCALE_MODE : integer := gSCALE_MODE; + PTS : integer := gPTS; + HALFPTS : integer := gHALFPTS; + inBuf_RWDLY : integer := gInBuf_RWDLY ); + PORT ( + clk,ifiStart,ifiNreset : IN std_logic; + ifiD_valid, ifiRead_y : IN std_logic; + ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0); + ifoLoad, ifoPong : OUT std_logic; + ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0); + ifoY_valid, ifoY_rdy : OUT std_logic); +END ENTITY fftTop; + +ARCHITECTURE translated OF fftTop IS + + COMPONENT autoScale + GENERIC (SCALE_MODE : integer := 1 ); + PORT (clk, clkEn, wLastStage : IN std_logic; + ldRiskOV, bflyRiskOV : IN std_logic; + startLoad, ifo_loadOn : IN std_logic; + bflyOutValid, startFFT : IN std_logic; + wEn_even, wEn_odd : IN std_logic; + upScale : OUT std_logic); + END COMPONENT; + + COMPONENT bfly2 + GENERIC ( RND_MODE : integer := 0; + WSIZE : integer := 16; + DWIDTH : integer := 32; + TWIDTH : integer := 16; + TDWIDTH : integer := 32 ); + PORT (clk, validIn : IN std_logic; + swCrossIn : IN std_logic; + upScale : IN std_logic; + inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + T : IN std_logic_vector(TDWIDTH-1 DOWNTO 0); + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0); + validOut, swCrossOut : OUT std_logic); + END COMPONENT; + + COMPONENT sm_top + GENERIC ( PTS : integer := 256; + HALFPTS : integer := 128; + LOGPTS : integer := 8; + LOGLOGPTS : integer := 3; + inBuf_RWDLY : integer := 12 ); + PORT (clk,clkEn : IN std_logic; + ifiStart, ifiNreset : IN std_logic; + ifiD_valid, ifiRead_y : IN std_logic; + ldA, rA, wA, tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0); + twid_wA, outBuf_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0); + outBuf_rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0); + wEn_even, wEn_odd : OUT std_logic; + preSwCross, twid_wEn : OUT std_logic; + inBuf_wEn, outBuf_wEn : OUT std_logic; + smPong, ldValid : OUT std_logic; + inBuf_rdValid : OUT std_logic; + wLastStage : OUT std_logic; + smStartFFTrd : OUT std_logic; + smStartLoad, ifoLoad : OUT std_logic; + ifoY_valid, ifoY_rdy : OUT std_logic); + END COMPONENT; + + COMPONENT twiddle + PORT (A : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + T : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT pipoBuffer + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT ( + clk, clkEn, pong, rEn : IN std_logic; + rA, wA_load, wA_bfly : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + wEn_bfly,wEn_even,wEn_odd : IN std_logic; + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) ); + END COMPONENT; + + COMPONENT switch + GENERIC ( DWIDTH : integer := 16 ); + PORT (clk, sel, validIn : IN std_logic; + inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0); + validOut : OUT std_logic); + END COMPONENT; + + COMPONENT twidLUT + GENERIC ( LOGPTS : integer := 8; + TDWIDTH : integer := 32 ); + PORT (clk, wEn : IN std_logic; + wA, rA : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + D : IN std_logic_vector(TDWIDTH-1 DOWNTO 0); + Q : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT outBuff + GENERIC ( LOGPTS : integer := 8; + DWIDTH : integer := 32 ); + PORT (clk, clkEn, wEn : IN std_logic; + inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + rA : IN std_logic_vector(LOGPTS-1 DOWNTO 0); + outD : OUT std_logic_vector(DWIDTH-1 DOWNTO 0)); + END COMPONENT; + + SIGNAL ldA_w, rA_w : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL wA_w, tA_w : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL twid_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL outBuf_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0); + SIGNAL outBuf_rA_w : std_logic_vector(LOGPTS-1 DOWNTO 0); + SIGNAL wEn_even_w : std_logic; + SIGNAL wEn_odd_w : std_logic; + SIGNAL inBuf_wEn_w : std_logic; + SIGNAL preSwCross_w : std_logic; + SIGNAL postSwCross_w : std_logic; + SIGNAL twid_wEn_w : std_logic; + SIGNAL outBuf_wEn_w : std_logic; + SIGNAL ldRiskOV_w : std_logic; + SIGNAL bflyRiskOV_w : std_logic; + SIGNAL readP_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL readQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL bflyInP_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL bflyInQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL bflyOutP_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL bflyOutQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL T_w : std_logic_vector(TDWIDTH-1 DOWNTO 0); + SIGNAL twidData_w : std_logic_vector(TDWIDTH-1 DOWNTO 0); + SIGNAL outEven_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL outOdd_w : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL inBufValid_w : std_logic; + SIGNAL preSwValid_w : std_logic; + SIGNAL bflyValid_w : std_logic; + SIGNAL wLastStage_w : std_logic; + SIGNAL startFFTrd_w : std_logic; + SIGNAL startLoad_w : std_logic; + SIGNAL upScale_w : std_logic; + SIGNAL port_xhdl15 : std_logic; + SIGNAL xhdl_17 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL xhdl_23 : std_logic_vector(DWIDTH-1 DOWNTO 0); + SIGNAL clkEn_const : std_logic; + SIGNAL ifoLoad_xhdl1 : std_logic; + SIGNAL ifoY_im_xhdl2 : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL ifoY_re_xhdl3 : std_logic_vector(WSIZE-1 DOWNTO 0); + SIGNAL ifoPong_xhdl4 : std_logic; + SIGNAL ifoY_valid_xhdl5 : std_logic; + SIGNAL ifoY_rdy_xhdl6 : std_logic; + SIGNAL displayBflyOutP : std_logic; + SIGNAL displayBflyOutQ : std_logic; + SIGNAL displayInBuf_wEn : std_logic; + SIGNAL ldValid_w : std_logic; + +BEGIN + ifoLoad <= ifoLoad_xhdl1; + ifoY_im <= ifoY_im_xhdl2; + ifoY_re <= ifoY_re_xhdl3; + ifoPong <= ifoPong_xhdl4; + ifoY_valid <= ifoY_valid_xhdl5; + ifoY_rdy <= ifoY_rdy_xhdl6; + -- debug only + displayBflyOutP <= bflyOutP_w(0) ; + displayBflyOutQ <= bflyOutQ_w(0) ; + displayInBuf_wEn <= inBuf_wEn_w ; + port_xhdl15 <= '1'; + + smTop_0 : sm_top + GENERIC MAP ( PTS => PTS, HALFPTS => HALFPTS, + LOGPTS => LOGPTS, LOGLOGPTS => LOGLOGPTS, inBuf_RWDLY => inBuf_RWDLY ) + PORT MAP ( + clk => clk, + clkEn => port_xhdl15, + ifiStart => ifiStart, + ifiNreset => ifiNreset, + ifiD_valid => ifiD_valid, + ifiRead_y => ifiRead_y, + ldA => ldA_w, + rA => rA_w, + wA => wA_w, + tA => tA_w, + twid_wA => twid_wA_w, + outBuf_wA => outBuf_wA_w, + outBuf_rA => outBuf_rA_w, + wEn_even => wEn_even_w, + wEn_odd => wEn_odd_w, + preSwCross => preSwCross_w, + twid_wEn => twid_wEn_w, + inBuf_wEn => inBuf_wEn_w, + outBuf_wEn => outBuf_wEn_w, + smPong => ifoPong_xhdl4, + ldValid => ldValid_w, + inBuf_rdValid => inBufValid_w, + wLastStage => wLastStage_w, + smStartFFTrd => startFFTrd_w, + smStartLoad => startLoad_w, + ifoLoad => ifoLoad_xhdl1, + ifoY_valid => ifoY_valid_xhdl5, + ifoY_rdy => ifoY_rdy_xhdl6); + + xhdl_17 <= ifiD_im & ifiD_re; + + inBuf_0 : pipoBuffer + GENERIC MAP ( LOGPTS => LOGPTS, + DWIDTH => DWIDTH ) + PORT MAP ( + clk => clk, + clkEn => '1', + rEn => '1', + rA => rA_w, + wA_load => ldA_w, + wA_bfly => wA_w, + ldData => xhdl_17, + wP_bfly => outEven_w, + wQ_bfly => outOdd_w, + wEn_bfly => inBuf_wEn_w, + wEn_even => wEn_even_w, + wEn_odd => wEn_odd_w, + pong => ifoPong_xhdl4, + outP => readP_w, + outQ => readQ_w); + + preBflySw_0 : switch + GENERIC MAP ( DWIDTH => DWIDTH ) + PORT MAP ( + clk => clk, + inP => readP_w, + inQ => readQ_w, + sel => preSwCross_w, + outP => bflyInP_w, + outQ => bflyInQ_w, + validIn => inBufValid_w, + validOut => preSwValid_w); + + bfly_0 : bfly2 + GENERIC MAP (RND_MODE => RND_MODE, WSIZE => WSIZE, DWIDTH => DWIDTH, + TWIDTH => TWIDTH, TDWIDTH => TDWIDTH ) + PORT MAP ( + clk => clk, + upScale => upScale_w, + inP => bflyInP_w, + inQ => bflyInQ_w, + T => T_w, + outP => bflyOutP_w, + outQ => bflyOutQ_w, + validIn => preSwValid_w, + validOut => bflyValid_w, + swCrossIn => preSwCross_w, + swCrossOut => postSwCross_w); + + lut_0 : twiddle + PORT MAP (A => twid_wA_w, T => twidData_w); + + twidLUT_1 : twidLUT + GENERIC MAP ( LOGPTS => LOGPTS, TDWIDTH => TDWIDTH ) + PORT MAP ( + clk => clk, + wA => twid_wA_w, + wEn => twid_wEn_w, + rA => tA_w, + D => twidData_w, + Q => T_w); + + postBflySw_0 : switch + GENERIC MAP ( DWIDTH => DWIDTH ) + PORT MAP ( + clk => clk, + inP => bflyOutP_w, + inQ => bflyOutQ_w, + sel => postSwCross_w, + outP => outEven_w, + outQ => outOdd_w, + validIn => bflyValid_w, + validOut => open); + + ifoY_im_xhdl2 <= xhdl_23(DWIDTH-1 DOWNTO WSIZE); + ifoY_re_xhdl3 <= xhdl_23(WSIZE-1 DOWNTO 0); + outBuff_0 : outBuff + GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH ) + PORT MAP ( + clk => clk, clkEn => '1', + rA => outBuf_rA_w, + wA => outBuf_wA_w, + inP => outEven_w, + inQ => outOdd_w, + wEn => outBuf_wEn_w, + outD => xhdl_23); + + -- Autoscaling + -- monitor if input data .im and .re have MSB == sign + ldRiskOV_w <= to_logic( + NOT ((ifiD_im(WSIZE-1) = ifiD_im(WSIZE-2)) + AND (ifiD_re(WSIZE-1) = ifiD_re(WSIZE-2))) ); + + bflyRiskOV_w <= to_logic( + NOT ((((bflyOutP_w(DWIDTH-1) = bflyOutP_w(DWIDTH- 2)) + AND (bflyOutP_w(WSIZE-1) = bflyOutP_w(WSIZE-2))) + AND (bflyOutQ_w(DWIDTH-1) = bflyOutQ_w(DWIDTH-2))) + AND (bflyOutQ_w(WSIZE-1) = bflyOutQ_w(WSIZE-2))) ); + clkEn_const <= '1'; + autoScale_0 : autoScale + GENERIC MAP (SCALE_MODE => SCALE_MODE) + PORT MAP ( + clk => clk, + clkEn => clkEn_const, + ldRiskOV => ldRiskOV_w, + bflyRiskOV => bflyRiskOV_w, + startLoad => startLoad_w, + startFFT => startFFTrd_w, + bflyOutValid => bflyValid_w, + wLastStage => wLastStage_w, + wEn_even => wEn_even_w, + wEn_odd => wEn_odd_w, + ifo_loadOn => ifoLoad_xhdl1, + upScale => upScale_w); + +END ARCHITECTURE translated; diff --git a/lib/lpp/dsp/lpp_fft_rtax/fft_components.vhd b/lib/lpp/dsp/lpp_fft_rtax/fft_components.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/fft_components.vhd @@ -0,0 +1,164 @@ +-------------------------------------------------------------------------------- +-- Copyright 2007 Actel Corporation. All rights reserved. + +-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN +-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED +-- IN ADVANCE IN WRITING. + +-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release +-- Package: fft_components.vhd +-- Description: CoreFFT +-- Core package +-- Rev: 0.1 8/31/2005 12:54PM VD : Pre Production +-- +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +USE IEEE.numeric_std.all; +USE std.textio.all; +USE IEEE.STD_LOGIC_TEXTIO.all; + +package FFT_COMPONENTS is + CONSTANT gPTS : integer:=256; --Number of FFT points + CONSTANT gLOGPTS : integer:=8; --Log2(PTS) + CONSTANT gLOGLOGPTS : integer:=3; --Stage counter width +------------------------------------------------- + CONSTANT gWSIZE : integer:=16; -- FFT bit resolution; length of a re or im sample + CONSTANT gTWIDTH : integer:=16; -- Twiddle, sin or cos bit resolution + CONSTANT gHALFPTS : integer:=gPTS/2; -- Num of FFT points (PTS) divided by 2 + CONSTANT gDWIDTH : integer:=2*gWSIZE; -- width of a complex input word, + CONSTANT gTDWIDTH : integer:=2*gTWIDTH; -- width of a complex twiddle factor + CONSTANT gRND_MODE : integer:=1; -- enable product rounding + CONSTANT gSCALE_MODE : integer:=0; -- scale mode + CONSTANT gInBuf_RWDLY : integer:=12; + + function to_logic ( x : integer) return std_logic; + function to_logic ( x : boolean) return std_logic; + FUNCTION to_integer( sig : std_logic_vector) return integer; + function to_integer( x : boolean) return integer; + function maskbar (barn, bar_enable,dma_reg_bar,dma_reg_loc : integer) return integer; + function anyfifo (bar0, bar1, bar2, bar3, bar4, bar5 : integer) return integer; + FUNCTION reverse (x : std_logic_vector) RETURN bit_vector; + FUNCTION reverseStd(x : std_logic_vector) RETURN std_logic_vector; + + COMPONENT counter + GENERIC ( + WIDTH : integer := 7; + TERMCOUNT : integer := 127 ); + PORT ( + clk, nGrst, rst, cntEn : IN std_logic; + tc : OUT std_logic; + Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT bcounter + GENERIC ( + WIDTH : integer := 7); + PORT ( + clk, nGrst, rst, cntEn : IN std_logic; + Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) ); + END COMPONENT; + + COMPONENT edgeDetect + GENERIC ( + INPIPE :integer := 0; --if (INPIPE==1) insert input pipeline reg + FEDGE :integer := 0);--If FEDGE==1 detect falling edge, else-rising edge + PORT ( + clk, clkEn, edgeIn : IN std_logic; + edgeOut : OUT std_logic); + END COMPONENT; + +end FFT_COMPONENTS; + +package body FFT_COMPONENTS is + + function to_logic ( x : integer) return std_logic is + variable y : std_logic; + begin + if x = 0 then + y := '0'; + else + y := '1'; + end if; + return y; + end to_logic; + + function to_logic( x : boolean) return std_logic is + variable y : std_logic; + begin + if x then + y := '1'; + else + y := '0'; + end if; + return(y); + end to_logic; + +-- added 081805 + function to_integer(sig : std_logic_vector) return integer is + variable num : integer := 0; -- descending sig as integer + begin + for i in sig'range loop + if sig(i)='1' then + num := num*2+1; + else -- use anything other than '1' as '0' + num := num*2; + end if; + end loop; -- i + return num; + end function to_integer; + + function to_integer( x : boolean) return integer is + variable y : integer; + begin + if x then + y := 1; + else + y := 0; + end if; + return(y); + end to_integer; + + function maskbar (barn, bar_enable,dma_reg_bar,dma_reg_loc : integer) return integer is + begin + if ( dma_reg_loc>= 2 and barn=dma_reg_bar) then + return(0); + else + return(bar_enable); + end if; + end maskbar; + + + function anyfifo ( bar0, bar1, bar2, bar3, bar4, bar5 : integer) return integer is + begin + if ( bar0=2 or bar1=2 or bar2=2 or bar3=2 or bar4=2 or bar5=2) then + return(1); + else + return(0); + end if; + end anyfifo; + + FUNCTION reverse (x :IN std_logic_vector) + RETURN bit_vector IS + VARIABLE i : integer; + VARIABLE reverse : bit_vector(x'HIGH DOWNTO x'LOW); + BEGIN + FOR i IN x'range LOOP + reverse(i) := To_bit( x(x'HIGH - i)); + END LOOP; + RETURN(reverse); + END FUNCTION reverse; + + FUNCTION reverseStd (x :IN std_logic_vector) + RETURN std_logic_vector IS + VARIABLE i : integer; + VARIABLE reverse : std_logic_vector(x'HIGH DOWNTO x'LOW); + BEGIN + FOR i IN x'range LOOP + reverse(i) := x(x'HIGH - i); + END LOOP; + RETURN(reverse); + END FUNCTION reverseStd; + +end FFT_COMPONENTS; diff --git a/lib/lpp/dsp/lpp_fft_rtax/lpp_fft.vhd b/lib/lpp/dsp/lpp_fft_rtax/lpp_fft.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/lpp_fft.vhd @@ -0,0 +1,260 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use std.textio.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.fft_components.all; + +--! Package contenant tous les programmes qui forment le composant intégré dans le léon + +package lpp_fft is + +component APB_FFT is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + Data_sz : integer := 16 + ); + port ( + clk : in std_logic; + rst : in std_logic; --! Reset general du composant + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type + ); +end component; + + +component APB_FFT_half is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + Data_sz : integer := 16 + ); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + Ren : in std_logic; + ready : out std_logic; + valid : out std_logic; + DataOut_re : out std_logic_vector(Data_sz-1 downto 0); + DataOut_im : out std_logic_vector(Data_sz-1 downto 0); + OUTfill : out std_logic; + OUTwrite : out std_logic; + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + ); +end component; + +component FFT is + generic( + Data_sz : integer := 16; + NbData : integer := 256); + port( + clkm : in std_logic; + rstn : in std_logic; + FifoIN_Empty : in std_logic_vector(4 downto 0); + FifoIN_Data : in std_logic_vector(79 downto 0); + FifoOUT_Full : in std_logic_vector(4 downto 0); + Load : out std_logic; + Read : out std_logic_vector(4 downto 0); + Write : out std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + Data : out std_logic_vector(79 downto 0) + ); +end component; + +component Flag_Extremum is + port( + clk,raz : in std_logic; --! Horloge et Reset général du composant + load : in std_logic; --! Signal en provenance de CoreFFT + y_rdy : in std_logic; --! Signal en provenance de CoreFFT + fill : out std_logic; --! Flag, Va permettre d'autoriser l'écriture (Driver C) + ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C) + ); +end component; + + +component Linker_FFT is +generic( + Data_sz : integer range 1 to 32 := 16; + NbData : integer range 1 to 512 := 256 + ); +port( + clk : in std_logic; + rstn : in std_logic; + Ready : in std_logic; + Valid : in std_logic; + Full : in std_logic_vector(4 downto 0); + Data_re : in std_logic_vector(Data_sz-1 downto 0); + Data_im : in std_logic_vector(Data_sz-1 downto 0); + Read : out std_logic; + Write : out std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + DATA : out std_logic_vector((5*Data_sz)-1 downto 0) +); +end component; + + +component Driver_FFT is +generic( + Data_sz : integer range 1 to 32 := 16; + NbData : integer range 1 to 512 := 256 + ); +port( + clk : in std_logic; + rstn : in std_logic; + Load : in std_logic; + Empty : in std_logic_vector(4 downto 0); + DATA : in std_logic_vector((5*Data_sz)-1 downto 0); + Valid : out std_logic; + Read : out std_logic_vector(4 downto 0); + Data_re : out std_logic_vector(Data_sz-1 downto 0); + Data_im : out std_logic_vector(Data_sz-1 downto 0) +); +end component; + +component FFTamont is +generic( + Data_sz : integer range 1 to 32 := 16; + NbData : integer range 1 to 512 := 256 + ); +port( + clk : in std_logic; + rstn : in std_logic; + Load : in std_logic; + Empty : in std_logic; + DATA : in std_logic_vector(Data_sz-1 downto 0); + Valid : out std_logic; + Read : out std_logic; + Data_re : out std_logic_vector(Data_sz-1 downto 0); + Data_im : out std_logic_vector(Data_sz-1 downto 0) +); +end component; + +component FFTaval is +generic( + Data_sz : integer range 1 to 32 := 8; + NbData : integer range 1 to 512 := 256 + ); +port( + clk : in std_logic; + rstn : in std_logic; + Ready : in std_logic; + Valid : in std_logic; + Full : in std_logic; + Data_re : in std_logic_vector(Data_sz-1 downto 0); + Data_im : in std_logic_vector(Data_sz-1 downto 0); + Read : out std_logic; + Write : out std_logic; + ReUse : out std_logic; + DATA : out std_logic_vector(Data_sz-1 downto 0) +); +end component; +--==============================================================| +--================== IP VHDL de la FFT actel ===================| +--================ non partagé dans la VHD_Lib =================| +--==============================================================| + +component CoreFFT IS + GENERIC ( + LOGPTS : integer := gLOGPTS; + LOGLOGPTS : integer := gLOGLOGPTS; + WSIZE : integer := gWSIZE; + TWIDTH : integer := gTWIDTH; + DWIDTH : integer := gDWIDTH; + TDWIDTH : integer := gTDWIDTH; + RND_MODE : integer := gRND_MODE; + SCALE_MODE : integer := gSCALE_MODE; + PTS : integer := gPTS; + HALFPTS : integer := gHALFPTS; + inBuf_RWDLY : integer := gInBuf_RWDLY ); + PORT ( + clk,ifiStart,ifiNreset : IN std_logic; + ifiD_valid, ifiRead_y : IN std_logic; + ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0); + ifoLoad, ifoPong : OUT std_logic; + ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0); + ifoY_valid, ifoY_rdy : OUT std_logic); +END component; + + + component actar is + port( DataA : in std_logic_vector(15 downto 0); DataB : in + std_logic_vector(15 downto 0); Mult : out + std_logic_vector(31 downto 0);Clock : in std_logic) ; + end component; + + component actram is + port( DI : in std_logic_vector(31 downto 0); DO : out + std_logic_vector(31 downto 0);WRB, RDB : in std_logic; + WADDR : in std_logic_vector(6 downto 0); RADDR : in + std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in + std_logic) ; + end component; + + component switch IS + GENERIC ( DWIDTH : integer := 32 ); + PORT ( + clk, sel, validIn : IN std_logic; + inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0); + outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0); + validOut : OUT std_logic); + END component; + + component twid_rA IS + GENERIC (LOGPTS : integer := 8; + LOGLOGPTS : integer := 3 ); + PORT (clk : IN std_logic; + timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0); + stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0); + tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0)); + END component; + + component counter IS + GENERIC ( + WIDTH : integer := 7; + TERMCOUNT : integer := 127 ); + PORT ( + clk, nGrst, rst, cntEn : IN std_logic; + tc : OUT std_logic; + Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) ); + END component; + + + component twiddle IS + PORT ( + A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0); + T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0)); + END component; + + +end; \ No newline at end of file diff --git a/lib/lpp/dsp/lpp_fft_rtax/primitives.vhd b/lib/lpp/dsp/lpp_fft_rtax/primitives.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/primitives.vhd @@ -0,0 +1,133 @@ +-------------------------------------------------------------------------------- +-- Copyright 2007 Actel Corporation. All rights reserved. + +-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN +-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED +-- IN ADVANCE IN WRITING. + +-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release +-- File: primitives.vhd +-- Description: CoreFFT +-- FFT primitives module +-- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production +-- +-- +-------------------------------------------------------------------------------- +-- counts up to TERMCOUNT, then jumps to 0. +-- Generates tc signal on count==TERMCOUNT-1 +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.numeric_std.all; +USE work.fft_components.all; + +ENTITY counter IS + GENERIC ( + WIDTH : integer := 7; + TERMCOUNT : integer := 127 ); + PORT ( + clk, nGrst, rst, cntEn : IN std_logic; + tc : OUT std_logic; + Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) ); +END ENTITY counter; + +ARCHITECTURE translated OF counter IS + SIGNAL tc_out : std_logic; + SIGNAL Q_out : unsigned(WIDTH-1 DOWNTO 0); + +BEGIN + tc <= tc_out; + Q <= std_logic_vector(Q_out); + PROCESS (clk, nGrst) + BEGIN + IF (nGrst = '0') THEN + Q_out <= (OTHERS => '0'); + tc_out <= '0'; + ELSIF (clk'EVENT AND clk = '1') THEN -- nGrst!=0 + IF (rst = '1') THEN + Q_out <= (OTHERS => '0'); + tc_out <= '0'; + ELSE + IF (cntEn = '1') THEN -- start cntEn + tc_out <= to_logic( Q_out = to_unsigned((TERMCOUNT-1),WIDTH)); + IF (Q_out = to_unsigned(TERMCOUNT, WIDTH)) THEN + Q_out <= (OTHERS => '0'); + ELSE + Q_out <= unsigned(Q_out) + to_unsigned(1, WIDTH); + END IF; + END IF; -- end cntEn + END IF; -- end rst + END IF; -- end nGrst + END PROCESS; +END ARCHITECTURE translated; + +-------------------------------------------------------------------------- +-- binary counter with no feedback. Counts up to 2^WIDTH - 1 +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.numeric_std.all; + +ENTITY bcounter IS + GENERIC (WIDTH : integer:=7 ); + PORT (clk, nGrst, rst, cntEn : IN std_logic; + Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0)); +END ENTITY bcounter; + +ARCHITECTURE translated OF bcounter IS + SIGNAL Q_out : unsigned(WIDTH-1 DOWNTO 0); + +BEGIN + Q <= std_logic_vector(Q_out); + PROCESS (clk, nGrst) + BEGIN + IF (nGrst = '0') THEN + Q_out <= (OTHERS => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (cntEn = '1') THEN + IF (rst = '1') THEN + Q_out <= (OTHERS => '0'); + ELSE + Q_out <= unsigned(Q_out) + to_unsigned(1, WIDTH); + END IF; + END IF; + END IF; + END PROCESS; +END ARCHITECTURE translated; +-------------------------------------------------------------------------- +-- rising-falling edge detector +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; + +ENTITY edgeDetect IS + GENERIC ( + INPIPE :integer := 0; --if (INPIPE==1) insert input pipeline reg + FEDGE :integer := 0);--If FEDGE==1 detect falling edge, else-rising edge + PORT ( + clk, clkEn, edgeIn : IN std_logic; + edgeOut : OUT std_logic); +END ENTITY edgeDetect; + +ARCHITECTURE translated OF edgeDetect IS + SIGNAL in_pipe, in_t1 : std_logic; -- regs + SIGNAL temp_input : std_logic; + SIGNAL in_w : std_logic; + SIGNAL temp_output : std_logic; + SIGNAL out_w : std_logic; + SIGNAL output_reg : std_logic; + +BEGIN + edgeOut <= output_reg; + temp_input <= (in_pipe) WHEN INPIPE /= 0 ELSE edgeIn; + in_w <= temp_input ; + temp_output<= + ((NOT in_w) AND in_t1) WHEN FEDGE /= 0 ELSE (in_w AND (NOT in_t1)); + out_w <= temp_output ; + + PROCESS (clk) + BEGIN + IF (clk'EVENT AND clk = '1') THEN + in_pipe <= edgeIn; + in_t1 <= in_w; + output_reg <= out_w; + END IF; + END PROCESS; +END ARCHITECTURE translated; diff --git a/lib/lpp/dsp/lpp_fft_rtax/twiddle.vhd b/lib/lpp/dsp/lpp_fft_rtax/twiddle.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/twiddle.vhd @@ -0,0 +1,171 @@ +-------------------------------------------------------------------------------- +-- Copyright 2007 Actel Corporation. All rights reserved. + +-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN +-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED +-- IN ADVANCE IN WRITING. + +-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release +-- File: twiddle.v +-- +-- Description: CoreFFT +-- Twiddle factor table +-- +-- Rev: 0.1 5/10/2005 8:36AM VD : Pre Production +-- History: 5/10/2005 8:36AM - created +-- +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE work.fft_components.all; + +ENTITY twiddle IS + PORT ( + A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0); + T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0)); +END ENTITY twiddle; + +ARCHITECTURE translated OF twiddle IS + SIGNAL T_int : std_logic_vector(gTDWIDTH-1 DOWNTO 0); + +BEGIN + T <= T_int; + + PROCESS (A) + VARIABLE T_int1 : std_logic_vector(gTDWIDTH-1 DOWNTO 0); + BEGIN + CASE A IS -- synopsys parallel_case + WHEN "0000000" => T_int1 := "00000000000000000111111111111111"; -- X0000 X7fff + WHEN "0000001" => T_int1 := "00000011001001000111111111110101"; -- X0324 X7ff5 + WHEN "0000010" => T_int1 := "00000110010010000111111111011000"; -- X0648 X7fd8 + WHEN "0000011" => T_int1 := "00001001011010100111111110100110"; -- X096a X7fa6 + WHEN "0000100" => T_int1 := "00001100100011000111111101100001"; -- X0c8c X7f61 + WHEN "0000101" => T_int1 := "00001111101010110111111100001001"; -- X0fab X7f09 + WHEN "0000110" => T_int1 := "00010010110010000111111010011100"; -- X12c8 X7e9c + WHEN "0000111" => T_int1 := "00010101111000100111111000011101"; -- X15e2 X7e1d + WHEN "0001000" => T_int1 := "00011000111110010111110110001001"; -- X18f9 X7d89 + WHEN "0001001" => T_int1 := "00011100000010110111110011100011"; -- X1c0b X7ce3 + WHEN "0001010" => T_int1 := "00011111000110100111110000101001"; -- X1f1a X7c29 + WHEN "0001011" => T_int1 := "00100010001000110111101101011100"; -- X2223 X7b5c + WHEN "0001100" => T_int1 := "00100101001010000111101001111100"; -- X2528 X7a7c + WHEN "0001101" => T_int1 := "00101000001001100111100110001001"; -- X2826 X7989 + WHEN "0001110" => T_int1 := "00101011000111110111100010000100"; -- X2b1f X7884 + WHEN "0001111" => T_int1 := "00101110000100010111011101101011"; -- X2e11 X776b + WHEN "0010000" => T_int1 := "00110000111110110111011001000001"; -- X30fb X7641 + WHEN "0010001" => T_int1 := "00110011110111110111010100000100"; -- X33df X7504 + WHEN "0010010" => T_int1 := "00110110101110100111001110110101"; -- X36ba X73b5 + WHEN "0010011" => T_int1 := "00111001100011000111001001010100"; -- X398c X7254 + WHEN "0010100" => T_int1 := "00111100010101100111000011100010"; -- X3c56 X70e2 + WHEN "0010101" => T_int1 := "00111111000101110110111101011110"; -- X3f17 X6f5e + WHEN "0010110" => T_int1 := "01000001110011100110110111001001"; -- X41ce X6dc9 + WHEN "0010111" => T_int1 := "01000100011110100110110000100011"; -- X447a X6c23 + WHEN "0011000" => T_int1 := "01000111000111000110101001101101"; -- X471c X6a6d + WHEN "0011001" => T_int1 := "01001001101101000110100010100110"; -- X49b4 X68a6 + WHEN "0011010" => T_int1 := "01001100001111110110011011001111"; -- X4c3f X66cf + WHEN "0011011" => T_int1 := "01001110101111110110010011101000"; -- X4ebf X64e8 + WHEN "0011100" => T_int1 := "01010001001100110110001011110001"; -- X5133 X62f1 + WHEN "0011101" => T_int1 := "01010011100110110110000011101011"; -- X539b X60eb + WHEN "0011110" => T_int1 := "01010101111101010101111011010111"; -- X55f5 X5ed7 + WHEN "0011111" => T_int1 := "01011000010000100101110010110011"; -- X5842 X5cb3 + WHEN "0100000" => T_int1 := "01011010100000100101101010000010"; -- X5a82 X5a82 + WHEN "0100001" => T_int1 := "01011100101100110101100001000010"; -- X5cb3 X5842 + WHEN "0100010" => T_int1 := "01011110110101110101010111110101"; -- X5ed7 X55f5 + WHEN "0100011" => T_int1 := "01100000111010110101001110011011"; -- X60eb X539b + WHEN "0100100" => T_int1 := "01100010111100010101000100110011"; -- X62f1 X5133 + WHEN "0100101" => T_int1 := "01100100111010000100111010111111"; -- X64e8 X4ebf + WHEN "0100110" => T_int1 := "01100110110011110100110000111111"; -- X66cf X4c3f + WHEN "0100111" => T_int1 := "01101000101001100100100110110100"; -- X68a6 X49b4 + WHEN "0101000" => T_int1 := "01101010011011010100011100011100"; -- X6a6d X471c + WHEN "0101001" => T_int1 := "01101100001000110100010001111010"; -- X6c23 X447a + WHEN "0101010" => T_int1 := "01101101110010010100000111001110"; -- X6dc9 X41ce + WHEN "0101011" => T_int1 := "01101111010111100011111100010111"; -- X6f5e X3f17 + WHEN "0101100" => T_int1 := "01110000111000100011110001010110"; -- X70e2 X3c56 + WHEN "0101101" => T_int1 := "01110010010101000011100110001100"; -- X7254 X398c + WHEN "0101110" => T_int1 := "01110011101101010011011010111010"; -- X73b5 X36ba + WHEN "0101111" => T_int1 := "01110101000001000011001111011111"; -- X7504 X33df + WHEN "0110000" => T_int1 := "01110110010000010011000011111011"; -- X7641 X30fb + WHEN "0110001" => T_int1 := "01110111011010110010111000010001"; -- X776b X2e11 + WHEN "0110010" => T_int1 := "01111000100001000010101100011111"; -- X7884 X2b1f + WHEN "0110011" => T_int1 := "01111001100010010010100000100110"; -- X7989 X2826 + WHEN "0110100" => T_int1 := "01111010011111000010010100101000"; -- X7a7c X2528 + WHEN "0110101" => T_int1 := "01111011010111000010001000100011"; -- X7b5c X2223 + WHEN "0110110" => T_int1 := "01111100001010010001111100011010"; -- X7c29 X1f1a + WHEN "0110111" => T_int1 := "01111100111000110001110000001011"; -- X7ce3 X1c0b + WHEN "0111000" => T_int1 := "01111101100010010001100011111001"; -- X7d89 X18f9 + WHEN "0111001" => T_int1 := "01111110000111010001010111100010"; -- X7e1d X15e2 + WHEN "0111010" => T_int1 := "01111110100111000001001011001000"; -- X7e9c X12c8 + WHEN "0111011" => T_int1 := "01111111000010010000111110101011"; -- X7f09 X0fab + WHEN "0111100" => T_int1 := "01111111011000010000110010001100"; -- X7f61 X0c8c + WHEN "0111101" => T_int1 := "01111111101001100000100101101010"; -- X7fa6 X096a + WHEN "0111110" => T_int1 := "01111111110110000000011001001000"; -- X7fd8 X0648 + WHEN "0111111" => T_int1 := "01111111111101010000001100100100"; -- X7ff5 X0324 + WHEN "1000000" => T_int1 := "01111111111111110000000000000000"; -- X7fff X0000 + WHEN "1000001" => T_int1 := "01111111111101011111110011011100"; -- X7ff5 Xfcdc + WHEN "1000010" => T_int1 := "01111111110110001111100110111000"; -- X7fd8 Xf9b8 + WHEN "1000011" => T_int1 := "01111111101001101111011010010110"; -- X7fa6 Xf696 + WHEN "1000100" => T_int1 := "01111111011000011111001101110100"; -- X7f61 Xf374 + WHEN "1000101" => T_int1 := "01111111000010011111000001010101"; -- X7f09 Xf055 + WHEN "1000110" => T_int1 := "01111110100111001110110100111000"; -- X7e9c Xed38 + WHEN "1000111" => T_int1 := "01111110000111011110101000011110"; -- X7e1d Xea1e + WHEN "1001000" => T_int1 := "01111101100010011110011100000111"; -- X7d89 Xe707 + WHEN "1001001" => T_int1 := "01111100111000111110001111110101"; -- X7ce3 Xe3f5 + WHEN "1001010" => T_int1 := "01111100001010011110000011100110"; -- X7c29 Xe0e6 + WHEN "1001011" => T_int1 := "01111011010111001101110111011101"; -- X7b5c Xdddd + WHEN "1001100" => T_int1 := "01111010011111001101101011011000"; -- X7a7c Xdad8 + WHEN "1001101" => T_int1 := "01111001100010011101011111011010"; -- X7989 Xd7da + WHEN "1001110" => T_int1 := "01111000100001001101010011100001"; -- X7884 Xd4e1 + WHEN "1001111" => T_int1 := "01110111011010111101000111101111"; -- X776b Xd1ef + WHEN "1010000" => T_int1 := "01110110010000011100111100000101"; -- X7641 Xcf05 + WHEN "1010001" => T_int1 := "01110101000001001100110000100001"; -- X7504 Xcc21 + WHEN "1010010" => T_int1 := "01110011101101011100100101000110"; -- X73b5 Xc946 + WHEN "1010011" => T_int1 := "01110010010101001100011001110100"; -- X7254 Xc674 + WHEN "1010100" => T_int1 := "01110000111000101100001110101010"; -- X70e2 Xc3aa + WHEN "1010101" => T_int1 := "01101111010111101100000011101001"; -- X6f5e Xc0e9 + WHEN "1010110" => T_int1 := "01101101110010011011111000110010"; -- X6dc9 Xbe32 + WHEN "1010111" => T_int1 := "01101100001000111011101110000110"; -- X6c23 Xbb86 + WHEN "1011000" => T_int1 := "01101010011011011011100011100100"; -- X6a6d Xb8e4 + WHEN "1011001" => T_int1 := "01101000101001101011011001001100"; -- X68a6 Xb64c + WHEN "1011010" => T_int1 := "01100110110011111011001111000001"; -- X66cf Xb3c1 + WHEN "1011011" => T_int1 := "01100100111010001011000101000001"; -- X64e8 Xb141 + WHEN "1011100" => T_int1 := "01100010111100011010111011001101"; -- X62f1 Xaecd + WHEN "1011101" => T_int1 := "01100000111010111010110001100101"; -- X60eb Xac65 + WHEN "1011110" => T_int1 := "01011110110101111010101000001011"; -- X5ed7 Xaa0b + WHEN "1011111" => T_int1 := "01011100101100111010011110111110"; -- X5cb3 Xa7be + WHEN "1100000" => T_int1 := "01011010100000101010010101111110"; -- X5a82 Xa57e + WHEN "1100001" => T_int1 := "01011000010000101010001101001101"; -- X5842 Xa34d + WHEN "1100010" => T_int1 := "01010101111101011010000100101001"; -- X55f5 Xa129 + WHEN "1100011" => T_int1 := "01010011100110111001111100010101"; -- X539b X9f15 + WHEN "1100100" => T_int1 := "01010001001100111001110100001111"; -- X5133 X9d0f + WHEN "1100101" => T_int1 := "01001110101111111001101100011000"; -- X4ebf X9b18 + WHEN "1100110" => T_int1 := "01001100001111111001100100110001"; -- X4c3f X9931 + WHEN "1100111" => T_int1 := "01001001101101001001011101011010"; -- X49b4 X975a + WHEN "1101000" => T_int1 := "01000111000111001001010110010011"; -- X471c X9593 + WHEN "1101001" => T_int1 := "01000100011110101001001111011101"; -- X447a X93dd + WHEN "1101010" => T_int1 := "01000001110011101001001000110111"; -- X41ce X9237 + WHEN "1101011" => T_int1 := "00111111000101111001000010100010"; -- X3f17 X90a2 + WHEN "1101100" => T_int1 := "00111100010101101000111100011110"; -- X3c56 X8f1e + WHEN "1101101" => T_int1 := "00111001100011001000110110101100"; -- X398c X8dac + WHEN "1101110" => T_int1 := "00110110101110101000110001001011"; -- X36ba X8c4b + WHEN "1101111" => T_int1 := "00110011110111111000101011111100"; -- X33df X8afc + WHEN "1110000" => T_int1 := "00110000111110111000100110111111"; -- X30fb X89bf + WHEN "1110001" => T_int1 := "00101110000100011000100010010101"; -- X2e11 X8895 + WHEN "1110010" => T_int1 := "00101011000111111000011101111100"; -- X2b1f X877c + WHEN "1110011" => T_int1 := "00101000001001101000011001110111"; -- X2826 X8677 + WHEN "1110100" => T_int1 := "00100101001010001000010110000100"; -- X2528 X8584 + WHEN "1110101" => T_int1 := "00100010001000111000010010100100"; -- X2223 X84a4 + WHEN "1110110" => T_int1 := "00011111000110101000001111010111"; -- X1f1a X83d7 + WHEN "1110111" => T_int1 := "00011100000010111000001100011101"; -- X1c0b X831d + WHEN "1111000" => T_int1 := "00011000111110011000001001110111"; -- X18f9 X8277 + WHEN "1111001" => T_int1 := "00010101111000101000000111100011"; -- X15e2 X81e3 + WHEN "1111010" => T_int1 := "00010010110010001000000101100100"; -- X12c8 X8164 + WHEN "1111011" => T_int1 := "00001111101010111000000011110111"; -- X0fab X80f7 + WHEN "1111100" => T_int1 := "00001100100011001000000010011111"; -- X0c8c X809f + WHEN "1111101" => T_int1 := "00001001011010101000000001011010"; -- X096a X805a + WHEN "1111110" => T_int1 := "00000110010010001000000000101000"; -- X0648 X8028 + WHEN "1111111" => T_int1 := "00000011001001001000000000001011"; -- X0324 X800b + WHEN OTHERS => NULL; + END CASE; + T_int <= T_int1; + END PROCESS; + +END ARCHITECTURE translated; diff --git a/lib/lpp/dsp/lpp_fft_rtax/vhdlsim.txt b/lib/lpp/dsp/lpp_fft_rtax/vhdlsim.txt new file mode 100644 diff --git a/lib/lpp/dsp/lpp_fft_rtax/vhdlsyn.txt b/lib/lpp/dsp/lpp_fft_rtax/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft_rtax/vhdlsyn.txt @@ -0,0 +1,16 @@ +fft_components.vhd +lpp_fft.vhd +actar.vhd +actram.vhd +CoreFFT.vhd +fftDp.vhd +fftSm.vhd +primitives.vhd +twiddle.vhd +APB_FFT.vhd +Driver_FFT.vhd +FFT.vhd +FFTamont.vhd +FFTaval.vhd +Flag_Extremum.vhd +Linker_FFT.vhd