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--------------------------------------------------------------------------------
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-- Copyright 2007 Actel Corporation. All rights reserved.
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-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
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-- IN ADVANCE IN WRITING.
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-- Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
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-- File: CoreFFT.vhd
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-- Description: CoreFFT
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-- Top level FFT module
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-- Rev: 0.1 8/31/2005 4:53PM VD : Pre Production
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-- Notes: FFT In/out pins:
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-- Input | Output | Comments
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-- ------------+------------+------------------
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-- clk | ifoPong |
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-- ifiNreset | |async reset active low
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-- start | |sync reset active high
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-- Load Input data group |
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-- d_im[15:0] | load |when high the inBuf is being loaded
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-- d_re[15:0] | |
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-- d_valid | |
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-- Upload Output data group |
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-- read_y | y_im[15:0] |
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-- | y_re[15:0] |
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-- | y_valid |marks a new output sample)
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-- | y_rdy |when high the results are being uploaded
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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USE work.fft_components.all;
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ENTITY CoreFFT IS
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GENERIC (
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LOGPTS : integer := gLOGPTS;
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LOGLOGPTS : integer := gLOGLOGPTS;
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WSIZE : integer := gWSIZE;
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TWIDTH : integer := gTWIDTH;
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DWIDTH : integer := gDWIDTH;
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TDWIDTH : integer := gTDWIDTH;
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RND_MODE : integer := gRND_MODE;
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SCALE_MODE : integer := gSCALE_MODE;
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PTS : integer := gPTS;
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HALFPTS : integer := gHALFPTS;
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inBuf_RWDLY : integer := gInBuf_RWDLY );
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PORT (
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clk,ifiStart,ifiNreset : IN std_logic;
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ifiD_valid, ifiRead_y : IN std_logic;
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ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
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ifoLoad, ifoPong : OUT std_logic;
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ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
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ifoY_valid, ifoY_rdy : OUT std_logic);
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END ENTITY CoreFFT;
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ARCHITECTURE translated OF CoreFFT IS
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COMPONENT autoScale
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GENERIC (SCALE_MODE : integer := 1 );
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PORT (clk, clkEn, wLastStage : IN std_logic;
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ldRiskOV, bflyRiskOV : IN std_logic;
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startLoad, ifo_loadOn : IN std_logic;
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bflyOutValid, startFFT : IN std_logic;
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wEn_even, wEn_odd : IN std_logic;
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upScale : OUT std_logic);
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END COMPONENT;
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COMPONENT bfly2
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GENERIC ( RND_MODE : integer := 0;
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WSIZE : integer := 16;
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DWIDTH : integer := 32;
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TWIDTH : integer := 16;
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TDWIDTH : integer := 32 );
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PORT (clk, validIn : IN std_logic;
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swCrossIn : IN std_logic;
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upScale : IN std_logic;
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inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
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T : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
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outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
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validOut, swCrossOut : OUT std_logic);
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END COMPONENT;
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COMPONENT sm_top
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GENERIC ( PTS : integer := 256;
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HALFPTS : integer := 128;
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LOGPTS : integer := 8;
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LOGLOGPTS : integer := 3;
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inBuf_RWDLY : integer := 12 );
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PORT (clk,clkEn : IN std_logic;
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ifiStart, ifiNreset : IN std_logic;
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ifiD_valid, ifiRead_y : IN std_logic;
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ldA, rA, wA, tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
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twid_wA, outBuf_wA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0);
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outBuf_rA : OUT std_logic_vector(LOGPTS-1 DOWNTO 0);
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wEn_even, wEn_odd : OUT std_logic;
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preSwCross, twid_wEn : OUT std_logic;
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inBuf_wEn, outBuf_wEn : OUT std_logic;
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smPong, ldValid : OUT std_logic;
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inBuf_rdValid : OUT std_logic;
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wLastStage : OUT std_logic;
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smStartFFTrd : OUT std_logic;
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smStartLoad, ifoLoad : OUT std_logic;
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ifoY_valid, ifoY_rdy : OUT std_logic);
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END COMPONENT;
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COMPONENT twiddle
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PORT (A : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
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T : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0));
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END COMPONENT;
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COMPONENT pipoBuffer
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GENERIC ( LOGPTS : integer := 8;
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DWIDTH : integer := 32 );
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PORT (
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clk, clkEn, pong, rEn : IN std_logic;
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rA, wA_load, wA_bfly : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
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ldData,wP_bfly,wQ_bfly : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
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wEn_bfly,wEn_even,wEn_odd : IN std_logic;
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outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0) );
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END COMPONENT;
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COMPONENT switch
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GENERIC ( DWIDTH : integer := 16 );
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PORT (clk, sel, validIn : IN std_logic;
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inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
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outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
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validOut : OUT std_logic);
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END COMPONENT;
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COMPONENT twidLUT
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GENERIC ( LOGPTS : integer := 8;
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TDWIDTH : integer := 32 );
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PORT (clk, wEn : IN std_logic;
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wA, rA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
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D : IN std_logic_vector(TDWIDTH-1 DOWNTO 0);
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Q : OUT std_logic_vector(TDWIDTH-1 DOWNTO 0));
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END COMPONENT;
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COMPONENT outBuff
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GENERIC ( LOGPTS : integer := 8;
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DWIDTH : integer := 32 );
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PORT (clk, clkEn, wEn : IN std_logic;
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inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
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wA : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
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rA : IN std_logic_vector(LOGPTS-1 DOWNTO 0);
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outD : OUT std_logic_vector(DWIDTH-1 DOWNTO 0));
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END COMPONENT;
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SIGNAL ldA_w, rA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
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SIGNAL wA_w, tA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
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SIGNAL twid_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
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SIGNAL outBuf_wA_w : std_logic_vector(LOGPTS-2 DOWNTO 0);
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SIGNAL outBuf_rA_w : std_logic_vector(LOGPTS-1 DOWNTO 0);
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SIGNAL wEn_even_w : std_logic;
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SIGNAL wEn_odd_w : std_logic;
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SIGNAL inBuf_wEn_w : std_logic;
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SIGNAL preSwCross_w : std_logic;
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SIGNAL postSwCross_w : std_logic;
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SIGNAL twid_wEn_w : std_logic;
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SIGNAL outBuf_wEn_w : std_logic;
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SIGNAL ldRiskOV_w : std_logic;
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SIGNAL bflyRiskOV_w : std_logic;
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SIGNAL readP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
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SIGNAL readQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
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SIGNAL bflyInP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
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SIGNAL bflyInQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
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SIGNAL bflyOutP_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
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SIGNAL bflyOutQ_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
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SIGNAL T_w : std_logic_vector(TDWIDTH-1 DOWNTO 0);
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SIGNAL twidData_w : std_logic_vector(TDWIDTH-1 DOWNTO 0);
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SIGNAL outEven_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
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SIGNAL outOdd_w : std_logic_vector(DWIDTH-1 DOWNTO 0);
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SIGNAL inBufValid_w : std_logic;
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SIGNAL preSwValid_w : std_logic;
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SIGNAL bflyValid_w : std_logic;
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SIGNAL wLastStage_w : std_logic;
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SIGNAL startFFTrd_w : std_logic;
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SIGNAL startLoad_w : std_logic;
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SIGNAL upScale_w : std_logic;
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SIGNAL port_xhdl15 : std_logic;
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SIGNAL xhdl_17 : std_logic_vector(DWIDTH-1 DOWNTO 0);
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SIGNAL xhdl_23 : std_logic_vector(DWIDTH-1 DOWNTO 0);
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SIGNAL clkEn_const : std_logic;
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SIGNAL ifoLoad_xhdl1 : std_logic;
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SIGNAL ifoY_im_xhdl2 : std_logic_vector(WSIZE-1 DOWNTO 0);
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SIGNAL ifoY_re_xhdl3 : std_logic_vector(WSIZE-1 DOWNTO 0);
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SIGNAL ifoPong_xhdl4 : std_logic;
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SIGNAL ifoY_valid_xhdl5 : std_logic;
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SIGNAL ifoY_rdy_xhdl6 : std_logic;
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SIGNAL displayBflyOutP : std_logic;
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SIGNAL displayBflyOutQ : std_logic;
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SIGNAL displayInBuf_wEn : std_logic;
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SIGNAL ldValid_w : std_logic;
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BEGIN
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ifoLoad <= ifoLoad_xhdl1;
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ifoY_im <= ifoY_im_xhdl2;
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ifoY_re <= ifoY_re_xhdl3;
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ifoPong <= ifoPong_xhdl4;
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ifoY_valid <= ifoY_valid_xhdl5;
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ifoY_rdy <= ifoY_rdy_xhdl6;
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-- debug only
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displayBflyOutP <= bflyOutP_w(0) ;
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displayBflyOutQ <= bflyOutQ_w(0) ;
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displayInBuf_wEn <= inBuf_wEn_w ;
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port_xhdl15 <= '1';
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smTop_0 : sm_top
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GENERIC MAP ( PTS => PTS, HALFPTS => HALFPTS,
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LOGPTS => LOGPTS, LOGLOGPTS => LOGLOGPTS, inBuf_RWDLY => inBuf_RWDLY )
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PORT MAP (
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clk => clk,
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clkEn => port_xhdl15,
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ifiStart => ifiStart,
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ifiNreset => ifiNreset,
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ifiD_valid => ifiD_valid,
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ifiRead_y => ifiRead_y,
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ldA => ldA_w,
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rA => rA_w,
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wA => wA_w,
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tA => tA_w,
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twid_wA => twid_wA_w,
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outBuf_wA => outBuf_wA_w,
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outBuf_rA => outBuf_rA_w,
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wEn_even => wEn_even_w,
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wEn_odd => wEn_odd_w,
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preSwCross => preSwCross_w,
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twid_wEn => twid_wEn_w,
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inBuf_wEn => inBuf_wEn_w,
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outBuf_wEn => outBuf_wEn_w,
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smPong => ifoPong_xhdl4,
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ldValid => ldValid_w,
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inBuf_rdValid => inBufValid_w,
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wLastStage => wLastStage_w,
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smStartFFTrd => startFFTrd_w,
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smStartLoad => startLoad_w,
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ifoLoad => ifoLoad_xhdl1,
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ifoY_valid => ifoY_valid_xhdl5,
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ifoY_rdy => ifoY_rdy_xhdl6);
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xhdl_17 <= ifiD_im & ifiD_re;
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inBuf_0 : pipoBuffer
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GENERIC MAP ( LOGPTS => LOGPTS,
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DWIDTH => DWIDTH )
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PORT MAP (
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clk => clk,
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clkEn => '1',
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rEn => '1',
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rA => rA_w,
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wA_load => ldA_w,
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wA_bfly => wA_w,
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ldData => xhdl_17,
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wP_bfly => outEven_w,
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wQ_bfly => outOdd_w,
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wEn_bfly => inBuf_wEn_w,
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wEn_even => wEn_even_w,
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wEn_odd => wEn_odd_w,
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pong => ifoPong_xhdl4,
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outP => readP_w,
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outQ => readQ_w);
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preBflySw_0 : switch
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GENERIC MAP ( DWIDTH => DWIDTH )
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PORT MAP (
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clk => clk,
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inP => readP_w,
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inQ => readQ_w,
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sel => preSwCross_w,
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outP => bflyInP_w,
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outQ => bflyInQ_w,
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validIn => inBufValid_w,
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validOut => preSwValid_w);
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bfly_0 : bfly2
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GENERIC MAP (RND_MODE => RND_MODE, WSIZE => WSIZE, DWIDTH => DWIDTH,
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TWIDTH => TWIDTH, TDWIDTH => TDWIDTH )
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PORT MAP (
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clk => clk,
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upScale => upScale_w,
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inP => bflyInP_w,
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inQ => bflyInQ_w,
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T => T_w,
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outP => bflyOutP_w,
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outQ => bflyOutQ_w,
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validIn => preSwValid_w,
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validOut => bflyValid_w,
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swCrossIn => preSwCross_w,
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swCrossOut => postSwCross_w);
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lut_0 : twiddle
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PORT MAP (A => twid_wA_w, T => twidData_w);
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twidLUT_1 : twidLUT
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GENERIC MAP ( LOGPTS => LOGPTS, TDWIDTH => TDWIDTH )
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PORT MAP (
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clk => clk,
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wA => twid_wA_w,
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wEn => twid_wEn_w,
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rA => tA_w,
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D => twidData_w,
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Q => T_w);
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postBflySw_0 : switch
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GENERIC MAP ( DWIDTH => DWIDTH )
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PORT MAP (
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clk => clk,
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inP => bflyOutP_w,
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inQ => bflyOutQ_w,
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sel => postSwCross_w,
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outP => outEven_w,
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outQ => outOdd_w,
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validIn => bflyValid_w,
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validOut => open);
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ifoY_im_xhdl2 <= xhdl_23(DWIDTH-1 DOWNTO WSIZE);
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ifoY_re_xhdl3 <= xhdl_23(WSIZE-1 DOWNTO 0);
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outBuff_0 : outBuff
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GENERIC MAP( LOGPTS => LOGPTS, DWIDTH => DWIDTH )
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PORT MAP (
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clk => clk, clkEn => '1',
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rA => outBuf_rA_w,
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wA => outBuf_wA_w,
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inP => outEven_w,
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inQ => outOdd_w,
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wEn => outBuf_wEn_w,
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outD => xhdl_23);
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-- Autoscaling
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-- monitor if input data .im and .re have MSB == sign
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ldRiskOV_w <= to_logic(
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NOT ((ifiD_im(WSIZE-1) = ifiD_im(WSIZE-2))
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AND (ifiD_re(WSIZE-1) = ifiD_re(WSIZE-2))) );
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bflyRiskOV_w <= to_logic(
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NOT ((((bflyOutP_w(DWIDTH-1) = bflyOutP_w(DWIDTH- 2))
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AND (bflyOutP_w(WSIZE-1) = bflyOutP_w(WSIZE-2)))
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AND (bflyOutQ_w(DWIDTH-1) = bflyOutQ_w(DWIDTH-2)))
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AND (bflyOutQ_w(WSIZE-1) = bflyOutQ_w(WSIZE-2))) );
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clkEn_const <= '1';
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autoScale_0 : autoScale
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GENERIC MAP (SCALE_MODE => SCALE_MODE)
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PORT MAP (
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clk => clk,
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clkEn => clkEn_const,
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ldRiskOV => ldRiskOV_w,
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bflyRiskOV => bflyRiskOV_w,
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startLoad => startLoad_w,
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startFFT => startFFTrd_w,
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bflyOutValid => bflyValid_w,
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wLastStage => wLastStage_w,
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wEn_even => wEn_even_w,
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wEn_odd => wEn_odd_w,
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ifo_loadOn => ifoLoad_xhdl1,
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upScale => upScale_w);
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END ARCHITECTURE translated;
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