HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r269:cda86f81a8b0

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Jeandet Alexis -

r269:cda86f81a8b0 alexis

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Makefile 0 -1

             SCRIPTSDIR=scripts/
             LIBDIR=lib/
             BOARDSDIR=boards/
             DESIGNSDIR=designs/
             .PHONY:doc
             all: help
             help:
             	@echo
             	@echo " batch targets:"
             	@echo
             	@echo " make link            : link lpp library to GRLIB at : $(GRLIB)"
             	@echo " make Patch-GRLIB     : install library into GRLIB at : $(GRLIB)"
             	@echo " make dist            : create a tar file for using into an other computer"
             	@echo " make Patched-dist    : create a tar file for with a patched grlib for using"
             	@echo "                        into an other computer"
             	@echo " make allGPL          : add a GPL HEADER in all vhdl Files"
             	@echo " make init            : add a GPL HEADER in all vhdl Files, init all files"
             	@echo " make doc             : make documentation for VHDL IPs"
             	@echo " make pdf             : make pdf documentation for VHDL IPs"
             	@echo " make C-libs          : make C drivers for APB devices"
             	@echo "                        binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes"
             	@echo
             allGPL:
             	@echo "Scanning VHDL files ..."
             	sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib
             	@echo "Scanning C files ..."
             	sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers
             	@echo "Scanning H files ..."
             	sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers
             init: C-libs
             	sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
             	sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp
             C-libs:APB_devs
             	make -C LPP_drivers
             APB_devs:
             	sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh
             Patch-GRLIB: init doc
             	sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
             link:
             	sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
             	sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
-            	sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB)
             dist: init
             	tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
             Patched-dist: Patch-GRLIB
             	tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
             doc:
             	mkdir -p doc/html
             	cp doc/ressources/*.jpg doc/html/
             	cp doc/ressources/doxygen.css doc/html/
             	make -C lib/lpp doc
             	make -C LPP_drivers doc
             pdf: doc
             	sh $(SCRIPTSDIR)/doc.sh

boards/BeagleSynth/default.ucf +2 -2

             NET "CLK"      CLOCK_DEDICATED_ROUTE = FALSE;
             NET "CLK"              LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL;
-            #NET "CLKM" TNM_NET = "clkm_net";
+            NET "CLKM" TNM_NET = "clkm_net";
-            #TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;
+            TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;
             NET "RESET"    CLOCK_DEDICATED_ROUTE = FALSE;
             NET "RESET"            LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL;
             NET "DAC_nCLR"     LOC = "R11" | IOSTANDARD=LVTTL;
             NET "DAC_nCS"      LOC = "T12" | IOSTANDARD=LVTTL;
             NET "CAL_IN_SCK"   LOC = "R13" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(0)"   LOC = "P5" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(1)"   LOC = "M5" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(2)"   LOC = "C8" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(3)"   LOC = "M6" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(4)"   LOC = "K22" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(5)"   LOC = "L22" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(6)"   LOC = "G19" | IOSTANDARD=LVTTL;
             NET "DAC_SDI(7)"   LOC = "F20" | IOSTANDARD=LVTTL;
             NET "TXD"          LOC = "V22"| slew=FAST  | IOSTANDARD=LVTTL;
             NET "RXD"          LOC = "U22"| slew=FAST  | IOSTANDARD=LVTTL;
             NET "LED(0)"       LOC = "AB9"| slew=FAST  | IOSTANDARD=LVTTL;
             NET "LED(1)"       LOC = "AB8"| slew=FAST  | IOSTANDARD=LVTTL;
             NET "LED(2)"       LOC = "AA8"| slew=FAST  | IOSTANDARD=LVTTL;
             NET "urxd1"        LOC = "D3" | IOSTANDARD=LVTTL; # Unused PIN
             NET "utxd1"        LOC = "C4" | IOSTANDARD=LVTTL; # Unused PIN
             NET "sdcke"        LOC = "B6" | slew=FAST | IOSTANDARD=LVTTL; # clk en
             NET "sdcsn"        LOC = "G20"| slew=FAST | IOSTANDARD=LVTTL; # chip sel
             NET "sdwen"        LOC = "D14"| slew=FAST | IOSTANDARD=LVTTL; # write en
             NET "sdrasn"       LOC = "H19"| slew=FAST | IOSTANDARD=LVTTL; # row addr stb
             NET "sdcasn"       LOC = "C14"| slew=FAST | IOSTANDARD=LVTTL; # col addr stb
             NET "sddqm(3)"     LOC = "A5" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
             NET "sddqm(2)"     LOC = "D21"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
             NET "sddqm(1)"     LOC = "C7" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
             NET "sddqm(0)"     LOC = "D15"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
             NET "sdclk"    CLOCK_DEDICATED_ROUTE = FALSE;
             NET "sdclk"        LOC = "A6" | slew=FAST  | IOSTANDARD=LVTTL; # sdram clk output
             NET "sdba(1)"      LOC = "J20"| slew=FAST  | IOSTANDARD=LVTTL; # bank select address
             NET "sdba(0)"      LOC = "G16"| slew=FAST  | IOSTANDARD=LVTTL; # bank select address
             NET "Address(11)"  LOC = "H8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(10)"  LOC = "G7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(9)"   LOC = "K7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(8)"   LOC = "H6"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(7)"   LOC = "H5"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(6)"   LOC = "K8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(5)"   LOC = "G4"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(4)"   LOC = "H3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(3)"   LOC = "D2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(2)"   LOC = "B3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(1)"   LOC = "A2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Address(0)"   LOC = "C22"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
             NET "Data(31)"     LOC = "C5" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(30)"     LOC = "A4" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(29)"     LOC = "A3" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(28)"     LOC = "B2" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(27)"     LOC = "B1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(26)"     LOC = "C1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(25)"     LOC = "D1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(24)"     LOC = "E1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(23)"     LOC = "J22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(22)"     LOC = "H22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(21)"     LOC = "H21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(20)"     LOC = "G22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(19)"     LOC = "F22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(18)"     LOC = "F21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(17)"     LOC = "E22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(16)"     LOC = "D22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(15)"     LOC = "A7" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(14)"     LOC = "B8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(13)"     LOC = "A8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(12)"     LOC = "C9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(11)"     LOC = "A9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(10)"     LOC = "B10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(9)"      LOC = "A10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(8)"      LOC = "C11"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(7)"      LOC = "A13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(6)"      LOC = "C13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(5)"      LOC = "B22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(4)"      LOC = "B21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(3)"      LOC = "B20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(2)"      LOC = "A20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(1)"      LOC = "B18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
             NET "Data(0)"      LOC = "A18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data

designs/BeagleSynth/BeagleSynth.vhd +7 -5

             library ieee;
             use ieee.std_logic_1164.all;
             use IEEE.numeric_std.all;
             library grlib, techmap;
             use grlib.amba.all;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use techmap.gencomp.all;
             use techmap.allclkgen.all;
             library gaisler;
             use gaisler.memctrl.all;
             use gaisler.leon3.all;
             use gaisler.uart.all;
             use gaisler.misc.all;
             library esa;
             use esa.memoryctrl.all;
             --use gaisler.sim.all;
             library lpp;
             use lpp.lpp_ad_conv.all;
             use lpp.lpp_amba.all;
             use lpp.apb_devices_list.all;
             use lpp.general_purpose.all;
             Library UNISIM;
             use UNISIM.vcomponents.all;
             use work.config.all;
             --==================================================================
             --
             --
             --			FPGA FREQ = 100MHz
             --
             --
             --==================================================================
             entity BeagleSynth is
               generic (
                 fabtech       : integer := CFG_FABTECH;
                 memtech       : integer := CFG_MEMTECH;
                 padtech       : integer := CFG_PADTECH;
                 clktech       : integer := CFG_CLKTECH
               );
               port (
                 reset         : in  std_ulogic;
                 clk           : in  std_ulogic;
             	 DAC_nCLR		: out std_ulogic;
             	 DAC_nCS       : out std_ulogic;
             	 CAL_IN_SCK		: out std_ulogic;
             	 DAC_SDI			: out std_ulogic_vector(7 downto 0);
             	 TXD				: out std_ulogic;
             	 RXD				: in  std_ulogic;
             	 urxd1	      : in  std_ulogic;
             	 utxd1         : out std_ulogic;
             	 LED				: out std_ulogic_vector(2 downto 0);
             --------------------------------------------------------
             ----       SDRAM
             ---- For SDRAM config have a look on leon3-altera-ep1c20
             ---- design from GRLIB, the  IS42S32400E is similar to
             ---- MT48LC4M32B2.
             --------------------------------------------------------
             	 sdcke         : out std_logic; -- clk en
             	 sdcsn         : out std_logic; -- chip sel
             	 sdwen         : out std_logic;                      -- write en
             	 sdrasn        : out std_logic;                      -- row addr stb
             	 sdcasn        : out std_logic;                      -- col addr stb
             	 sddqm         : out std_logic_vector (3 downto 0);  -- data i/o mask
             	 sdclk         : out std_logic;                      -- sdram clk output
             	 sdba          : out std_logic_vector (1 downto 0);  -- bank select address
             	 Address       : out std_logic_vector(11 downto 0);  -- sdram address
             	 Data          : inout std_logic_vector(31 downto 0) -- optional sdram data
             	 );
             end;
             architecture rtl of BeagleSynth is
             constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
             	CFG_GRETH+CFG_AHB_JTAG;
             constant maxahbm : integer := maxahbmsp;
             constant IOAEN  : integer := CFG_CAN;
             constant boardfreq : integer := 100000;
             signal clk2x    : std_ulogic;
             signal lclk     : std_ulogic;
             signal clkm     : std_ulogic;
             signal rstn     : std_ulogic;
             signal rst      : std_ulogic;
             signal rstraw   : std_ulogic;
             signal pciclk   : std_ulogic;
             signal sdclkl   : std_ulogic;
             signal sdclkl_DDR2   : std_ulogic;
             signal cgi      : clkgen_in_type;
             signal cgo      : clkgen_out_type;
             --- AHB / APB
             signal apbi     : apb_slv_in_type;
             signal apbo     : apb_slv_out_vector := (others => apb_none);
             signal ahbsi    : ahb_slv_in_type;
             signal ahbso    : ahb_slv_out_vector := (others => ahbs_none);
             signal ahbmi    : ahb_mst_in_type;
             signal ahbmo    : ahb_mst_out_vector := (others => ahbm_none);
             --- MEM CTRLR
             signal sdi : sdctrl_in_type;
             signal sdo : sdctrl_out_type;
             --UART
             signal ahbuarti : uart_in_type;
             signal ahbuarto : uart_out_type;
             signal apbuarti : uart_in_type;
             signal apbuarto : uart_out_type;
             signal led2int  : std_logic;
             begin
             DAC_nCLR		<= '1';
             DAC_nCS     <= '1';
             CAL_IN_SCK  <= '1';
             DAC_SDI		<= (others =>'1');
             resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
               rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
               --rstn	<= reset;
               --lclk <= clk;
               clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
               cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
               clkgen0 : clkgen  		-- clock generator
                 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
                 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
             --  sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
             --sdclk <= sdclkl;
             sdclk <= sdclkl_DDR2;
+            LED(1)  <= not cgo.clklock;
+            LED(0)  <= cgo.clklock;
             ODDR2_inst : ODDR2
                generic map(
-                  DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1"
+                  DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
                   INIT => '0', -- Sets initial state of the Q output to '0' or '1'
-                  SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
+                  SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
                port map (
                   Q => sdclkl_DDR2, -- 1-bit output data
                   C0 => sdclkl, -- 1-bit clock input
                   C1 => not sdclkl, -- 1-bit clock input
                   CE => '1',  -- 1-bit clock enable input
                   D0 => '1',   -- 1-bit data input (associated with C0)
                   D1 => '0',   -- 1-bit data input (associated with C1)
                   R =>  '0',    -- 1-bit reset input
                   S => '0'     -- 1-bit set input
                );
             ----------------------------------------------------------------------
             ---  AHB CONTROLLER  -------------------------------------------------
             ----------------------------------------------------------------------
               ahb0 : ahbctrl 		-- AHB arbiter/multiplexer
               generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
             	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
             	ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
               port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
             ----------------------------------------------------------------------
             ---  AHB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               dcomgen : if CFG_AHB_UART = 1 generate
                 dcom0: ahbuart		-- Debug UART
                 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
                 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
                 ahbuarti.rxd  <= RXD;
                 TXD           <= ahbuarto.txd;
-                led(0) <= ahbuarti.rxd; led(1) <= ahbuarto.txd;
               end generate;
               nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
             ----------------------------------------------------------------------
             ---  APB Bridge  -----------------------------------------------------
             ----------------------------------------------------------------------
               apb0 : apbctrl				-- AHB/APB bridge
               generic map (hindex => 1, haddr => CFG_APBADDR)
               port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
             ----------------------------------------------------------------------
             ---  APB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               ua1 : if CFG_UART1_ENABLE /= 0 generate
                 uart1 : apbuart			-- UART 1
                 generic map (pindex => 1, paddr => 1,  pirq => 2, console => CFG_DUART,
             	fifosize => CFG_UART1_FIFO)
                 port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
                 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
                 apbuarti.ctsn <= '0';
               end generate;
               noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
             --div0: Clk_divider
             --	 generic map( 100000000,1)
             --    Port map( clkm,rstn,LED(2));
             LED(2) <= led2int;
             process(clkm,rstn)
             begin
             	if rstn = '0' then
             		led2int <= '0';
             	elsif clkm'event and clkm='1' then
             		led2int <= not led2int;
             	end if;
             end process;
             sdc : sdctrl
                generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0,
             	invclk => 0,sdbits =>32)
             	port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo);
             --Alternative data pad instantiation with vectored bdrive
             sd_pad : iopadvv generic map (tech=> padtech,width => 32)
             port map (
               data(31 downto 0),
               sdo.data(31 downto 0),
               sdo.vbdrive(31 downto 0),
               sdi.data(31 downto 0));
             -- connect memory controller outputs to entity output signals
             Address <= sdo.address(13 downto 2);
-            sdba	  <= sdo.address(16 downto 15);
+            --sdba	  <= sdo.address(16 downto 15);
+            sdba	  <= "00";
             sdcke <= sdo.sdcke(0);
             sdwen <= sdo.sdwen;
             sdcsn <= sdo.sdcsn(0);
             sdrasn <= sdo.rasn;
             sdcasn <= sdo.casn;
             sddqm <= sdo.dqm(3 downto 0);
-            --sdi.data(31 downto 0) <= data(31 downto 0);
             end rtl;

designs/BeagleSynth/Makefile +1 -1

             include .config
             #GRLIB=$(GRLIB)
             TOP=BeagleSynth
             BOARD=BeagleSynth
             #BOARD=SP601
             include ../../boards/$(BOARD)/Makefile.inc
             DEVICE=$(PART)-$(PACKAGE)$(SPEED)
             #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
             UCF=../../boards/$(BOARD)/default.ucf
             QSF=../../boards/$(BOARD)/$(TOP).qsf
             EFFORT=high
             ISEMAPOPT="-timing"
             XSTOPT=""
             SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
             VHDLOPTSYNFILES=
             VHDLSYNFILES= \
-            	config.vhd  BeagleSynth.vhd
+            	config.vhd  BeagleSynth.vhd BeagleSynth_MCTRL.vhd
             #VHDLSIMFILES=testbench.vhd
             #SIMTOP=testbench
             #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
             SDCFILE=default.sdc
             BITGEN=../../boards/$(BOARD)/default.ut
             CLEAN=soft-clean
             VCOMOPT=-explicit
             TECHLIBS = secureip unisim
             LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
             	tmtc openchip cypress ihp gleichmann gsi fmf spansion
             DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
             	leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
             	ac97 hcan usb
             DIRADD =
             FILEADD =
             FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
             include $(GRLIB)/bin/Makefile
             include $(GRLIB)/software/leon3/Makefile
             ##################  project specific targets ##########################
             flash:
             	xc3sprog -c ftdi -p 1 BeagleSynth.bit
             ram:
             	xc3sprog -c ftdi -p 0 BeagleSynth.bit

designs/BeagleSynth/config.vhd +4 -3

             -----------------------------------------------------------------------------
             -- LEON3 Demonstration design test bench configuration
             -- Copyright (C) 2009 Aeroflex Gaisler
             ------------------------------------------------------------------------------
             library techmap;
             use techmap.gencomp.all;
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             package config is
             -- Technology and synthesis options
               constant CFG_FABTECH : integer := spartan6;
               constant CFG_MEMTECH : integer := spartan6;
               constant CFG_PADTECH : integer := spartan6;
             -- Clock generator
+            --  ON Spartan 6 VCO freq must be between 400MHz and 1GHz
               constant CFG_CLKTECH : integer := spartan6;
-              constant CFG_CLKMUL : integer := (2);
+              constant CFG_CLKMUL : integer := (6);
-              constant CFG_CLKDIV : integer := (8);
+              constant CFG_CLKDIV : integer := (12);
               constant CFG_OCLKDIV : integer := (1);
               constant CFG_PCIDLL : integer := 0;
               constant CFG_PCISYSCLK: integer := 0;
               constant CFG_CLK_NOFB : integer := 0;
             -- AMBA settings
               constant CFG_DEFMST : integer := (0);
               constant CFG_RROBIN : integer := 1;
               constant CFG_SPLIT : integer := 0;
               constant CFG_AHBIO : integer := 16#FFF#;
               constant CFG_APBADDR : integer := 16#800#;
               constant CFG_AHB_MON : integer := 0;
               constant CFG_AHB_MONERR : integer := 0;
               constant CFG_AHB_MONWAR : integer := 0;
             -- LEON3 processor core
               constant CFG_LEON3 : integer := 0;
               constant CFG_NCPU : integer := (0);
             -- DSU UART
               constant CFG_AHB_UART : integer := 1;
             -- JTAG based DSU interface
               constant CFG_AHB_JTAG : integer := 0;
             -- UART 1
               constant CFG_UART1_ENABLE : integer := 1;
               constant CFG_UART1_FIFO : integer := 1;
             -- GRLIB debugging
               constant CFG_DUART : integer := 0;
             -- LEON2 memory controller
               constant CFG_MCTRL_LEON2 : integer := 1;
               constant CFG_MCTRL_RAM8BIT : integer := 1;
               constant CFG_MCTRL_RAM16BIT : integer := 0;
               constant CFG_MCTRL_5CS : integer := 0;
               constant CFG_MCTRL_SDEN : integer := 1;
               constant CFG_MCTRL_SEPBUS : integer := 0;
               constant CFG_MCTRL_INVCLK : integer := 0;
               constant CFG_MCTRL_SD64 : integer := 0;
               constant CFG_MCTRL_PAGE : integer := 1 + 0;
             -- Gaisler Ethernet core
               constant CFG_GRETH : integer := 0;
             -- CAN 2.0 interface
               constant CFG_CAN : integer := 0;
             end;

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