diff --git a/Makefile b/Makefile
--- a/Makefile
+++ b/Makefile
@@ -54,7 +54,6 @@ Patch-GRLIB: init doc
 link:
 	sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
 	sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
-	sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB)
 
 dist: init
 	tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
diff --git a/boards/BeagleSynth/default.ucf b/boards/BeagleSynth/default.ucf
--- a/boards/BeagleSynth/default.ucf
+++ b/boards/BeagleSynth/default.ucf
@@ -1,8 +1,8 @@
 
 NET "CLK"      CLOCK_DEDICATED_ROUTE = FALSE;
 NET "CLK"              LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL;
-#NET "CLKM" TNM_NET = "clkm_net";
-#TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;

+NET "CLKM" TNM_NET = "clkm_net";
+TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;

 
 NET "RESET"    CLOCK_DEDICATED_ROUTE = FALSE;
 NET "RESET"            LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL;
diff --git a/designs/BeagleSynth/BeagleSynth.vhd b/designs/BeagleSynth/BeagleSynth.vhd
--- a/designs/BeagleSynth/BeagleSynth.vhd
+++ b/designs/BeagleSynth/BeagleSynth.vhd
@@ -133,11 +133,14 @@ resetn_pad : inpad generic map (tech => 
 --sdclk <= sdclkl;
 sdclk <= sdclkl_DDR2;
 
+LED(1)  <= not cgo.clklock;
+LED(0)  <= cgo.clklock;
+
 ODDR2_inst : ODDR2
    generic map(
-      DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1" 
+      DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
       INIT => '0', -- Sets initial state of the Q output to '0' or '1'
-      SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
+      SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
    port map (
       Q => sdclkl_DDR2, -- 1-bit output data
       C0 => sdclkl, -- 1-bit clock input
@@ -169,7 +172,6 @@ ODDR2_inst : ODDR2
     port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
     ahbuarti.rxd  <= RXD; 
     TXD           <= ahbuarto.txd;
-    led(0) <= ahbuarti.rxd; led(1) <= ahbuarto.txd;
   end generate;
   nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
 
@@ -234,14 +236,14 @@ port map (
 
 -- connect memory controller outputs to entity output signals
 Address <= sdo.address(13 downto 2);
-sdba	  <= sdo.address(16 downto 15);
+--sdba	  <= sdo.address(16 downto 15);
+sdba	  <= "00";
 sdcke <= sdo.sdcke(0); 
 sdwen <= sdo.sdwen; 
 sdcsn <= sdo.sdcsn(0);
 sdrasn <= sdo.rasn; 
 sdcasn <= sdo.casn; 
 sddqm <= sdo.dqm(3 downto 0);
---sdi.data(31 downto 0) <= data(31 downto 0);
 
 
 
diff --git a/designs/BeagleSynth/Makefile b/designs/BeagleSynth/Makefile
--- a/designs/BeagleSynth/Makefile
+++ b/designs/BeagleSynth/Makefile
@@ -17,7 +17,7 @@ VHDLOPTSYNFILES=
 
 
 VHDLSYNFILES= \
-	config.vhd  BeagleSynth.vhd
+	config.vhd  BeagleSynth.vhd BeagleSynth_MCTRL.vhd
 #VHDLSIMFILES=testbench.vhd
 #SIMTOP=testbench
 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
diff --git a/designs/BeagleSynth/config.vhd b/designs/BeagleSynth/config.vhd
--- a/designs/BeagleSynth/config.vhd
+++ b/designs/BeagleSynth/config.vhd
@@ -20,10 +20,11 @@ package config is
   constant CFG_MEMTECH : integer := spartan6;
   constant CFG_PADTECH : integer := spartan6;
   
--- Clock generator
+-- Clock generator   
+--  ON Spartan 6 VCO freq must be between 400MHz and 1GHz
   constant CFG_CLKTECH : integer := spartan6;
-  constant CFG_CLKMUL : integer := (2);
-  constant CFG_CLKDIV : integer := (8);
+  constant CFG_CLKMUL : integer := (6);
+  constant CFG_CLKDIV : integer := (12);
   constant CFG_OCLKDIV : integer := (1);
   constant CFG_PCIDLL : integer := 0;
   constant CFG_PCISYSCLK: integer := 0;