| @@ -54,7 +54,6 Patch-GRLIB: init doc | |||
|
|
54 | 54 | link: |
|
|
55 | 55 | sh $(SCRIPTSDIR)/vhdlsynPatcher.sh |
|
|
56 | 56 | sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB) |
|
|
57 | sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB) | |
|
|
58 | 57 | |
|
|
59 | 58 | dist: init |
|
|
60 | 59 | tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/* |
| @@ -1,8 +1,8 | |||
|
|
1 | 1 | |
|
|
2 | 2 | NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; |
|
|
3 | 3 | NET "CLK" LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL; |
|
|
4 |
|
|
|
|
5 |
|
|
|
|
4 | NET "CLKM" TNM_NET = "clkm_net"; | |
|
|
5 | TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%; | |
|
|
6 | 6 | |
|
|
7 | 7 | NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE; |
|
|
8 | 8 | NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL; |
| @@ -133,11 +133,14 resetn_pad : inpad generic map (tech => | |||
|
|
133 | 133 | --sdclk <= sdclkl; |
|
|
134 | 134 | sdclk <= sdclkl_DDR2; |
|
|
135 | 135 | |
|
|
136 | LED(1) <= not cgo.clklock; | |
|
|
137 | LED(0) <= cgo.clklock; | |
|
|
138 | ||
|
|
136 | 139 | ODDR2_inst : ODDR2 |
|
|
137 | 140 | generic map( |
|
|
138 |
DDR_ALIGNMENT => " |
|
|
|
141 | DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" | |
|
|
139 | 142 | INIT => '0', -- Sets initial state of the Q output to '0' or '1' |
|
|
140 |
SRTYPE => " |
|
|
|
143 | SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset | |
|
|
141 | 144 | port map ( |
|
|
142 | 145 | Q => sdclkl_DDR2, -- 1-bit output data |
|
|
143 | 146 | C0 => sdclkl, -- 1-bit clock input |
| @@ -169,7 +172,6 ODDR2_inst : ODDR2 | |||
|
|
169 | 172 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); |
|
|
170 | 173 | ahbuarti.rxd <= RXD; |
|
|
171 | 174 | TXD <= ahbuarto.txd; |
|
|
172 | led(0) <= ahbuarti.rxd; led(1) <= ahbuarto.txd; | |
|
|
173 | 175 | end generate; |
|
|
174 | 176 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; |
|
|
175 | 177 | |
| @@ -234,14 +236,14 port map ( | |||
|
|
234 | 236 | |
|
|
235 | 237 | -- connect memory controller outputs to entity output signals |
|
|
236 | 238 | Address <= sdo.address(13 downto 2); |
|
|
237 | sdba <= sdo.address(16 downto 15); | |
|
|
239 | --sdba <= sdo.address(16 downto 15); | |
|
|
240 | sdba <= "00"; | |
|
|
238 | 241 | sdcke <= sdo.sdcke(0); |
|
|
239 | 242 | sdwen <= sdo.sdwen; |
|
|
240 | 243 | sdcsn <= sdo.sdcsn(0); |
|
|
241 | 244 | sdrasn <= sdo.rasn; |
|
|
242 | 245 | sdcasn <= sdo.casn; |
|
|
243 | 246 | sddqm <= sdo.dqm(3 downto 0); |
|
|
244 | --sdi.data(31 downto 0) <= data(31 downto 0); | |
|
|
245 | 247 | |
|
|
246 | 248 | |
|
|
247 | 249 | |
| @@ -17,7 +17,7 VHDLOPTSYNFILES= | |||
|
|
17 | 17 | |
|
|
18 | 18 | |
|
|
19 | 19 | VHDLSYNFILES= \ |
|
|
20 | config.vhd BeagleSynth.vhd | |
|
|
20 | config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd | |
|
|
21 | 21 | #VHDLSIMFILES=testbench.vhd |
|
|
22 | 22 | #SIMTOP=testbench |
|
|
23 | 23 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc |
| @@ -20,10 +20,11 package config is | |||
|
|
20 | 20 | constant CFG_MEMTECH : integer := spartan6; |
|
|
21 | 21 | constant CFG_PADTECH : integer := spartan6; |
|
|
22 | 22 | |
|
|
23 | -- Clock generator | |
|
|
23 | -- Clock generator | |
|
|
24 | -- ON Spartan 6 VCO freq must be between 400MHz and 1GHz | |
|
|
24 | 25 | constant CFG_CLKTECH : integer := spartan6; |
|
|
25 |
constant CFG_CLKMUL : integer := ( |
|
|
|
26 |
constant CFG_CLKDIV : integer := ( |
|
|
|
26 | constant CFG_CLKMUL : integer := (6); | |
|
|
27 | constant CFG_CLKDIV : integer := (12); | |
|
|
27 | 28 | constant CFG_OCLKDIV : integer := (1); |
|
|
28 | 29 | constant CFG_PCIDLL : integer := 0; |
|
|
29 | 30 | constant CFG_PCISYSCLK: integer := 0; |
General Comments 0
You need to be logged in to leave comments.
Login now