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1 | VHDLIB=../.. | |||
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2 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |||
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3 | ||||
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4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |||
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5 | TOP=TB | |||
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6 | ||||
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7 | CMD_VLIB=vlib | |||
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8 | CMD_VMAP=vmap | |||
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9 | CMD_VCOM=@vcom -quiet -93 -work | |||
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10 | ||||
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11 | ################## project specific targets ########################## | |||
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12 | ||||
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13 | all: | |||
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14 | @echo "make vsim" | |||
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15 | @echo "make libs" | |||
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16 | @echo "make clean" | |||
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17 | @echo "make vcom_grlib vcom_lpp vcom_tb" | |||
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18 | ||||
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19 | run: | |||
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20 | @vsim work.TB -do run.do | |||
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21 | # @vsim work.TB | |||
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22 | # @vsim lpp.lpp_lfr_ms | |||
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23 | ||||
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24 | vsim: libs vcom run | |||
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25 | ||||
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26 | libs: | |||
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27 | @$(CMD_VLIB) modelsim | |||
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28 | @$(CMD_VMAP) modelsim modelsim | |||
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29 | @$(CMD_VLIB) modelsim/techmap | |||
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30 | @$(CMD_VMAP) techmap modelsim/techmap | |||
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31 | @$(CMD_VLIB) modelsim/grlib | |||
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32 | @$(CMD_VMAP) grlib modelsim/grlib | |||
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33 | @$(CMD_VLIB) modelsim/gaisler | |||
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34 | @$(CMD_VMAP) gaisler modelsim/gaisler | |||
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35 | @$(CMD_VLIB) modelsim/work | |||
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36 | @$(CMD_VMAP) work modelsim/work | |||
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37 | @$(CMD_VLIB) modelsim/lpp | |||
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38 | @$(CMD_VMAP) lpp modelsim/lpp | |||
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39 | @$(CMD_VLIB) modelsim/esa | |||
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40 | @$(CMD_VMAP) esa modelsim/esa | |||
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41 | @echo "libs done" | |||
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42 | ||||
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43 | ||||
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44 | clean: | |||
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45 | @rm -Rf modelsim | |||
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46 | @rm -Rf modelsim.ini | |||
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47 | @rm -Rf *~ | |||
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48 | @rm -Rf transcript | |||
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49 | @rm -Rf wlft* | |||
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50 | @rm -Rf *.wlf | |||
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51 | @rm -Rf vish_stacktrace.vstf | |||
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52 | @rm -Rf libs.do | |||
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53 | ||||
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54 | vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_esa vcom_tb | |||
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55 | ||||
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56 | ||||
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57 | vcom_tb: | |||
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58 | ## $(CMD_VCOM) lpp lpp_memory.vhd | |||
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59 | ## $(CMD_VCOM) lpp lppFIFOxN.vhd | |||
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60 | ## $(CMD_VCOM) lpp lpp_FIFO.vhd | |||
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61 | ## $(CMD_VCOM) lpp lpp_lfr_ms.vhd | |||
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62 | $(CMD_VCOM) lpp ../MINI-LFR_testdma/lpp_lfr_apbreg.vhd | |||
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63 | $(CMD_VCOM) lpp testbench_package.vhd | |||
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64 | $(CMD_VCOM) lpp testbench_package.vhd | |||
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65 | $(CMD_VCOM) work TB.vhd | |||
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66 | @echo "vcom done" | |||
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67 | ||||
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68 | vcom_esa: | |||
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69 | $(CMD_VCOM) esa $(GRLIB)/lib/esa/memoryctrl/memoryctrl.vhd | |||
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70 | $(CMD_VCOM) esa $(GRLIB)/lib/esa/memoryctrl/mctrl.vhd | |||
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71 | @echo "lib esa done" | |||
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72 | ||||
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73 | vcom_grlib: | |||
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74 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd | |||
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75 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd | |||
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76 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd | |||
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77 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd | |||
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78 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd | |||
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79 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd | |||
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80 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd | |||
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81 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd | |||
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82 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd | |||
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83 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd | |||
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84 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd | |||
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85 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd | |||
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86 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd | |||
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87 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd | |||
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88 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd | |||
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89 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd | |||
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90 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd | |||
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91 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd | |||
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92 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd | |||
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93 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd | |||
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94 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd | |||
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95 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd | |||
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96 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd | |||
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97 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd | |||
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98 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd | |||
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99 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd | |||
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100 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd | |||
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101 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd | |||
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102 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd | |||
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103 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd | |||
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104 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd | |||
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105 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd | |||
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106 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd | |||
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107 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd | |||
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108 | @echo "vcom grlib done" | |||
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109 | ||||
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110 | vcom_gaisler: | |||
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111 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd | |||
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112 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd | |||
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113 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd | |||
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114 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd | |||
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115 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd | |||
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116 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd | |||
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117 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd | |||
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118 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd | |||
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119 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd | |||
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120 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd | |||
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121 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd | |||
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122 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd | |||
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123 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd | |||
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124 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd | |||
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125 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd | |||
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126 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd | |||
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127 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd | |||
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128 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd | |||
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129 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd | |||
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130 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd | |||
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131 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd | |||
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132 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd | |||
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133 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd | |||
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134 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd | |||
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135 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd | |||
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136 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd | |||
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137 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd | |||
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138 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd | |||
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139 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd | |||
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140 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd | |||
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141 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd | |||
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142 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd | |||
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143 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd | |||
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144 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd | |||
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145 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd | |||
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146 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd | |||
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147 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd | |||
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148 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd | |||
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149 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd | |||
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150 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd | |||
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151 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd | |||
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152 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd | |||
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153 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd | |||
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154 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd | |||
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155 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd | |||
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156 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd | |||
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157 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd | |||
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158 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd | |||
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159 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd | |||
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160 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd | |||
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161 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd | |||
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162 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd | |||
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163 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd | |||
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164 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd | |||
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165 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd | |||
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166 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd | |||
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167 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd | |||
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168 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd | |||
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169 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd | |||
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170 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd | |||
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171 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd | |||
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172 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd | |||
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173 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd | |||
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174 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd | |||
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175 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd | |||
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176 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd | |||
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177 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd | |||
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178 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd | |||
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179 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd | |||
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180 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd | |||
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181 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd | |||
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182 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd | |||
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183 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd | |||
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184 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd | |||
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185 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd | |||
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186 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd | |||
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187 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd | |||
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188 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd | |||
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189 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd | |||
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190 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd | |||
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191 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd | |||
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192 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd | |||
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193 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd | |||
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194 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd | |||
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195 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd | |||
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196 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd | |||
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197 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd | |||
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198 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd | |||
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199 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd | |||
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200 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd | |||
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201 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd | |||
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202 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd | |||
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203 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd | |||
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204 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd | |||
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205 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd | |||
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206 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd | |||
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207 | ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd | |||
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208 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd | |||
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209 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd | |||
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210 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd | |||
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211 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd | |||
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212 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd | |||
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213 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd | |||
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214 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd | |||
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215 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd | |||
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216 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd | |||
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217 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd | |||
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218 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd | |||
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219 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd | |||
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220 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd | |||
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221 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd | |||
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222 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd | |||
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223 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd | |||
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224 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd | |||
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225 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd | |||
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226 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd | |||
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227 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd | |||
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228 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd | |||
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229 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd | |||
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230 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd | |||
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231 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd | |||
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232 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd | |||
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233 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd | |||
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234 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd | |||
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235 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd | |||
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236 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd | |||
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237 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd | |||
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238 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd | |||
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239 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd | |||
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240 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd | |||
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241 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd | |||
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242 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd | |||
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243 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd | |||
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244 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd | |||
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245 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd | |||
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246 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd | |||
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247 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd | |||
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248 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd | |||
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249 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd | |||
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250 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd | |||
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251 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd | |||
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252 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd | |||
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253 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd | |||
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254 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd | |||
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255 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd | |||
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256 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd | |||
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257 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd | |||
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258 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd | |||
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259 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd | |||
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260 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd | |||
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261 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd | |||
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262 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd | |||
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263 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd | |||
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264 | @echo "vcom gaisler done" | |||
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265 | ||||
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266 | vcom_techmap: | |||
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267 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd | |||
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268 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd | |||
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269 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd | |||
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270 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd | |||
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271 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd | |||
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272 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd | |||
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273 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd | |||
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274 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd | |||
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275 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd | |||
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276 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd | |||
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277 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd | |||
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278 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd | |||
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279 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd | |||
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280 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd | |||
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281 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd | |||
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282 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd | |||
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283 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd | |||
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284 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd | |||
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285 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd | |||
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|
286 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd | |||
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287 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd | |||
|
|
288 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd | |||
|
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289 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd | |||
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290 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd | |||
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291 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd | |||
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|
292 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd | |||
|
|
293 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd | |||
|
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294 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd | |||
|
|
295 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd | |||
|
|
296 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd | |||
|
|
297 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd | |||
|
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298 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd | |||
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299 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd | |||
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|
300 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd | |||
|
|
301 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd | |||
|
|
302 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd | |||
|
|
303 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd | |||
|
|
304 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd | |||
|
|
305 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd | |||
|
|
306 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd | |||
|
|
307 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd | |||
|
|
308 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd | |||
|
|
309 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd | |||
|
|
310 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd | |||
|
|
311 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd | |||
|
|
312 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd | |||
|
|
313 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd | |||
|
|
314 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd | |||
|
|
315 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd | |||
|
|
316 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd | |||
|
|
317 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd | |||
|
|
318 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd | |||
|
|
319 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd | |||
|
|
320 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd | |||
|
|
321 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd | |||
|
|
322 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd | |||
|
|
323 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd | |||
|
|
324 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd | |||
|
|
325 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd | |||
|
|
326 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd | |||
|
|
327 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd | |||
|
|
328 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd | |||
|
|
329 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd | |||
|
|
330 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd | |||
|
|
331 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd | |||
|
|
332 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd | |||
|
|
333 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd | |||
|
|
334 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd | |||
|
|
335 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd | |||
|
|
336 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd | |||
|
|
337 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd | |||
|
|
338 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd | |||
|
|
339 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd | |||
|
|
340 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd | |||
|
|
341 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd | |||
|
|
342 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd | |||
|
|
343 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd | |||
|
|
344 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd | |||
|
|
345 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd | |||
|
|
346 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd | |||
|
|
347 | @echo "vcom techmap done" | |||
|
|
348 | ||||
|
|
349 | vcom_lpp: | |||
|
|
350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/apb_devices_list.vhd | |||
|
|
351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd | |||
|
|
352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd | |||
|
|
353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd | |||
|
|
354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd | |||
|
|
355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd | |||
|
|
356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd | |||
|
|
357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |||
|
|
358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |||
|
|
359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |||
|
|
360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |||
|
|
361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |||
|
|
362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |||
|
|
363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |||
|
|
364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |||
|
|
365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |||
|
|
366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |||
|
|
367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |||
|
|
368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |||
|
|
369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |||
|
|
370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |||
|
|
371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |||
|
|
372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |||
|
|
373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |||
|
|
374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |||
|
|
375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |||
|
|
376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |||
|
|
377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |||
|
|
378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |||
|
|
379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |||
|
|
380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |||
|
|
381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |||
|
|
382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd | |||
|
|
383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |||
|
|
384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |||
|
|
385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |||
|
|
386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd | |||
|
|
387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |||
|
|
388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd | |||
|
|
389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd | |||
|
|
390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd | |||
|
|
391 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd | |||
|
|
392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd | |||
|
|
393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |||
|
|
394 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd | |||
|
|
395 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd | |||
|
|
396 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd | |||
|
|
397 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd | |||
|
|
398 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd | |||
|
|
399 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd | |||
|
|
400 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd | |||
|
|
401 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd | |||
|
|
402 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared.vhd | |||
|
|
403 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_control.vhd | |||
|
|
404 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd | |||
|
|
405 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd | |||
|
|
406 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd | |||
|
|
407 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd | |||
|
|
408 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd | |||
|
|
409 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd | |||
|
|
410 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd | |||
|
|
411 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd | |||
|
|
412 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |||
|
|
413 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/general_purpose.vhd | |||
|
|
414 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/ADDRcntr.vhd | |||
|
|
415 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/ALU.vhd | |||
|
|
416 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Adder.vhd | |||
|
|
417 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clk_Divider2.vhd | |||
|
|
418 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clk_divider.vhd | |||
|
|
419 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC.vhd | |||
|
|
420 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_CONTROLER.vhd | |||
|
|
421 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_MUX.vhd | |||
|
|
422 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_MUX2.vhd | |||
|
|
423 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_REG.vhd | |||
|
|
424 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MUX2.vhd | |||
|
|
425 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MUXN.vhd | |||
|
|
426 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Multiplier.vhd | |||
|
|
427 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/REG.vhd | |||
|
|
428 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/SYNC_FF.vhd | |||
|
|
429 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Shifter.vhd | |||
|
|
430 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/TwoComplementer.vhd | |||
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|
431 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clock_Divider.vhd | |||
|
|
432 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_to_level.vhd | |||
|
|
433 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_detection.vhd | |||
|
|
434 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd | |||
|
|
435 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd | |||
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436 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/RR_Arbiter_4.vhd | |||
|
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437 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/general_counter.vhd | |||
|
|
438 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/apb_devices_list.vhd | |||
|
|
439 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd | |||
|
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440 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd | |||
|
|
441 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd | |||
|
|
442 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM.vhd | |||
|
|
443 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd | |||
|
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444 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd | |||
|
|
445 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd | |||
|
|
446 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |||
|
|
447 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd | |||
|
|
448 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd | |||
|
|
449 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd | |||
|
|
450 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/lpp_lfr_time_management.vhd | |||
|
|
451 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/apb_lfr_time_management.vhd | |||
|
|
452 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/lfr_time_management.vhd | |||
|
|
453 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/fine_time_counter.vhd | |||
|
|
454 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/coarse_time_counter.vhd | |||
|
|
455 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd | |||
|
|
456 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/RHF1401.vhd | |||
|
|
457 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd | |||
|
|
458 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd | |||
|
|
459 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd | |||
|
|
460 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd | |||
|
|
461 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd | |||
|
|
462 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd | |||
|
|
463 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/MS_control.vhd | |||
|
|
464 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd | |||
|
|
465 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd | |||
|
|
466 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_demux/DEMUX.vhd | |||
|
|
467 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_demux/lpp_demux.vhd | |||
|
|
468 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/lpp_Header.vhd | |||
|
|
469 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/HeaderBuilder.vhd | |||
|
|
470 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/ALU_Driver.vhd | |||
|
|
471 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd | |||
|
|
472 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/Dispatch.vhd | |||
|
|
473 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/DriveInputs.vhd | |||
|
|
474 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/GetResult.vhd | |||
|
|
475 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd | |||
|
|
476 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/Matrix.vhd | |||
|
|
477 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/SpectralMatrix.vhd | |||
|
|
478 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd | |||
|
|
479 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/lpp_matrix.vhd | |||
|
|
480 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lpp_memory.vhd | |||
|
|
481 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lpp_FIFO.vhd | |||
|
|
482 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lppFIFOxN.vhd | |||
|
|
483 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd | |||
|
|
484 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/fifo_latency_correction.vhd | |||
|
|
485 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd | |||
|
|
486 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma.vhd | |||
|
|
487 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_ip.vhd | |||
|
|
488 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd | |||
|
|
489 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd | |||
|
|
490 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd | |||
|
|
491 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform.vhd | |||
|
|
492 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd | |||
|
|
493 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd | |||
|
|
494 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd | |||
|
|
495 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd | |||
|
|
496 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd | |||
|
|
497 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd | |||
|
|
498 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd | |||
|
|
499 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd | |||
|
|
500 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd | |||
|
|
501 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd | |||
|
|
502 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd | |||
|
|
503 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd | |||
|
|
504 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd | |||
|
|
505 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd | |||
|
|
506 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd | |||
|
|
507 | ## $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd | |||
|
|
508 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd | |||
|
|
509 | ## $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd | |||
|
|
510 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |||
|
|
511 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd | |||
|
|
512 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd | |||
|
|
513 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd | |||
|
|
514 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/lpp_Header.vhd | |||
|
|
515 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/HeaderBuilder.vhd | |||
|
|
516 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd | |||
|
|
517 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd | |||
|
|
518 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd | |||
|
|
519 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd | |||
|
|
520 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd | |||
|
|
521 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd | |||
|
|
522 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr.vhd | |||
|
|
523 | ## $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd | |||
|
|
524 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd | |||
|
|
525 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd | |||
|
|
526 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |||
|
|
527 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd | |||
|
|
528 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/DMA_SubSystem.vhd | |||
|
|
529 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd | |||
|
|
530 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/DMA_SubSystem_Arbiter.vhd | |||
|
|
531 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/DMA_SubSystem_MUX.vhd | |||
|
|
532 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/package_utility.vhd | |||
|
|
533 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/package_timing.vhd | |||
|
|
534 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33_pkg.vhd | |||
|
|
535 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd | |||
|
|
536 | @echo "vcom lpp done" | |||
|
|
537 | ||||
|
|
538 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |||
|
|
539 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |||
|
|
540 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |||
|
|
541 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |||
|
|
542 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |||
|
|
543 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |||
|
|
544 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |||
|
|
545 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |||
|
|
546 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |||
|
|
547 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |||
|
|
548 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |||
|
|
549 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |||
|
|
550 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |||
|
|
551 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |||
|
|
552 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |||
|
|
553 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |||
|
|
554 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |||
|
|
555 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |||
|
|
556 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |||
|
|
557 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |||
|
|
558 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |||
|
|
559 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |||
|
|
560 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |||
|
|
561 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |||
|
|
562 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |||
|
|
563 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd | |||
|
|
564 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd | |||
|
|
565 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd | |||
|
|
566 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd | |||
|
|
567 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd | |||
|
|
568 | # @echo "vcom lpp done" | |||
|
|
569 | ||||
|
|
570 | #include Makefile_vcom_lpp | |||
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1 | ------------------------------------------------------------------------------ | |||
|
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------- | |||
|
|
19 | -- Author : Jean-christophe Pellion | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------- | |||
|
|
22 | ||||
|
|
23 | LIBRARY IEEE; | |||
|
|
24 | USE IEEE.STD_LOGIC_1164.ALL; | |||
|
|
25 | USE IEEE.NUMERIC_STD.ALL; | |||
|
|
26 | ||||
|
|
27 | LIBRARY lpp; | |||
|
|
28 | USE lpp.lpp_ad_conv.ALL; | |||
|
|
29 | USE lpp.iir_filter.ALL; | |||
|
|
30 | USE lpp.FILTERcfg.ALL; | |||
|
|
31 | USE lpp.lpp_memory.ALL; | |||
|
|
32 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
33 | USE lpp.lpp_dma_pkg.ALL; | |||
|
|
34 | USE lpp.lpp_top_lfr_pkg.ALL; | |||
|
|
35 | USE lpp.lpp_lfr_pkg.ALL; | |||
|
|
36 | USE lpp.general_purpose.ALL; | |||
|
|
37 | USE lpp.lpp_lfr_pkg.ALL; | |||
|
|
38 | USE lpp.lpp_memory.ALL; | |||
|
|
39 | USE lpp.iir_filter.ALL; | |||
|
|
40 | USE lpp.spectral_matrix_package.ALL; | |||
|
|
41 | USE lpp.lpp_fft.ALL; | |||
|
|
42 | USE lpp.fft_components.ALL; | |||
|
|
43 | USE lpp.CY7C1061DV33_pkg.ALL; | |||
|
|
44 | USE lpp.testbench_package.ALL; | |||
|
|
45 | ||||
|
|
46 | ||||
|
|
47 | LIBRARY grlib; | |||
|
|
48 | USE grlib.amba.ALL; | |||
|
|
49 | USE grlib.stdlib.ALL; | |||
|
|
50 | USE grlib.devices.ALL; | |||
|
|
51 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
|
52 | ||||
|
|
53 | LIBRARY gaisler; | |||
|
|
54 | USE gaisler.memctrl.ALL; | |||
|
|
55 | USE gaisler.misc.ALL; | |||
|
|
56 | ||||
|
|
57 | LIBRARY techmap; | |||
|
|
58 | USE techmap.gencomp.ALL; | |||
|
|
59 | ||||
|
|
60 | LIBRARY esa; | |||
|
|
61 | USE esa.memoryctrl.ALL; | |||
|
|
62 | ||||
|
|
63 | ||||
|
|
64 | ENTITY TB IS | |||
|
|
65 | END TB; | |||
|
|
66 | ||||
|
|
67 | ||||
|
|
68 | ARCHITECTURE beh OF TB IS | |||
|
|
69 | ||||
|
|
70 | COMPONENT lpp_lfr_apbreg_tb | |||
|
|
71 | GENERIC ( | |||
|
|
72 | pindex : INTEGER; | |||
|
|
73 | paddr : INTEGER; | |||
|
|
74 | pmask : INTEGER); | |||
|
|
75 | PORT ( | |||
|
|
76 | HCLK : IN STD_ULOGIC; | |||
|
|
77 | HRESETn : IN STD_ULOGIC; | |||
|
|
78 | apbi : IN apb_slv_in_type; | |||
|
|
79 | apbo : OUT apb_slv_out_type; | |||
|
|
80 | fifo_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
81 | fifo_wdata : OUT STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |||
|
|
82 | fifo_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
83 | fifo_full_almost : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
84 | fifo_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
85 | fifo_empty_threshold : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
86 | buffer_new : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
87 | buffer_length : OUT STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); | |||
|
|
88 | buffer_addr : OUT STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |||
|
|
89 | buffer_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
90 | buffer_full_err : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
91 | grant_error : IN STD_LOGIC); | |||
|
|
92 | END COMPONENT; | |||
|
|
93 | ||||
|
|
94 | COMPONENT DMA_SubSystem | |||
|
|
95 | GENERIC ( | |||
|
|
96 | hindex : INTEGER); | |||
|
|
97 | PORT ( | |||
|
|
98 | clk : IN STD_LOGIC; | |||
|
|
99 | rstn : IN STD_LOGIC; | |||
|
|
100 | run : IN STD_LOGIC; | |||
|
|
101 | ahbi : IN AHB_Mst_In_Type; | |||
|
|
102 | ahbo : OUT AHB_Mst_Out_Type; | |||
|
|
103 | fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
104 | fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |||
|
|
105 | fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
106 | buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
107 | buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |||
|
|
108 | buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); | |||
|
|
109 | buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
110 | buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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111 | grant_error : OUT STD_LOGIC); | |||
|
|
112 | END COMPONENT; | |||
|
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113 | ||||
|
|
114 | CONSTANT INDEX_DMA_SUBSYSTEM : INTEGER := 15; | |||
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115 | CONSTANT ADDR_DMA_SUBSYSTEM : INTEGER := 15; | |||
|
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116 | ||||
|
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117 | ||||
|
|
118 | -- REG DMA_SubSystem | |||
|
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119 | CONSTANT ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00"; | |||
|
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120 | CONSTANT ADDR_DMA_SUBSYSTEM_F0_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; | |||
|
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121 | CONSTANT ADDR_DMA_SUBSYSTEM_F0_LENGTH : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; | |||
|
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122 | ||||
|
|
123 | CONSTANT ADDR_DMA_SUBSYSTEM_F1_wDATA_rSTATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; | |||
|
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124 | CONSTANT ADDR_DMA_SUBSYSTEM_F1_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; | |||
|
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125 | CONSTANT ADDR_DMA_SUBSYSTEM_F1_LENGTH : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; | |||
|
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126 | ||||
|
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127 | CONSTANT ADDR_DMA_SUBSYSTEM_F2_wDATA_rSTATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; | |||
|
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128 | CONSTANT ADDR_DMA_SUBSYSTEM_F2_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; | |||
|
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129 | CONSTANT ADDR_DMA_SUBSYSTEM_F2_LENGTH : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; | |||
|
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130 | ||||
|
|
131 | CONSTANT ADDR_DMA_SUBSYSTEM_F3_wDATA_rSTATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; | |||
|
|
132 | CONSTANT ADDR_DMA_SUBSYSTEM_F3_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; | |||
|
|
133 | CONSTANT ADDR_DMA_SUBSYSTEM_F3_LENGTH : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; | |||
|
|
134 | ||||
|
|
135 | CONSTANT ADDR_DMA_SUBSYSTEM_F4_wDATA_rSTATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; | |||
|
|
136 | CONSTANT ADDR_DMA_SUBSYSTEM_F4_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; | |||
|
|
137 | CONSTANT ADDR_DMA_SUBSYSTEM_F4_LENGTH : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; | |||
|
|
138 | -- RAM ADDRESS | |||
|
|
139 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#000#; | |||
|
|
140 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; | |||
|
|
141 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; | |||
|
|
142 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; | |||
|
|
143 | ||||
|
|
144 | ||||
|
|
145 | -- Common signal | |||
|
|
146 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; | |||
|
|
147 | SIGNAL clk25MHz : STD_LOGIC := '0'; | |||
|
|
148 | SIGNAL rstn : STD_LOGIC := '0'; | |||
|
|
149 | ||||
|
|
150 | -- ADC interface | |||
|
|
151 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT | |||
|
|
152 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT | |||
|
|
153 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN | |||
|
|
154 | ||||
|
|
155 | -- AD Converter RHF1401 | |||
|
|
156 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |||
|
|
157 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |||
|
|
158 | SIGNAL sample_val : STD_LOGIC; | |||
|
|
159 | ||||
|
|
160 | -- AHB/APB SIGNAL | |||
|
|
161 | SIGNAL apbi : apb_slv_in_type; | |||
|
|
162 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |||
|
|
163 | SIGNAL ahbsi : ahb_slv_in_type; | |||
|
|
164 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |||
|
|
165 | SIGNAL ahbmi : ahb_mst_in_type; | |||
|
|
166 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |||
|
|
167 | ||||
|
|
168 | SIGNAL bias_fail_bw : STD_LOGIC; | |||
|
|
169 | ||||
|
|
170 | ----------------------------------------------------------------------------- | |||
|
|
171 | -- LPP_WAVEFORM | |||
|
|
172 | ----------------------------------------------------------------------------- | |||
|
|
173 | CONSTANT data_size : INTEGER := 96; | |||
|
|
174 | CONSTANT nb_burst_available_size : INTEGER := 50; | |||
|
|
175 | CONSTANT nb_snapshot_param_size : INTEGER := 2; | |||
|
|
176 | CONSTANT delta_vector_size : INTEGER := 2; | |||
|
|
177 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; | |||
|
|
178 | ||||
|
|
179 | SIGNAL reg_run : STD_LOGIC; | |||
|
|
180 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |||
|
|
181 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |||
|
|
182 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |||
|
|
183 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |||
|
|
184 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |||
|
|
185 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |||
|
|
186 | SIGNAL enable_f0 : STD_LOGIC; | |||
|
|
187 | SIGNAL enable_f1 : STD_LOGIC; | |||
|
|
188 | SIGNAL enable_f2 : STD_LOGIC; | |||
|
|
189 | SIGNAL enable_f3 : STD_LOGIC; | |||
|
|
190 | SIGNAL burst_f0 : STD_LOGIC; | |||
|
|
191 | SIGNAL burst_f1 : STD_LOGIC; | |||
|
|
192 | SIGNAL burst_f2 : STD_LOGIC; | |||
|
|
193 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
|
194 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
|
195 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
196 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
197 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
198 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
199 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
200 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
201 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
202 | SIGNAL data_f0_in_valid : STD_LOGIC; | |||
|
|
203 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
204 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
205 | SIGNAL data_f1_in_valid : STD_LOGIC; | |||
|
|
206 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
207 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
208 | SIGNAL data_f2_in_valid : STD_LOGIC; | |||
|
|
209 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
210 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
211 | SIGNAL data_f3_in_valid : STD_LOGIC; | |||
|
|
212 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
|
213 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
214 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
215 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |||
|
|
216 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |||
|
|
217 | SIGNAL data_f0_data_out_ack : STD_LOGIC; | |||
|
|
218 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
219 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
220 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |||
|
|
221 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |||
|
|
222 | SIGNAL data_f1_data_out_ack : STD_LOGIC; | |||
|
|
223 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
224 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
225 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |||
|
|
226 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |||
|
|
227 | SIGNAL data_f2_data_out_ack : STD_LOGIC; | |||
|
|
228 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
229 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
230 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |||
|
|
231 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |||
|
|
232 | SIGNAL data_f3_data_out_ack : STD_LOGIC; | |||
|
|
233 | ||||
|
|
234 | --MEM CTRLR | |||
|
|
235 | SIGNAL memi : memory_in_type; | |||
|
|
236 | SIGNAL memo : memory_out_type; | |||
|
|
237 | SIGNAL wpo : wprot_out_type; | |||
|
|
238 | SIGNAL sdo : sdram_out_type; | |||
|
|
239 | ||||
|
|
240 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; | |||
|
|
241 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
242 | SIGNAL nSRAM_BE0 : STD_LOGIC; | |||
|
|
243 | SIGNAL nSRAM_BE1 : STD_LOGIC; | |||
|
|
244 | SIGNAL nSRAM_BE2 : STD_LOGIC; | |||
|
|
245 | SIGNAL nSRAM_BE3 : STD_LOGIC; | |||
|
|
246 | SIGNAL nSRAM_WE : STD_LOGIC; | |||
|
|
247 | SIGNAL nSRAM_CE : STD_LOGIC; | |||
|
|
248 | SIGNAL nSRAM_OE : STD_LOGIC; | |||
|
|
249 | ||||
|
|
250 | CONSTANT padtech : INTEGER := inferred; | |||
|
|
251 | SIGNAL not_ramsn_0 : STD_LOGIC; | |||
|
|
252 | ||||
|
|
253 | ----------------------------------------------------------------------------- | |||
|
|
254 | SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
255 | SIGNAL read_buffer : STD_LOGIC; | |||
|
|
256 | ----------------------------------------------------------------------------- | |||
|
|
257 | SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; | |||
|
|
258 | SIGNAL state_read_buffer_on_going : STD_LOGIC; | |||
|
|
259 | CONSTANT hindex : INTEGER := 1; | |||
|
|
260 | SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |||
|
|
261 | SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |||
|
|
262 | SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |||
|
|
263 | SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0); | |||
|
|
264 | ||||
|
|
265 | SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
266 | SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
267 | SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
268 | SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
269 | ----------------------------------------------------------------------------- | |||
|
|
270 | ||||
|
|
271 | ||||
|
|
272 | ||||
|
|
273 | ----------------------------------------------------------------------------- | |||
|
|
274 | SIGNAL run : STD_LOGIC; | |||
|
|
275 | ||||
|
|
276 | SIGNAL fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
277 | SIGNAL fifo_wdata : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |||
|
|
278 | SIGNAL fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
279 | SIGNAL fifo_rdata : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |||
|
|
280 | ||||
|
|
281 | SIGNAL fifo_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
282 | SIGNAL fifo_full_almost : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
283 | SIGNAL fifo_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
284 | SIGNAL fifo_empty_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
285 | SIGNAL fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
286 | ||||
|
|
287 | SIGNAL buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
288 | SIGNAL buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); | |||
|
|
289 | SIGNAL buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); | |||
|
|
290 | SIGNAL buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
291 | SIGNAL buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
292 | ||||
|
|
293 | SIGNAL grant_error :STD_LOGIC; | |||
|
|
294 | ||||
|
|
295 | BEGIN | |||
|
|
296 | ||||
|
|
297 | ----------------------------------------------------------------------------- | |||
|
|
298 | ||||
|
|
299 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz | |||
|
|
300 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz | |||
|
|
301 | ||||
|
|
302 | ||||
|
|
303 | ||||
|
|
304 | ----------------------------------------------------------------------------- | |||
|
|
305 | -- DMA SUBSYSTEM | |||
|
|
306 | ----------------------------------------------------------------------------- | |||
|
|
307 | lpp_lfr_apbreg_tb_1: lpp_lfr_apbreg_tb | |||
|
|
308 | GENERIC MAP ( | |||
|
|
309 | pindex => INDEX_DMA_SUBSYSTEM, | |||
|
|
310 | paddr => ADDR_DMA_SUBSYSTEM, | |||
|
|
311 | pmask => 16#fff#) | |||
|
|
312 | PORT MAP ( | |||
|
|
313 | HCLK => clk25MHz, | |||
|
|
314 | HRESETn => rstn, | |||
|
|
315 | apbi => apbi, | |||
|
|
316 | apbo => apbo(INDEX_DMA_SUBSYSTEM), | |||
|
|
317 | ||||
|
|
318 | fifo_wen => fifo_wen, | |||
|
|
319 | fifo_wdata => fifo_wdata, | |||
|
|
320 | fifo_full => fifo_full, | |||
|
|
321 | fifo_full_almost => fifo_full_almost, | |||
|
|
322 | fifo_empty => fifo_empty, | |||
|
|
323 | fifo_empty_threshold => fifo_empty_threshold, | |||
|
|
324 | ||||
|
|
325 | buffer_new => buffer_new, | |||
|
|
326 | buffer_length => buffer_length, | |||
|
|
327 | buffer_addr => buffer_addr, | |||
|
|
328 | buffer_full => buffer_full, | |||
|
|
329 | buffer_full_err => buffer_full_err, | |||
|
|
330 | ||||
|
|
331 | grant_error => grant_error); | |||
|
|
332 | ||||
|
|
333 | all_fifo: FOR I IN 4 DOWNTO 0 GENERATE | |||
|
|
334 | lpp_fifo_I: lpp_fifo | |||
|
|
335 | GENERIC MAP ( | |||
|
|
336 | tech => inferred, | |||
|
|
337 | Mem_use => use_RAM, | |||
|
|
338 | EMPTY_THRESHOLD_LIMIT => 15, | |||
|
|
339 | FULL_THRESHOLD_LIMIT => 1, | |||
|
|
340 | DataSz => 32, | |||
|
|
341 | AddrSz => 7) | |||
|
|
342 | PORT MAP ( | |||
|
|
343 | clk => clk25MHz, | |||
|
|
344 | rstn => rstn, | |||
|
|
345 | reUse => '0', | |||
|
|
346 | run => run, | |||
|
|
347 | ||||
|
|
348 | ren => fifo_ren(I), | |||
|
|
349 | rdata => fifo_rdata(32*(I+1)-1 DOWNTO 32*i), | |||
|
|
350 | ||||
|
|
351 | wen => fifo_wen(I), | |||
|
|
352 | wdata => fifo_wdata(32*(I+1)-1 DOWNTO 32*i), | |||
|
|
353 | ||||
|
|
354 | empty => fifo_empty(I), | |||
|
|
355 | full => fifo_full(I), | |||
|
|
356 | full_almost => fifo_full_almost(I), | |||
|
|
357 | empty_threshold => fifo_empty_threshold(I), | |||
|
|
358 | ||||
|
|
359 | full_threshold => OPEN); | |||
|
|
360 | ||||
|
|
361 | fifo_burst_valid(I) <= NOT fifo_empty_threshold(I); | |||
|
|
362 | ||||
|
|
363 | END GENERATE all_fifo; | |||
|
|
364 | ||||
|
|
365 | ||||
|
|
366 | ||||
|
|
367 | DMA_SubSystem_1: DMA_SubSystem | |||
|
|
368 | GENERIC MAP ( | |||
|
|
369 | hindex => 0) | |||
|
|
370 | PORT MAP ( | |||
|
|
371 | clk => clk25MHz, | |||
|
|
372 | rstn => rstn, | |||
|
|
373 | run => run, | |||
|
|
374 | ahbi => ahbmi, | |||
|
|
375 | ahbo => ahbmo(0), | |||
|
|
376 | ||||
|
|
377 | fifo_burst_valid => fifo_burst_valid, | |||
|
|
378 | fifo_data => fifo_rdata, | |||
|
|
379 | fifo_ren => fifo_ren, | |||
|
|
380 | buffer_new => buffer_new, | |||
|
|
381 | buffer_addr => buffer_addr, | |||
|
|
382 | buffer_length => buffer_length, | |||
|
|
383 | buffer_full => buffer_full, | |||
|
|
384 | buffer_full_err => buffer_full_err, | |||
|
|
385 | grant_error => grant_error); | |||
|
|
386 | ||||
|
|
387 | ||||
|
|
388 | ----------------------------------------------------------------------------- | |||
|
|
389 | --- AHB CONTROLLER ------------------------------------------------- | |||
|
|
390 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |||
|
|
391 | GENERIC MAP (defmast => 0, split => 0, | |||
|
|
392 | rrobin => 1, ioaddr => 16#FFF#, | |||
|
|
393 | ioen => 0, nahbm => 2, nahbs => 1) | |||
|
|
394 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); | |||
|
|
395 | ||||
|
|
396 | ||||
|
|
397 | ||||
|
|
398 | --- AHB RAM ---------------------------------------------------------- | |||
|
|
399 | --ahbram0 : ahbram | |||
|
|
400 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) | |||
|
|
401 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); | |||
|
|
402 | --ahbram1 : ahbram | |||
|
|
403 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) | |||
|
|
404 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); | |||
|
|
405 | --ahbram2 : ahbram | |||
|
|
406 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) | |||
|
|
407 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); | |||
|
|
408 | --ahbram3 : ahbram | |||
|
|
409 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) | |||
|
|
410 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); | |||
|
|
411 | ||||
|
|
412 | ----------------------------------------------------------------------------- | |||
|
|
413 | ---------------------------------------------------------------------- | |||
|
|
414 | --- Memory controllers --------------------------------------------- | |||
|
|
415 | ---------------------------------------------------------------------- | |||
|
|
416 | memctrlr : mctrl GENERIC MAP ( | |||
|
|
417 | hindex => 0, | |||
|
|
418 | pindex => 0, | |||
|
|
419 | paddr => 0, | |||
|
|
420 | srbanks => 1 | |||
|
|
421 | ) | |||
|
|
422 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |||
|
|
423 | ||||
|
|
424 | memi.brdyn <= '1'; | |||
|
|
425 | memi.bexcn <= '1'; | |||
|
|
426 | memi.writen <= '1'; | |||
|
|
427 | memi.wrn <= "1111"; | |||
|
|
428 | memi.bwidth <= "10"; | |||
|
|
429 | ||||
|
|
430 | bdr : FOR i IN 0 TO 3 GENERATE | |||
|
|
431 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |||
|
|
432 | PORT MAP ( | |||
|
|
433 | data(31-i*8 DOWNTO 24-i*8), | |||
|
|
434 | memo.data(31-i*8 DOWNTO 24-i*8), | |||
|
|
435 | memo.bdrive(i), | |||
|
|
436 | memi.data(31-i*8 DOWNTO 24-i*8)); | |||
|
|
437 | END GENERATE; | |||
|
|
438 | ||||
|
|
439 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |||
|
|
440 | PORT MAP (address, memo.address(21 DOWNTO 2)); | |||
|
|
441 | ||||
|
|
442 | not_ramsn_0 <= NOT(memo.ramsn(0)); | |||
|
|
443 | ||||
|
|
444 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); | |||
|
|
445 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |||
|
|
446 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |||
|
|
447 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |||
|
|
448 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |||
|
|
449 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |||
|
|
450 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |||
|
|
451 | ||||
|
|
452 | async_1Mx16_0 : CY7C1061DV33 | |||
|
|
453 | GENERIC MAP ( | |||
|
|
454 | ADDR_BITS => 20, | |||
|
|
455 | DATA_BITS => 16, | |||
|
|
456 | depth => 1048576, | |||
|
|
457 | MEM_ARRAY_DEBUG => 32, | |||
|
|
458 | TimingInfo => true, | |||
|
|
459 | TimingChecks => '1') | |||
|
|
460 | PORT MAP ( | |||
|
|
461 | CE1_b => '0', | |||
|
|
462 | CE2 => nSRAM_CE, | |||
|
|
463 | WE_b => nSRAM_WE, | |||
|
|
464 | OE_b => nSRAM_OE, | |||
|
|
465 | BHE_b => nSRAM_BE1, | |||
|
|
466 | BLE_b => nSRAM_BE0, | |||
|
|
467 | A => address, | |||
|
|
468 | DQ => data(15 DOWNTO 0)); | |||
|
|
469 | ||||
|
|
470 | async_1Mx16_1 : CY7C1061DV33 | |||
|
|
471 | GENERIC MAP ( | |||
|
|
472 | ADDR_BITS => 20, | |||
|
|
473 | DATA_BITS => 16, | |||
|
|
474 | depth => 1048576, | |||
|
|
475 | MEM_ARRAY_DEBUG => 32, | |||
|
|
476 | TimingInfo => true, | |||
|
|
477 | TimingChecks => '1') | |||
|
|
478 | PORT MAP ( | |||
|
|
479 | CE1_b => '0', | |||
|
|
480 | CE2 => nSRAM_CE, | |||
|
|
481 | WE_b => nSRAM_WE, | |||
|
|
482 | OE_b => nSRAM_OE, | |||
|
|
483 | BHE_b => nSRAM_BE3, | |||
|
|
484 | BLE_b => nSRAM_BE2, | |||
|
|
485 | A => address, | |||
|
|
486 | DQ => data(31 DOWNTO 16)); | |||
|
|
487 | ||||
|
|
488 | ||||
|
|
489 | ----------------------------------------------------------------------------- | |||
|
|
490 | ||||
|
|
491 | WaveGen_Proc : PROCESS | |||
|
|
492 | BEGIN | |||
|
|
493 | ||||
|
|
494 | -- insert signal assignments here | |||
|
|
495 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
496 | run <= '0'; | |||
|
|
497 | rstn <= '0'; | |||
|
|
498 | apbi.psel(15) <= '0'; | |||
|
|
499 | apbi.pwrite <= '0'; | |||
|
|
500 | apbi.penable <= '0'; | |||
|
|
501 | apbi.paddr <= (OTHERS => '0'); | |||
|
|
502 | apbi.pwdata <= (OTHERS => '0'); | |||
|
|
503 | fine_time <= (OTHERS => '0'); | |||
|
|
504 | coarse_time <= (OTHERS => '0'); | |||
|
|
505 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
506 | ||||
|
|
507 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
508 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
509 | rstn <= '1'; | |||
|
|
510 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
511 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
512 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
513 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
514 | run <= '1'; | |||
|
|
515 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
516 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
517 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
518 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
519 | ||||
|
|
520 | WAIT UNTIL clk25MHz = '1'; | |||
|
|
521 | ||||
|
|
522 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_ADDR , X"40000000"); | |||
|
|
523 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_LENGTH , X"00000002"); | |||
|
|
524 | ||||
|
|
525 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000001"); --1 | |||
|
|
526 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000002"); | |||
|
|
527 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000003"); | |||
|
|
528 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000004"); | |||
|
|
529 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000005"); | |||
|
|
530 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000006"); | |||
|
|
531 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000007"); | |||
|
|
532 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000008"); | |||
|
|
533 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000009"); | |||
|
|
534 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000A"); | |||
|
|
535 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000B"); | |||
|
|
536 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000C"); | |||
|
|
537 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000D"); | |||
|
|
538 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000E"); | |||
|
|
539 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000F"); | |||
|
|
540 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000010"); --16 | |||
|
|
541 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000011"); | |||
|
|
542 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000012"); | |||
|
|
543 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000013"); | |||
|
|
544 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000014"); | |||
|
|
545 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000015"); | |||
|
|
546 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000016"); | |||
|
|
547 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000017"); | |||
|
|
548 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000018"); | |||
|
|
549 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000019"); | |||
|
|
550 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001A"); | |||
|
|
551 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001B"); | |||
|
|
552 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001C"); | |||
|
|
553 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001D"); | |||
|
|
554 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001E"); | |||
|
|
555 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001F"); | |||
|
|
556 | APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000020"); --32 | |||
|
|
557 | ||||
|
|
558 | ||||
|
|
559 | WAIT FOR 1 ms; | |||
|
|
560 | REPORT "*** END simulation ***" SEVERITY failure; | |||
|
|
561 | ||||
|
|
562 | ||||
|
|
563 | WAIT; | |||
|
|
564 | ||||
|
|
565 | END PROCESS WaveGen_Proc; | |||
|
|
566 | ----------------------------------------------------------------------------- | |||
|
|
567 | ||||
|
|
568 | END beh; | |||
|
|
569 | ||||
| @@ -0,0 +1,136 | |||||
|
|
1 | ||||
|
|
2 | LIBRARY ieee; | |||
|
|
3 | USE ieee.std_logic_1164.ALL; | |||
|
|
4 | LIBRARY grlib; | |||
|
|
5 | USE grlib.amba.ALL; | |||
|
|
6 | USE grlib.stdlib.ALL; | |||
|
|
7 | --LIBRARY gaisler; | |||
|
|
8 | --USE gaisler.libdcom.ALL; | |||
|
|
9 | --USE gaisler.sim.ALL; | |||
|
|
10 | --USE gaisler.jtagtst.ALL; | |||
|
|
11 | --LIBRARY techmap; | |||
|
|
12 | --USE techmap.gencomp.ALL; | |||
|
|
13 | ||||
|
|
14 | ||||
|
|
15 | PACKAGE testbench_package IS | |||
|
|
16 | ||||
|
|
17 | PROCEDURE APB_WRITE ( | |||
|
|
18 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
19 | CONSTANT pindex : IN INTEGER; | |||
|
|
20 | SIGNAL apbi : OUT apb_slv_in_type; | |||
|
|
21 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
22 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
23 | ); | |||
|
|
24 | ||||
|
|
25 | PROCEDURE APB_READ ( | |||
|
|
26 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
27 | CONSTANT pindex : IN INTEGER; | |||
|
|
28 | SIGNAL apbi : OUT apb_slv_in_type; | |||
|
|
29 | SIGNAL apbo : IN apb_slv_out_type; | |||
|
|
30 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
31 | SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
32 | ); | |||
|
|
33 | ||||
|
|
34 | PROCEDURE AHB_READ ( | |||
|
|
35 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
36 | CONSTANT hindex : IN INTEGER; | |||
|
|
37 | SIGNAL ahbmi : IN ahb_mst_in_type; | |||
|
|
38 | SIGNAL ahbmo : OUT ahb_mst_out_type; | |||
|
|
39 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
40 | SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
41 | ); | |||
|
|
42 | ||||
|
|
43 | END testbench_package; | |||
|
|
44 | ||||
|
|
45 | PACKAGE BODY testbench_package IS | |||
|
|
46 | ||||
|
|
47 | PROCEDURE APB_WRITE ( | |||
|
|
48 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
49 | CONSTANT pindex : IN INTEGER; | |||
|
|
50 | SIGNAL apbi : OUT apb_slv_in_type; | |||
|
|
51 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
52 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
53 | ) IS | |||
|
|
54 | BEGIN | |||
|
|
55 | apbi.psel(pindex) <= '1'; | |||
|
|
56 | apbi.pwrite <= '1'; | |||
|
|
57 | apbi.penable <= '1'; | |||
|
|
58 | apbi.paddr <= paddr; | |||
|
|
59 | apbi.pwdata <= pwdata; | |||
|
|
60 | WAIT UNTIL clk = '0'; | |||
|
|
61 | WAIT UNTIL clk = '1'; | |||
|
|
62 | apbi.psel(pindex) <= '0'; | |||
|
|
63 | apbi.pwrite <= '0'; | |||
|
|
64 | apbi.penable <= '0'; | |||
|
|
65 | apbi.paddr <= (OTHERS => '0'); | |||
|
|
66 | apbi.pwdata <= (OTHERS => '0'); | |||
|
|
67 | WAIT UNTIL clk = '0'; | |||
|
|
68 | WAIT UNTIL clk = '1'; | |||
|
|
69 | ||||
|
|
70 | END APB_WRITE; | |||
|
|
71 | ||||
|
|
72 | PROCEDURE APB_READ ( | |||
|
|
73 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
74 | CONSTANT pindex : IN INTEGER; | |||
|
|
75 | SIGNAL apbi : OUT apb_slv_in_type; | |||
|
|
76 | SIGNAL apbo : IN apb_slv_out_type; | |||
|
|
77 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
78 | SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
79 | ) IS | |||
|
|
80 | BEGIN | |||
|
|
81 | apbi.psel(pindex) <= '1'; | |||
|
|
82 | apbi.pwrite <= '0'; | |||
|
|
83 | apbi.penable <= '1'; | |||
|
|
84 | apbi.paddr <= paddr; | |||
|
|
85 | WAIT UNTIL clk = '0'; | |||
|
|
86 | WAIT UNTIL clk = '1'; | |||
|
|
87 | apbi.psel(pindex) <= '0'; | |||
|
|
88 | apbi.pwrite <= '0'; | |||
|
|
89 | apbi.penable <= '0'; | |||
|
|
90 | apbi.paddr <= (OTHERS => '0'); | |||
|
|
91 | WAIT UNTIL clk = '0'; | |||
|
|
92 | WAIT UNTIL clk = '1'; | |||
|
|
93 | prdata <= apbo.prdata; | |||
|
|
94 | END APB_READ; | |||
|
|
95 | ||||
|
|
96 | PROCEDURE AHB_READ ( | |||
|
|
97 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
98 | CONSTANT hindex : IN INTEGER; | |||
|
|
99 | SIGNAL ahbmi : IN ahb_mst_in_type; | |||
|
|
100 | SIGNAL ahbmo : OUT ahb_mst_out_type; | |||
|
|
101 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
102 | SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
103 | ) IS | |||
|
|
104 | BEGIN | |||
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|
105 | WAIT UNTIL clk = '1'; | |||
|
|
106 | ahbmo.HADDR <= haddr; | |||
|
|
107 | ahbmo.HPROT <= "0011"; | |||
|
|
108 | ahbmo.HIRQ <= (OTHERS => '0'); | |||
|
|
109 | ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); | |||
|
|
110 | ahbmo.HINDEX <= hindex; | |||
|
|
111 | ahbmo.HBUSREQ <= '1'; | |||
|
|
112 | ahbmo.HLOCK <= '1'; | |||
|
|
113 | ahbmo.HSIZE <= HSIZE_WORD; | |||
|
|
114 | ahbmo.HBURST <= HBURST_SINGLE; | |||
|
|
115 | ahbmo.HTRANS <= HTRANS_NONSEQ; | |||
|
|
116 | ahbmo.HWRITE <= '0'; | |||
|
|
117 | WHILE ahbmi.HREADY = '0' LOOP | |||
|
|
118 | WAIT UNTIL clk = '1'; | |||
|
|
119 | END LOOP; | |||
|
|
120 | WAIT UNTIL clk = '1'; | |||
|
|
121 | --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; | |||
|
|
122 | ahbmo.HBUSREQ <= '0'; | |||
|
|
123 | ahbmo.HLOCK <= '0'; | |||
|
|
124 | ahbmo.HTRANS <= HTRANS_IDLE; | |||
|
|
125 | WHILE ahbmi.HREADY = '0' LOOP | |||
|
|
126 | WAIT UNTIL clk = '1'; | |||
|
|
127 | END LOOP; | |||
|
|
128 | WAIT UNTIL clk = '1'; | |||
|
|
129 | hrdata <= ahbmi.HRDATA; | |||
|
|
130 | --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; | |||
|
|
131 | ahbmo.HLOCK <= '0'; | |||
|
|
132 | WAIT UNTIL clk = '1'; | |||
|
|
133 | ||||
|
|
134 | END AHB_READ; | |||
|
|
135 | ||||
|
|
136 | END testbench_package; | |||
| @@ -0,0 +1,46 | |||||
|
|
1 | onerror {resume} | |||
|
|
2 | quietly WaveActivateNextPane {} 0 | |||
|
|
3 | add wave -noupdate -expand -group APB_REG -expand -group BUFFER_CONFIG /tb/lpp_lfr_apbreg_tb_1/buffer_new | |||
|
|
4 | add wave -noupdate -expand -group APB_REG -expand -group BUFFER_CONFIG /tb/lpp_lfr_apbreg_tb_1/buffer_length | |||
|
|
5 | add wave -noupdate -expand -group APB_REG -expand -group BUFFER_CONFIG /tb/lpp_lfr_apbreg_tb_1/buffer_addr | |||
|
|
6 | add wave -noupdate -expand -group APB_REG /tb/lpp_lfr_apbreg_tb_1/buffer_full | |||
|
|
7 | add wave -noupdate -expand -group APB_REG /tb/lpp_lfr_apbreg_tb_1/buffer_full_err | |||
|
|
8 | add wave -noupdate -expand -group APB_REG /tb/lpp_lfr_apbreg_tb_1/grant_error | |||
|
|
9 | add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_wen | |||
|
|
10 | add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_wdata | |||
|
|
11 | add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_full | |||
|
|
12 | add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_full_almost | |||
|
|
13 | add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_empty | |||
|
|
14 | add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_empty_threshold | |||
|
|
15 | add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group AHB /tb/dma_subsystem_1/ahbi | |||
|
|
16 | add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group AHB /tb/dma_subsystem_1/ahbo | |||
|
|
17 | add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group FIFO_READ /tb/dma_subsystem_1/fifo_burst_valid | |||
|
|
18 | add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group FIFO_READ /tb/dma_subsystem_1/fifo_data | |||
|
|
19 | add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group FIFO_READ /tb/dma_subsystem_1/fifo_ren | |||
|
|
20 | add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group BUFFER_CONFIG&STATUS /tb/dma_subsystem_1/buffer_new | |||
|
|
21 | add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group BUFFER_CONFIG&STATUS /tb/dma_subsystem_1/buffer_addr | |||
|
|
22 | add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group BUFFER_CONFIG&STATUS /tb/dma_subsystem_1/buffer_length | |||
|
|
23 | add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group BUFFER_CONFIG&STATUS /tb/dma_subsystem_1/buffer_full | |||
|
|
24 | add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group BUFFER_CONFIG&STATUS /tb/dma_subsystem_1/buffer_full_err | |||
|
|
25 | add wave -noupdate -expand -group DMA_SUBSYSTEM /tb/dma_subsystem_1/grant_error | |||
|
|
26 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_0/mem_array_0(31) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(30) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(29) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(28) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(27) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(26) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(25) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(24) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(23) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(22) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(21) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(20) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(19) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(18) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(17) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(16) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(15) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(14) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(13) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(12) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(11) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(10) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(9) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(8) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(7) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(6) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(5) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(4) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(3) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(2) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(1) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(0) {-radix hexadecimal}} /tb/async_1mx16_0/mem_array_0 | |||
|
|
27 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_1/mem_array_0(31) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(30) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(29) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(28) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(27) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(26) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(25) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(24) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(23) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(22) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(21) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(20) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(19) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(18) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(17) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(16) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(15) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(14) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(13) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(12) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(11) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(10) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(9) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(8) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(7) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(6) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(5) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(4) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(3) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(2) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(1) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(0) {-radix hexadecimal}} /tb/async_1mx16_1/mem_array_0 | |||
|
|
28 | TreeUpdate [SetDefaultTree] | |||
|
|
29 | WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {1151509 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {27526990683 ps} 0} | |||
|
|
30 | configure wave -namecolwidth 618 | |||
|
|
31 | configure wave -valuecolwidth 472 | |||
|
|
32 | configure wave -justifyvalue left | |||
|
|
33 | configure wave -signalnamewidth 0 | |||
|
|
34 | configure wave -snapdistance 10 | |||
|
|
35 | configure wave -datasetprefix 0 | |||
|
|
36 | configure wave -rowmargin 4 | |||
|
|
37 | configure wave -childrowmargin 2 | |||
|
|
38 | configure wave -gridoffset 0 | |||
|
|
39 | configure wave -gridperiod 1 | |||
|
|
40 | configure wave -griddelta 40 | |||
|
|
41 | configure wave -timeline 0 | |||
|
|
42 | configure wave -timelineunits ps | |||
|
|
43 | update | |||
|
|
44 | WaveRestoreZoom {0 ps} {2011303 ps} | |||
|
|
45 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 | |||
|
|
46 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 | |||
| @@ -0,0 +1,80 | |||||
|
|
1 | onerror {resume} | |||
|
|
2 | quietly WaveActivateNextPane {} 0 | |||
|
|
3 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata | |||
|
|
4 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata | |||
|
|
5 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata | |||
|
|
6 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata | |||
|
|
7 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val | |||
|
|
8 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val | |||
|
|
9 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val | |||
|
|
10 | add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val | |||
|
|
11 | add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/enable | |||
|
|
12 | add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/burst_enable | |||
|
|
13 | add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/start_snapshot | |||
|
|
14 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/state_on | |||
|
|
15 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on_s | |||
|
|
16 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0_pre | |||
|
|
17 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_decount | |||
|
|
18 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_init | |||
|
|
19 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot | |||
|
|
20 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_f0 | |||
|
|
21 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/send_start_snapshot_f0 | |||
|
|
22 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f0_valid | |||
|
|
23 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f2_valid | |||
|
|
24 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0 | |||
|
|
25 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f1 | |||
|
|
26 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f2 | |||
|
|
27 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on | |||
|
|
28 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in | |||
|
|
29 | add wave -noupdate -group temp -subitemconfig {/tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.haddr {-height 15 -radix hexadecimal} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hwdata {-height 15 -radix hexadecimal}} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out | |||
|
|
30 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/send | |||
|
|
31 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst | |||
|
|
32 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/done | |||
|
|
33 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ren | |||
|
|
34 | add wave -noupdate -group temp -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/address | |||
|
|
35 | add wave -noupdate -group temp -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/data | |||
|
|
36 | add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay | |||
|
|
37 | add wave -noupdate -group temp /tb/async_1mx16_0/ce1_b | |||
|
|
38 | add wave -noupdate -group temp /tb/async_1mx16_0/ce2 | |||
|
|
39 | add wave -noupdate -group temp /tb/async_1mx16_0/we_b | |||
|
|
40 | add wave -noupdate -group temp /tb/async_1mx16_0/oe_b | |||
|
|
41 | add wave -noupdate -group temp /tb/async_1mx16_0/bhe_b | |||
|
|
42 | add wave -noupdate -group temp /tb/async_1mx16_0/ble_b | |||
|
|
43 | add wave -noupdate -group temp /tb/async_1mx16_0/a | |||
|
|
44 | add wave -noupdate -group temp /tb/async_1mx16_0/dq | |||
|
|
45 | add wave -noupdate -radix hexadecimal -subitemconfig {/tb/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /tb/async_1mx16_0/mem_array_0 | |||
|
|
46 | add wave -noupdate -radix hexadecimal -subitemconfig {/tb/async_1mx16_0/mem_array_1(31) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(30) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(29) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(28) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(27) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(26) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(25) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(24) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(23) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(22) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(21) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(20) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(19) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(18) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(17) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(16) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(15) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(14) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(13) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(12) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(11) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(10) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(9) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(8) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(7) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(6) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(5) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(4) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(3) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(2) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(1) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(0) {-height 15 -radix hexadecimal}} /tb/async_1mx16_0/mem_array_1 | |||
|
|
47 | add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_2 | |||
|
|
48 | add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_3 | |||
|
|
49 | add wave -noupdate -format Analog-Step -height 70 -max 256.0 -radix unsigned /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect | |||
|
|
50 | add wave -noupdate -radix hexadecimal -subitemconfig {/tb/ahbmi.hirq(31) {-radix hexadecimal} /tb/ahbmi.hirq(30) {-radix hexadecimal} /tb/ahbmi.hirq(29) {-radix hexadecimal} /tb/ahbmi.hirq(28) {-radix hexadecimal} /tb/ahbmi.hirq(27) {-radix hexadecimal} /tb/ahbmi.hirq(26) {-radix hexadecimal} /tb/ahbmi.hirq(25) {-radix hexadecimal} /tb/ahbmi.hirq(24) {-radix hexadecimal} /tb/ahbmi.hirq(23) {-radix hexadecimal} /tb/ahbmi.hirq(22) {-radix hexadecimal} /tb/ahbmi.hirq(21) {-radix hexadecimal} /tb/ahbmi.hirq(20) {-radix hexadecimal} /tb/ahbmi.hirq(19) {-radix hexadecimal} /tb/ahbmi.hirq(18) {-radix hexadecimal} /tb/ahbmi.hirq(17) {-radix hexadecimal} /tb/ahbmi.hirq(16) {-radix hexadecimal} /tb/ahbmi.hirq(15) {-radix hexadecimal} /tb/ahbmi.hirq(14) {-radix hexadecimal} /tb/ahbmi.hirq(13) {-radix hexadecimal} /tb/ahbmi.hirq(12) {-radix hexadecimal} /tb/ahbmi.hirq(11) {-radix hexadecimal} /tb/ahbmi.hirq(10) {-radix hexadecimal} /tb/ahbmi.hirq(9) {-radix hexadecimal} /tb/ahbmi.hirq(8) {-radix hexadecimal} /tb/ahbmi.hirq(7) {-radix hexadecimal} /tb/ahbmi.hirq(6) {-radix hexadecimal} /tb/ahbmi.hirq(5) {-radix hexadecimal} /tb/ahbmi.hirq(4) {-radix hexadecimal} /tb/ahbmi.hirq(3) {-radix hexadecimal} /tb/ahbmi.hirq(2) {-radix hexadecimal} /tb/ahbmi.hirq(1) {-radix hexadecimal} /tb/ahbmi.hirq(0) {-radix hexadecimal}} /tb/ahbmi.hirq | |||
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51 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/status_full | |||
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52 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/status_full_ack | |||
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53 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/status_full_err | |||
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54 | add wave -noupdate -radix unsigned /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/nb_data_by_buffer | |||
|
|
55 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_p(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_p(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_p(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_p(0) {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_p | |||
|
|
56 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_b(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_b(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_b(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_b(0) {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_b | |||
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|
57 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_data_f0 | |||
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|
58 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_data_f1 | |||
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59 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_data_f2 | |||
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|
60 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_data_f3 | |||
|
|
61 | add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/run | |||
|
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62 | TreeUpdate [SetDefaultTree] | |||
|
|
63 | WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {265000 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {27526990683 ps} 0} | |||
|
|
64 | configure wave -namecolwidth 518 | |||
|
|
65 | configure wave -valuecolwidth 227 | |||
|
|
66 | configure wave -justifyvalue left | |||
|
|
67 | configure wave -signalnamewidth 0 | |||
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68 | configure wave -snapdistance 10 | |||
|
|
69 | configure wave -datasetprefix 0 | |||
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|
70 | configure wave -rowmargin 4 | |||
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|
71 | configure wave -childrowmargin 2 | |||
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|
72 | configure wave -gridoffset 0 | |||
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|
73 | configure wave -gridperiod 1 | |||
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74 | configure wave -griddelta 40 | |||
|
|
75 | configure wave -timeline 0 | |||
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|
76 | configure wave -timelineunits ps | |||
|
|
77 | update | |||
|
|
78 | WaveRestoreZoom {0 ps} {966012 ps} | |||
|
|
79 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 | |||
|
|
80 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 | |||
| @@ -0,0 +1,54 | |||||
|
|
1 | #GRLIB=../.. | |||
|
|
2 | VHDLIB=../.. | |||
|
|
3 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |||
|
|
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |||
|
|
5 | TOP=leon3mp | |||
|
|
6 | BOARD=em-LeonLPP-A3PE3kL-v3-core1 | |||
|
|
7 | include $(GRLIB)/boards/$(BOARD)/Makefile.inc | |||
|
|
8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |||
|
|
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |||
|
|
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |||
|
|
11 | EFFORT=high | |||
|
|
12 | XSTOPT= | |||
|
|
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |||
|
|
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |||
|
|
15 | VHDLSYNFILES= | |||
|
|
16 | VHDLSIMFILES= tb.vhd | |||
|
|
17 | SIMTOP=testbench | |||
|
|
18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |||
|
|
19 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc | |||
|
|
20 | PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc | |||
|
|
21 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut | |||
|
|
22 | CLEAN=soft-clean | |||
|
|
23 | ||||
|
|
24 | TECHLIBS = proasic3e | |||
|
|
25 | ||||
|
|
26 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |||
|
|
27 | tmtc openchip hynix ihp gleichmann micron usbhc | |||
|
|
28 | ||||
|
|
29 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |||
|
|
30 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ | |||
|
|
31 | ./amba_lcd_16x2_ctrlr \ | |||
|
|
32 | ./general_purpose/lpp_AMR \ | |||
|
|
33 | ./general_purpose/lpp_balise \ | |||
|
|
34 | ./general_purpose/lpp_delay \ | |||
|
|
35 | ./lpp_bootloader \ | |||
|
|
36 | ./lpp_cna \ | |||
|
|
37 | ./lpp_uart \ | |||
|
|
38 | ./lpp_usb \ | |||
|
|
39 | ./dsp/lpp_fft_rtax \ | |||
|
|
40 | ./lpp_sim/CY7C1061DV33 \ | |||
|
|
41 | ||||
|
|
42 | FILESKIP = i2cmst.vhd \ | |||
|
|
43 | APB_MULTI_DIODE.vhd \ | |||
|
|
44 | APB_MULTI_DIODE.vhd \ | |||
|
|
45 | Top_MatrixSpec.vhd \ | |||
|
|
46 | APB_FFT.vhd \ | |||
|
|
47 | CoreFFT_simu.vhd \ | |||
|
|
48 | lpp_lfr_apbreg_simu.vhd | |||
|
|
49 | ||||
|
|
50 | include $(GRLIB)/bin/Makefile | |||
|
|
51 | include $(GRLIB)/software/leon3/Makefile | |||
|
|
52 | ||||
|
|
53 | ################## project specific targets ########################## | |||
|
|
54 | ||||
| @@ -0,0 +1,9 | |||||
|
|
1 | vcom -quiet -93 -work work tb.vhd | |||
|
|
2 | ||||
|
|
3 | vsim work.testbench | |||
|
|
4 | ||||
|
|
5 | log -r * | |||
|
|
6 | ||||
|
|
7 | do wave.do | |||
|
|
8 | ||||
|
|
9 | run -all | |||
| @@ -0,0 +1,33 | |||||
|
|
1 | #vsim -c -do "run_nowindow.do" -goutput_file_name="output_data.txt" -ginput_file_name="input_data.txt" | |||
|
|
2 | ||||
|
|
3 | quietly set args [ split $argv {\ } ] | |||
|
|
4 | set argc [ llength $args ] | |||
|
|
5 | ||||
|
|
6 | set outputfile "output\_data\.txt" | |||
|
|
7 | set inputfile "input\_data\.txt" | |||
|
|
8 | ||||
|
|
9 | #puts "there are $argc arguments to this script" | |||
|
|
10 | #puts "The name of this script is $argv0" | |||
|
|
11 | ||||
|
|
12 | #foreach arg $::argv {puts $arg} | |||
|
|
13 | ||||
|
|
14 | #puts [ lindex $args 4 ] | |||
|
|
15 | ||||
|
|
16 | for { set i 0 } { $i < $argc } { incr i 1 } { | |||
|
|
17 | puts "$i : [ lindex $args $i ]" | |||
|
|
18 | if { [ string match -goutput_file_name=* [ lindex $args $i ] ] } { | |||
|
|
19 | set outputfile [ lindex [ split [ lindex $args $i ] {=} ] 1 ] | |||
|
|
20 | #set outputfile [ lindex [ split $argv {=} ] 1 ] | |||
|
|
21 | puts "OUTPUT_FILE : $outputfile" | |||
|
|
22 | } | |||
|
|
23 | if { [ string match -ginput_file_name=* [ lindex $args $i ] ] } { | |||
|
|
24 | set inputfile [ lindex [ split [ lindex $args $i ] {=} ] 1 ] | |||
|
|
25 | #set inputfile [ lindex [ split $argv {=} ] 1 ] | |||
|
|
26 | puts "INPUT_FILE : $inputfile" | |||
|
|
27 | } | |||
|
|
28 | } | |||
|
|
29 | ||||
|
|
30 | vsim work.testbench -goutput_file_name=$outputfile -ginput_file_name=$inputfile | |||
|
|
31 | when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation"; exit ;} | |||
|
|
32 | run -all | |||
|
|
33 | exit | |||
| @@ -0,0 +1,10 | |||||
|
|
1 | #!/bin/sh | |||
|
|
2 | ||||
|
|
3 | for FILE_NAME in "$@" | |||
|
|
4 | do | |||
|
|
5 | vsim -c -do "run_nowindow.do" -goutput_file_name=$FILE_NAME".FFT_output" -ginput_file_name=$FILE_NAME | |||
|
|
6 | done | |||
|
|
7 | ||||
|
|
8 | ||||
|
|
9 | ||||
|
|
10 | ||||
| @@ -0,0 +1,186 | |||||
|
|
1 | ||||
|
|
2 | LIBRARY ieee; | |||
|
|
3 | USE ieee.std_logic_1164.ALL; | |||
|
|
4 | USE IEEE.MATH_REAL.ALL; | |||
|
|
5 | USE ieee.numeric_std.ALL; | |||
|
|
6 | ||||
|
|
7 | LIBRARY std; | |||
|
|
8 | use std.textio.all; | |||
|
|
9 | ||||
|
|
10 | LIBRARY lpp; | |||
|
|
11 | USE lpp.cic_pkg.ALL; | |||
|
|
12 | USE lpp.chirp_pkg.ALL; | |||
|
|
13 | USE lpp.lpp_fft.ALL; | |||
|
|
14 | USE lpp.lpp_lfr_pkg.ALL; | |||
|
|
15 | ||||
|
|
16 | ENTITY testbench IS | |||
|
|
17 | GENERIC ( | |||
|
|
18 | input_file_name : STRING := "input_data_2.txt"; | |||
|
|
19 | output_file_name : STRING := "output_data.txt"); | |||
|
|
20 | END; | |||
|
|
21 | ||||
|
|
22 | ARCHITECTURE behav OF testbench IS | |||
|
|
23 | ||||
|
|
24 | SIGNAL clk : STD_LOGIC := '0'; | |||
|
|
25 | SIGNAL rstn : STD_LOGIC; | |||
|
|
26 | ||||
|
|
27 | -- IN | |||
|
|
28 | SIGNAL sample_valid : STD_LOGIC; | |||
|
|
29 | SIGNAL fft_read : STD_LOGIC; | |||
|
|
30 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
31 | SIGNAL sample_load : STD_LOGIC; | |||
|
|
32 | -- OUT | |||
|
|
33 | SIGNAL fft_pong : STD_LOGIC; | |||
|
|
34 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
35 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
36 | SIGNAL fft_data_valid : STD_LOGIC; | |||
|
|
37 | SIGNAL fft_ready : STD_LOGIC; | |||
|
|
38 | SIGNAL fft_component_number : INTEGER; | |||
|
|
39 | ||||
|
|
40 | SIGNAL end_of_sim : STD_LOGIC := '0'; | |||
|
|
41 | ||||
|
|
42 | BEGIN | |||
|
|
43 | ||||
|
|
44 | clk <= NOT clk AFTER 5 ns; | |||
|
|
45 | ||||
|
|
46 | PROCESS | |||
|
|
47 | FILE file_pointer : TEXT; | |||
|
|
48 | VARIABLE line_read : LINE; | |||
|
|
49 | VARIABLE line_content : STRING(1 TO 4); | |||
|
|
50 | VARIABLE line_write : LINE; | |||
|
|
51 | VARIABLE line_content_write : STRING(1 TO 8); | |||
|
|
52 | VARIABLE char_read : CHARACTER; | |||
|
|
53 | VARIABLE data_read : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
54 | VARIABLE signal_part : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
55 | ||||
|
|
56 | BEGIN -- PROCESS | |||
|
|
57 | WAIT UNTIL clk = '1'; | |||
|
|
58 | rstn <= '0'; | |||
|
|
59 | fft_read <= '0'; | |||
|
|
60 | sample_valid <= '0'; | |||
|
|
61 | fft_component_number <= 0; | |||
|
|
62 | WAIT UNTIL clk = '1'; | |||
|
|
63 | rstn <= '1'; | |||
|
|
64 | WAIT UNTIL clk = '1'; | |||
|
|
65 | WAIT UNTIL clk = '1'; | |||
|
|
66 | WAIT UNTIL clk = '1'; | |||
|
|
67 | WAIT UNTIL clk = '1'; | |||
|
|
68 | ||||
|
|
69 | WHILE sample_load = '0' LOOP | |||
|
|
70 | WAIT UNTIL clk = '1'; | |||
|
|
71 | END LOOP; | |||
|
|
72 | WAIT UNTIL clk = '1'; | |||
|
|
73 | ||||
|
|
74 | file_open(file_pointer,input_file_name,READ_MODE); | |||
|
|
75 | WHILE NOT endfile(file_pointer) LOOP | |||
|
|
76 | readline(file_pointer, line_read); | |||
|
|
77 | read(line_read,line_content); | |||
|
|
78 | FOR i IN 1 TO 4 LOOP | |||
|
|
79 | char_read := line_content(5-i); | |||
|
|
80 | CASE char_read IS | |||
|
|
81 | WHEN '0' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0000"; | |||
|
|
82 | WHEN '1' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0001"; | |||
|
|
83 | WHEN '2' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0010"; | |||
|
|
84 | WHEN '3' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0011"; | |||
|
|
85 | WHEN '4' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0100"; | |||
|
|
86 | WHEN '5' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0101"; | |||
|
|
87 | WHEN '6' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0110"; | |||
|
|
88 | WHEN '7' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0111"; | |||
|
|
89 | WHEN '8' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1000"; | |||
|
|
90 | WHEN '9' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1001"; | |||
|
|
91 | WHEN 'a' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1010"; | |||
|
|
92 | WHEN 'b' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1011"; | |||
|
|
93 | WHEN 'c' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1100"; | |||
|
|
94 | WHEN 'd' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1101"; | |||
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95 | WHEN 'e' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1110"; | |||
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96 | WHEN 'f' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1111"; | |||
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97 | WHEN OTHERS => NULL; | |||
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98 | END CASE; | |||
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99 | END LOOP; | |||
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100 | sample_data <= data_read; | |||
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101 | sample_valid <= '1'; | |||
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102 | WAIT UNTIL clk = '1'; | |||
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103 | END LOOP; | |||
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104 | file_close(file_pointer); | |||
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105 | sample_valid <= '0'; | |||
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106 | WAIT UNTIL clk = '1'; | |||
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107 | WAIT UNTIL clk = '1'; | |||
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108 | WHILE fft_ready = '0' LOOP | |||
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109 | WAIT UNTIL clk = '1'; | |||
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110 | END LOOP; | |||
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111 | WAIT UNTIL clk = '1'; | |||
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112 | ||||
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113 | ||||
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114 | file_open(file_pointer,output_file_name,WRITE_MODE); | |||
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115 | WHILE fft_ready = '1' LOOP | |||
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116 | IF fft_data_valid = '1' THEN | |||
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117 | FOR j IN 0 TO 1 LOOP | |||
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118 | FOR i IN 1 TO 4 LOOP | |||
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119 | IF j = 0 THEN | |||
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120 | signal_part := fft_data_im(i*4-1 DOWNTO (i-1)*4); | |||
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121 | ELSE | |||
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122 | signal_part := fft_data_re(i*4-1 DOWNTO (i-1)*4); | |||
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123 | END IF; | |||
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124 | CASE signal_part IS | |||
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125 | WHEN "0000" => line_content(i) := '0'; | |||
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126 | WHEN "0001" => line_content(i) := '1'; | |||
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127 | WHEN "0010" => line_content(i) := '2'; | |||
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128 | WHEN "0011" => line_content(i) := '3'; | |||
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129 | WHEN "0100" => line_content(i) := '4'; | |||
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130 | WHEN "0101" => line_content(i) := '5'; | |||
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131 | WHEN "0110" => line_content(i) := '6'; | |||
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132 | WHEN "0111" => line_content(i) := '7'; | |||
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133 | WHEN "1000" => line_content(i) := '8'; | |||
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134 | WHEN "1001" => line_content(i) := '9'; | |||
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135 | WHEN "1010" => line_content(i) := 'a'; | |||
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136 | WHEN "1011" => line_content(i) := 'b'; | |||
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137 | WHEN "1100" => line_content(i) := 'c'; | |||
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138 | WHEN "1101" => line_content(i) := 'd'; | |||
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139 | WHEN "1110" => line_content(i) := 'e'; | |||
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140 | WHEN "1111" => line_content(i) := 'f'; | |||
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141 | WHEN OTHERS => NULL; | |||
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142 | END CASE; | |||
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143 | END LOOP; -- i | |||
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144 | line_content_write(j*4+1) := line_content(4); | |||
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145 | line_content_write(j*4+2) := line_content(3); | |||
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146 | line_content_write(j*4+3) := line_content(2); | |||
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147 | line_content_write(j*4+4) := line_content(1); | |||
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148 | END LOOP; -- j | |||
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149 | write(line_write,line_content_write); | |||
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150 | writeline(file_pointer,line_write); | |||
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151 | fft_component_number <= fft_component_number + 1; | |||
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152 | END IF; | |||
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153 | fft_read <= '1'; | |||
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154 | WAIT UNTIL clk = '1'; | |||
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155 | END LOOP; | |||
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156 | file_close(file_pointer); | |||
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157 | ||||
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158 | fft_read <= '0'; | |||
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159 | WAIT UNTIL clk = '1'; | |||
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160 | ||||
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161 | ||||
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162 | WAIT FOR 1 us; | |||
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163 | end_of_sim <= '1'; | |||
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164 | WAIT FOR 100 ns; | |||
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165 | REPORT "*** END simulation ***" SEVERITY failure; | |||
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166 | WAIT; | |||
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167 | END PROCESS; | |||
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168 | ----------------------------------------------------------------------------- | |||
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169 | ||||
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170 | lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT | |||
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171 | PORT MAP ( | |||
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172 | clk => clk, | |||
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173 | rstn => rstn, | |||
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174 | -- IN | |||
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175 | sample_valid => sample_valid, -- in | |||
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176 | fft_read => fft_read, -- in | |||
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177 | sample_data => sample_data, -- in | |||
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178 | sample_load => sample_load, -- out | |||
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179 | -- OUT | |||
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180 | fft_pong => fft_pong, -- out | |||
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181 | fft_data_im => fft_data_im, -- out | |||
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182 | fft_data_re => fft_data_re, -- out | |||
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183 | fft_data_valid => fft_data_valid, -- out | |||
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184 | fft_ready => fft_ready); -- out | |||
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185 | ||||
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186 | END; | |||
| @@ -0,0 +1,46 | |||||
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1 | onerror {resume} | |||
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2 | quietly WaveActivateNextPane {} 0 | |||
|
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3 | add wave -noupdate /testbench/message_simu | |||
|
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4 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp | |||
|
|
5 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp | |||
|
|
6 | add wave -noupdate /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/ongoing | |||
|
|
7 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_full | |||
|
|
8 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen | |||
|
|
9 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_write_error | |||
|
|
10 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_data | |||
|
|
11 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/fsm_state | |||
|
|
12 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data2 | |||
|
|
13 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data | |||
|
|
14 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full_s | |||
|
|
15 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen_s | |||
|
|
16 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_empty | |||
|
|
17 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full | |||
|
|
18 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_data | |||
|
|
19 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_wen | |||
|
|
20 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/rdata | |||
|
|
21 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/almost_full | |||
|
|
22 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/full | |||
|
|
23 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/empty | |||
|
|
24 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/ren | |||
|
|
25 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/wdata | |||
|
|
26 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/wen | |||
|
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27 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/run | |||
|
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28 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/ReUse | |||
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29 | TreeUpdate [SetDefaultTree] | |||
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30 | WaveRestoreCursors {{Cursor 1} {48603668788 ps} 0} | |||
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31 | quietly wave cursor active 1 | |||
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32 | configure wave -namecolwidth 539 | |||
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33 | configure wave -valuecolwidth 100 | |||
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34 | configure wave -justifyvalue left | |||
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35 | configure wave -signalnamewidth 0 | |||
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36 | configure wave -snapdistance 10 | |||
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37 | configure wave -datasetprefix 0 | |||
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38 | configure wave -rowmargin 4 | |||
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39 | configure wave -childrowmargin 2 | |||
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40 | configure wave -gridoffset 0 | |||
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41 | configure wave -gridperiod 1 | |||
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42 | configure wave -griddelta 40 | |||
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43 | configure wave -timeline 0 | |||
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44 | configure wave -timelineunits ns | |||
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45 | update | |||
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46 | WaveRestoreZoom {0 ps} {84406089600 ps} | |||
| @@ -0,0 +1,53 | |||||
|
|
1 | #GRLIB=../.. | |||
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2 | VHDLIB=../.. | |||
|
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3 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |||
|
|
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |||
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5 | TOP=leon3mp | |||
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6 | BOARD=em-LeonLPP-A3PE3kL-v3-core1 | |||
|
|
7 | include $(GRLIB)/boards/$(BOARD)/Makefile.inc | |||
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8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |||
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|
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |||
|
|
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |||
|
|
11 | EFFORT=high | |||
|
|
12 | XSTOPT= | |||
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|
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |||
|
|
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |||
|
|
15 | VHDLSYNFILES= | |||
|
|
16 | VHDLSIMFILES= tb.vhd | |||
|
|
17 | SIMTOP=testbench | |||
|
|
18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |||
|
|
19 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc | |||
|
|
20 | PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc | |||
|
|
21 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut | |||
|
|
22 | CLEAN=soft-clean | |||
|
|
23 | ||||
|
|
24 | TECHLIBS = proasic3e | |||
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25 | ||||
|
|
26 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |||
|
|
27 | tmtc openchip hynix ihp gleichmann micron usbhc | |||
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28 | ||||
|
|
29 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |||
|
|
30 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ | |||
|
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31 | ./amba_lcd_16x2_ctrlr \ | |||
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32 | ./general_purpose/lpp_AMR \ | |||
|
|
33 | ./general_purpose/lpp_balise \ | |||
|
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34 | ./general_purpose/lpp_delay \ | |||
|
|
35 | ./lpp_bootloader \ | |||
|
|
36 | ./lpp_cna \ | |||
|
|
37 | ./lpp_uart \ | |||
|
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38 | ./lpp_usb \ | |||
|
|
39 | ./dsp/lpp_fft_rtax \ | |||
|
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40 | ||||
|
|
41 | FILESKIP = i2cmst.vhd \ | |||
|
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42 | APB_MULTI_DIODE.vhd \ | |||
|
|
43 | APB_MULTI_DIODE.vhd \ | |||
|
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44 | Top_MatrixSpec.vhd \ | |||
|
|
45 | APB_FFT.vhd \ | |||
|
|
46 | lpp_lfr_apbreg.vhd \ | |||
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47 | CoreFFT.vhd | |||
|
|
48 | ||||
|
|
49 | include $(GRLIB)/bin/Makefile | |||
|
|
50 | include $(GRLIB)/software/leon3/Makefile | |||
|
|
51 | ||||
|
|
52 | ################## project specific targets ########################## | |||
|
|
53 | ||||
| @@ -0,0 +1,9 | |||||
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|
1 | vcom -quiet -93 -work work tb.vhd | |||
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|
2 | ||||
|
|
3 | vsim work.testbench | |||
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|
4 | ||||
|
|
5 | log -r * | |||
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|
6 | ||||
|
|
7 | do wave.do | |||
|
|
8 | ||||
|
|
9 | run -all | |||
| @@ -0,0 +1,9 | |||||
|
|
1 | vcom -quiet -93 -work work tb_with_head_reg_latency_0.vhd | |||
|
|
2 | ||||
|
|
3 | vsim work.testbench | |||
|
|
4 | ||||
|
|
5 | log -r * | |||
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|
6 | ||||
|
|
7 | do wave_head_reg_latency_0.do | |||
|
|
8 | ||||
|
|
9 | run -all | |||
| @@ -0,0 +1,9 | |||||
|
|
1 | vcom -quiet -93 -work work tb_with_head_reg_latency_1.vhd | |||
|
|
2 | ||||
|
|
3 | vsim work.testbench | |||
|
|
4 | ||||
|
|
5 | log -r * | |||
|
|
6 | ||||
|
|
7 | do wave_head_reg_latency_1.do | |||
|
|
8 | ||||
|
|
9 | run -all | |||
| This diff has been collapsed as it changes many lines, (608 lines changed) Show them Hide them | |||||
| @@ -0,0 +1,608 | |||||
|
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1 | ||||
|
|
2 | LIBRARY ieee; | |||
|
|
3 | USE ieee.std_logic_1164.ALL; | |||
|
|
4 | USE IEEE.MATH_REAL.ALL; | |||
|
|
5 | USE ieee.numeric_std.ALL; | |||
|
|
6 | ||||
|
|
7 | LIBRARY lpp; | |||
|
|
8 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
9 | ||||
|
|
10 | LIBRARY lpp; | |||
|
|
11 | USE lpp.lpp_memory.ALL; | |||
|
|
12 | USE lpp.iir_filter.ALL; | |||
|
|
13 | ||||
|
|
14 | ENTITY testbench IS | |||
|
|
15 | END; | |||
|
|
16 | ||||
|
|
17 | ARCHITECTURE behav OF testbench IS | |||
|
|
18 | ----------------------------------------------------------------------------- | |||
|
|
19 | -- Common signal | |||
|
|
20 | SIGNAL clk : STD_LOGIC := '0'; | |||
|
|
21 | SIGNAL rstn : STD_LOGIC := '0'; | |||
|
|
22 | SIGNAL run : STD_LOGIC := '0'; | |||
|
|
23 | ||||
|
|
24 | ----------------------------------------------------------------------------- | |||
|
|
25 | TYPE DATA_FIFO_VECTOR IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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|
26 | SIGNAL data_out_obs : DATA_FIFO_VECTOR; | |||
|
|
27 | SIGNAL data_out_obs_read : DATA_FIFO_VECTOR; | |||
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|
28 | SIGNAL data_out_obs_1 : DATA_FIFO_VECTOR; | |||
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|
29 | SIGNAL data_out_obs_2 : DATA_FIFO_VECTOR; | |||
|
|
30 | ||||
|
|
31 | SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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|
32 | SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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|
33 | SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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|
34 | SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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|
35 | ||||
|
|
36 | SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b | |||
|
|
37 | SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
38 | SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '1'); | |||
|
|
39 | SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
40 | ||||
|
|
41 | SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
42 | SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
43 | SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
44 | SIGNAL data_out : DATA_FIFO_VECTOR; | |||
|
|
45 | ||||
|
|
46 | SIGNAL empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
47 | SIGNAL empty_reg_2 : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
48 | SIGNAL data_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
49 | ||||
|
|
50 | SIGNAL full_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
51 | ----------------------------------------------------------------------------- | |||
|
|
52 | TYPE DATA_CHANNEL IS ARRAY (0 TO 128/4-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
53 | TYPE DATA_ARRAY IS ARRAY (0 TO 3) OF DATA_CHANNEL; | |||
|
|
54 | SIGNAL data_in : DATA_ARRAY; | |||
|
|
55 | ||||
|
|
56 | ----------------------------------------------------------------------------- | |||
|
|
57 | CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1+2+2; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE | |||
|
|
58 | CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0; | |||
|
|
59 | SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
60 | -- | |||
|
|
61 | SIGNAL rand_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
62 | SIGNAL rand_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
63 | ||||
|
|
64 | TYPE POINTER IS ARRAY (0 TO 3) OF INTEGER; | |||
|
|
65 | SIGNAL pointer_read : POINTER; | |||
|
|
66 | SIGNAL pointer_write : POINTER := (0, 0, 0, 0); | |||
|
|
67 | ||||
|
|
68 | --SIGNAL data_f0_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
69 | --SIGNAL data_f0_data_out_obs : STD_LOGIC; | |||
|
|
70 | --SIGNAL data_f1_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
71 | --SIGNAL data_f1_data_out_obs : STD_LOGIC; | |||
|
|
72 | --SIGNAL data_f2_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
73 | --SIGNAL data_f2_data_out_obs : STD_LOGIC; | |||
|
|
74 | --SIGNAL data_f3_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
75 | --SIGNAL data_f3_data_out_obs : STD_LOGIC; | |||
|
|
76 | SIGNAL error_now : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
77 | SIGNAL error_new : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
78 | ||||
|
|
79 | SIGNAL WARNING_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
80 | ||||
|
|
81 | ||||
|
|
82 | SIGNAL read_stop : STD_LOGIC; | |||
|
|
83 | SIGNAL write_stop : STD_LOGIC; | |||
|
|
84 | ||||
|
|
85 | -- SIGNAL empty_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
86 | ||||
|
|
87 | ----------------------------------------------------------------------------- | |||
|
|
88 | BEGIN | |||
|
|
89 | ||||
|
|
90 | all_I : FOR I IN 0 TO 3 GENERATE | |||
|
|
91 | all_J : FOR J IN 0 TO 128/4-1 GENERATE | |||
|
|
92 | data_in(I)(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+I*(2**28)+1, 32)); | |||
|
|
93 | END GENERATE all_J; | |||
|
|
94 | END GENERATE all_I; | |||
|
|
95 | ||||
|
|
96 | ||||
|
|
97 | ----------------------------------------------------------------------------- | |||
|
|
98 | --lpp_waveform_fifo_1 : lpp_waveform_fifo | |||
|
|
99 | -- GENERIC MAP (tech => 0) | |||
|
|
100 | -- PORT MAP ( | |||
|
|
101 | -- clk => clk, | |||
|
|
102 | -- rstn => rstn, | |||
|
|
103 | -- run => run, | |||
|
|
104 | ||||
|
|
105 | -- empty => s_empty, | |||
|
|
106 | -- empty_almost => s_empty_almost, | |||
|
|
107 | -- data_ren => s_data_ren, | |||
|
|
108 | -- rdata => s_rdata, | |||
|
|
109 | ||||
|
|
110 | -- full_almost => full_almost, | |||
|
|
111 | -- full => full, | |||
|
|
112 | -- data_wen => data_wen, | |||
|
|
113 | -- wdata => wdata); | |||
|
|
114 | ||||
|
|
115 | lpp_fifo_4_shared_1 : lpp_fifo_4_shared | |||
|
|
116 | GENERIC MAP ( | |||
|
|
117 | tech => 0, | |||
|
|
118 | Mem_use => use_RAM, | |||
|
|
119 | EMPTY_ALMOST_LIMIT => 16, | |||
|
|
120 | FULL_ALMOST_LIMIT => 5, | |||
|
|
121 | DataSz => 32, | |||
|
|
122 | AddrSz => 7) | |||
|
|
123 | PORT MAP ( | |||
|
|
124 | clk => clk, | |||
|
|
125 | rstn => rstn, | |||
|
|
126 | run => run, | |||
|
|
127 | empty_almost => s_empty_almost, | |||
|
|
128 | empty => s_empty, | |||
|
|
129 | r_en => s_data_ren, | |||
|
|
130 | r_data => s_rdata, | |||
|
|
131 | ||||
|
|
132 | full_almost => full_almost, | |||
|
|
133 | full => full, | |||
|
|
134 | w_en => data_wen, | |||
|
|
135 | w_data => wdata); | |||
|
|
136 | ||||
|
|
137 | ||||
|
|
138 | empty_almost <= s_empty_almost; | |||
|
|
139 | empty <= s_empty; | |||
|
|
140 | ||||
|
|
141 | s_data_ren <= data_ren; | |||
|
|
142 | data_out(0) <= s_rdata; | |||
|
|
143 | data_out(1) <= s_rdata; | |||
|
|
144 | data_out(2) <= s_rdata; | |||
|
|
145 | data_out(3) <= s_rdata; | |||
|
|
146 | ||||
|
|
147 | ||||
|
|
148 | ||||
|
|
149 | --lpp_fifo_4_shared_headreg_1: lpp_fifo_4_shared_headreg | |||
|
|
150 | -- PORT MAP ( | |||
|
|
151 | -- clk => clk, | |||
|
|
152 | -- rstn => rstn, | |||
|
|
153 | -- run => run, | |||
|
|
154 | ||||
|
|
155 | -- o_empty_almost => empty_almost, | |||
|
|
156 | -- o_empty => empty, | |||
|
|
157 | ||||
|
|
158 | -- o_data_ren => data_ren, | |||
|
|
159 | -- o_rdata_0 => data_out(0), | |||
|
|
160 | -- o_rdata_1 => data_out(1), | |||
|
|
161 | -- o_rdata_2 => data_out(2), | |||
|
|
162 | -- o_rdata_3 => data_out(3), | |||
|
|
163 | ||||
|
|
164 | -- i_empty_almost => s_empty_almost, | |||
|
|
165 | -- i_empty => s_empty, | |||
|
|
166 | -- i_data_ren => s_data_ren, | |||
|
|
167 | -- i_rdata => s_rdata); | |||
|
|
168 | ||||
|
|
169 | --lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg | |||
|
|
170 | -- GENERIC MAP (tech => 0) | |||
|
|
171 | -- PORT MAP ( | |||
|
|
172 | -- clk => clk, | |||
|
|
173 | -- rstn => rstn, | |||
|
|
174 | -- run => run, | |||
|
|
175 | -- o_empty_almost => empty_almost, | |||
|
|
176 | -- o_empty => empty, | |||
|
|
177 | ||||
|
|
178 | -- o_data_ren => data_ren, | |||
|
|
179 | -- o_rdata_0 => data_out(0), | |||
|
|
180 | -- o_rdata_1 => data_out(1), | |||
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181 | -- o_rdata_2 => data_out(2), | |||
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182 | -- o_rdata_3 => data_out(3), | |||
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183 | ||||
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184 | -- i_empty_almost => s_empty_almost, | |||
|
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185 | -- i_empty => s_empty, | |||
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186 | -- i_data_ren => s_data_ren, | |||
|
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187 | -- i_rdata => s_rdata); | |||
|
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188 | ----------------------------------------------------------------------------- | |||
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189 | ||||
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190 | ||||
|
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191 | ||||
|
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192 | ----------------------------------------------------------------------------- | |||
|
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193 | all_data_channel : FOR I IN 0 TO 3 GENERATE | |||
|
|
194 | ----------------------------------------------------------------------------- | |||
|
|
195 | -- READ | |||
|
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196 | ----------------------------------------------------------------------------- | |||
|
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197 | ||||
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198 | PROCESS (clk, rstn) | |||
|
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199 | BEGIN -- PROCESS | |||
|
|
200 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
201 | empty_reg(I) <= '1'; | |||
|
|
202 | empty_reg_2(I) <= '1'; | |||
|
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203 | data_ren_reg(I) <= '1'; | |||
|
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204 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
205 | empty_reg(I) <= empty(I); | |||
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|
206 | empty_reg_2(I) <= empty_reg(I); | |||
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207 | ||||
|
|
208 | data_ren_reg(I) <= data_ren(I); | |||
|
|
209 | END IF; | |||
|
|
210 | END PROCESS; | |||
|
|
211 | ||||
|
|
212 | PROCESS (clk, rstn) | |||
|
|
213 | BEGIN -- PROCESS | |||
|
|
214 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
215 | data_out_obs(I) <= (OTHERS => '0'); | |||
|
|
216 | ||||
|
|
217 | pointer_read(I) <= 0; | |||
|
|
218 | error_now(I) <= '0'; | |||
|
|
219 | error_new(I) <= '0'; | |||
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220 | ||||
|
|
221 | WARNING_DATA(I) <= '0'; | |||
|
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222 | ||||
|
|
223 | data_out_obs(I) <= data_in(I)(0); | |||
|
|
224 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
225 | IF data_out(I) = data_out_obs(I) THEN | |||
|
|
226 | WARNING_DATA(I) <= '0'; | |||
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227 | ELSE | |||
|
|
228 | WARNING_DATA(I) <= '1'; | |||
|
|
229 | END IF; | |||
|
|
230 | ||||
|
|
231 | error_now(I) <= '0'; | |||
|
|
232 | IF empty_reg_2(I) = '0' THEN | |||
|
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233 | IF data_ren_reg(I) = '0' THEN | |||
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234 | ||||
|
|
235 | error_new(I) <= '0'; | |||
|
|
236 | --data_out_obs(I) <= data_out(I); | |||
|
|
237 | data_out_obs(I) <= data_in(I)(pointer_read(I)); | |||
|
|
238 | ||||
|
|
239 | ||||
|
|
240 | IF pointer_read(I) < 128/4-1 THEN | |||
|
|
241 | pointer_read(I) <= pointer_read(I) + 1; | |||
|
|
242 | ELSE | |||
|
|
243 | pointer_read(I) <= 0; | |||
|
|
244 | END IF; | |||
|
|
245 | ||||
|
|
246 | IF data_out(I) /= data_in(I)(pointer_read(I)) THEN | |||
|
|
247 | data_out_obs_1(I) <= data_out(I); | |||
|
|
248 | data_out_obs_2(I) <= data_in(I)(pointer_read(I)); | |||
|
|
249 | error_now(I) <= '1'; | |||
|
|
250 | error_new(I) <= '1'; | |||
|
|
251 | END IF; | |||
|
|
252 | END IF; | |||
|
|
253 | ||||
|
|
254 | END IF; | |||
|
|
255 | END IF; | |||
|
|
256 | END PROCESS; | |||
|
|
257 | ||||
|
|
258 | ||||
|
|
259 | ||||
|
|
260 | ----------------------------------------------------------------------------- | |||
|
|
261 | -- WRITE | |||
|
|
262 | ----------------------------------------------------------------------------- | |||
|
|
263 | PROCESS (clk, rstn) | |||
|
|
264 | BEGIN -- PROCESS | |||
|
|
265 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
266 | full_reg(I) <= '0'; | |||
|
|
267 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
268 | full_reg(I) <= full(I); | |||
|
|
269 | END IF; | |||
|
|
270 | END PROCESS; | |||
|
|
271 | ||||
|
|
272 | PROCESS (clk, rstn) | |||
|
|
273 | BEGIN -- PROCESS proc_verif | |||
|
|
274 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
275 | pointer_write(I) <= 0; | |||
|
|
276 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
277 | IF data_wen(I) = '0' THEN | |||
|
|
278 | IF full_reg(I) = '0' THEN | |||
|
|
279 | IF pointer_write(I) < 128/4-1 THEN | |||
|
|
280 | pointer_write(I) <= pointer_write(I)+1; | |||
|
|
281 | ELSE | |||
|
|
282 | pointer_write(I) <= 0; | |||
|
|
283 | END IF; | |||
|
|
284 | END IF; | |||
|
|
285 | END IF; | |||
|
|
286 | END IF; | |||
|
|
287 | END PROCESS; | |||
|
|
288 | END GENERATE all_data_channel; | |||
|
|
289 | ||||
|
|
290 | wdata <= data_in(0)(pointer_write(0)) WHEN data_wen = "1110" ELSE | |||
|
|
291 | data_in(1)(pointer_write(1)) WHEN data_wen = "1101" ELSE | |||
|
|
292 | data_in(2)(pointer_write(2)) WHEN data_wen = "1011" ELSE | |||
|
|
293 | data_in(3)(pointer_write(3)) WHEN data_wen = "0111" ELSE | |||
|
|
294 | (OTHERS => 'X'); | |||
|
|
295 | ||||
|
|
296 | ----------------------------------------------------------------------------- | |||
|
|
297 | ||||
|
|
298 | ||||
|
|
299 | ||||
|
|
300 | ----------------------------------------------------------------------------- | |||
|
|
301 | clk <= NOT clk AFTER 5 ns; -- 100 MHz | |||
|
|
302 | ----------------------------------------------------------------------------- | |||
|
|
303 | WaveGen_Proc : PROCESS | |||
|
|
304 | BEGIN | |||
|
|
305 | -- insert signal assignments here | |||
|
|
306 | WAIT UNTIL clk = '1'; | |||
|
|
307 | rstn <= '0'; | |||
|
|
308 | run <= '0'; | |||
|
|
309 | read_stop <= '1'; | |||
|
|
310 | write_stop <= '0'; | |||
|
|
311 | WAIT UNTIL clk = '1'; | |||
|
|
312 | WAIT UNTIL clk = '1'; | |||
|
|
313 | WAIT UNTIL clk = '1'; | |||
|
|
314 | rstn <= '1'; | |||
|
|
315 | WAIT UNTIL clk = '1'; | |||
|
|
316 | WAIT UNTIL clk = '1'; | |||
|
|
317 | WAIT UNTIL clk = '1'; | |||
|
|
318 | WAIT UNTIL clk = '1'; | |||
|
|
319 | WAIT UNTIL clk = '1'; | |||
|
|
320 | run <= '1'; | |||
|
|
321 | WAIT UNTIL clk = '1'; | |||
|
|
322 | WAIT FOR 10 us; | |||
|
|
323 | read_stop <= '0'; | |||
|
|
324 | WAIT UNTIL clk = '1'; | |||
|
|
325 | WAIT UNTIL clk = '1'; | |||
|
|
326 | WAIT UNTIL clk = '1'; | |||
|
|
327 | WAIT FOR 10 us; | |||
|
|
328 | read_stop <= '1'; | |||
|
|
329 | WAIT FOR 10 us; | |||
|
|
330 | read_stop <= '0'; | |||
|
|
331 | WAIT FOR 1 us; | |||
|
|
332 | write_stop <= '1'; | |||
|
|
333 | WAIT FOR 10 us; | |||
|
|
334 | write_stop <= '0'; | |||
|
|
335 | WAIT FOR 80 us; | |||
|
|
336 | REPORT "*** END simulation ***" SEVERITY failure; | |||
|
|
337 | WAIT; | |||
|
|
338 | END PROCESS WaveGen_Proc; | |||
|
|
339 | ----------------------------------------------------------------------------- | |||
|
|
340 | ||||
|
|
341 | ||||
|
|
342 | ||||
|
|
343 | ||||
|
|
344 | ||||
|
|
345 | ----------------------------------------------------------------------------- | |||
|
|
346 | -- RANDOM GENERATOR | |||
|
|
347 | ----------------------------------------------------------------------------- | |||
|
|
348 | PROCESS (clk, rstn) | |||
|
|
349 | VARIABLE seed1, seed2 : POSITIVE; | |||
|
|
350 | VARIABLE rand1 : REAL; | |||
|
|
351 | VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
352 | BEGIN -- PROCESS | |||
|
|
353 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
354 | random_vector <= (OTHERS => '0'); | |||
|
|
355 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
356 | UNIFORM(seed1, seed2, rand1); | |||
|
|
357 | RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR( | |||
|
|
358 | to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)), | |||
|
|
359 | RANDOM_VECTOR_VAR'LENGTH) | |||
|
|
360 | ); | |||
|
|
361 | ||||
|
|
362 | random_vector <= RANDOM_VECTOR_VAR; | |||
|
|
363 | END IF; | |||
|
|
364 | END PROCESS; | |||
|
|
365 | ----------------------------------------------------------------------------- | |||
|
|
366 | rand_ren <= "1111" WHEN random_vector(0) = '0' ELSE | |||
|
|
367 | "1110" WHEN random_vector(2 DOWNTO 1) = "00" ELSE | |||
|
|
368 | "1101" WHEN random_vector(2 DOWNTO 1) = "01" ELSE | |||
|
|
369 | "1011" WHEN random_vector(2 DOWNTO 1) = "10" ELSE | |||
|
|
370 | "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE | |||
|
|
371 | ||||
|
|
372 | rand_wen <= "1111" WHEN random_vector(3) = '0' ELSE | |||
|
|
373 | "1110" WHEN random_vector(5 DOWNTO 4) = "00" ELSE | |||
|
|
374 | "1101" WHEN random_vector(5 DOWNTO 4) = "01" ELSE | |||
|
|
375 | "1011" WHEN random_vector(5 DOWNTO 4) = "10" ELSE | |||
|
|
376 | "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE | |||
|
|
377 | ----------------------------------------------------------------------------- | |||
|
|
378 | PROCESS (clk, rstn) | |||
|
|
379 | BEGIN -- PROCESS | |||
|
|
380 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
381 | data_wen <= (OTHERS => '1'); | |||
|
|
382 | data_ren <= (OTHERS => '1'); | |||
|
|
383 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
384 | ||||
|
|
385 | IF write_stop = '0' THEN | |||
|
|
386 | data_wen <= rand_ren; | |||
|
|
387 | ELSE | |||
|
|
388 | data_ren <= (OTHERS => '1'); | |||
|
|
389 | END IF; | |||
|
|
390 | ||||
|
|
391 | IF read_stop = '0' THEN | |||
|
|
392 | all_ren_bits : FOR I IN 0 TO 3 LOOP | |||
|
|
393 | IF empty(I) = '1' THEN | |||
|
|
394 | data_ren(I) <= '1'; | |||
|
|
395 | ELSE | |||
|
|
396 | data_ren(I) <= rand_ren(I); | |||
|
|
397 | END IF; | |||
|
|
398 | END LOOP all_ren_bits; | |||
|
|
399 | ELSE | |||
|
|
400 | data_ren <= (OTHERS => '1'); | |||
|
|
401 | END IF; | |||
|
|
402 | ||||
|
|
403 | END IF; | |||
|
|
404 | END PROCESS; | |||
|
|
405 | ----------------------------------------------------------------------------- | |||
|
|
406 | ||||
|
|
407 | ||||
|
|
408 | --PROCESS (clk, rstn) | |||
|
|
409 | --BEGIN -- PROCESS | |||
|
|
410 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
411 | -- empty <= (OTHERS => '1'); | |||
|
|
412 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
413 | -- empty <= empty_s; | |||
|
|
414 | -- END IF; | |||
|
|
415 | --END PROCESS; | |||
|
|
416 | ||||
|
|
417 | ||||
|
|
418 | --PROCESS (clk, rstn) | |||
|
|
419 | --BEGIN -- PROCESS | |||
|
|
420 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
421 | -- data_f0_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
422 | -- data_f1_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
423 | -- data_f2_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
424 | -- data_f3_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
425 | -- data_f0_data_out_obs <= '0'; | |||
|
|
426 | -- data_f1_data_out_obs <= '0'; | |||
|
|
427 | -- data_f2_data_out_obs <= '0'; | |||
|
|
428 | -- data_f3_data_out_obs <= '0'; | |||
|
|
429 | ||||
|
|
430 | -- pointer_read <= (0, 0, 0, 0); | |||
|
|
431 | -- error_now <= (OTHERS => '0'); | |||
|
|
432 | -- error_new <= (OTHERS => '0'); | |||
|
|
433 | ||||
|
|
434 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
435 | -- error_now <= (OTHERS => '0'); | |||
|
|
436 | -- CASE data_ren IS | |||
|
|
437 | -- WHEN "1110" => | |||
|
|
438 | -- IF empty(0) = '0' THEN | |||
|
|
439 | -- error_new(0) <= '0'; | |||
|
|
440 | -- data_f0_data_out_obs_data <= data_f0_data_out(5 DOWNTO 0); | |||
|
|
441 | -- IF pointer_read(0) < 31 THEN | |||
|
|
442 | -- pointer_read(0) <= pointer_read(0)+1; | |||
|
|
443 | -- ELSE | |||
|
|
444 | -- pointer_read(0) <= 0; | |||
|
|
445 | -- END IF; | |||
|
|
446 | -- IF data_f0_data_out /= data_in(0)(pointer_read(0)) THEN | |||
|
|
447 | -- error_now(0) <= '1'; | |||
|
|
448 | -- error_new(0) <= '1'; | |||
|
|
449 | -- data_f0_data_out_obs <= '1'; | |||
|
|
450 | -- END IF; | |||
|
|
451 | -- --IF data_f0_data_out(29 DOWNTO 28) /= "00" THEN | |||
|
|
452 | -- -- data_f0_data_out_obs <= '1'; | |||
|
|
453 | -- --END IF; | |||
|
|
454 | -- END IF; | |||
|
|
455 | ||||
|
|
456 | -- WHEN "1101" => | |||
|
|
457 | -- IF empty(1) = '0' THEN | |||
|
|
458 | -- error_new(1) <= '0'; | |||
|
|
459 | -- data_f1_data_out_obs_data <= data_f1_data_out(5 DOWNTO 0); | |||
|
|
460 | -- IF pointer_read(1) < 31 THEN | |||
|
|
461 | -- pointer_read(1) <= pointer_read(1)+1; | |||
|
|
462 | -- ELSE | |||
|
|
463 | -- pointer_read(1) <= 0; | |||
|
|
464 | -- END IF; | |||
|
|
465 | -- IF data_f1_data_out /= data_in(1)(pointer_read(1)) THEN | |||
|
|
466 | -- error_new(1) <= '1'; | |||
|
|
467 | -- error_now(1) <= '1'; | |||
|
|
468 | -- data_f1_data_out_obs <= '1'; | |||
|
|
469 | -- END IF; | |||
|
|
470 | -- END IF; | |||
|
|
471 | -- WHEN "1011" => | |||
|
|
472 | -- IF empty(2) = '0' THEN | |||
|
|
473 | -- error_new(2) <= '0'; | |||
|
|
474 | -- data_f2_data_out_obs_data <= data_f2_data_out(5 DOWNTO 0); | |||
|
|
475 | -- IF pointer_read(2) < 31 THEN | |||
|
|
476 | -- pointer_read(2) <= pointer_read(2)+1; | |||
|
|
477 | -- ELSE | |||
|
|
478 | -- pointer_read(2) <= 0; | |||
|
|
479 | -- END IF; | |||
|
|
480 | -- IF data_f2_data_out /= data_in(2)(pointer_read(2)) THEN | |||
|
|
481 | -- error_new(2) <= '1'; | |||
|
|
482 | -- error_now(2) <= '1'; | |||
|
|
483 | -- data_f2_data_out_obs <= '1'; | |||
|
|
484 | -- END IF; | |||
|
|
485 | -- END IF; | |||
|
|
486 | -- WHEN "0111" => | |||
|
|
487 | -- IF empty(3) = '0' THEN | |||
|
|
488 | -- error_new(3) <= '0'; | |||
|
|
489 | -- data_f3_data_out_obs_data <= data_f3_data_out(5 DOWNTO 0); | |||
|
|
490 | -- IF pointer_read(3) < 31 THEN | |||
|
|
491 | -- pointer_read(3) <= pointer_read(3)+1; | |||
|
|
492 | -- ELSE | |||
|
|
493 | -- pointer_read(3) <= 0; | |||
|
|
494 | -- END IF; | |||
|
|
495 | -- IF data_f3_data_out /= data_in(3)(pointer_read(3)) THEN | |||
|
|
496 | -- error_new(3) <= '1'; | |||
|
|
497 | -- error_now(3) <= '1'; | |||
|
|
498 | -- data_f3_data_out_obs <= '1'; | |||
|
|
499 | -- END IF; | |||
|
|
500 | -- END IF; | |||
|
|
501 | -- WHEN "1111" => | |||
|
|
502 | -- NULL; | |||
|
|
503 | ||||
|
|
504 | ||||
|
|
505 | -- WHEN OTHERS => | |||
|
|
506 | -- REPORT "*** ERROR_DATA_REN ***" SEVERITY failure; | |||
|
|
507 | -- NULL; | |||
|
|
508 | -- END CASE; | |||
|
|
509 | ||||
|
|
510 | -- END IF; | |||
|
|
511 | --END PROCESS; | |||
|
|
512 | ||||
|
|
513 | ||||
|
|
514 | ------------------------------------------------------------------------------- | |||
|
|
515 | --clk <= NOT clk AFTER 5 ns; -- 100 MHz | |||
|
|
516 | ||||
|
|
517 | ------------------------------------------------------------------------------- | |||
|
|
518 | --WaveGen_Proc : PROCESS | |||
|
|
519 | --BEGIN | |||
|
|
520 | ||||
|
|
521 | -- -- insert signal assignments here | |||
|
|
522 | -- WAIT UNTIL clk = '1'; | |||
|
|
523 | -- rstn <= '0'; | |||
|
|
524 | -- run <= '0'; | |||
|
|
525 | -- WAIT UNTIL clk = '1'; | |||
|
|
526 | -- WAIT UNTIL clk = '1'; | |||
|
|
527 | -- WAIT UNTIL clk = '1'; | |||
|
|
528 | -- rstn <= '1'; | |||
|
|
529 | -- WAIT UNTIL clk = '1'; | |||
|
|
530 | -- WAIT UNTIL clk = '1'; | |||
|
|
531 | -- WAIT UNTIL clk = '1'; | |||
|
|
532 | -- WAIT UNTIL clk = '1'; | |||
|
|
533 | -- WAIT UNTIL clk = '1'; | |||
|
|
534 | -- run <= '1'; | |||
|
|
535 | -- WAIT UNTIL clk = '1'; | |||
|
|
536 | -- WAIT UNTIL clk = '1'; | |||
|
|
537 | -- WAIT UNTIL clk = '1'; | |||
|
|
538 | -- WAIT UNTIL clk = '1'; | |||
|
|
539 | ||||
|
|
540 | -- WAIT FOR 100 us; | |||
|
|
541 | -- REPORT "*** END simulation ***" SEVERITY failure; | |||
|
|
542 | -- WAIT; | |||
|
|
543 | ||||
|
|
544 | --END PROCESS WaveGen_Proc; | |||
|
|
545 | ||||
|
|
546 | ------------------------------------------------------------------------------- | |||
|
|
547 | --proc_verif : PROCESS (clk, rstn) | |||
|
|
548 | --BEGIN -- PROCESS proc_verif | |||
|
|
549 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
550 | -- pointer_write <= (0, 0, 0, 0); | |||
|
|
551 | -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
552 | -- --IF rand_wen = "1111" THEN | |||
|
|
553 | -- CASE rand_wen IS | |||
|
|
554 | -- WHEN "1110" => | |||
|
|
555 | -- IF full(0) = '0' THEN | |||
|
|
556 | -- IF pointer_write(0) = 128/4-1 THEN | |||
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557 | -- pointer_write(0) <= 0; | |||
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558 | -- ELSE | |||
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559 | -- pointer_write(0) <= pointer_write(0)+1; | |||
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560 | -- END IF; | |||
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561 | -- END IF; | |||
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562 | ||||
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563 | -- WHEN "1101" => | |||
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564 | -- IF full(1) = '0' THEN | |||
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565 | -- IF pointer_write(1) = 128/4-1 THEN | |||
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566 | -- pointer_write(1) <= 0; | |||
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567 | -- ELSE | |||
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568 | -- pointer_write(1) <= pointer_write(1)+1; | |||
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569 | -- END IF; | |||
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570 | -- END IF; | |||
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571 | ||||
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572 | -- WHEN "1011" => | |||
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573 | -- IF full(2) = '0' THEN | |||
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574 | -- IF pointer_write(2) = 128/4-1 THEN | |||
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575 | -- pointer_write(2) <= 0; | |||
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576 | -- ELSE | |||
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577 | -- pointer_write(2) <= pointer_write(2)+1; | |||
|
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578 | -- END IF; | |||
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579 | -- END IF; | |||
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580 | -- WHEN "0111" => | |||
|
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581 | -- IF full(3) = '0' THEN | |||
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582 | -- IF pointer_write(3) = 128/4-1 THEN | |||
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583 | -- pointer_write(3) <= 0; | |||
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584 | -- ELSE | |||
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585 | -- pointer_write(3) <= pointer_write(3)+1; | |||
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586 | -- END IF; | |||
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587 | -- END IF; | |||
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588 | -- WHEN OTHERS => NULL; | |||
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589 | -- END CASE; | |||
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590 | ||||
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591 | -- --END IF; | |||
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592 | -- END IF; | |||
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593 | --END PROCESS proc_verif; | |||
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594 | ||||
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595 | --wdata <= data_in(0)(pointer_write(0)) WHEN rand_wen(0) = '0' ELSE | |||
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596 | -- data_in(1)(pointer_write(1)) WHEN rand_wen(1) = '0' ELSE | |||
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597 | -- data_in(2)(pointer_write(2)) WHEN rand_wen(2) = '0' ELSE | |||
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598 | -- data_in(3)(pointer_write(3)) WHEN rand_wen(3) = '0' ELSE | |||
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599 | -- (OTHERS => '0'); | |||
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600 | ||||
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601 | --data_wen <= rand_wen; | |||
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602 | ||||
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603 | --data_ren <= rand_ren OR empty; | |||
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604 | ||||
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605 | ||||
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606 | ||||
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607 | ||||
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608 | END; | |||
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1 | ||||
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2 | LIBRARY ieee; | |||
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3 | USE ieee.std_logic_1164.ALL; | |||
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4 | USE IEEE.MATH_REAL.ALL; | |||
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5 | USE ieee.numeric_std.ALL; | |||
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6 | ||||
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7 | LIBRARY lpp; | |||
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8 | USE lpp.lpp_waveform_pkg.ALL; | |||
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9 | ||||
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10 | LIBRARY lpp; | |||
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11 | USE lpp.lpp_memory.ALL; | |||
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12 | USE lpp.iir_filter.ALL; | |||
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13 | ||||
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14 | ENTITY testbench IS | |||
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15 | END; | |||
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16 | ||||
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17 | ARCHITECTURE behav OF testbench IS | |||
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18 | ||||
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19 | COMPONENT lpp_fifo_4_shared_headreg_latency_0 | |||
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20 | PORT ( | |||
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21 | clk : IN STD_LOGIC; | |||
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22 | rstn : IN STD_LOGIC; | |||
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23 | run : IN STD_LOGIC; | |||
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24 | o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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25 | o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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26 | o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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27 | o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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28 | o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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29 | o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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30 | o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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31 | i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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32 | i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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33 | i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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34 | i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
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35 | END COMPONENT; | |||
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36 | ||||
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37 | ----------------------------------------------------------------------------- | |||
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38 | -- Common signal | |||
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39 | SIGNAL clk : STD_LOGIC := '0'; | |||
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40 | SIGNAL rstn : STD_LOGIC := '0'; | |||
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41 | SIGNAL run : STD_LOGIC := '0'; | |||
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42 | ||||
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43 | ----------------------------------------------------------------------------- | |||
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44 | TYPE DATA_FIFO_VECTOR IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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45 | SIGNAL data_out_obs : DATA_FIFO_VECTOR; | |||
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46 | SIGNAL data_out_obs_1 : DATA_FIFO_VECTOR; | |||
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47 | SIGNAL data_out_obs_2 : DATA_FIFO_VECTOR; | |||
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48 | ||||
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49 | SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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50 | SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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51 | SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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52 | SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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53 | ||||
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54 | SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b | |||
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55 | SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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56 | SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '1'); | |||
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57 | SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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58 | ||||
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59 | SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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60 | SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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61 | SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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62 | SIGNAL data_out : DATA_FIFO_VECTOR; | |||
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63 | ||||
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64 | SIGNAL empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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65 | SIGNAL empty_reg_2 : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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66 | SIGNAL data_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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67 | ||||
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68 | SIGNAL full_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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69 | ----------------------------------------------------------------------------- | |||
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70 | TYPE DATA_CHANNEL IS ARRAY (0 TO 128/4-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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71 | TYPE DATA_ARRAY IS ARRAY (0 TO 3) OF DATA_CHANNEL; | |||
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72 | SIGNAL data_in : DATA_ARRAY; | |||
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73 | ||||
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74 | ----------------------------------------------------------------------------- | |||
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75 | CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1+2+2; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE | |||
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76 | CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0; | |||
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77 | SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); | |||
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78 | -- | |||
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79 | SIGNAL rand_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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80 | SIGNAL rand_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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81 | ||||
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82 | TYPE POINTER IS ARRAY (0 TO 3) OF INTEGER; | |||
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83 | SIGNAL pointer_read : POINTER; | |||
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84 | SIGNAL pointer_write : POINTER := (0, 0, 0, 0); | |||
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85 | ||||
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86 | --SIGNAL data_f0_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
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87 | --SIGNAL data_f0_data_out_obs : STD_LOGIC; | |||
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88 | --SIGNAL data_f1_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
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89 | --SIGNAL data_f1_data_out_obs : STD_LOGIC; | |||
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90 | --SIGNAL data_f2_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
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91 | --SIGNAL data_f2_data_out_obs : STD_LOGIC; | |||
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92 | --SIGNAL data_f3_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
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93 | --SIGNAL data_f3_data_out_obs : STD_LOGIC; | |||
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94 | SIGNAL error_now : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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95 | SIGNAL error_new : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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96 | ||||
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97 | SIGNAL read_stop : STD_LOGIC; | |||
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98 | ||||
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99 | -- SIGNAL empty_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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100 | ||||
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101 | ----------------------------------------------------------------------------- | |||
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102 | BEGIN | |||
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103 | ||||
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104 | all_I : FOR I IN 0 TO 3 GENERATE | |||
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105 | all_J : FOR J IN 0 TO 128/4-1 GENERATE | |||
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106 | data_in(I)(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+I*(2**28)+1, 32)); | |||
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107 | END GENERATE all_J; | |||
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108 | END GENERATE all_I; | |||
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109 | ||||
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110 | ||||
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111 | ----------------------------------------------------------------------------- | |||
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112 | --lpp_waveform_fifo_1 : lpp_waveform_fifo | |||
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113 | -- GENERIC MAP (tech => 0) | |||
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114 | -- PORT MAP ( | |||
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115 | -- clk => clk, | |||
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116 | -- rstn => rstn, | |||
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117 | -- run => run, | |||
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118 | ||||
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119 | -- empty => s_empty, | |||
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120 | -- empty_almost => s_empty_almost, | |||
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121 | -- data_ren => s_data_ren, | |||
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122 | -- rdata => s_rdata, | |||
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123 | ||||
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124 | -- full_almost => full_almost, | |||
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125 | -- full => full, | |||
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126 | -- data_wen => data_wen, | |||
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127 | -- wdata => wdata); | |||
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128 | ||||
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129 | lpp_fifo_4_shared_1 : lpp_fifo_4_shared | |||
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130 | GENERIC MAP ( | |||
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131 | tech => 0, | |||
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132 | Mem_use => use_RAM, | |||
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133 | EMPTY_ALMOST_LIMIT => 16, | |||
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134 | FULL_ALMOST_LIMIT => 5, | |||
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135 | DataSz => 32, | |||
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136 | AddrSz => 7) | |||
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137 | PORT MAP ( | |||
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138 | clk => clk, | |||
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139 | rstn => rstn, | |||
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140 | run => run, | |||
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141 | empty_almost => s_empty_almost, | |||
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142 | empty => s_empty, | |||
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143 | r_en => s_data_ren, | |||
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144 | r_data => s_rdata, | |||
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145 | ||||
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146 | full_almost => full_almost, | |||
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147 | full => full, | |||
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148 | w_en => data_wen, | |||
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149 | w_data => wdata); | |||
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150 | ||||
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151 | ||||
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152 | --empty_almost <= s_empty_almost; | |||
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153 | --empty <= s_empty; | |||
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154 | ||||
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155 | --s_data_ren <= data_ren; | |||
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156 | --data_out(0) <= s_rdata; | |||
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157 | --data_out(1) <= s_rdata; | |||
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158 | --data_out(2) <= s_rdata; | |||
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159 | --data_out(3) <= s_rdata; | |||
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160 | ||||
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161 | ||||
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162 | ||||
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163 | lpp_fifo_4_shared_headreg_1: lpp_fifo_4_shared_headreg_latency_0 | |||
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164 | PORT MAP ( | |||
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165 | clk => clk, | |||
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166 | rstn => rstn, | |||
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167 | run => run, | |||
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168 | ||||
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169 | o_empty_almost => empty_almost, | |||
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170 | o_empty => empty, | |||
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171 | ||||
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172 | o_data_ren => data_ren, | |||
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173 | o_rdata_0 => data_out(0), | |||
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174 | o_rdata_1 => data_out(1), | |||
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175 | o_rdata_2 => data_out(2), | |||
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176 | o_rdata_3 => data_out(3), | |||
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177 | ||||
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178 | i_empty_almost => s_empty_almost, | |||
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179 | i_empty => s_empty, | |||
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180 | i_data_ren => s_data_ren, | |||
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181 | i_rdata => s_rdata); | |||
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182 | ||||
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183 | --lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg | |||
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184 | -- GENERIC MAP (tech => 0) | |||
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185 | -- PORT MAP ( | |||
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186 | -- clk => clk, | |||
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187 | -- rstn => rstn, | |||
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188 | -- run => run, | |||
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189 | -- o_empty_almost => empty_almost, | |||
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190 | -- o_empty => empty, | |||
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191 | ||||
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192 | -- o_data_ren => data_ren, | |||
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193 | -- o_rdata_0 => data_out(0), | |||
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194 | -- o_rdata_1 => data_out(1), | |||
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195 | -- o_rdata_2 => data_out(2), | |||
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196 | -- o_rdata_3 => data_out(3), | |||
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197 | ||||
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198 | -- i_empty_almost => s_empty_almost, | |||
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199 | -- i_empty => s_empty, | |||
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200 | -- i_data_ren => s_data_ren, | |||
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201 | -- i_rdata => s_rdata); | |||
|
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202 | ----------------------------------------------------------------------------- | |||
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203 | ||||
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204 | ||||
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205 | ||||
|
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206 | ----------------------------------------------------------------------------- | |||
|
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207 | all_data_channel : FOR I IN 0 TO 3 GENERATE | |||
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208 | ----------------------------------------------------------------------------- | |||
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209 | -- READ | |||
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210 | ----------------------------------------------------------------------------- | |||
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211 | ||||
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212 | PROCESS (clk, rstn) | |||
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213 | BEGIN -- PROCESS | |||
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214 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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215 | empty_reg(I) <= '1'; | |||
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216 | empty_reg_2(I) <= '1'; | |||
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217 | data_ren_reg(I) <= '1'; | |||
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218 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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219 | empty_reg(I) <= empty(I); | |||
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220 | empty_reg_2(I) <= empty_reg(I); | |||
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221 | ||||
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222 | data_ren_reg(I) <= data_ren(I); | |||
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223 | END IF; | |||
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224 | END PROCESS; | |||
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225 | ||||
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226 | PROCESS (clk, rstn) | |||
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227 | BEGIN -- PROCESS | |||
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228 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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229 | data_out_obs(I) <= (OTHERS => '0'); | |||
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230 | ||||
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231 | pointer_read(I) <= 0; | |||
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232 | error_now(I) <= '0'; | |||
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233 | error_new(I) <= '0'; | |||
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234 | ||||
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235 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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236 | error_now(I) <= '0'; | |||
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237 | IF empty(I) = '0' THEN | |||
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238 | IF data_ren(I) = '0' THEN | |||
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239 | ||||
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240 | error_new(I) <= '0'; | |||
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241 | data_out_obs(I) <= data_out(I); | |||
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242 | ||||
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243 | IF pointer_read(I) < 128/4-1 THEN | |||
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244 | pointer_read(I) <= pointer_read(I) + 1; | |||
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245 | ELSE | |||
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246 | pointer_read(I) <= 0; | |||
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247 | END IF; | |||
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248 | ||||
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249 | IF data_out(I) /= data_in(I)(pointer_read(I)) THEN | |||
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250 | data_out_obs_1(I) <= data_out(I); | |||
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251 | data_out_obs_2(I) <= data_in(I)(pointer_read(I)); | |||
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252 | error_now(I) <= '1'; | |||
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253 | error_new(I) <= '1'; | |||
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254 | END IF; | |||
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255 | END IF; | |||
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256 | ||||
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257 | END IF; | |||
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258 | END IF; | |||
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259 | END PROCESS; | |||
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260 | ||||
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261 | ----------------------------------------------------------------------------- | |||
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262 | -- WRITE | |||
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263 | ----------------------------------------------------------------------------- | |||
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264 | PROCESS (clk, rstn) | |||
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265 | BEGIN -- PROCESS | |||
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266 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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267 | full_reg(I) <= '0'; | |||
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268 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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269 | full_reg(I) <= full(I); | |||
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270 | END IF; | |||
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271 | END PROCESS; | |||
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272 | ||||
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273 | PROCESS (clk, rstn) | |||
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274 | BEGIN -- PROCESS proc_verif | |||
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275 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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276 | pointer_write(I) <= 0; | |||
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277 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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278 | IF data_wen(I) = '0' THEN | |||
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279 | IF full_reg(I) = '0' THEN | |||
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280 | IF pointer_write(I) < 128/4-1 THEN | |||
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281 | pointer_write(I) <= pointer_write(I)+1; | |||
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282 | ELSE | |||
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283 | pointer_write(I) <= 0; | |||
|
|
284 | END IF; | |||
|
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285 | END IF; | |||
|
|
286 | END IF; | |||
|
|
287 | END IF; | |||
|
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288 | END PROCESS; | |||
|
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289 | END GENERATE all_data_channel; | |||
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290 | ||||
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291 | wdata <= data_in(0)(pointer_write(0)) WHEN data_wen = "1110" ELSE | |||
|
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292 | data_in(1)(pointer_write(1)) WHEN data_wen = "1101" ELSE | |||
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293 | data_in(2)(pointer_write(2)) WHEN data_wen = "1011" ELSE | |||
|
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294 | data_in(3)(pointer_write(3)) WHEN data_wen = "0111" ELSE | |||
|
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295 | (OTHERS => 'X'); | |||
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296 | ||||
|
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297 | ----------------------------------------------------------------------------- | |||
|
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298 | ||||
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299 | ||||
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300 | ||||
|
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301 | ----------------------------------------------------------------------------- | |||
|
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302 | clk <= NOT clk AFTER 5 ns; -- 100 MHz | |||
|
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303 | ----------------------------------------------------------------------------- | |||
|
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304 | WaveGen_Proc : PROCESS | |||
|
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305 | BEGIN | |||
|
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306 | -- insert signal assignments here | |||
|
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307 | WAIT UNTIL clk = '1'; | |||
|
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308 | read_stop <= '0'; | |||
|
|
309 | rstn <= '0'; | |||
|
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310 | run <= '0'; | |||
|
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311 | WAIT UNTIL clk = '1'; | |||
|
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312 | WAIT UNTIL clk = '1'; | |||
|
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313 | WAIT UNTIL clk = '1'; | |||
|
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314 | rstn <= '1'; | |||
|
|
315 | WAIT UNTIL clk = '1'; | |||
|
|
316 | WAIT UNTIL clk = '1'; | |||
|
|
317 | WAIT UNTIL clk = '1'; | |||
|
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318 | WAIT UNTIL clk = '1'; | |||
|
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319 | WAIT UNTIL clk = '1'; | |||
|
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320 | run <= '1'; | |||
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321 | WAIT UNTIL clk = '1'; | |||
|
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322 | WAIT UNTIL clk = '1'; | |||
|
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323 | WAIT UNTIL clk = '1'; | |||
|
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324 | WAIT UNTIL clk = '1'; | |||
|
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325 | WAIT FOR 10 us; | |||
|
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326 | read_stop <= '1'; | |||
|
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327 | WAIT FOR 10 us; | |||
|
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328 | read_stop <= '0'; | |||
|
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329 | WAIT FOR 80 us; | |||
|
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330 | REPORT "*** END simulation ***" SEVERITY failure; | |||
|
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331 | WAIT; | |||
|
|
332 | END PROCESS WaveGen_Proc; | |||
|
|
333 | ----------------------------------------------------------------------------- | |||
|
|
334 | ||||
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335 | ||||
|
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336 | ||||
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337 | ||||
|
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338 | ||||
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339 | ----------------------------------------------------------------------------- | |||
|
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340 | -- RANDOM GENERATOR | |||
|
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341 | ----------------------------------------------------------------------------- | |||
|
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342 | PROCESS (clk, rstn) | |||
|
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343 | VARIABLE seed1, seed2 : POSITIVE; | |||
|
|
344 | VARIABLE rand1 : REAL; | |||
|
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345 | VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); | |||
|
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346 | BEGIN -- PROCESS | |||
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347 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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348 | random_vector <= (OTHERS => '0'); | |||
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349 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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350 | UNIFORM(seed1, seed2, rand1); | |||
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351 | RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR( | |||
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352 | to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)), | |||
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353 | RANDOM_VECTOR_VAR'LENGTH) | |||
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354 | ); | |||
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355 | ||||
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356 | random_vector <= RANDOM_VECTOR_VAR; | |||
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357 | END IF; | |||
|
|
358 | END PROCESS; | |||
|
|
359 | ----------------------------------------------------------------------------- | |||
|
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360 | rand_ren <= "1111" WHEN random_vector(0) = '0' ELSE | |||
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361 | "1110" WHEN random_vector(2 DOWNTO 1) = "00" ELSE | |||
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362 | "1101" WHEN random_vector(2 DOWNTO 1) = "01" ELSE | |||
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363 | "1011" WHEN random_vector(2 DOWNTO 1) = "10" ELSE | |||
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364 | "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE | |||
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365 | ||||
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366 | rand_wen <= "1111" WHEN random_vector(3) = '0' ELSE | |||
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367 | "1110" WHEN random_vector(5 DOWNTO 4) = "00" ELSE | |||
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368 | "1101" WHEN random_vector(5 DOWNTO 4) = "01" ELSE | |||
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369 | "1011" WHEN random_vector(5 DOWNTO 4) = "10" ELSE | |||
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370 | "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE | |||
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371 | ----------------------------------------------------------------------------- | |||
|
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372 | PROCESS (clk, rstn) | |||
|
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373 | BEGIN -- PROCESS | |||
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374 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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375 | data_wen <= (OTHERS => '1'); | |||
|
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376 | data_ren <= (OTHERS => '1'); | |||
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377 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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378 | data_wen <= rand_wen; | |||
|
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379 | IF read_stop = '0' THEN | |||
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380 | all_ren_bits : FOR I IN 0 TO 3 LOOP | |||
|
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381 | IF empty(I) = '1' THEN | |||
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382 | data_ren(I) <= '1'; | |||
|
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383 | ELSE | |||
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384 | data_ren(I) <= rand_ren(I); | |||
|
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385 | END IF; | |||
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386 | END LOOP all_ren_bits; | |||
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387 | ELSE | |||
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388 | data_ren <= (OTHERS => '1'); | |||
|
|
389 | END IF; | |||
|
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390 | END IF; | |||
|
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391 | END PROCESS; | |||
|
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392 | ----------------------------------------------------------------------------- | |||
|
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393 | ||||
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394 | ||||
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395 | --PROCESS (clk, rstn) | |||
|
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396 | --BEGIN -- PROCESS | |||
|
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397 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
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398 | -- empty <= (OTHERS => '1'); | |||
|
|
399 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
400 | -- empty <= empty_s; | |||
|
|
401 | -- END IF; | |||
|
|
402 | --END PROCESS; | |||
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403 | ||||
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404 | ||||
|
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405 | --PROCESS (clk, rstn) | |||
|
|
406 | --BEGIN -- PROCESS | |||
|
|
407 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
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408 | -- data_f0_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
409 | -- data_f1_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
410 | -- data_f2_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
411 | -- data_f3_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
412 | -- data_f0_data_out_obs <= '0'; | |||
|
|
413 | -- data_f1_data_out_obs <= '0'; | |||
|
|
414 | -- data_f2_data_out_obs <= '0'; | |||
|
|
415 | -- data_f3_data_out_obs <= '0'; | |||
|
|
416 | ||||
|
|
417 | -- pointer_read <= (0, 0, 0, 0); | |||
|
|
418 | -- error_now <= (OTHERS => '0'); | |||
|
|
419 | -- error_new <= (OTHERS => '0'); | |||
|
|
420 | ||||
|
|
421 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
422 | -- error_now <= (OTHERS => '0'); | |||
|
|
423 | -- CASE data_ren IS | |||
|
|
424 | -- WHEN "1110" => | |||
|
|
425 | -- IF empty(0) = '0' THEN | |||
|
|
426 | -- error_new(0) <= '0'; | |||
|
|
427 | -- data_f0_data_out_obs_data <= data_f0_data_out(5 DOWNTO 0); | |||
|
|
428 | -- IF pointer_read(0) < 31 THEN | |||
|
|
429 | -- pointer_read(0) <= pointer_read(0)+1; | |||
|
|
430 | -- ELSE | |||
|
|
431 | -- pointer_read(0) <= 0; | |||
|
|
432 | -- END IF; | |||
|
|
433 | -- IF data_f0_data_out /= data_in(0)(pointer_read(0)) THEN | |||
|
|
434 | -- error_now(0) <= '1'; | |||
|
|
435 | -- error_new(0) <= '1'; | |||
|
|
436 | -- data_f0_data_out_obs <= '1'; | |||
|
|
437 | -- END IF; | |||
|
|
438 | -- --IF data_f0_data_out(29 DOWNTO 28) /= "00" THEN | |||
|
|
439 | -- -- data_f0_data_out_obs <= '1'; | |||
|
|
440 | -- --END IF; | |||
|
|
441 | -- END IF; | |||
|
|
442 | ||||
|
|
443 | -- WHEN "1101" => | |||
|
|
444 | -- IF empty(1) = '0' THEN | |||
|
|
445 | -- error_new(1) <= '0'; | |||
|
|
446 | -- data_f1_data_out_obs_data <= data_f1_data_out(5 DOWNTO 0); | |||
|
|
447 | -- IF pointer_read(1) < 31 THEN | |||
|
|
448 | -- pointer_read(1) <= pointer_read(1)+1; | |||
|
|
449 | -- ELSE | |||
|
|
450 | -- pointer_read(1) <= 0; | |||
|
|
451 | -- END IF; | |||
|
|
452 | -- IF data_f1_data_out /= data_in(1)(pointer_read(1)) THEN | |||
|
|
453 | -- error_new(1) <= '1'; | |||
|
|
454 | -- error_now(1) <= '1'; | |||
|
|
455 | -- data_f1_data_out_obs <= '1'; | |||
|
|
456 | -- END IF; | |||
|
|
457 | -- END IF; | |||
|
|
458 | -- WHEN "1011" => | |||
|
|
459 | -- IF empty(2) = '0' THEN | |||
|
|
460 | -- error_new(2) <= '0'; | |||
|
|
461 | -- data_f2_data_out_obs_data <= data_f2_data_out(5 DOWNTO 0); | |||
|
|
462 | -- IF pointer_read(2) < 31 THEN | |||
|
|
463 | -- pointer_read(2) <= pointer_read(2)+1; | |||
|
|
464 | -- ELSE | |||
|
|
465 | -- pointer_read(2) <= 0; | |||
|
|
466 | -- END IF; | |||
|
|
467 | -- IF data_f2_data_out /= data_in(2)(pointer_read(2)) THEN | |||
|
|
468 | -- error_new(2) <= '1'; | |||
|
|
469 | -- error_now(2) <= '1'; | |||
|
|
470 | -- data_f2_data_out_obs <= '1'; | |||
|
|
471 | -- END IF; | |||
|
|
472 | -- END IF; | |||
|
|
473 | -- WHEN "0111" => | |||
|
|
474 | -- IF empty(3) = '0' THEN | |||
|
|
475 | -- error_new(3) <= '0'; | |||
|
|
476 | -- data_f3_data_out_obs_data <= data_f3_data_out(5 DOWNTO 0); | |||
|
|
477 | -- IF pointer_read(3) < 31 THEN | |||
|
|
478 | -- pointer_read(3) <= pointer_read(3)+1; | |||
|
|
479 | -- ELSE | |||
|
|
480 | -- pointer_read(3) <= 0; | |||
|
|
481 | -- END IF; | |||
|
|
482 | -- IF data_f3_data_out /= data_in(3)(pointer_read(3)) THEN | |||
|
|
483 | -- error_new(3) <= '1'; | |||
|
|
484 | -- error_now(3) <= '1'; | |||
|
|
485 | -- data_f3_data_out_obs <= '1'; | |||
|
|
486 | -- END IF; | |||
|
|
487 | -- END IF; | |||
|
|
488 | -- WHEN "1111" => | |||
|
|
489 | -- NULL; | |||
|
|
490 | ||||
|
|
491 | ||||
|
|
492 | -- WHEN OTHERS => | |||
|
|
493 | -- REPORT "*** ERROR_DATA_REN ***" SEVERITY failure; | |||
|
|
494 | -- NULL; | |||
|
|
495 | -- END CASE; | |||
|
|
496 | ||||
|
|
497 | -- END IF; | |||
|
|
498 | --END PROCESS; | |||
|
|
499 | ||||
|
|
500 | ||||
|
|
501 | ------------------------------------------------------------------------------- | |||
|
|
502 | --clk <= NOT clk AFTER 5 ns; -- 100 MHz | |||
|
|
503 | ||||
|
|
504 | ------------------------------------------------------------------------------- | |||
|
|
505 | --WaveGen_Proc : PROCESS | |||
|
|
506 | --BEGIN | |||
|
|
507 | ||||
|
|
508 | -- -- insert signal assignments here | |||
|
|
509 | -- WAIT UNTIL clk = '1'; | |||
|
|
510 | -- rstn <= '0'; | |||
|
|
511 | -- run <= '0'; | |||
|
|
512 | -- WAIT UNTIL clk = '1'; | |||
|
|
513 | -- WAIT UNTIL clk = '1'; | |||
|
|
514 | -- WAIT UNTIL clk = '1'; | |||
|
|
515 | -- rstn <= '1'; | |||
|
|
516 | -- WAIT UNTIL clk = '1'; | |||
|
|
517 | -- WAIT UNTIL clk = '1'; | |||
|
|
518 | -- WAIT UNTIL clk = '1'; | |||
|
|
519 | -- WAIT UNTIL clk = '1'; | |||
|
|
520 | -- WAIT UNTIL clk = '1'; | |||
|
|
521 | -- run <= '1'; | |||
|
|
522 | -- WAIT UNTIL clk = '1'; | |||
|
|
523 | -- WAIT UNTIL clk = '1'; | |||
|
|
524 | -- WAIT UNTIL clk = '1'; | |||
|
|
525 | -- WAIT UNTIL clk = '1'; | |||
|
|
526 | ||||
|
|
527 | -- WAIT FOR 100 us; | |||
|
|
528 | -- REPORT "*** END simulation ***" SEVERITY failure; | |||
|
|
529 | -- WAIT; | |||
|
|
530 | ||||
|
|
531 | --END PROCESS WaveGen_Proc; | |||
|
|
532 | ||||
|
|
533 | ------------------------------------------------------------------------------- | |||
|
|
534 | --proc_verif : PROCESS (clk, rstn) | |||
|
|
535 | --BEGIN -- PROCESS proc_verif | |||
|
|
536 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
537 | -- pointer_write <= (0, 0, 0, 0); | |||
|
|
538 | -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
539 | -- --IF rand_wen = "1111" THEN | |||
|
|
540 | -- CASE rand_wen IS | |||
|
|
541 | -- WHEN "1110" => | |||
|
|
542 | -- IF full(0) = '0' THEN | |||
|
|
543 | -- IF pointer_write(0) = 128/4-1 THEN | |||
|
|
544 | -- pointer_write(0) <= 0; | |||
|
|
545 | -- ELSE | |||
|
|
546 | -- pointer_write(0) <= pointer_write(0)+1; | |||
|
|
547 | -- END IF; | |||
|
|
548 | -- END IF; | |||
|
|
549 | ||||
|
|
550 | -- WHEN "1101" => | |||
|
|
551 | -- IF full(1) = '0' THEN | |||
|
|
552 | -- IF pointer_write(1) = 128/4-1 THEN | |||
|
|
553 | -- pointer_write(1) <= 0; | |||
|
|
554 | -- ELSE | |||
|
|
555 | -- pointer_write(1) <= pointer_write(1)+1; | |||
|
|
556 | -- END IF; | |||
|
|
557 | -- END IF; | |||
|
|
558 | ||||
|
|
559 | -- WHEN "1011" => | |||
|
|
560 | -- IF full(2) = '0' THEN | |||
|
|
561 | -- IF pointer_write(2) = 128/4-1 THEN | |||
|
|
562 | -- pointer_write(2) <= 0; | |||
|
|
563 | -- ELSE | |||
|
|
564 | -- pointer_write(2) <= pointer_write(2)+1; | |||
|
|
565 | -- END IF; | |||
|
|
566 | -- END IF; | |||
|
|
567 | -- WHEN "0111" => | |||
|
|
568 | -- IF full(3) = '0' THEN | |||
|
|
569 | -- IF pointer_write(3) = 128/4-1 THEN | |||
|
|
570 | -- pointer_write(3) <= 0; | |||
|
|
571 | -- ELSE | |||
|
|
572 | -- pointer_write(3) <= pointer_write(3)+1; | |||
|
|
573 | -- END IF; | |||
|
|
574 | -- END IF; | |||
|
|
575 | -- WHEN OTHERS => NULL; | |||
|
|
576 | -- END CASE; | |||
|
|
577 | ||||
|
|
578 | -- --END IF; | |||
|
|
579 | -- END IF; | |||
|
|
580 | --END PROCESS proc_verif; | |||
|
|
581 | ||||
|
|
582 | --wdata <= data_in(0)(pointer_write(0)) WHEN rand_wen(0) = '0' ELSE | |||
|
|
583 | -- data_in(1)(pointer_write(1)) WHEN rand_wen(1) = '0' ELSE | |||
|
|
584 | -- data_in(2)(pointer_write(2)) WHEN rand_wen(2) = '0' ELSE | |||
|
|
585 | -- data_in(3)(pointer_write(3)) WHEN rand_wen(3) = '0' ELSE | |||
|
|
586 | -- (OTHERS => '0'); | |||
|
|
587 | ||||
|
|
588 | --data_wen <= rand_wen; | |||
|
|
589 | ||||
|
|
590 | --data_ren <= rand_ren OR empty; | |||
|
|
591 | ||||
|
|
592 | ||||
|
|
593 | ||||
|
|
594 | ||||
|
|
595 | END; | |||
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| @@ -0,0 +1,610 | |||||
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1 | ||||
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2 | LIBRARY ieee; | |||
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3 | USE ieee.std_logic_1164.ALL; | |||
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4 | USE IEEE.MATH_REAL.ALL; | |||
|
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5 | USE ieee.numeric_std.ALL; | |||
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6 | ||||
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7 | LIBRARY lpp; | |||
|
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8 | USE lpp.lpp_waveform_pkg.ALL; | |||
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9 | ||||
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10 | LIBRARY lpp; | |||
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11 | USE lpp.lpp_memory.ALL; | |||
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12 | USE lpp.iir_filter.ALL; | |||
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13 | ||||
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14 | ENTITY testbench IS | |||
|
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15 | END; | |||
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16 | ||||
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17 | ARCHITECTURE behav OF testbench IS | |||
|
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18 | ||||
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19 | COMPONENT lpp_fifo_4_shared_headreg_latency_1 | |||
|
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20 | PORT ( | |||
|
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21 | clk : IN STD_LOGIC; | |||
|
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22 | rstn : IN STD_LOGIC; | |||
|
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23 | run : IN STD_LOGIC; | |||
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24 | o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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25 | o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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26 | o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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27 | o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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28 | o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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29 | o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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30 | o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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31 | i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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32 | i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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33 | i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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34 | i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
|
35 | END COMPONENT; | |||
|
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36 | ||||
|
|
37 | ----------------------------------------------------------------------------- | |||
|
|
38 | -- Common signal | |||
|
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39 | SIGNAL clk : STD_LOGIC := '0'; | |||
|
|
40 | SIGNAL rstn : STD_LOGIC := '0'; | |||
|
|
41 | SIGNAL run : STD_LOGIC := '0'; | |||
|
|
42 | ||||
|
|
43 | ----------------------------------------------------------------------------- | |||
|
|
44 | TYPE DATA_FIFO_VECTOR IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
45 | SIGNAL data_out_obs : DATA_FIFO_VECTOR; | |||
|
|
46 | SIGNAL data_out_obs_1 : DATA_FIFO_VECTOR; | |||
|
|
47 | SIGNAL data_out_obs_2 : DATA_FIFO_VECTOR; | |||
|
|
48 | ||||
|
|
49 | SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
50 | SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
51 | SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
52 | SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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53 | ||||
|
|
54 | SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b | |||
|
|
55 | SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
56 | SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '1'); | |||
|
|
57 | SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
58 | ||||
|
|
59 | SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
60 | SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
61 | SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
62 | SIGNAL data_out : DATA_FIFO_VECTOR; | |||
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63 | ||||
|
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64 | SIGNAL empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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65 | SIGNAL empty_reg_2 : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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66 | SIGNAL data_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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67 | ||||
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68 | SIGNAL full_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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69 | ----------------------------------------------------------------------------- | |||
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70 | TYPE DATA_CHANNEL IS ARRAY (0 TO 128/4-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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71 | TYPE DATA_ARRAY IS ARRAY (0 TO 3) OF DATA_CHANNEL; | |||
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72 | SIGNAL data_in : DATA_ARRAY; | |||
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73 | ||||
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74 | ----------------------------------------------------------------------------- | |||
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75 | CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1+2+2; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE | |||
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76 | CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0; | |||
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77 | SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); | |||
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78 | -- | |||
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79 | SIGNAL rand_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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80 | SIGNAL rand_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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81 | ||||
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82 | TYPE POINTER IS ARRAY (0 TO 3) OF INTEGER; | |||
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83 | SIGNAL pointer_read : POINTER; | |||
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84 | SIGNAL pointer_write : POINTER := (0, 0, 0, 0); | |||
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85 | ||||
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86 | --SIGNAL data_f0_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
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87 | --SIGNAL data_f0_data_out_obs : STD_LOGIC; | |||
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88 | --SIGNAL data_f1_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
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89 | --SIGNAL data_f1_data_out_obs : STD_LOGIC; | |||
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90 | --SIGNAL data_f2_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
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91 | --SIGNAL data_f2_data_out_obs : STD_LOGIC; | |||
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92 | --SIGNAL data_f3_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
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93 | --SIGNAL data_f3_data_out_obs : STD_LOGIC; | |||
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94 | SIGNAL error_now : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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95 | SIGNAL error_new : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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96 | ||||
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97 | SIGNAL WARNING_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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98 | ||||
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99 | SIGNAL read_stop : STD_LOGIC; | |||
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100 | SIGNAL write_stop : STD_LOGIC; | |||
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101 | ||||
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102 | -- SIGNAL empty_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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103 | ||||
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104 | ----------------------------------------------------------------------------- | |||
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105 | BEGIN | |||
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106 | ||||
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107 | all_I : FOR I IN 0 TO 3 GENERATE | |||
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108 | all_J : FOR J IN 0 TO 128/4-1 GENERATE | |||
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109 | data_in(I)(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+I*(2**28)+1, 32)); | |||
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110 | END GENERATE all_J; | |||
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111 | END GENERATE all_I; | |||
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112 | ||||
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113 | ||||
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114 | ----------------------------------------------------------------------------- | |||
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115 | --lpp_waveform_fifo_1 : lpp_waveform_fifo | |||
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116 | -- GENERIC MAP (tech => 0) | |||
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117 | -- PORT MAP ( | |||
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118 | -- clk => clk, | |||
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119 | -- rstn => rstn, | |||
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120 | -- run => run, | |||
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121 | ||||
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122 | -- empty => s_empty, | |||
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123 | -- empty_almost => s_empty_almost, | |||
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124 | -- data_ren => s_data_ren, | |||
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125 | -- rdata => s_rdata, | |||
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126 | ||||
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127 | -- full_almost => full_almost, | |||
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128 | -- full => full, | |||
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129 | -- data_wen => data_wen, | |||
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130 | -- wdata => wdata); | |||
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131 | ||||
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132 | lpp_fifo_4_shared_1 : lpp_fifo_4_shared | |||
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133 | GENERIC MAP ( | |||
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134 | tech => 0, | |||
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135 | Mem_use => use_RAM, | |||
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136 | EMPTY_ALMOST_LIMIT => 16, | |||
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137 | FULL_ALMOST_LIMIT => 5, | |||
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138 | DataSz => 32, | |||
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139 | AddrSz => 7) | |||
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140 | PORT MAP ( | |||
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141 | clk => clk, | |||
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142 | rstn => rstn, | |||
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143 | run => run, | |||
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144 | empty_almost => s_empty_almost, | |||
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145 | empty => s_empty, | |||
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146 | r_en => s_data_ren, | |||
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147 | r_data => s_rdata, | |||
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148 | ||||
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149 | full_almost => full_almost, | |||
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150 | full => full, | |||
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151 | w_en => data_wen, | |||
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152 | w_data => wdata); | |||
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153 | ||||
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154 | ||||
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155 | ||||
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156 | lpp_fifo_4_shared_headreg_1: lpp_fifo_4_shared_headreg_latency_1 | |||
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157 | PORT MAP ( | |||
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158 | clk => clk, | |||
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159 | rstn => rstn, | |||
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160 | run => run, | |||
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161 | ||||
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162 | o_empty_almost => empty_almost, | |||
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163 | o_empty => empty, | |||
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164 | ||||
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165 | o_data_ren => data_ren, | |||
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166 | o_rdata_0 => data_out(0), | |||
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167 | o_rdata_1 => data_out(1), | |||
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168 | o_rdata_2 => data_out(2), | |||
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169 | o_rdata_3 => data_out(3), | |||
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170 | ||||
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171 | i_empty_almost => s_empty_almost, | |||
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172 | i_empty => s_empty, | |||
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173 | i_data_ren => s_data_ren, | |||
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174 | i_rdata => s_rdata); | |||
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175 | ||||
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176 | --lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg | |||
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177 | -- GENERIC MAP (tech => 0) | |||
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178 | -- PORT MAP ( | |||
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179 | -- clk => clk, | |||
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180 | -- rstn => rstn, | |||
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181 | -- run => run, | |||
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182 | -- o_empty_almost => empty_almost, | |||
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183 | -- o_empty => empty, | |||
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184 | ||||
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185 | -- o_data_ren => data_ren, | |||
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186 | -- o_rdata_0 => data_out(0), | |||
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187 | -- o_rdata_1 => data_out(1), | |||
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188 | -- o_rdata_2 => data_out(2), | |||
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|
189 | -- o_rdata_3 => data_out(3), | |||
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190 | ||||
|
|
191 | -- i_empty_almost => s_empty_almost, | |||
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192 | -- i_empty => s_empty, | |||
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|
193 | -- i_data_ren => s_data_ren, | |||
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|
194 | -- i_rdata => s_rdata); | |||
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|
195 | ----------------------------------------------------------------------------- | |||
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|
196 | ||||
|
|
197 | ||||
|
|
198 | ||||
|
|
199 | ----------------------------------------------------------------------------- | |||
|
|
200 | all_data_channel : FOR I IN 0 TO 3 GENERATE | |||
|
|
201 | ----------------------------------------------------------------------------- | |||
|
|
202 | -- READ | |||
|
|
203 | ----------------------------------------------------------------------------- | |||
|
|
204 | ||||
|
|
205 | PROCESS (clk, rstn) | |||
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206 | BEGIN -- PROCESS | |||
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|
207 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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208 | empty_reg(I) <= '1'; | |||
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209 | empty_reg_2(I) <= '1'; | |||
|
|
210 | data_ren_reg(I) <= '1'; | |||
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211 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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|
212 | empty_reg(I) <= empty(I); | |||
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|
213 | empty_reg_2(I) <= empty_reg(I); | |||
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214 | ||||
|
|
215 | data_ren_reg(I) <= data_ren(I); | |||
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|
216 | END IF; | |||
|
|
217 | END PROCESS; | |||
|
|
218 | ||||
|
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219 | PROCESS (clk, rstn) | |||
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220 | BEGIN -- PROCESS | |||
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221 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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222 | data_out_obs(I) <= (OTHERS => '0'); | |||
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223 | ||||
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224 | pointer_read(I) <= 0; | |||
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225 | error_now(I) <= '0'; | |||
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|
226 | error_new(I) <= '0'; | |||
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|
227 | ||||
|
|
228 | WARNING_DATA(I) <= '0'; | |||
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229 | ||||
|
|
230 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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|
231 | IF data_out_obs(I) = data_in(I)(pointer_read(I)) THEN | |||
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|
232 | WARNING_DATA(I) <= '0'; | |||
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233 | ELSE | |||
|
|
234 | WARNING_DATA(I) <= '1'; | |||
|
|
235 | END IF; | |||
|
|
236 | ||||
|
|
237 | error_now(I) <= '0'; | |||
|
|
238 | IF empty_reg_2(I) = '0' THEN | |||
|
|
239 | IF data_ren_reg(I) = '0' THEN | |||
|
|
240 | ||||
|
|
241 | error_new(I) <= '0'; | |||
|
|
242 | data_out_obs(I) <= data_out(I); | |||
|
|
243 | ||||
|
|
244 | IF pointer_read(I) < 128/4-1 THEN | |||
|
|
245 | pointer_read(I) <= pointer_read(I) + 1; | |||
|
|
246 | ELSE | |||
|
|
247 | pointer_read(I) <= 0; | |||
|
|
248 | END IF; | |||
|
|
249 | ||||
|
|
250 | IF data_out(I) /= data_in(I)(pointer_read(I)) THEN | |||
|
|
251 | data_out_obs_1(I) <= data_out(I); | |||
|
|
252 | data_out_obs_2(I) <= data_in(I)(pointer_read(I)); | |||
|
|
253 | error_now(I) <= '1'; | |||
|
|
254 | error_new(I) <= '1'; | |||
|
|
255 | END IF; | |||
|
|
256 | END IF; | |||
|
|
257 | ||||
|
|
258 | END IF; | |||
|
|
259 | END IF; | |||
|
|
260 | END PROCESS; | |||
|
|
261 | ||||
|
|
262 | ----------------------------------------------------------------------------- | |||
|
|
263 | -- WRITE | |||
|
|
264 | ----------------------------------------------------------------------------- | |||
|
|
265 | PROCESS (clk, rstn) | |||
|
|
266 | BEGIN -- PROCESS | |||
|
|
267 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
268 | full_reg(I) <= '0'; | |||
|
|
269 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
270 | full_reg(I) <= full(I); | |||
|
|
271 | END IF; | |||
|
|
272 | END PROCESS; | |||
|
|
273 | ||||
|
|
274 | PROCESS (clk, rstn) | |||
|
|
275 | BEGIN -- PROCESS proc_verif | |||
|
|
276 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
277 | pointer_write(I) <= 0; | |||
|
|
278 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
279 | IF data_wen(I) = '0' THEN | |||
|
|
280 | IF full_reg(I) = '0' THEN | |||
|
|
281 | IF pointer_write(I) < 128/4-1 THEN | |||
|
|
282 | pointer_write(I) <= pointer_write(I)+1; | |||
|
|
283 | ELSE | |||
|
|
284 | pointer_write(I) <= 0; | |||
|
|
285 | END IF; | |||
|
|
286 | END IF; | |||
|
|
287 | END IF; | |||
|
|
288 | END IF; | |||
|
|
289 | END PROCESS; | |||
|
|
290 | END GENERATE all_data_channel; | |||
|
|
291 | ||||
|
|
292 | wdata <= data_in(0)(pointer_write(0)) WHEN data_wen = "1110" ELSE | |||
|
|
293 | data_in(1)(pointer_write(1)) WHEN data_wen = "1101" ELSE | |||
|
|
294 | data_in(2)(pointer_write(2)) WHEN data_wen = "1011" ELSE | |||
|
|
295 | data_in(3)(pointer_write(3)) WHEN data_wen = "0111" ELSE | |||
|
|
296 | (OTHERS => 'X'); | |||
|
|
297 | ||||
|
|
298 | ----------------------------------------------------------------------------- | |||
|
|
299 | ||||
|
|
300 | ||||
|
|
301 | ||||
|
|
302 | ----------------------------------------------------------------------------- | |||
|
|
303 | clk <= NOT clk AFTER 5 ns; -- 100 MHz | |||
|
|
304 | ----------------------------------------------------------------------------- | |||
|
|
305 | WaveGen_Proc : PROCESS | |||
|
|
306 | BEGIN | |||
|
|
307 | -- insert signal assignments here | |||
|
|
308 | WAIT UNTIL clk = '1'; | |||
|
|
309 | rstn <= '0'; | |||
|
|
310 | run <= '0'; | |||
|
|
311 | read_stop <= '1'; | |||
|
|
312 | write_stop <= '0'; | |||
|
|
313 | WAIT UNTIL clk = '1'; | |||
|
|
314 | WAIT UNTIL clk = '1'; | |||
|
|
315 | WAIT UNTIL clk = '1'; | |||
|
|
316 | rstn <= '1'; | |||
|
|
317 | WAIT UNTIL clk = '1'; | |||
|
|
318 | WAIT UNTIL clk = '1'; | |||
|
|
319 | WAIT UNTIL clk = '1'; | |||
|
|
320 | WAIT UNTIL clk = '1'; | |||
|
|
321 | WAIT UNTIL clk = '1'; | |||
|
|
322 | run <= '1'; | |||
|
|
323 | WAIT UNTIL clk = '1'; | |||
|
|
324 | WAIT FOR 10 us; | |||
|
|
325 | read_stop <= '0'; | |||
|
|
326 | WAIT UNTIL clk = '1'; | |||
|
|
327 | WAIT UNTIL clk = '1'; | |||
|
|
328 | WAIT UNTIL clk = '1'; | |||
|
|
329 | WAIT FOR 10 us; | |||
|
|
330 | read_stop <= '1'; | |||
|
|
331 | WAIT FOR 10 us; | |||
|
|
332 | read_stop <= '0'; | |||
|
|
333 | WAIT FOR 1 us; | |||
|
|
334 | write_stop <= '1'; | |||
|
|
335 | WAIT FOR 10 us; | |||
|
|
336 | write_stop <= '0'; | |||
|
|
337 | WAIT FOR 80 us; | |||
|
|
338 | REPORT "*** END simulation ***" SEVERITY failure; | |||
|
|
339 | WAIT; | |||
|
|
340 | END PROCESS WaveGen_Proc; | |||
|
|
341 | ----------------------------------------------------------------------------- | |||
|
|
342 | ||||
|
|
343 | ||||
|
|
344 | ||||
|
|
345 | ||||
|
|
346 | ||||
|
|
347 | ----------------------------------------------------------------------------- | |||
|
|
348 | -- RANDOM GENERATOR | |||
|
|
349 | ----------------------------------------------------------------------------- | |||
|
|
350 | PROCESS (clk, rstn) | |||
|
|
351 | VARIABLE seed1, seed2 : POSITIVE; | |||
|
|
352 | VARIABLE rand1 : REAL; | |||
|
|
353 | VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
354 | BEGIN -- PROCESS | |||
|
|
355 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
356 | random_vector <= (OTHERS => '0'); | |||
|
|
357 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
358 | UNIFORM(seed1, seed2, rand1); | |||
|
|
359 | RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR( | |||
|
|
360 | to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)), | |||
|
|
361 | RANDOM_VECTOR_VAR'LENGTH) | |||
|
|
362 | ); | |||
|
|
363 | ||||
|
|
364 | random_vector <= RANDOM_VECTOR_VAR; | |||
|
|
365 | END IF; | |||
|
|
366 | END PROCESS; | |||
|
|
367 | ----------------------------------------------------------------------------- | |||
|
|
368 | rand_ren <= "1111" WHEN random_vector(0) = '0' ELSE | |||
|
|
369 | "1110" WHEN random_vector(2 DOWNTO 1) = "00" ELSE | |||
|
|
370 | "1101" WHEN random_vector(2 DOWNTO 1) = "01" ELSE | |||
|
|
371 | "1011" WHEN random_vector(2 DOWNTO 1) = "10" ELSE | |||
|
|
372 | "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE | |||
|
|
373 | ||||
|
|
374 | rand_wen <= "1111" WHEN random_vector(3) = '0' ELSE | |||
|
|
375 | "1110" WHEN random_vector(5 DOWNTO 4) = "00" ELSE | |||
|
|
376 | "1101" WHEN random_vector(5 DOWNTO 4) = "01" ELSE | |||
|
|
377 | "1011" WHEN random_vector(5 DOWNTO 4) = "10" ELSE | |||
|
|
378 | "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE | |||
|
|
379 | ----------------------------------------------------------------------------- | |||
|
|
380 | PROCESS (clk, rstn) | |||
|
|
381 | BEGIN -- PROCESS | |||
|
|
382 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
383 | data_wen <= (OTHERS => '1'); | |||
|
|
384 | data_ren <= (OTHERS => '1'); | |||
|
|
385 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
386 | ||||
|
|
387 | IF write_stop = '0' THEN | |||
|
|
388 | data_wen <= rand_ren; | |||
|
|
389 | ELSE | |||
|
|
390 | data_ren <= (OTHERS => '1'); | |||
|
|
391 | END IF; | |||
|
|
392 | ||||
|
|
393 | IF read_stop = '0' THEN | |||
|
|
394 | all_ren_bits : FOR I IN 0 TO 3 LOOP | |||
|
|
395 | IF empty(I) = '1' THEN | |||
|
|
396 | data_ren(I) <= '1'; | |||
|
|
397 | ELSE | |||
|
|
398 | data_ren(I) <= rand_ren(I); | |||
|
|
399 | END IF; | |||
|
|
400 | END LOOP all_ren_bits; | |||
|
|
401 | ELSE | |||
|
|
402 | data_ren <= (OTHERS => '1'); | |||
|
|
403 | END IF; | |||
|
|
404 | ||||
|
|
405 | END IF; | |||
|
|
406 | END PROCESS; | |||
|
|
407 | ----------------------------------------------------------------------------- | |||
|
|
408 | ||||
|
|
409 | ||||
|
|
410 | --PROCESS (clk, rstn) | |||
|
|
411 | --BEGIN -- PROCESS | |||
|
|
412 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
413 | -- empty <= (OTHERS => '1'); | |||
|
|
414 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
415 | -- empty <= empty_s; | |||
|
|
416 | -- END IF; | |||
|
|
417 | --END PROCESS; | |||
|
|
418 | ||||
|
|
419 | ||||
|
|
420 | --PROCESS (clk, rstn) | |||
|
|
421 | --BEGIN -- PROCESS | |||
|
|
422 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
423 | -- data_f0_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
424 | -- data_f1_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
425 | -- data_f2_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
426 | -- data_f3_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
427 | -- data_f0_data_out_obs <= '0'; | |||
|
|
428 | -- data_f1_data_out_obs <= '0'; | |||
|
|
429 | -- data_f2_data_out_obs <= '0'; | |||
|
|
430 | -- data_f3_data_out_obs <= '0'; | |||
|
|
431 | ||||
|
|
432 | -- pointer_read <= (0, 0, 0, 0); | |||
|
|
433 | -- error_now <= (OTHERS => '0'); | |||
|
|
434 | -- error_new <= (OTHERS => '0'); | |||
|
|
435 | ||||
|
|
436 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
437 | -- error_now <= (OTHERS => '0'); | |||
|
|
438 | -- CASE data_ren IS | |||
|
|
439 | -- WHEN "1110" => | |||
|
|
440 | -- IF empty(0) = '0' THEN | |||
|
|
441 | -- error_new(0) <= '0'; | |||
|
|
442 | -- data_f0_data_out_obs_data <= data_f0_data_out(5 DOWNTO 0); | |||
|
|
443 | -- IF pointer_read(0) < 31 THEN | |||
|
|
444 | -- pointer_read(0) <= pointer_read(0)+1; | |||
|
|
445 | -- ELSE | |||
|
|
446 | -- pointer_read(0) <= 0; | |||
|
|
447 | -- END IF; | |||
|
|
448 | -- IF data_f0_data_out /= data_in(0)(pointer_read(0)) THEN | |||
|
|
449 | -- error_now(0) <= '1'; | |||
|
|
450 | -- error_new(0) <= '1'; | |||
|
|
451 | -- data_f0_data_out_obs <= '1'; | |||
|
|
452 | -- END IF; | |||
|
|
453 | -- --IF data_f0_data_out(29 DOWNTO 28) /= "00" THEN | |||
|
|
454 | -- -- data_f0_data_out_obs <= '1'; | |||
|
|
455 | -- --END IF; | |||
|
|
456 | -- END IF; | |||
|
|
457 | ||||
|
|
458 | -- WHEN "1101" => | |||
|
|
459 | -- IF empty(1) = '0' THEN | |||
|
|
460 | -- error_new(1) <= '0'; | |||
|
|
461 | -- data_f1_data_out_obs_data <= data_f1_data_out(5 DOWNTO 0); | |||
|
|
462 | -- IF pointer_read(1) < 31 THEN | |||
|
|
463 | -- pointer_read(1) <= pointer_read(1)+1; | |||
|
|
464 | -- ELSE | |||
|
|
465 | -- pointer_read(1) <= 0; | |||
|
|
466 | -- END IF; | |||
|
|
467 | -- IF data_f1_data_out /= data_in(1)(pointer_read(1)) THEN | |||
|
|
468 | -- error_new(1) <= '1'; | |||
|
|
469 | -- error_now(1) <= '1'; | |||
|
|
470 | -- data_f1_data_out_obs <= '1'; | |||
|
|
471 | -- END IF; | |||
|
|
472 | -- END IF; | |||
|
|
473 | -- WHEN "1011" => | |||
|
|
474 | -- IF empty(2) = '0' THEN | |||
|
|
475 | -- error_new(2) <= '0'; | |||
|
|
476 | -- data_f2_data_out_obs_data <= data_f2_data_out(5 DOWNTO 0); | |||
|
|
477 | -- IF pointer_read(2) < 31 THEN | |||
|
|
478 | -- pointer_read(2) <= pointer_read(2)+1; | |||
|
|
479 | -- ELSE | |||
|
|
480 | -- pointer_read(2) <= 0; | |||
|
|
481 | -- END IF; | |||
|
|
482 | -- IF data_f2_data_out /= data_in(2)(pointer_read(2)) THEN | |||
|
|
483 | -- error_new(2) <= '1'; | |||
|
|
484 | -- error_now(2) <= '1'; | |||
|
|
485 | -- data_f2_data_out_obs <= '1'; | |||
|
|
486 | -- END IF; | |||
|
|
487 | -- END IF; | |||
|
|
488 | -- WHEN "0111" => | |||
|
|
489 | -- IF empty(3) = '0' THEN | |||
|
|
490 | -- error_new(3) <= '0'; | |||
|
|
491 | -- data_f3_data_out_obs_data <= data_f3_data_out(5 DOWNTO 0); | |||
|
|
492 | -- IF pointer_read(3) < 31 THEN | |||
|
|
493 | -- pointer_read(3) <= pointer_read(3)+1; | |||
|
|
494 | -- ELSE | |||
|
|
495 | -- pointer_read(3) <= 0; | |||
|
|
496 | -- END IF; | |||
|
|
497 | -- IF data_f3_data_out /= data_in(3)(pointer_read(3)) THEN | |||
|
|
498 | -- error_new(3) <= '1'; | |||
|
|
499 | -- error_now(3) <= '1'; | |||
|
|
500 | -- data_f3_data_out_obs <= '1'; | |||
|
|
501 | -- END IF; | |||
|
|
502 | -- END IF; | |||
|
|
503 | -- WHEN "1111" => | |||
|
|
504 | -- NULL; | |||
|
|
505 | ||||
|
|
506 | ||||
|
|
507 | -- WHEN OTHERS => | |||
|
|
508 | -- REPORT "*** ERROR_DATA_REN ***" SEVERITY failure; | |||
|
|
509 | -- NULL; | |||
|
|
510 | -- END CASE; | |||
|
|
511 | ||||
|
|
512 | -- END IF; | |||
|
|
513 | --END PROCESS; | |||
|
|
514 | ||||
|
|
515 | ||||
|
|
516 | ------------------------------------------------------------------------------- | |||
|
|
517 | --clk <= NOT clk AFTER 5 ns; -- 100 MHz | |||
|
|
518 | ||||
|
|
519 | ------------------------------------------------------------------------------- | |||
|
|
520 | --WaveGen_Proc : PROCESS | |||
|
|
521 | --BEGIN | |||
|
|
522 | ||||
|
|
523 | -- -- insert signal assignments here | |||
|
|
524 | -- WAIT UNTIL clk = '1'; | |||
|
|
525 | -- rstn <= '0'; | |||
|
|
526 | -- run <= '0'; | |||
|
|
527 | -- WAIT UNTIL clk = '1'; | |||
|
|
528 | -- WAIT UNTIL clk = '1'; | |||
|
|
529 | -- WAIT UNTIL clk = '1'; | |||
|
|
530 | -- rstn <= '1'; | |||
|
|
531 | -- WAIT UNTIL clk = '1'; | |||
|
|
532 | -- WAIT UNTIL clk = '1'; | |||
|
|
533 | -- WAIT UNTIL clk = '1'; | |||
|
|
534 | -- WAIT UNTIL clk = '1'; | |||
|
|
535 | -- WAIT UNTIL clk = '1'; | |||
|
|
536 | -- run <= '1'; | |||
|
|
537 | -- WAIT UNTIL clk = '1'; | |||
|
|
538 | -- WAIT UNTIL clk = '1'; | |||
|
|
539 | -- WAIT UNTIL clk = '1'; | |||
|
|
540 | -- WAIT UNTIL clk = '1'; | |||
|
|
541 | ||||
|
|
542 | -- WAIT FOR 100 us; | |||
|
|
543 | -- REPORT "*** END simulation ***" SEVERITY failure; | |||
|
|
544 | -- WAIT; | |||
|
|
545 | ||||
|
|
546 | --END PROCESS WaveGen_Proc; | |||
|
|
547 | ||||
|
|
548 | ------------------------------------------------------------------------------- | |||
|
|
549 | --proc_verif : PROCESS (clk, rstn) | |||
|
|
550 | --BEGIN -- PROCESS proc_verif | |||
|
|
551 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
552 | -- pointer_write <= (0, 0, 0, 0); | |||
|
|
553 | -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
554 | -- --IF rand_wen = "1111" THEN | |||
|
|
555 | -- CASE rand_wen IS | |||
|
|
556 | -- WHEN "1110" => | |||
|
|
557 | -- IF full(0) = '0' THEN | |||
|
|
558 | -- IF pointer_write(0) = 128/4-1 THEN | |||
|
|
559 | -- pointer_write(0) <= 0; | |||
|
|
560 | -- ELSE | |||
|
|
561 | -- pointer_write(0) <= pointer_write(0)+1; | |||
|
|
562 | -- END IF; | |||
|
|
563 | -- END IF; | |||
|
|
564 | ||||
|
|
565 | -- WHEN "1101" => | |||
|
|
566 | -- IF full(1) = '0' THEN | |||
|
|
567 | -- IF pointer_write(1) = 128/4-1 THEN | |||
|
|
568 | -- pointer_write(1) <= 0; | |||
|
|
569 | -- ELSE | |||
|
|
570 | -- pointer_write(1) <= pointer_write(1)+1; | |||
|
|
571 | -- END IF; | |||
|
|
572 | -- END IF; | |||
|
|
573 | ||||
|
|
574 | -- WHEN "1011" => | |||
|
|
575 | -- IF full(2) = '0' THEN | |||
|
|
576 | -- IF pointer_write(2) = 128/4-1 THEN | |||
|
|
577 | -- pointer_write(2) <= 0; | |||
|
|
578 | -- ELSE | |||
|
|
579 | -- pointer_write(2) <= pointer_write(2)+1; | |||
|
|
580 | -- END IF; | |||
|
|
581 | -- END IF; | |||
|
|
582 | -- WHEN "0111" => | |||
|
|
583 | -- IF full(3) = '0' THEN | |||
|
|
584 | -- IF pointer_write(3) = 128/4-1 THEN | |||
|
|
585 | -- pointer_write(3) <= 0; | |||
|
|
586 | -- ELSE | |||
|
|
587 | -- pointer_write(3) <= pointer_write(3)+1; | |||
|
|
588 | -- END IF; | |||
|
|
589 | -- END IF; | |||
|
|
590 | -- WHEN OTHERS => NULL; | |||
|
|
591 | -- END CASE; | |||
|
|
592 | ||||
|
|
593 | -- --END IF; | |||
|
|
594 | -- END IF; | |||
|
|
595 | --END PROCESS proc_verif; | |||
|
|
596 | ||||
|
|
597 | --wdata <= data_in(0)(pointer_write(0)) WHEN rand_wen(0) = '0' ELSE | |||
|
|
598 | -- data_in(1)(pointer_write(1)) WHEN rand_wen(1) = '0' ELSE | |||
|
|
599 | -- data_in(2)(pointer_write(2)) WHEN rand_wen(2) = '0' ELSE | |||
|
|
600 | -- data_in(3)(pointer_write(3)) WHEN rand_wen(3) = '0' ELSE | |||
|
|
601 | -- (OTHERS => '0'); | |||
|
|
602 | ||||
|
|
603 | --data_wen <= rand_wen; | |||
|
|
604 | ||||
|
|
605 | --data_ren <= rand_ren OR empty; | |||
|
|
606 | ||||
|
|
607 | ||||
|
|
608 | ||||
|
|
609 | ||||
|
|
610 | END; | |||
| @@ -0,0 +1,136 | |||||
|
|
1 | ||||
|
|
2 | LIBRARY ieee; | |||
|
|
3 | USE ieee.std_logic_1164.ALL; | |||
|
|
4 | LIBRARY grlib; | |||
|
|
5 | USE grlib.amba.ALL; | |||
|
|
6 | USE grlib.stdlib.ALL; | |||
|
|
7 | --LIBRARY gaisler; | |||
|
|
8 | --USE gaisler.libdcom.ALL; | |||
|
|
9 | --USE gaisler.sim.ALL; | |||
|
|
10 | --USE gaisler.jtagtst.ALL; | |||
|
|
11 | --LIBRARY techmap; | |||
|
|
12 | --USE techmap.gencomp.ALL; | |||
|
|
13 | ||||
|
|
14 | ||||
|
|
15 | PACKAGE testbench_package IS | |||
|
|
16 | ||||
|
|
17 | PROCEDURE APB_WRITE ( | |||
|
|
18 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
19 | CONSTANT pindex : IN INTEGER; | |||
|
|
20 | SIGNAL apbi : OUT apb_slv_in_type; | |||
|
|
21 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
22 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
23 | ); | |||
|
|
24 | ||||
|
|
25 | PROCEDURE APB_READ ( | |||
|
|
26 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
27 | CONSTANT pindex : IN INTEGER; | |||
|
|
28 | SIGNAL apbi : OUT apb_slv_in_type; | |||
|
|
29 | SIGNAL apbo : IN apb_slv_out_type; | |||
|
|
30 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
31 | SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
32 | ); | |||
|
|
33 | ||||
|
|
34 | PROCEDURE AHB_READ ( | |||
|
|
35 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
36 | CONSTANT hindex : IN INTEGER; | |||
|
|
37 | SIGNAL ahbmi : IN ahb_mst_in_type; | |||
|
|
38 | SIGNAL ahbmo : OUT ahb_mst_out_type; | |||
|
|
39 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
40 | SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
41 | ); | |||
|
|
42 | ||||
|
|
43 | END testbench_package; | |||
|
|
44 | ||||
|
|
45 | PACKAGE BODY testbench_package IS | |||
|
|
46 | ||||
|
|
47 | PROCEDURE APB_WRITE ( | |||
|
|
48 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
49 | CONSTANT pindex : IN INTEGER; | |||
|
|
50 | SIGNAL apbi : OUT apb_slv_in_type; | |||
|
|
51 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
52 | CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
53 | ) IS | |||
|
|
54 | BEGIN | |||
|
|
55 | apbi.psel(pindex) <= '1'; | |||
|
|
56 | apbi.pwrite <= '1'; | |||
|
|
57 | apbi.penable <= '1'; | |||
|
|
58 | apbi.paddr <= paddr; | |||
|
|
59 | apbi.pwdata <= pwdata; | |||
|
|
60 | WAIT UNTIL clk = '0'; | |||
|
|
61 | WAIT UNTIL clk = '1'; | |||
|
|
62 | apbi.psel(pindex) <= '0'; | |||
|
|
63 | apbi.pwrite <= '0'; | |||
|
|
64 | apbi.penable <= '0'; | |||
|
|
65 | apbi.paddr <= (OTHERS => '0'); | |||
|
|
66 | apbi.pwdata <= (OTHERS => '0'); | |||
|
|
67 | WAIT UNTIL clk = '0'; | |||
|
|
68 | WAIT UNTIL clk = '1'; | |||
|
|
69 | ||||
|
|
70 | END APB_WRITE; | |||
|
|
71 | ||||
|
|
72 | PROCEDURE APB_READ ( | |||
|
|
73 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
74 | CONSTANT pindex : IN INTEGER; | |||
|
|
75 | SIGNAL apbi : OUT apb_slv_in_type; | |||
|
|
76 | SIGNAL apbo : IN apb_slv_out_type; | |||
|
|
77 | CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
78 | SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
79 | ) IS | |||
|
|
80 | BEGIN | |||
|
|
81 | apbi.psel(pindex) <= '1'; | |||
|
|
82 | apbi.pwrite <= '0'; | |||
|
|
83 | apbi.penable <= '1'; | |||
|
|
84 | apbi.paddr <= paddr; | |||
|
|
85 | WAIT UNTIL clk = '0'; | |||
|
|
86 | WAIT UNTIL clk = '1'; | |||
|
|
87 | apbi.psel(pindex) <= '0'; | |||
|
|
88 | apbi.pwrite <= '0'; | |||
|
|
89 | apbi.penable <= '0'; | |||
|
|
90 | apbi.paddr <= (OTHERS => '0'); | |||
|
|
91 | WAIT UNTIL clk = '0'; | |||
|
|
92 | WAIT UNTIL clk = '1'; | |||
|
|
93 | prdata <= apbo.prdata; | |||
|
|
94 | END APB_READ; | |||
|
|
95 | ||||
|
|
96 | PROCEDURE AHB_READ ( | |||
|
|
97 | SIGNAL clk : IN STD_LOGIC; | |||
|
|
98 | CONSTANT hindex : IN INTEGER; | |||
|
|
99 | SIGNAL ahbmi : IN ahb_mst_in_type; | |||
|
|
100 | SIGNAL ahbmo : OUT ahb_mst_out_type; | |||
|
|
101 | CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
102 | SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
|
103 | ) IS | |||
|
|
104 | BEGIN | |||
|
|
105 | WAIT UNTIL clk = '1'; | |||
|
|
106 | ahbmo.HADDR <= haddr; | |||
|
|
107 | ahbmo.HPROT <= "0011"; | |||
|
|
108 | ahbmo.HIRQ <= (OTHERS => '0'); | |||
|
|
109 | ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); | |||
|
|
110 | ahbmo.HINDEX <= hindex; | |||
|
|
111 | ahbmo.HBUSREQ <= '1'; | |||
|
|
112 | ahbmo.HLOCK <= '1'; | |||
|
|
113 | ahbmo.HSIZE <= HSIZE_WORD; | |||
|
|
114 | ahbmo.HBURST <= HBURST_SINGLE; | |||
|
|
115 | ahbmo.HTRANS <= HTRANS_NONSEQ; | |||
|
|
116 | ahbmo.HWRITE <= '0'; | |||
|
|
117 | WHILE ahbmi.HREADY = '0' LOOP | |||
|
|
118 | WAIT UNTIL clk = '1'; | |||
|
|
119 | END LOOP; | |||
|
|
120 | WAIT UNTIL clk = '1'; | |||
|
|
121 | --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; | |||
|
|
122 | ahbmo.HBUSREQ <= '0'; | |||
|
|
123 | ahbmo.HLOCK <= '0'; | |||
|
|
124 | ahbmo.HTRANS <= HTRANS_IDLE; | |||
|
|
125 | WHILE ahbmi.HREADY = '0' LOOP | |||
|
|
126 | WAIT UNTIL clk = '1'; | |||
|
|
127 | END LOOP; | |||
|
|
128 | WAIT UNTIL clk = '1'; | |||
|
|
129 | hrdata <= ahbmi.HRDATA; | |||
|
|
130 | --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; | |||
|
|
131 | ahbmo.HLOCK <= '0'; | |||
|
|
132 | WAIT UNTIL clk = '1'; | |||
|
|
133 | ||||
|
|
134 | END AHB_READ; | |||
|
|
135 | ||||
|
|
136 | END testbench_package; | |||
| @@ -0,0 +1,27 | |||||
|
|
1 | onerror {resume} | |||
|
|
2 | quietly WaveActivateNextPane {} 0 | |||
|
|
3 | add wave -noupdate /testbench/clk | |||
|
|
4 | add wave -noupdate /testbench/rstn | |||
|
|
5 | add wave -noupdate /testbench/run | |||
|
|
6 | add wave -noupdate /testbench/read_stop | |||
|
|
7 | add wave -noupdate /testbench/write_stop | |||
|
|
8 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/error_now(3) {-height 15 -radix hexadecimal} /testbench/error_now(2) {-height 15 -radix hexadecimal} /testbench/error_now(1) {-height 15 -radix hexadecimal} /testbench/error_now(0) {-height 15 -radix hexadecimal}} /testbench/error_now | |||
|
|
9 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/error_new(3) {-height 15 -radix hexadecimal} /testbench/error_new(2) {-height 15 -radix hexadecimal} /testbench/error_new(1) {-height 15 -radix hexadecimal} /testbench/error_new(0) {-height 15 -radix hexadecimal}} /testbench/error_new | |||
|
|
10 | add wave -noupdate /testbench/warning_data | |||
|
|
11 | TreeUpdate [SetDefaultTree] | |||
|
|
12 | WaveRestoreCursors {{Cursor 1} {41355000 ps} 0} | |||
|
|
13 | configure wave -namecolwidth 341 | |||
|
|
14 | configure wave -valuecolwidth 172 | |||
|
|
15 | configure wave -justifyvalue left | |||
|
|
16 | configure wave -signalnamewidth 0 | |||
|
|
17 | configure wave -snapdistance 10 | |||
|
|
18 | configure wave -datasetprefix 0 | |||
|
|
19 | configure wave -rowmargin 4 | |||
|
|
20 | configure wave -childrowmargin 2 | |||
|
|
21 | configure wave -gridoffset 0 | |||
|
|
22 | configure wave -gridperiod 1 | |||
|
|
23 | configure wave -griddelta 40 | |||
|
|
24 | configure wave -timeline 0 | |||
|
|
25 | configure wave -timelineunits ns | |||
|
|
26 | update | |||
|
|
27 | WaveRestoreZoom {0 ps} {699496876 ps} | |||
| @@ -0,0 +1,59 | |||||
|
|
1 | onerror {resume} | |||
|
|
2 | quietly WaveActivateNextPane {} 0 | |||
|
|
3 | add wave -noupdate /testbench/clk | |||
|
|
4 | add wave -noupdate /testbench/rstn | |||
|
|
5 | add wave -noupdate /testbench/run | |||
|
|
6 | add wave -noupdate -expand -group FIFO_IN /testbench/full_almost | |||
|
|
7 | add wave -noupdate -expand -group FIFO_IN /testbench/full | |||
|
|
8 | add wave -noupdate -expand -group FIFO_IN -expand /testbench/data_wen | |||
|
|
9 | add wave -noupdate -expand -group FIFO_IN -radix hexadecimal /testbench/wdata | |||
|
|
10 | add wave -noupdate -expand -group internal /testbench/s_empty_almost | |||
|
|
11 | add wave -noupdate -expand -group internal -expand /testbench/s_empty | |||
|
|
12 | add wave -noupdate -expand -group internal -expand /testbench/s_data_ren | |||
|
|
13 | add wave -noupdate -expand -group internal -radix hexadecimal /testbench/s_rdata | |||
|
|
14 | add wave -noupdate /testbench/pointer_write | |||
|
|
15 | add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty_almost | |||
|
|
16 | add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty | |||
|
|
17 | add wave -noupdate -expand -group FIFO_OUT -radix binary -expand -subitemconfig {/testbench/data_ren(3) {-radix binary} /testbench/data_ren(2) {-radix binary} /testbench/data_ren(1) {-radix binary} /testbench/data_ren(0) {-radix binary}} /testbench/data_ren | |||
|
|
18 | add wave -noupdate -expand -group FIFO_OUT -radix hexadecimal -expand -subitemconfig {/testbench/data_out(0) {-height 15 -radix hexadecimal} /testbench/data_out(1) {-height 15 -radix hexadecimal} /testbench/data_out(2) {-height 15 -radix hexadecimal} /testbench/data_out(3) {-height 15 -radix hexadecimal}} /testbench/data_out | |||
|
|
19 | add wave -noupdate -expand /testbench/pointer_read | |||
|
|
20 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/error_now(3) {-height 15 -radix hexadecimal} /testbench/error_now(2) {-height 15 -radix hexadecimal} /testbench/error_now(1) {-height 15 -radix hexadecimal} /testbench/error_now(0) {-height 15 -radix hexadecimal}} /testbench/error_now | |||
|
|
21 | add wave -noupdate -radix hexadecimal /testbench/error_new | |||
|
|
22 | add wave -noupdate /testbench/read_stop | |||
|
|
23 | add wave -noupdate -expand /testbench/empty_reg | |||
|
|
24 | add wave -noupdate -expand /testbench/data_ren | |||
|
|
25 | add wave -noupdate -expand -group Head_REG /testbench/lpp_fifo_4_shared_headreg_1/o_empty_almost | |||
|
|
26 | add wave -noupdate -expand -group Head_REG /testbench/lpp_fifo_4_shared_headreg_1/o_empty | |||
|
|
27 | add wave -noupdate -expand -group Head_REG /testbench/lpp_fifo_4_shared_headreg_1/o_data_ren | |||
|
|
28 | add wave -noupdate -expand -group Head_REG -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/o_rdata_0 | |||
|
|
29 | add wave -noupdate -expand -group Head_REG -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/o_rdata_1 | |||
|
|
30 | add wave -noupdate -expand -group Head_REG -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/o_rdata_2 | |||
|
|
31 | add wave -noupdate -expand -group Head_REG -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/o_rdata_3 | |||
|
|
32 | add wave -noupdate -expand -group {HEAD_REG - FIFO_Shared} /testbench/lpp_fifo_4_shared_headreg_1/i_empty_almost | |||
|
|
33 | add wave -noupdate -expand -group {HEAD_REG - FIFO_Shared} /testbench/lpp_fifo_4_shared_headreg_1/i_empty | |||
|
|
34 | add wave -noupdate -expand -group {HEAD_REG - FIFO_Shared} /testbench/lpp_fifo_4_shared_headreg_1/i_data_ren | |||
|
|
35 | add wave -noupdate -expand -group {HEAD_REG - FIFO_Shared} -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/i_rdata | |||
|
|
36 | add wave -noupdate -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/reg_head_data | |||
|
|
37 | add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/reg_head_full | |||
|
|
38 | add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/i_data_ren_pre | |||
|
|
39 | add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/o_data_ren_pre | |||
|
|
40 | add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/i_data_ren_s_temp | |||
|
|
41 | add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/i_data_ren_s | |||
|
|
42 | add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/i_empty_reg | |||
|
|
43 | TreeUpdate [SetDefaultTree] | |||
|
|
44 | WaveRestoreCursors {{Cursor 1} {75000 ps} 0} | |||
|
|
45 | configure wave -namecolwidth 341 | |||
|
|
46 | configure wave -valuecolwidth 172 | |||
|
|
47 | configure wave -justifyvalue left | |||
|
|
48 | configure wave -signalnamewidth 0 | |||
|
|
49 | configure wave -snapdistance 10 | |||
|
|
50 | configure wave -datasetprefix 0 | |||
|
|
51 | configure wave -rowmargin 4 | |||
|
|
52 | configure wave -childrowmargin 2 | |||
|
|
53 | configure wave -gridoffset 0 | |||
|
|
54 | configure wave -gridperiod 1 | |||
|
|
55 | configure wave -griddelta 40 | |||
|
|
56 | configure wave -timeline 0 | |||
|
|
57 | configure wave -timelineunits ns | |||
|
|
58 | update | |||
|
|
59 | WaveRestoreZoom {0 ps} {215438 ps} | |||
| @@ -0,0 +1,41 | |||||
|
|
1 | onerror {resume} | |||
|
|
2 | quietly WaveActivateNextPane {} 0 | |||
|
|
3 | add wave -noupdate /testbench/clk | |||
|
|
4 | add wave -noupdate /testbench/rstn | |||
|
|
5 | add wave -noupdate /testbench/run | |||
|
|
6 | add wave -noupdate -expand /testbench/empty | |||
|
|
7 | add wave -noupdate /testbench/full | |||
|
|
8 | add wave -noupdate /testbench/read_stop | |||
|
|
9 | add wave -noupdate /testbench/write_stop | |||
|
|
10 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/error_now(3) {-height 15 -radix hexadecimal} /testbench/error_now(2) {-height 15 -radix hexadecimal} /testbench/error_now(1) {-height 15 -radix hexadecimal} /testbench/error_now(0) {-height 15 -radix hexadecimal}} /testbench/error_now | |||
|
|
11 | add wave -noupdate -radix hexadecimal /testbench/error_new | |||
|
|
12 | add wave -noupdate -expand -group FIFO_IN /testbench/full_almost | |||
|
|
13 | add wave -noupdate -expand -group FIFO_IN /testbench/full | |||
|
|
14 | add wave -noupdate -expand -group FIFO_IN /testbench/data_wen | |||
|
|
15 | add wave -noupdate -expand -group FIFO_IN -radix hexadecimal /testbench/wdata | |||
|
|
16 | add wave -noupdate -group internal /testbench/s_empty_almost | |||
|
|
17 | add wave -noupdate -group internal -expand /testbench/s_empty | |||
|
|
18 | add wave -noupdate -group internal -expand /testbench/s_data_ren | |||
|
|
19 | add wave -noupdate -group internal -radix hexadecimal /testbench/s_rdata | |||
|
|
20 | add wave -noupdate /testbench/pointer_write | |||
|
|
21 | add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty_almost | |||
|
|
22 | add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty | |||
|
|
23 | add wave -noupdate -expand -group FIFO_OUT -radix binary -expand -subitemconfig {/testbench/data_ren(3) {-height 15 -radix binary} /testbench/data_ren(2) {-height 15 -radix binary} /testbench/data_ren(1) {-height 15 -radix binary} /testbench/data_ren(0) {-height 15 -radix binary}} /testbench/data_ren | |||
|
|
24 | add wave -noupdate -expand -group FIFO_OUT -radix hexadecimal -expand -subitemconfig {/testbench/data_out(0) {-height 15 -radix hexadecimal} /testbench/data_out(1) {-height 15 -radix hexadecimal} /testbench/data_out(2) {-height 15 -radix hexadecimal} /testbench/data_out(3) {-height 15 -radix hexadecimal}} /testbench/data_out | |||
|
|
25 | TreeUpdate [SetDefaultTree] | |||
|
|
26 | WaveRestoreCursors {{Cursor 1} {41365000 ps} 0} | |||
|
|
27 | configure wave -namecolwidth 341 | |||
|
|
28 | configure wave -valuecolwidth 172 | |||
|
|
29 | configure wave -justifyvalue left | |||
|
|
30 | configure wave -signalnamewidth 0 | |||
|
|
31 | configure wave -snapdistance 10 | |||
|
|
32 | configure wave -datasetprefix 0 | |||
|
|
33 | configure wave -rowmargin 4 | |||
|
|
34 | configure wave -childrowmargin 2 | |||
|
|
35 | configure wave -gridoffset 0 | |||
|
|
36 | configure wave -gridperiod 1 | |||
|
|
37 | configure wave -griddelta 40 | |||
|
|
38 | configure wave -timeline 0 | |||
|
|
39 | configure wave -timelineunits ns | |||
|
|
40 | update | |||
|
|
41 | WaveRestoreZoom {40912888 ps} {42319723 ps} | |||
| @@ -0,0 +1,128 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------- | |||
|
|
19 | -- Author : Jean-christophe Pellion | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------- | |||
|
|
22 | LIBRARY IEEE; | |||
|
|
23 | USE IEEE.numeric_std.ALL; | |||
|
|
24 | USE IEEE.std_logic_1164.ALL; | |||
|
|
25 | ||||
|
|
26 | LIBRARY techmap; | |||
|
|
27 | USE techmap.gencomp.ALL; | |||
|
|
28 | ||||
|
|
29 | LIBRARY lpp; | |||
|
|
30 | USE lpp.iir_filter.ALL; | |||
|
|
31 | USE lpp.FILTERcfg.ALL; | |||
|
|
32 | USE lpp.lpp_lfr_filter_coeff.ALL; | |||
|
|
33 | USE lpp.general_purpose.ALL; | |||
|
|
34 | ||||
|
|
35 | ENTITY IIR_CEL_TEST IS | |||
|
|
36 | PORT ( | |||
|
|
37 | rstn : IN STD_LOGIC; | |||
|
|
38 | clk : IN STD_LOGIC; | |||
|
|
39 | ||||
|
|
40 | sample_in_val : IN STD_LOGIC; | |||
|
|
41 | sample_in : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
42 | ||||
|
|
43 | sample_out_val : OUT STD_LOGIC; | |||
|
|
44 | sample_out : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0)); | |||
|
|
45 | END IIR_CEL_TEST; | |||
|
|
46 | ||||
|
|
47 | ARCHITECTURE beh OF IIR_CEL_TEST IS | |||
|
|
48 | CONSTANT ChanelCount : INTEGER := 8; | |||
|
|
49 | CONSTANT Coef_SZ : INTEGER := 9; | |||
|
|
50 | CONSTANT CoefCntPerCel : INTEGER := 6; | |||
|
|
51 | CONSTANT CoefPerCel : INTEGER := 5; | |||
|
|
52 | CONSTANT Cels_count : INTEGER := 5; | |||
|
|
53 | ||||
|
|
54 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |||
|
|
55 | ||||
|
|
56 | ||||
|
|
57 | ----------------------------------------------------------------------------- | |||
|
|
58 | CONSTANT CEL_NUMBER : INTEGER := 5; | |||
|
|
59 | CONSTANT COEFFICIENT_SIZE : INTEGER := 9; | |||
|
|
60 | CONSTANT POINT_POSITION : INTEGER := 7; | |||
|
|
61 | CONSTANT COEFFICIENT_PER_CEL : INTEGER := 5; | |||
|
|
62 | SIGNAL coeff_test : STD_LOGIC_VECTOR((CEL_NUMBER * 5 * COEFFICIENT_SIZE)-1 DOWNTO 0); | |||
|
|
63 | SIGNAL f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := | |||
|
|
64 | ( | |||
|
|
65 | (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), | |||
|
|
66 | (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), | |||
|
|
67 | (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), | |||
|
|
68 | (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), | |||
|
|
69 | (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) | |||
|
|
70 | ); | |||
|
|
71 | SIGNAL f0_to_f1_gain : COEFF_CEL_REAL := | |||
|
|
72 | ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); | |||
|
|
73 | ||||
|
|
74 | SUBTYPE COEFFICIENT IS STD_LOGIC_VECTOR(COEFFICIENT_SIZE-1 DOWNTO 0); | |||
|
|
75 | TYPE COEFFICIENT_CEL IS ARRAY (1 TO 5) OF COEFFICIENT; | |||
|
|
76 | TYPE COEFFICIENT_GLOBAL IS ARRAY (INTEGER RANGE <>) OF COEFFICIENT_CEL; | |||
|
|
77 | ||||
|
|
78 | SIGNAL coeff_test_2 : COEFFICIENT_GLOBAL(1 TO 5); | |||
|
|
79 | ----------------------------------------------------------------------------- | |||
|
|
80 | SIGNAL f_to_f0_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := | |||
|
|
81 | ( | |||
|
|
82 | (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), | |||
|
|
83 | (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), | |||
|
|
84 | (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), | |||
|
|
85 | (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), | |||
|
|
86 | (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) | |||
|
|
87 | ); | |||
|
|
88 | SIGNAL f_to_f0_gain : COEFF_CEL_REAL := | |||
|
|
89 | ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); | |||
|
|
90 | ||||
|
|
91 | BEGIN -- beh | |||
|
|
92 | ||||
|
|
93 | coeff_test <= | |||
|
|
94 | get_IIR_CEL_FILTER_CONFIG( | |||
|
|
95 | COEFFICIENT_SIZE, POINT_POSITION, CEL_NUMBER, | |||
|
|
96 | f0_to_f1_sos, f0_to_f1_gain); | |||
|
|
97 | ||||
|
|
98 | all_cel: FOR I IN 0 TO 4 GENERATE | |||
|
|
99 | all_coeff: FOR J IN 0 TO 4 GENERATE | |||
|
|
100 | coeff_test_2(I+1)(J+1) <= | |||
|
|
101 | coeff_test((I*5+J+1)*COEFFICIENT_SIZE-1 DOWNTO (I*5+J)*COEFFICIENT_SIZE); | |||
|
|
102 | END GENERATE all_coeff; | |||
|
|
103 | END GENERATE all_cel; | |||
|
|
104 | ||||
|
|
105 | ||||
|
|
106 | coefs_v2 <= CoefsInitValCst_v2; | |||
|
|
107 | ||||
|
|
108 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |||
|
|
109 | GENERIC MAP ( | |||
|
|
110 | tech => 0, | |||
|
|
111 | Mem_use => use_CEL, -- use_RAM | |||
|
|
112 | Sample_SZ => 18, | |||
|
|
113 | Coef_SZ => Coef_SZ, | |||
|
|
114 | Coef_Nb => 25, | |||
|
|
115 | Coef_sel_SZ => 5, | |||
|
|
116 | Cels_count => Cels_count, | |||
|
|
117 | ChanelsCount => ChanelCount) | |||
|
|
118 | PORT MAP ( | |||
|
|
119 | rstn => rstn, | |||
|
|
120 | clk => clk, | |||
|
|
121 | virg_pos => 7, | |||
|
|
122 | coefs => coefs_v2, | |||
|
|
123 | sample_in_val => sample_in_val, | |||
|
|
124 | sample_in => sample_in, | |||
|
|
125 | sample_out_val => sample_out_val, | |||
|
|
126 | sample_out => sample_out); | |||
|
|
127 | ||||
|
|
128 | END beh; | |||
| @@ -0,0 +1,157 | |||||
|
|
1 | ------------------------------------------------------------------------------ | |||
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
|
4 | -- | |||
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
|
8 | -- (at your option) any later version. | |||
|
|
9 | -- | |||
|
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
|
13 | -- GNU General Public License for more details. | |||
|
|
14 | -- | |||
|
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
|
16 | -- along with this program; if not, write to the Free Software | |||
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
|
18 | ------------------------------------------------------------------------------- | |||
|
|
19 | -- Author : Jean-christophe Pellion | |||
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
|
21 | ------------------------------------------------------------------------------- | |||
|
|
22 | LIBRARY IEEE; | |||
|
|
23 | USE IEEE.numeric_std.ALL; | |||
|
|
24 | USE IEEE.std_logic_1164.ALL; | |||
|
|
25 | ||||
|
|
26 | LIBRARY techmap; | |||
|
|
27 | USE techmap.gencomp.ALL; | |||
|
|
28 | ||||
|
|
29 | LIBRARY lpp; | |||
|
|
30 | USE lpp.iir_filter.ALL; | |||
|
|
31 | USE lpp.FILTERcfg.ALL; | |||
|
|
32 | USE lpp.lpp_lfr_filter_coeff.ALL; | |||
|
|
33 | USE lpp.general_purpose.ALL; | |||
|
|
34 | ||||
|
|
35 | ENTITY IIR_CEL_TEST_v3 IS | |||
|
|
36 | PORT ( | |||
|
|
37 | rstn : IN STD_LOGIC; | |||
|
|
38 | clk : IN STD_LOGIC; | |||
|
|
39 | ||||
|
|
40 | sample_in1_val : IN STD_LOGIC; | |||
|
|
41 | sample_in1 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
42 | sample_in2_val : IN STD_LOGIC; | |||
|
|
43 | sample_in2 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
44 | ||||
|
|
45 | sample_out1_val : OUT STD_LOGIC; | |||
|
|
46 | sample_out1 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
47 | sample_out2_val : OUT STD_LOGIC; | |||
|
|
48 | sample_out2 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0) | |||
|
|
49 | ); | |||
|
|
50 | END IIR_CEL_TEST_v3; | |||
|
|
51 | ||||
|
|
52 | ARCHITECTURE beh OF IIR_CEL_TEST_v3 IS | |||
|
|
53 | CONSTANT ChanelCount : INTEGER := 8; | |||
|
|
54 | CONSTANT Coef_SZ : INTEGER := 9; | |||
|
|
55 | CONSTANT CoefCntPerCel : INTEGER := 6; | |||
|
|
56 | CONSTANT CoefPerCel : INTEGER := 5; | |||
|
|
57 | CONSTANT Cels_count : INTEGER := 5; | |||
|
|
58 | ||||
|
|
59 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |||
|
|
60 | ||||
|
|
61 | ||||
|
|
62 | ----------------------------------------------------------------------------- | |||
|
|
63 | CONSTANT CEL_NUMBER : INTEGER := 5; | |||
|
|
64 | CONSTANT COEFFICIENT_SIZE : INTEGER := 9; | |||
|
|
65 | CONSTANT POINT_POSITION : INTEGER := 7; | |||
|
|
66 | CONSTANT COEFFICIENT_PER_CEL : INTEGER := 5; | |||
|
|
67 | SIGNAL coeff_test : STD_LOGIC_VECTOR((CEL_NUMBER * 5 * COEFFICIENT_SIZE)-1 DOWNTO 0); | |||
|
|
68 | SIGNAL f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := | |||
|
|
69 | ( | |||
|
|
70 | (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), | |||
|
|
71 | (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), | |||
|
|
72 | (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), | |||
|
|
73 | (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), | |||
|
|
74 | (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) | |||
|
|
75 | ); | |||
|
|
76 | SIGNAL f0_to_f1_gain : COEFF_CEL_REAL := | |||
|
|
77 | ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); | |||
|
|
78 | ||||
|
|
79 | SUBTYPE COEFFICIENT IS STD_LOGIC_VECTOR(COEFFICIENT_SIZE-1 DOWNTO 0); | |||
|
|
80 | TYPE COEFFICIENT_CEL IS ARRAY (1 TO 5) OF COEFFICIENT; | |||
|
|
81 | TYPE COEFFICIENT_GLOBAL IS ARRAY (INTEGER RANGE <>) OF COEFFICIENT_CEL; | |||
|
|
82 | ||||
|
|
83 | SIGNAL coeff_test_2 : COEFFICIENT_GLOBAL(1 TO 5); | |||
|
|
84 | ----------------------------------------------------------------------------- | |||
|
|
85 | SIGNAL f_to_f0_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := | |||
|
|
86 | ( | |||
|
|
87 | (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), | |||
|
|
88 | (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), | |||
|
|
89 | (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), | |||
|
|
90 | (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), | |||
|
|
91 | (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) | |||
|
|
92 | ); | |||
|
|
93 | SIGNAL f_to_f0_gain : COEFF_CEL_REAL := | |||
|
|
94 | ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); | |||
|
|
95 | ||||
|
|
96 | BEGIN -- beh | |||
|
|
97 | ||||
|
|
98 | coeff_test <= | |||
|
|
99 | get_IIR_CEL_FILTER_CONFIG( | |||
|
|
100 | COEFFICIENT_SIZE, POINT_POSITION, CEL_NUMBER, | |||
|
|
101 | f0_to_f1_sos, f0_to_f1_gain); | |||
|
|
102 | ||||
|
|
103 | all_cel: FOR I IN 0 TO 4 GENERATE | |||
|
|
104 | all_coeff: FOR J IN 0 TO 4 GENERATE | |||
|
|
105 | coeff_test_2(I+1)(J+1) <= | |||
|
|
106 | coeff_test((I*5+J+1)*COEFFICIENT_SIZE-1 DOWNTO (I*5+J)*COEFFICIENT_SIZE); | |||
|
|
107 | END GENERATE all_coeff; | |||
|
|
108 | END GENERATE all_cel; | |||
|
|
109 | ||||
|
|
110 | ||||
|
|
111 | coefs_v2 <= CoefsInitValCst_v2; | |||
|
|
112 | ||||
|
|
113 | --IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |||
|
|
114 | -- GENERIC MAP ( | |||
|
|
115 | -- tech => 0, | |||
|
|
116 | -- Mem_use => use_CEL, -- use_RAM | |||
|
|
117 | -- Sample_SZ => 18, | |||
|
|
118 | -- Coef_SZ => Coef_SZ, | |||
|
|
119 | -- Coef_Nb => 25, | |||
|
|
120 | -- Coef_sel_SZ => 5, | |||
|
|
121 | -- Cels_count => Cels_count, | |||
|
|
122 | -- ChanelsCount => ChanelCount) | |||
|
|
123 | -- PORT MAP ( | |||
|
|
124 | -- rstn => rstn, | |||
|
|
125 | -- clk => clk, | |||
|
|
126 | -- virg_pos => 7, | |||
|
|
127 | -- coefs => coefs_v2, | |||
|
|
128 | -- sample_in_val => sample_in_val, | |||
|
|
129 | -- sample_in => sample_in, | |||
|
|
130 | -- sample_out_val => sample_out_val, | |||
|
|
131 | -- sample_out => sample_out); | |||
|
|
132 | ||||
|
|
133 | IIR_CEL_CTRLR_v3_1: IIR_CEL_CTRLR_v3 | |||
|
|
134 | GENERIC MAP ( | |||
|
|
135 | tech => 0, | |||
|
|
136 | Mem_use => use_CEL, | |||
|
|
137 | Sample_SZ => 18, | |||
|
|
138 | Coef_SZ => Coef_SZ, | |||
|
|
139 | Coef_Nb => 25, | |||
|
|
140 | Coef_sel_SZ => 5, | |||
|
|
141 | Cels_count => Cels_count, | |||
|
|
142 | ChanelsCount => ChanelCount) | |||
|
|
143 | PORT MAP ( | |||
|
|
144 | rstn => rstn, | |||
|
|
145 | clk => clk, | |||
|
|
146 | virg_pos => 7, | |||
|
|
147 | coefs => coefs_v2, | |||
|
|
148 | sample_in1_val => sample_in1_val, | |||
|
|
149 | sample_in1 => sample_in1, | |||
|
|
150 | sample_in2_val => sample_in2_val, | |||
|
|
151 | sample_in2 => sample_in2, | |||
|
|
152 | sample_out1_val => sample_out1_val, | |||
|
|
153 | sample_out1 => sample_out1, | |||
|
|
154 | sample_out2_val => sample_out2_val, | |||
|
|
155 | sample_out2 => sample_out2); | |||
|
|
156 | ||||
|
|
157 | END beh; | |||
| @@ -0,0 +1,53 | |||||
|
|
1 | #GRLIB=../.. | |||
|
|
2 | VHDLIB=../.. | |||
|
|
3 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |||
|
|
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |||
|
|
5 | TOP=leon3mp | |||
|
|
6 | BOARD=em-LeonLPP-A3PE3kL-v3-core1 | |||
|
|
7 | include $(GRLIB)/boards/$(BOARD)/Makefile.inc | |||
|
|
8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |||
|
|
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |||
|
|
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |||
|
|
11 | EFFORT=high | |||
|
|
12 | XSTOPT= | |||
|
|
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |||
|
|
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |||
|
|
15 | VHDLSYNFILES= | |||
|
|
16 | VHDLSIMFILES= tb.vhd | |||
|
|
17 | SIMTOP=testbench | |||
|
|
18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |||
|
|
19 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc | |||
|
|
20 | PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc | |||
|
|
21 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut | |||
|
|
22 | CLEAN=soft-clean | |||
|
|
23 | ||||
|
|
24 | TECHLIBS = proasic3e | |||
|
|
25 | ||||
|
|
26 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |||
|
|
27 | tmtc openchip hynix ihp gleichmann micron usbhc | |||
|
|
28 | ||||
|
|
29 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |||
|
|
30 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ | |||
|
|
31 | ./amba_lcd_16x2_ctrlr \ | |||
|
|
32 | ./general_purpose/lpp_AMR \ | |||
|
|
33 | ./general_purpose/lpp_balise \ | |||
|
|
34 | ./general_purpose/lpp_delay \ | |||
|
|
35 | ./lpp_bootloader \ | |||
|
|
36 | ./lpp_cna \ | |||
|
|
37 | ./lpp_uart \ | |||
|
|
38 | ./lpp_usb \ | |||
|
|
39 | ./dsp/lpp_fft_rtax \ | |||
|
|
40 | ||||
|
|
41 | FILESKIP = i2cmst.vhd \ | |||
|
|
42 | APB_MULTI_DIODE.vhd \ | |||
|
|
43 | APB_MULTI_DIODE.vhd \ | |||
|
|
44 | Top_MatrixSpec.vhd \ | |||
|
|
45 | APB_FFT.vhd \ | |||
|
|
46 | lpp_lfr_apbreg.vhd \ | |||
|
|
47 | CoreFFT.vhd | |||
|
|
48 | ||||
|
|
49 | include $(GRLIB)/bin/Makefile | |||
|
|
50 | include $(GRLIB)/software/leon3/Makefile | |||
|
|
51 | ||||
|
|
52 | ################## project specific targets ########################## | |||
|
|
53 | ||||
| @@ -0,0 +1,20 | |||||
|
|
1 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/iir_filter.vhd | |||
|
|
2 | ||||
|
|
3 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd | |||
|
|
4 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd | |||
|
|
5 | ||||
|
|
6 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd | |||
|
|
7 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd | |||
|
|
8 | ||||
|
|
9 | vcom -quiet -93 -work work IIR_CEL_TEST.vhd | |||
|
|
10 | vcom -quiet -93 -work work IIR_CEL_TEST_v3.vhd | |||
|
|
11 | vcom -quiet -93 -work work tb.vhd | |||
|
|
12 | ||||
|
|
13 | vsim work.testbench | |||
|
|
14 | ||||
|
|
15 | log -r * | |||
|
|
16 | ||||
|
|
17 | do wave.do | |||
|
|
18 | ||||
|
|
19 | run -all | |||
|
|
20 | ||||
| @@ -0,0 +1,12 | |||||
|
|
1 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_pkg.vhd | |||
|
|
2 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd | |||
|
|
3 | ||||
|
|
4 | vcom -quiet -93 -work work tb_cic_lfr_add_sub.vhd | |||
|
|
5 | ||||
|
|
6 | vsim work.testbench | |||
|
|
7 | ||||
|
|
8 | log -r * | |||
|
|
9 | ||||
|
|
10 | do wave_add_sub.do | |||
|
|
11 | ||||
|
|
12 | run -all | |||
| @@ -0,0 +1,10 | |||||
|
|
1 | vcom -quiet -93 -work work tb_calc.vhd | |||
|
|
2 | ||||
|
|
3 | vsim work.testbench | |||
|
|
4 | ||||
|
|
5 | log -r * | |||
|
|
6 | ||||
|
|
7 | do wave_calc.do | |||
|
|
8 | ||||
|
|
9 | run -all | |||
|
|
10 | ||||
| @@ -0,0 +1,10 | |||||
|
|
1 | vcom -quiet -93 -work work tb_calc.vhd | |||
|
|
2 | ||||
|
|
3 | vsim work.testbench | |||
|
|
4 | ||||
|
|
5 | log -r * | |||
|
|
6 | ||||
|
|
7 | do wave_calc.do | |||
|
|
8 | ||||
|
|
9 | run -all | |||
|
|
10 | ||||
| @@ -0,0 +1,262 | |||||
|
|
1 | ||||
|
|
2 | LIBRARY ieee; | |||
|
|
3 | USE ieee.std_logic_1164.ALL; | |||
|
|
4 | USE IEEE.MATH_REAL.ALL; | |||
|
|
5 | USE ieee.numeric_std.ALL; | |||
|
|
6 | ||||
|
|
7 | LIBRARY techmap; | |||
|
|
8 | USE techmap.gencomp.ALL; | |||
|
|
9 | ||||
|
|
10 | LIBRARY lpp; | |||
|
|
11 | USE lpp.iir_filter.ALL; | |||
|
|
12 | USE lpp.lpp_ad_conv.ALL; | |||
|
|
13 | USE lpp.FILTERcfg.ALL; | |||
|
|
14 | USE lpp.lpp_lfr_filter_coeff.ALL; | |||
|
|
15 | USE lpp.general_purpose.ALL; | |||
|
|
16 | USE lpp.data_type_pkg.ALL; | |||
|
|
17 | USE lpp.chirp_pkg.ALL; | |||
|
|
18 | USE lpp.lpp_lfr_pkg.ALL; | |||
|
|
19 | USE lpp.general_purpose.ALL; | |||
|
|
20 | ||||
|
|
21 | ENTITY testbench IS | |||
|
|
22 | END; | |||
|
|
23 | ||||
|
|
24 | ARCHITECTURE behav OF testbench IS | |||
|
|
25 | ||||
|
|
26 | COMPONENT IIR_CEL_TEST | |||
|
|
27 | PORT ( | |||
|
|
28 | rstn : IN STD_LOGIC; | |||
|
|
29 | clk : IN STD_LOGIC; | |||
|
|
30 | sample_in_val : IN STD_LOGIC; | |||
|
|
31 | sample_in : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
32 | sample_out_val : OUT STD_LOGIC; | |||
|
|
33 | sample_out : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0)); | |||
|
|
34 | END COMPONENT; | |||
|
|
35 | ||||
|
|
36 | COMPONENT IIR_CEL_TEST_v3 | |||
|
|
37 | PORT ( | |||
|
|
38 | rstn : IN STD_LOGIC; | |||
|
|
39 | clk : IN STD_LOGIC; | |||
|
|
40 | sample_in1_val : IN STD_LOGIC; | |||
|
|
41 | sample_in1 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
42 | sample_in2_val : IN STD_LOGIC; | |||
|
|
43 | sample_in2 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
44 | sample_out1_val : OUT STD_LOGIC; | |||
|
|
45 | sample_out1 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
46 | sample_out2_val : OUT STD_LOGIC; | |||
|
|
47 | sample_out2 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0)); | |||
|
|
48 | END COMPONENT; | |||
|
|
49 | ||||
|
|
50 | SIGNAL clk : STD_LOGIC := '0'; | |||
|
|
51 | SIGNAL clk_24k : STD_LOGIC := '0'; | |||
|
|
52 | SIGNAL clk_24k_r : STD_LOGIC := '0'; | |||
|
|
53 | SIGNAL rstn : STD_LOGIC; | |||
|
|
54 | ||||
|
|
55 | SIGNAL sample : Samples(7 DOWNTO 0); | |||
|
|
56 | SIGNAL sample_val : STD_LOGIC; | |||
|
|
57 | SIGNAL sample_val_2 : STD_LOGIC; | |||
|
|
58 | ||||
|
|
59 | SIGNAL data_chirp : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
60 | SIGNAL data_chirp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
61 | ||||
|
|
62 | SIGNAL sample_s : samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
63 | SIGNAL sample_out_s : samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
64 | SIGNAL sample_out_s2 : samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
65 | SIGNAL sample_out_val : STD_LOGIC; | |||
|
|
66 | ||||
|
|
67 | ||||
|
|
68 | SIGNAL sample_out1_val : STD_LOGIC; | |||
|
|
69 | SIGNAL sample_out2_val : STD_LOGIC; | |||
|
|
70 | SIGNAL sample_out1 : samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
71 | SIGNAL sample_out2 : samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
72 | SIGNAL sample_out1_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
73 | SIGNAL sample_out2_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
74 | ||||
|
|
75 | SIGNAL sample_s_v3 : samplT(7 DOWNTO 0, 17 DOWNTO 0); | |||
|
|
76 | SIGNAL sample_val_v3 : STD_LOGIC; | |||
|
|
77 | SIGNAL sample_val_v3_2 : STD_LOGIC; | |||
|
|
78 | ||||
|
|
79 | SIGNAL temp : STD_LOGIC; | |||
|
|
80 | BEGIN | |||
|
|
81 | ||||
|
|
82 | ----------------------------------------------------------------------------- | |||
|
|
83 | -- CLOCK and RESET | |||
|
|
84 | ----------------------------------------------------------------------------- | |||
|
|
85 | clk <= NOT clk AFTER 5 ns; | |||
|
|
86 | PROCESS | |||
|
|
87 | BEGIN -- PROCESS | |||
|
|
88 | WAIT UNTIL clk = '1'; | |||
|
|
89 | rstn <= '0'; | |||
|
|
90 | WAIT UNTIL clk = '1'; | |||
|
|
91 | WAIT UNTIL clk = '1'; | |||
|
|
92 | WAIT UNTIL clk = '1'; | |||
|
|
93 | rstn <= '1'; | |||
|
|
94 | WAIT FOR 30 ms; | |||
|
|
95 | REPORT "*** END simulation ***" SEVERITY failure; | |||
|
|
96 | WAIT; | |||
|
|
97 | END PROCESS; | |||
|
|
98 | ----------------------------------------------------------------------------- | |||
|
|
99 | ||||
|
|
100 | ||||
|
|
101 | ----------------------------------------------------------------------------- | |||
|
|
102 | -- LPP_LFR_FILTER | |||
|
|
103 | ----------------------------------------------------------------------------- | |||
|
|
104 | lpp_lfr_filter_1: lpp_lfr_filter | |||
|
|
105 | GENERIC MAP ( | |||
|
|
106 | Mem_use => use_CEL) | |||
|
|
107 | PORT MAP ( | |||
|
|
108 | sample => sample, | |||
|
|
109 | sample_val => sample_val, | |||
|
|
110 | ||||
|
|
111 | clk => clk, | |||
|
|
112 | rstn => rstn, | |||
|
|
113 | ||||
|
|
114 | data_shaping_SP0 => '0', | |||
|
|
115 | data_shaping_SP1 => '0', | |||
|
|
116 | data_shaping_R0 => '0', | |||
|
|
117 | data_shaping_R1 => '0', | |||
|
|
118 | data_shaping_R2 => '0', | |||
|
|
119 | ||||
|
|
120 | sample_f0_val => OPEN, | |||
|
|
121 | sample_f1_val => OPEN, | |||
|
|
122 | sample_f2_val => OPEN, | |||
|
|
123 | sample_f3_val => OPEN, | |||
|
|
124 | sample_f0_wdata => OPEN, | |||
|
|
125 | sample_f1_wdata => OPEN, | |||
|
|
126 | sample_f2_wdata => OPEN, | |||
|
|
127 | sample_f3_wdata => OPEN); | |||
|
|
128 | ----------------------------------------------------------------------------- | |||
|
|
129 | ||||
|
|
130 | ||||
|
|
131 | ----------------------------------------------------------------------------- | |||
|
|
132 | -- SAMPLE GENERATION | |||
|
|
133 | ----------------------------------------------------------------------------- | |||
|
|
134 | clk_24k <= NOT clk_24k AFTER 20345 ns; | |||
|
|
135 | ||||
|
|
136 | PROCESS (clk, rstn) | |||
|
|
137 | BEGIN -- PROCESS | |||
|
|
138 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
139 | sample_val <= '0'; | |||
|
|
140 | sample_val_2 <= '0'; | |||
|
|
141 | clk_24k_r <= '0'; | |||
|
|
142 | temp <= '0'; | |||
|
|
143 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
144 | clk_24k_r <= clk_24k; | |||
|
|
145 | IF clk_24k = '1' AND clk_24k_r = '0' THEN | |||
|
|
146 | sample_val <= '1'; | |||
|
|
147 | sample_val_2 <= temp; | |||
|
|
148 | temp <= NOT temp; | |||
|
|
149 | ELSE | |||
|
|
150 | sample_val <= '0'; | |||
|
|
151 | sample_val_2 <= '0'; | |||
|
|
152 | END IF; | |||
|
|
153 | END IF; | |||
|
|
154 | END PROCESS; | |||
|
|
155 | ----------------------------------------------------------------------------- | |||
|
|
156 | chirp_1: chirp | |||
|
|
157 | GENERIC MAP ( | |||
|
|
158 | LOW_FREQUENCY_LIMIT => 0, | |||
|
|
159 | HIGH_FREQUENCY_LIMIT => 2000, | |||
|
|
160 | NB_POINT_TO_GEN => 10000, | |||
|
|
161 | AMPLITUDE => 100, | |||
|
|
162 | NB_BITS => 16) | |||
|
|
163 | PORT MAP ( | |||
|
|
164 | clk => clk, | |||
|
|
165 | rstn => rstn, | |||
|
|
166 | run => '1', | |||
|
|
167 | data_ack => sample_val, | |||
|
|
168 | data => data_chirp); | |||
|
|
169 | ||||
|
|
170 | chirp_2: chirp | |||
|
|
171 | GENERIC MAP ( | |||
|
|
172 | LOW_FREQUENCY_LIMIT => 0, | |||
|
|
173 | HIGH_FREQUENCY_LIMIT => 2000, | |||
|
|
174 | NB_POINT_TO_GEN => 100000, | |||
|
|
175 | AMPLITUDE => 200, | |||
|
|
176 | NB_BITS => 16) | |||
|
|
177 | PORT MAP ( | |||
|
|
178 | clk => clk, | |||
|
|
179 | rstn => rstn, | |||
|
|
180 | run => '1', | |||
|
|
181 | data_ack => sample_val, | |||
|
|
182 | data => data_chirp_2); | |||
|
|
183 | ||||
|
|
184 | all_channel: FOR I IN 0 TO 3 GENERATE | |||
|
|
185 | sample(2*I) <= data_chirp; | |||
|
|
186 | sample(2*I+1) <= data_chirp_2; | |||
|
|
187 | END GENERATE all_channel; | |||
|
|
188 | ----------------------------------------------------------------------------- | |||
|
|
189 | ||||
|
|
190 | all_channel_test: FOR I IN 0 TO 3 GENERATE | |||
|
|
191 | all_bit_test: FOR J IN 0 TO 15 GENERATE | |||
|
|
192 | sample_s(2*I ,J) <= data_chirp(J); | |||
|
|
193 | sample_s(2*I+1,J) <= data_chirp_2(J); | |||
|
|
194 | END GENERATE all_bit_test; | |||
|
|
195 | sample_s(2*I,16) <= data_chirp(15); | |||
|
|
196 | sample_s(2*I,17) <= data_chirp(15); | |||
|
|
197 | sample_s(2*I+1,16) <= data_chirp_2(15); | |||
|
|
198 | sample_s(2*I+1,17) <= data_chirp_2(15); | |||
|
|
199 | END GENERATE all_channel_test; | |||
|
|
200 | ||||
|
|
201 | IIR_CEL_TEST_1: IIR_CEL_TEST | |||
|
|
202 | PORT MAP ( | |||
|
|
203 | rstn => rstn, | |||
|
|
204 | clk => clk, | |||
|
|
205 | sample_in_val => sample_val, | |||
|
|
206 | sample_in => sample_s, | |||
|
|
207 | sample_out_val => sample_out_val, | |||
|
|
208 | sample_out => sample_out_s); | |||
|
|
209 | ||||
|
|
210 | PROCESS (clk, rstn) | |||
|
|
211 | BEGIN -- PROCESS | |||
|
|
212 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
213 | all_channel: FOR I IN 0 TO 7 LOOP | |||
|
|
214 | all_bit: FOR J IN 0 TO 17 LOOP | |||
|
|
215 | sample_out_s2(I,J) <= '0'; | |||
|
|
216 | END LOOP all_bit; | |||
|
|
217 | END LOOP all_channel; | |||
|
|
218 | ||||
|
|
219 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
220 | IF sample_out_val = '1' THEN | |||
|
|
221 | sample_out_s2 <= sample_out_s; | |||
|
|
222 | END IF; | |||
|
|
223 | END IF; | |||
|
|
224 | END PROCESS; | |||
|
|
225 | ----------------------------------------------------------------------------- | |||
|
|
226 | IIR_CEL_TEST_v3_1: IIR_CEL_TEST_v3 | |||
|
|
227 | PORT MAP ( | |||
|
|
228 | rstn => rstn, | |||
|
|
229 | clk => clk, | |||
|
|
230 | sample_in1_val => sample_val_v3, | |||
|
|
231 | sample_in1 => sample_s_v3, | |||
|
|
232 | sample_in2_val => sample_val_v3_2, | |||
|
|
233 | sample_in2 => sample_s_v3, | |||
|
|
234 | sample_out1_val => sample_out1_val, | |||
|
|
235 | sample_out1 => sample_out1, | |||
|
|
236 | sample_out2_val => sample_out2_val, | |||
|
|
237 | sample_out2 => sample_out2); | |||
|
|
238 | ||||
|
|
239 | PROCESS (clk, rstn) | |||
|
|
240 | BEGIN -- PROCESS | |||
|
|
241 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
242 | ||||
|
|
243 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
244 | IF sample_val = '1' THEN | |||
|
|
245 | sample_s_v3 <= sample_s; | |||
|
|
246 | END IF; | |||
|
|
247 | sample_val_v3 <= sample_val; | |||
|
|
248 | sample_val_v3_2 <= sample_val_2; | |||
|
|
249 | ||||
|
|
250 | IF sample_out1_val = '1' THEN | |||
|
|
251 | sample_out1_reg <= sample_out1; | |||
|
|
252 | END IF; | |||
|
|
253 | IF sample_out2_val = '1' THEN | |||
|
|
254 | sample_out2_reg <= sample_out2; | |||
|
|
255 | END IF; | |||
|
|
256 | END IF; | |||
|
|
257 | ||||
|
|
258 | END PROCESS; | |||
|
|
259 | ||||
|
|
260 | ||||
|
|
261 | ||||
|
|
262 | END; | |||
| @@ -0,0 +1,124 | |||||
|
|
1 | LIBRARY ieee; | |||
|
|
2 | USE ieee.std_logic_1164.ALL; | |||
|
|
3 | USE ieee.numeric_std.ALL; | |||
|
|
4 | ||||
|
|
5 | LIBRARY lpp; | |||
|
|
6 | USE lpp.cic_pkg.ALL; | |||
|
|
7 | USE lpp.data_type_pkg.ALL; | |||
|
|
8 | USE lpp.chirp_pkg.ALL; | |||
|
|
9 | ||||
|
|
10 | ENTITY testbench IS | |||
|
|
11 | END; | |||
|
|
12 | ||||
|
|
13 | ARCHITECTURE behav OF testbench IS | |||
|
|
14 | ||||
|
|
15 | SIGNAL clk : STD_LOGIC := '0'; | |||
|
|
16 | SIGNAL rstn : STD_LOGIC; | |||
|
|
17 | ||||
|
|
18 | CONSTANT VECTOR_SIZE : INTEGER := 4*2; | |||
|
|
19 | SIGNAL VECTOR_1 : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
20 | SIGNAL VECTOR_MIN : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
21 | SIGNAL VECTOR_MAX : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
22 | ||||
|
|
23 | SIGNAL all_done : STD_LOGIC; | |||
|
|
24 | SIGNAL all_ok : STD_LOGIC; | |||
|
|
25 | SIGNAL all_ok_E : STD_LOGIC; | |||
|
|
26 | ||||
|
|
27 | SIGNAL A : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
28 | SIGNAL B : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
29 | ||||
|
|
30 | SIGNAL C : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
31 | ||||
|
|
32 | SIGNAL D_0 : STD_LOGIC_VECTOR(VECTOR_SIZE/2 DOWNTO 0); | |||
|
|
33 | SIGNAL D_1 : STD_LOGIC_VECTOR(VECTOR_SIZE/2-1 DOWNTO 0); | |||
|
|
34 | SIGNAL D : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
35 | ||||
|
|
36 | SIGNAL E : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
37 | ||||
|
|
38 | ||||
|
|
39 | BEGIN | |||
|
|
40 | VECTOR_1(0) <= '1'; | |||
|
|
41 | VECTOR_1(VECTOR_SIZE-1 DOWNTO 1) <= (OTHERS => '0') ; | |||
|
|
42 | ||||
|
|
43 | VECTOR_MIN(VECTOR_SIZE-1) <= '1'; | |||
|
|
44 | VECTOR_MIN(VECTOR_SIZE-2 DOWNTO 0) <= (OTHERS => '0') ; | |||
|
|
45 | VECTOR_MAX(VECTOR_SIZE-1) <= '0'; | |||
|
|
46 | VECTOR_MAX(VECTOR_SIZE-2 DOWNTO 0) <= (OTHERS => '1') ; | |||
|
|
47 | ||||
|
|
48 | clk <= NOT clk AFTER 5 ns; | |||
|
|
49 | ||||
|
|
50 | PROCESSD_0(VECTOR_SIZE/2) | |||
|
|
51 | BEGIN -- PROCESS | |||
|
|
52 | WAIT UNTIL clk = '1'; | |||
|
|
53 | rstn <= '0'; | |||
|
|
54 | WAIT UNTIL clk = '1'; | |||
|
|
55 | rstn <= '1'; | |||
|
|
56 | WAIT UNTIL clk = '1'; | |||
|
|
57 | ||||
|
|
58 | ||||
|
|
59 | WAIT FOR 2 ms; | |||
|
|
60 | REPORT "*** END simulation ***" SEVERITY failure; | |||
|
|
61 | WAIT; | |||
|
|
62 | END PROCESS; | |||
|
|
63 | ||||
|
|
64 | PROCESS (clk, rstn) | |||
|
|
65 | BEGIN -- PROCESS | |||
|
|
66 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
67 | A <= VECTOR_MIN; | |||
|
|
68 | B <= VECTOR_MIN; | |||
|
|
69 | all_done <= '0'; | |||
|
|
70 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
71 | all_done <= '0'; | |||
|
|
72 | IF A = VECTOR_MAX THEN | |||
|
|
73 | A <= VECTOR_MIN; | |||
|
|
74 | IF B = VECTOR_MAX THEN | |||
|
|
75 | B <= VECTOR_MIN; | |||
|
|
76 | all_done <= '1'; | |||
|
|
77 | ELSE | |||
|
|
78 | B <= STD_LOGIC_VECTOR(signed(B) + signed(VECTOR_1)); | |||
|
|
79 | END IF; | |||
|
|
80 | ELSE | |||
|
|
81 | A <= STD_LOGIC_VECTOR(signed(A) + signed(VECTOR_1)); | |||
|
|
82 | END IF; | |||
|
|
83 | END IF; | |||
|
|
84 | END PROCESS; | |||
|
|
85 | ||||
|
|
86 | ||||
|
|
87 | C <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B)); | |||
|
|
88 | ||||
|
|
89 | E <= STD_LOGIC_VECTOR(UNSIGNED(A) - UNSIGNED(B)); | |||
|
|
90 | ||||
|
|
91 | ||||
|
|
92 | ||||
|
|
93 | ||||
|
|
94 | D_0 <= STD_LOGIC_VECTOR(SIGNED('0'&A(VECTOR_SIZE/2-1 DOWNTO 0)) - SIGNED('0' & B(VECTOR_SIZE/2-1 DOWNTO 0))); | |||
|
|
95 | ||||
|
|
96 | D_1 <= STD_LOGIC_VECTOR( SIGNED(A(VECTOR_SIZE-1 DOWNTO VECTOR_SIZE/2)) | |||
|
|
97 | - SIGNED(B(VECTOR_SIZE-1 DOWNTO VECTOR_SIZE/2)) | |||
|
|
98 | - SIGNED(VECTOR_1(VECTOR_SIZE/2-1 DOWNTO 1) & D_0(VECTOR_SIZE/2) )); | |||
|
|
99 | ||||
|
|
100 | D <= D_1(VECTOR_SIZE/2-1 DOWNTO 0) & D_0(VECTOR_SIZE/2-1 DOWNTO 0); | |||
|
|
101 | ||||
|
|
102 | ||||
|
|
103 | PROCESS (clk, rstn) | |||
|
|
104 | BEGIN -- PROCESS | |||
|
|
105 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
106 | all_ok <= '1'; | |||
|
|
107 | all_ok_E <= '1'; | |||
|
|
108 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
109 | IF D = C THEN | |||
|
|
110 | all_ok <= '1'; | |||
|
|
111 | ELSE | |||
|
|
112 | all_ok <= '0'; | |||
|
|
113 | END IF; | |||
|
|
114 | ||||
|
|
115 | IF E = C THEN | |||
|
|
116 | all_ok_E <= '1'; | |||
|
|
117 | ELSE | |||
|
|
118 | all_ok_E <= '0'; | |||
|
|
119 | END IF; | |||
|
|
120 | END IF; | |||
|
|
121 | END PROCESS; | |||
|
|
122 | ||||
|
|
123 | END; | |||
|
|
124 | ||||
| @@ -0,0 +1,173 | |||||
|
|
1 | ||||
|
|
2 | LIBRARY ieee; | |||
|
|
3 | USE ieee.std_logic_1164.ALL; | |||
|
|
4 | USE IEEE.MATH_REAL.ALL; | |||
|
|
5 | USE ieee.numeric_std.ALL; | |||
|
|
6 | ||||
|
|
7 | LIBRARY lpp; | |||
|
|
8 | USE lpp.cic_pkg.ALL; | |||
|
|
9 | USE lpp.data_type_pkg.ALL; | |||
|
|
10 | USE lpp.chirp_pkg.ALL; | |||
|
|
11 | ||||
|
|
12 | ENTITY testbench IS | |||
|
|
13 | ||||
|
|
14 | END; | |||
|
|
15 | ||||
|
|
16 | ARCHITECTURE behav OF testbench IS | |||
|
|
17 | ||||
|
|
18 | SIGNAL clk : STD_LOGIC := '0'; | |||
|
|
19 | SIGNAL clk_24k : STD_LOGIC := '0'; | |||
|
|
20 | SIGNAL clk_24k_r : STD_LOGIC := '0'; | |||
|
|
21 | SIGNAL rstn : STD_LOGIC; | |||
|
|
22 | SIGNAL run : STD_LOGIC; | |||
|
|
23 | SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
24 | SIGNAL data_in_v : sample_vector(5 DOWNTO 0,15 DOWNTO 0); | |||
|
|
25 | SIGNAL data_in_valid : STD_LOGIC; | |||
|
|
26 | ----------------------------------------------------------------------------- | |||
|
|
27 | CONSTANT CARRY : STD_LOGIC := '1'; | |||
|
|
28 | CONSTANT CARRY_NO : STD_LOGIC := '0'; | |||
|
|
29 | CONSTANT ADD : STD_LOGIC := '0'; | |||
|
|
30 | CONSTANT SUB : STD_LOGIC := '1'; | |||
|
|
31 | SIGNAL OP : STD_LOGIC; | |||
|
|
32 | SIGNAL OP_0 : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
33 | SIGNAL OP_1 : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
34 | SIGNAL data_out_verif : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
35 | SIGNAL data_out_verif_s : STD_LOGIC_VECTOR(32 DOWNTO 0); | |||
|
|
36 | SIGNAL data_in_A_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
37 | SIGNAL data_in_B_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
38 | SIGNAL data_in_A : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
39 | SIGNAL data_in_B : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
40 | SIGNAL data_out_s : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
41 | SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
42 | SIGNAL data_out_pre : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
43 | SIGNAL data_out_diff : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
44 | SIGNAL data_out_Carry : STD_LOGIC; | |||
|
|
45 | ||||
|
|
46 | SIGNAL COUNTER_A : INTEGER; | |||
|
|
47 | SIGNAL COUNTER_B : INTEGER; | |||
|
|
48 | CONSTANT COUNTER_MIN : INTEGER := INTEGER'LOW; | |||
|
|
49 | CONSTANT COUNTER_MAX : INTEGER := INTEGER'HIGH; | |||
|
|
50 | CONSTANT COUNTER_STEP : INTEGER := INTEGER'HIGH/100; | |||
|
|
51 | ||||
|
|
52 | SIGNAL ALL_is_OK : STD_LOGIC; | |||
|
|
53 | BEGIN | |||
|
|
54 | ||||
|
|
55 | clk <= NOT clk AFTER 5 ns; | |||
|
|
56 | ||||
|
|
57 | ----------------------------------------------------------------------------- | |||
|
|
58 | PROCESS | |||
|
|
59 | BEGIN -- PROCESS | |||
|
|
60 | WAIT UNTIL clk = '1'; | |||
|
|
61 | rstn <= '0'; | |||
|
|
62 | run <= '0'; | |||
|
|
63 | WAIT UNTIL clk = '1'; | |||
|
|
64 | rstn <= '1'; | |||
|
|
65 | WAIT UNTIL clk = '1'; | |||
|
|
66 | WAIT UNTIL clk = '1'; | |||
|
|
67 | run <= '1'; | |||
|
|
68 | WAIT UNTIL clk = '1'; | |||
|
|
69 | OP <= ADD; | |||
|
|
70 | WAIT FOR 500 us; | |||
|
|
71 | OP <= SUB; | |||
|
|
72 | WAIT FOR 500 us; | |||
|
|
73 | REPORT "*** END simulation ***" SEVERITY failure; | |||
|
|
74 | WAIT; | |||
|
|
75 | END PROCESS; | |||
|
|
76 | ||||
|
|
77 | PROCESS (clk, rstn) | |||
|
|
78 | BEGIN -- PROCESS | |||
|
|
79 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
80 | COUNTER_A <= COUNTER_MIN; | |||
|
|
81 | COUNTER_B <= COUNTER_MIN; | |||
|
|
82 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
83 | IF COUNTER_A < COUNTER_MAX - COUNTER_STEP THEN | |||
|
|
84 | COUNTER_A <= COUNTER_A + COUNTER_STEP; | |||
|
|
85 | ELSE | |||
|
|
86 | COUNTER_A <= COUNTER_MIN; | |||
|
|
87 | IF COUNTER_B < COUNTER_MAX - COUNTER_STEP THEN | |||
|
|
88 | COUNTER_B <= COUNTER_B + COUNTER_STEP; | |||
|
|
89 | ELSE | |||
|
|
90 | COUNTER_B <= COUNTER_MIN; | |||
|
|
91 | END IF; | |||
|
|
92 | END IF; | |||
|
|
93 | END IF; | |||
|
|
94 | END PROCESS; | |||
|
|
95 | ||||
|
|
96 | data_in_A <= STD_LOGIC_VECTOR(to_signed(COUNTER_A,32)); | |||
|
|
97 | data_in_B <= STD_LOGIC_VECTOR(to_signed(COUNTER_B,32)); | |||
|
|
98 | ||||
|
|
99 | ----------------------------------------------------------------------------- | |||
|
|
100 | OP_0 <= CARRY_NO & OP; | |||
|
|
101 | OP_1 <= CARRY & OP; | |||
|
|
102 | cic_lfr_add_sub_1: cic_lfr_add_sub | |||
|
|
103 | PORT MAP ( | |||
|
|
104 | clk => clk, | |||
|
|
105 | rstn => rstn, | |||
|
|
106 | run => run, | |||
|
|
107 | OP => OP_0, | |||
|
|
108 | data_in_A => data_in_A(15 DOWNTO 0), | |||
|
|
109 | data_in_B => data_in_B(15 DOWNTO 0), | |||
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110 | data_in_Carry => '0', | |||
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111 | data_out => data_out_s, | |||
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112 | data_out_Carry => data_out_Carry); | |||
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113 | ||||
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114 | PROCESS (clk, rstn) | |||
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115 | BEGIN -- PROCESS | |||
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116 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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117 | data_in_A_reg <= (OTHERS => '0'); | |||
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118 | data_in_B_reg <= (OTHERS => '0'); | |||
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119 | data_out(15 DOWNTO 0) <= (OTHERS => '0'); | |||
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120 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
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121 | data_in_A_reg <= data_in_A; | |||
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122 | data_in_B_reg <= data_in_B; | |||
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123 | data_out(15 DOWNTO 0) <= data_out_s; | |||
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124 | END IF; | |||
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125 | END PROCESS; | |||
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126 | ||||
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127 | cic_lfr_add_sub_2: cic_lfr_add_sub | |||
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128 | PORT MAP ( | |||
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129 | clk => clk, | |||
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130 | rstn => rstn, | |||
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131 | run => run, | |||
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132 | OP => OP_1, | |||
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133 | data_in_A => data_in_A_reg(31 DOWNTO 16), | |||
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134 | data_in_B => data_in_B_reg(31 DOWNTO 16), | |||
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135 | data_in_Carry => data_out_Carry, | |||
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136 | data_out => data_out(31 DOWNTO 16), | |||
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137 | data_out_Carry => OPEN); | |||
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138 | ----------------------------------------------------------------------------- | |||
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139 | data_out_verif_s <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_in_A_reg)) + to_integer(SIGNED(data_in_B_reg)),33)) WHEN OP = ADD ELSE | |||
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140 | STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_in_A_reg)) - to_integer(SIGNED(data_in_B_reg)),33)); | |||
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141 | PROCESS (clk, rstn) | |||
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142 | BEGIN -- PROCESS | |||
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143 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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144 | data_out_verif <= (OTHERS => '0'); | |||
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145 | ALL_is_OK <= '0'; | |||
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146 | data_out_pre <= (OTHERS => '0'); | |||
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147 | data_out_diff <= (OTHERS => '0'); | |||
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148 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
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149 | data_out_verif <= data_out_verif_s(31 DOWNTO 0); | |||
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150 | IF data_out_verif = data_out THEN | |||
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151 | ALL_is_OK <= '1'; | |||
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152 | ELSE | |||
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153 | ALL_is_OK <= '0'; | |||
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154 | END IF; | |||
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155 | ------------------------------------------------------------------------- | |||
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156 | data_out_pre <= data_out; | |||
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157 | IF OP = ADD THEN | |||
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158 | data_out_diff <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_out)) - to_integer(SIGNED(data_out_pre) ),32)); | |||
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159 | ELSE | |||
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160 | data_out_diff <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_out)) - to_integer(SIGNED(data_out_pre) ),32)); | |||
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161 | END IF; | |||
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162 | END IF; | |||
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163 | END PROCESS; | |||
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164 | ----------------------------------------------------------------------------- | |||
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165 | ||||
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166 | ||||
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167 | ||||
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168 | ||||
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169 | ||||
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170 | ||||
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171 | ||||
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172 | ||||
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173 | END; | |||
| @@ -0,0 +1,77 | |||||
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1 | onerror {resume} | |||
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|
2 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(15 downto 0)} DATA_F0_0 | |||
|
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3 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(31 downto 16)} dATa_F0_1 | |||
|
|
4 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(47 downto 32)} DATA_F0_2 | |||
|
|
5 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(63 downto 48)} DATA_F0_3 | |||
|
|
6 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(79 downto 63)} DATA_F0_4 | |||
|
|
7 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(95 downto 80)} DATA_F0_5 | |||
|
|
8 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(79 downto 64)} DATA_F0_4001 | |||
|
|
9 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(15 downto 0)} DATA_F1_0 | |||
|
|
10 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(31 downto 16)} DATA_F1_1 | |||
|
|
11 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(47 downto 31)} DATA_F1_2 | |||
|
|
12 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(63 downto 48)} DATA_F1_3 | |||
|
|
13 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(79 downto 64)} DATA_F1_4 | |||
|
|
14 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(95 downto 81)} DATA_F1_5 | |||
|
|
15 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(95 downto 80)} DATA_F1_5001 | |||
|
|
16 | quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(47 downto 32)} DATA_F1_2001 | |||
|
|
17 | quietly virtual signal -install /testbench/IIR_CEL_TEST_1 { /testbench/IIR_CEL_TEST_1/coeff_test(9 downto 0)} b0_2 | |||
|
|
18 | quietly virtual signal -install /testbench/IIR_CEL_TEST_1 { /testbench/IIR_CEL_TEST_1/coeff_test(19 downto 10)} b0_1 | |||
|
|
19 | quietly virtual signal -install /testbench/IIR_CEL_TEST_1 { /testbench/IIR_CEL_TEST_1/coeff_test(29 downto 20)} b0_0 | |||
|
|
20 | quietly virtual signal -install /testbench/IIR_CEL_TEST_1 { /testbench/IIR_CEL_TEST_1/coeff_test(39 downto 30)} a0_2 | |||
|
|
21 | quietly virtual signal -install /testbench/IIR_CEL_TEST_1 { /testbench/IIR_CEL_TEST_1/coeff_test(49 downto 40)} a0_1 | |||
|
|
22 | quietly WaveActivateNextPane {} 0 | |||
|
|
23 | add wave -noupdate -group INPUT /testbench/lpp_lfr_filter_1/sample | |||
|
|
24 | add wave -noupdate -group INPUT /testbench/lpp_lfr_filter_1/sample_val | |||
|
|
25 | add wave -noupdate -group OUTPUT /testbench/lpp_lfr_filter_1/sample_f2_wdata | |||
|
|
26 | add wave -noupdate -group OUTPUT /testbench/lpp_lfr_filter_1/sample_f2_val | |||
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27 | add wave -noupdate -group OUTPUT /testbench/lpp_lfr_filter_1/sample_f3_wdata | |||
|
|
28 | add wave -noupdate -group OUTPUT /testbench/lpp_lfr_filter_1/sample_f3_val | |||
|
|
29 | add wave -noupdate -group OUTPUT -group F0 /testbench/lpp_lfr_filter_1/sample_f0_val | |||
|
|
30 | add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_0 -max 84.0 -min -97.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F0_0 | |||
|
|
31 | add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_1 -max 172.00000000000003 -min -183.0 -radix decimal /testbench/lpp_lfr_filter_1/dATa_F0_1 | |||
|
|
32 | add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_2 -max 84.0 -min -97.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F0_2 | |||
|
|
33 | add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_3 -max 172.00000000000003 -min -183.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F0_3 | |||
|
|
34 | add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_4 -max 84.0 -min -97.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F0_4001 | |||
|
|
35 | add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_5 -max 172.00000000000003 -min -183.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F0_5 | |||
|
|
36 | add wave -noupdate -group OUTPUT -group F1 /testbench/lpp_lfr_filter_1/sample_f1_val | |||
|
|
37 | add wave -noupdate -group OUTPUT -group F1 -format Analog-Step -height 74 -label DATA_F1_0 -max 68.0 -min -102.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F1_0 | |||
|
|
38 | add wave -noupdate -group OUTPUT -group F1 -format Analog-Step -height 74 -label DATA_F1_1 -max 158.0 -min -15.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F1_1 | |||
|
|
39 | add wave -noupdate -group OUTPUT -group F1 -format Analog-Step -height 74 -label DATA_F1_2 -max 68.0 -min -102.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F1_2001 | |||
|
|
40 | add wave -noupdate -group OUTPUT -group F1 -format Analog-Step -height 74 -label DATA_F1_3 -max 158.0 -min -15.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F1_3 | |||
|
|
41 | add wave -noupdate -group OUTPUT -group F1 -format Analog-Step -height 74 -label DATA_F1_4 -max 68.0 -min -102.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F1_4 | |||
|
|
42 | add wave -noupdate -group OUTPUT -group F1 -format Analog-Step -height 74 -label DATA_F1_5 -max 158.0 -min -15.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F1_5001 | |||
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|
43 | add wave -noupdate /testbench/sample_out_s2 | |||
|
|
44 | add wave -noupdate -radix decimal -childformat {{/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(5) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(4) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(3) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(2) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(1) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(0) -radix decimal}} -subitemconfig {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(5) {-format Analog-Step -height 74 -max 172.00000000000003 -min -183.0 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(4) {-format Analog-Step -height 74 -max 84.0 -min -97.0 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(3) {-format Analog-Step -height 74 -max 172.00000000000003 -min -183.0 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(2) {-format Analog-Step -height 74 -max 84.0 -min -97.0 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(1) {-height 15 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(0) {-height 15 -radix decimal}} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in | |||
|
|
45 | add wave -noupdate -radix decimal /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in_val | |||
|
|
46 | add wave -noupdate -childformat {{/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(5) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(4) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(3) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(2) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(1) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(0) -radix decimal}} -subitemconfig {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(5) {-format Analog-Step -height 74 -max 130689.99999999997 -min -130153.0 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(4) {-format Analog-Step -height 74 -max 130689.99999999997 -min -130153.0 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(3) {-format Analog-Step -height 74 -max 130689.99999999997 -min -130153.0 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(2) {-format Analog-Step -height 74 -max 130689.99999999997 -min -130153.0 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(1) {-format Analog-Step -height 74 -max 130689.99999999997 -min -130153.0 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out(0) {-format Analog-Step -height 74 -max 130689.99999999997 -min -130153.0 -radix decimal}} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out | |||
|
|
47 | add wave -noupdate -format Literal -max 1.0 /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_out_val | |||
|
|
48 | add wave -noupdate -childformat {{/testbench/IIR_CEL_TEST_1/coeff_test_2(1) -radix decimal -childformat {{/testbench/IIR_CEL_TEST_1/coeff_test_2(1)(1) -radix decimal} {/testbench/IIR_CEL_TEST_1/coeff_test_2(1)(2) -radix decimal} {/testbench/IIR_CEL_TEST_1/coeff_test_2(1)(3) -radix decimal} {/testbench/IIR_CEL_TEST_1/coeff_test_2(1)(4) -radix decimal} {/testbench/IIR_CEL_TEST_1/coeff_test_2(1)(5) -radix decimal}}} {/testbench/IIR_CEL_TEST_1/coeff_test_2(2) -radix decimal} {/testbench/IIR_CEL_TEST_1/coeff_test_2(3) -radix decimal} {/testbench/IIR_CEL_TEST_1/coeff_test_2(4) -radix decimal} {/testbench/IIR_CEL_TEST_1/coeff_test_2(5) -radix decimal}} -subitemconfig {/testbench/IIR_CEL_TEST_1/coeff_test_2(1) {-height 15 -radix decimal -childformat {{/testbench/IIR_CEL_TEST_1/coeff_test_2(1)(1) -radix decimal} {/testbench/IIR_CEL_TEST_1/coeff_test_2(1)(2) -radix decimal} {/testbench/IIR_CEL_TEST_1/coeff_test_2(1)(3) -radix decimal} {/testbench/IIR_CEL_TEST_1/coeff_test_2(1)(4) -radix decimal} {/testbench/IIR_CEL_TEST_1/coeff_test_2(1)(5) -radix decimal}} -expand} /testbench/IIR_CEL_TEST_1/coeff_test_2(1)(1) {-height 15 -radix decimal} /testbench/IIR_CEL_TEST_1/coeff_test_2(1)(2) {-height 15 -radix decimal} /testbench/IIR_CEL_TEST_1/coeff_test_2(1)(3) {-height 15 -radix decimal} /testbench/IIR_CEL_TEST_1/coeff_test_2(1)(4) {-height 15 -radix decimal} /testbench/IIR_CEL_TEST_1/coeff_test_2(1)(5) {-height 15 -radix decimal} /testbench/IIR_CEL_TEST_1/coeff_test_2(2) {-height 15 -radix decimal} /testbench/IIR_CEL_TEST_1/coeff_test_2(3) {-height 15 -radix decimal} /testbench/IIR_CEL_TEST_1/coeff_test_2(4) {-height 15 -radix decimal} /testbench/IIR_CEL_TEST_1/coeff_test_2(5) {-height 15 -radix decimal}} /testbench/IIR_CEL_TEST_1/coeff_test_2 | |||
|
|
49 | add wave -noupdate /testbench/IIR_CEL_TEST_1/coeff_test | |||
|
|
50 | add wave -noupdate -radix decimal /testbench/IIR_CEL_TEST_1/b0_2 | |||
|
|
51 | add wave -noupdate -radix decimal /testbench/IIR_CEL_TEST_1/b0_1 | |||
|
|
52 | add wave -noupdate -radix decimal /testbench/IIR_CEL_TEST_1/b0_0 | |||
|
|
53 | add wave -noupdate -radix decimal /testbench/IIR_CEL_TEST_1/a0_2 | |||
|
|
54 | add wave -noupdate -radix decimal /testbench/IIR_CEL_TEST_1/a0_1 | |||
|
|
55 | add wave -noupdate -radix binary -childformat {{/testbench/IIR_CEL_TEST_1/coeff_test(224) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(223) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(222) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(221) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(220) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(219) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(218) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(217) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(216) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(215) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(214) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(213) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(212) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(211) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(210) -radix binary} {/testbench/IIR_CEL_TEST_1/coeff_test(209) -radix binary} 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/testbench/IIR_CEL_TEST_1/coeff_test(172) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(171) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(170) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(169) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(168) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(167) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(166) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(165) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(164) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(163) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(162) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(161) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(160) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(159) {-height 15 -radix binary} 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/testbench/IIR_CEL_TEST_1/coeff_test(144) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(143) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(142) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(141) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(140) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(139) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(138) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(137) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(136) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(135) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(134) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(133) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(132) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(131) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(130) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(129) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(128) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(127) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(126) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(125) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(124) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(123) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(122) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(121) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(120) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(119) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(118) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(117) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(116) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(115) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(114) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(113) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(112) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(111) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(110) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(109) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(108) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(107) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(106) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(105) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(104) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(103) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(102) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(101) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(100) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(99) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(98) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(97) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(96) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(95) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(94) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(93) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(92) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(91) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(90) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(89) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(88) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(87) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(86) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(85) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(84) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(83) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(82) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(81) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(80) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(79) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(78) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(77) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(76) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(75) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(74) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(73) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(72) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(71) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(70) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(69) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(68) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(67) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(66) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(65) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(64) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(63) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(62) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(61) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(60) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(59) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(58) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(57) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(56) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(55) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(54) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(53) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(52) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(51) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(50) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(49) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(48) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(47) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(46) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(45) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(44) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(43) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(42) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(41) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(40) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(39) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(38) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(37) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(36) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(35) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(34) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(33) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(32) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(31) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(30) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(29) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(28) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(27) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(26) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(25) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(24) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(23) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(22) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(21) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(20) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(19) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(18) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(17) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(16) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(15) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(14) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(13) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(12) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(11) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(10) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(9) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(8) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(7) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(6) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(5) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(4) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(3) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(2) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(1) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(0) {-height 15 -radix binary}} /testbench/IIR_CEL_TEST_1/coeff_test | |||
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56 | add wave -noupdate -radix decimal -childformat {{/testbench/sample_out1_reg(7) -radix decimal} {/testbench/sample_out1_reg(6) -radix decimal} {/testbench/sample_out1_reg(5) -radix decimal} {/testbench/sample_out1_reg(4) -radix decimal} {/testbench/sample_out1_reg(3) -radix decimal} {/testbench/sample_out1_reg(2) -radix decimal} {/testbench/sample_out1_reg(1) -radix decimal} {/testbench/sample_out1_reg(0) -radix decimal}} -expand -subitemconfig {/testbench/sample_out1_reg(7) {-radix decimal} /testbench/sample_out1_reg(6) {-radix decimal} /testbench/sample_out1_reg(5) {-radix decimal} /testbench/sample_out1_reg(4) {-radix decimal} /testbench/sample_out1_reg(3) {-radix decimal} /testbench/sample_out1_reg(2) {-radix decimal} /testbench/sample_out1_reg(1) {-format Analog-Step -height 74 -max 200.0 -min -200.0 -radix decimal} /testbench/sample_out1_reg(0) {-format Analog-Step -height 74 -max 100.0 -min -100.0 -radix decimal}} /testbench/sample_out1_reg | |||
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57 | add wave -noupdate -radix decimal -childformat {{/testbench/sample_out2_reg(7) -radix decimal} {/testbench/sample_out2_reg(6) -radix decimal} {/testbench/sample_out2_reg(5) -radix decimal} {/testbench/sample_out2_reg(4) -radix decimal} {/testbench/sample_out2_reg(3) -radix decimal} {/testbench/sample_out2_reg(2) -radix decimal} {/testbench/sample_out2_reg(1) -radix decimal} {/testbench/sample_out2_reg(0) -radix decimal}} -expand -subitemconfig {/testbench/sample_out2_reg(7) {-radix decimal} /testbench/sample_out2_reg(6) {-radix decimal} /testbench/sample_out2_reg(5) {-radix decimal} /testbench/sample_out2_reg(4) {-radix decimal} /testbench/sample_out2_reg(3) {-radix decimal} /testbench/sample_out2_reg(2) {-radix decimal} /testbench/sample_out2_reg(1) {-format Analog-Step -height 74 -max 200.0 -min -200.0 -radix decimal} /testbench/sample_out2_reg(0) {-format Analog-Step -height 74 -max 100.0 -min -100.0 -radix decimal}} /testbench/sample_out2_reg | |||
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58 | add wave -noupdate /testbench/IIR_CEL_TEST_v3_1/sample_out1_val | |||
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59 | add wave -noupdate /testbench/IIR_CEL_TEST_v3_1/sample_out2_val | |||
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60 | TreeUpdate [SetDefaultTree] | |||
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61 | WaveRestoreCursors {{Cursor 4} {0 ps} 0} | |||
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62 | quietly wave cursor active 1 | |||
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63 | configure wave -namecolwidth 377 | |||
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64 | configure wave -valuecolwidth 254 | |||
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65 | configure wave -justifyvalue left | |||
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66 | configure wave -signalnamewidth 0 | |||
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67 | configure wave -snapdistance 10 | |||
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68 | configure wave -datasetprefix 0 | |||
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69 | configure wave -rowmargin 4 | |||
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70 | configure wave -childrowmargin 2 | |||
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71 | configure wave -gridoffset 0 | |||
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72 | configure wave -gridperiod 1 | |||
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73 | configure wave -griddelta 40 | |||
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74 | configure wave -timeline 0 | |||
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75 | configure wave -timelineunits ns | |||
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76 | update | |||
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77 | WaveRestoreZoom {5127439409 ps} {5439678593 ps} | |||
| @@ -0,0 +1,27 | |||||
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1 | onerror {resume} | |||
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2 | quietly WaveActivateNextPane {} 0 | |||
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3 | add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_in_a | |||
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4 | add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_in_b | |||
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5 | add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_out | |||
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6 | add wave -noupdate /testbench/data_out_carry | |||
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7 | add wave -noupdate /testbench/all_is_ok | |||
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8 | add wave -noupdate -radix hexadecimal /testbench/data_out | |||
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9 | add wave -noupdate -radix hexadecimal /testbench/data_out_pre | |||
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10 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/data_out_diff(31) {-radix hexadecimal} /testbench/data_out_diff(30) {-radix hexadecimal} /testbench/data_out_diff(29) {-radix hexadecimal} /testbench/data_out_diff(28) {-radix hexadecimal} /testbench/data_out_diff(27) {-radix hexadecimal} /testbench/data_out_diff(26) {-radix hexadecimal} /testbench/data_out_diff(25) {-radix hexadecimal} /testbench/data_out_diff(24) {-radix hexadecimal} /testbench/data_out_diff(23) {-radix hexadecimal} /testbench/data_out_diff(22) {-radix hexadecimal} /testbench/data_out_diff(21) {-radix hexadecimal} /testbench/data_out_diff(20) {-radix hexadecimal} /testbench/data_out_diff(19) {-radix hexadecimal} /testbench/data_out_diff(18) {-radix hexadecimal} /testbench/data_out_diff(17) {-radix hexadecimal} /testbench/data_out_diff(16) {-radix hexadecimal} /testbench/data_out_diff(15) {-radix hexadecimal} /testbench/data_out_diff(14) {-radix hexadecimal} /testbench/data_out_diff(13) {-radix hexadecimal} /testbench/data_out_diff(12) {-radix hexadecimal} /testbench/data_out_diff(11) {-radix hexadecimal} /testbench/data_out_diff(10) {-radix hexadecimal} /testbench/data_out_diff(9) {-radix hexadecimal} /testbench/data_out_diff(8) {-radix hexadecimal} /testbench/data_out_diff(7) {-radix hexadecimal} /testbench/data_out_diff(6) {-radix hexadecimal} /testbench/data_out_diff(5) {-radix hexadecimal} /testbench/data_out_diff(4) {-radix hexadecimal} /testbench/data_out_diff(3) {-radix hexadecimal} /testbench/data_out_diff(2) {-radix hexadecimal} /testbench/data_out_diff(1) {-radix hexadecimal} /testbench/data_out_diff(0) {-radix hexadecimal}} /testbench/data_out_diff | |||
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11 | TreeUpdate [SetDefaultTree] | |||
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12 | WaveRestoreCursors {{Cursor 1} {55000 ps} 0} | |||
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13 | configure wave -namecolwidth 182 | |||
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14 | configure wave -valuecolwidth 97 | |||
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15 | configure wave -justifyvalue left | |||
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16 | configure wave -signalnamewidth 0 | |||
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17 | configure wave -snapdistance 10 | |||
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18 | configure wave -datasetprefix 0 | |||
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19 | configure wave -rowmargin 4 | |||
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20 | configure wave -childrowmargin 2 | |||
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21 | configure wave -gridoffset 0 | |||
|
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22 | configure wave -gridperiod 1 | |||
|
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23 | configure wave -griddelta 40 | |||
|
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24 | configure wave -timeline 0 | |||
|
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25 | configure wave -timelineunits ns | |||
|
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26 | update | |||
|
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27 | WaveRestoreZoom {0 ps} {424577 ps} | |||
| @@ -0,0 +1,23 | |||||
|
|
1 | onerror {resume} | |||
|
|
2 | quietly WaveActivateNextPane {} 0 | |||
|
|
3 | add wave -noupdate /testbench/a | |||
|
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4 | add wave -noupdate /testbench/b | |||
|
|
5 | add wave -noupdate /testbench/c | |||
|
|
6 | add wave -noupdate /testbench/all_done | |||
|
|
7 | TreeUpdate [SetDefaultTree] | |||
|
|
8 | WaveRestoreCursors {{Cursor 1} {631245000 ps} 1} {{Cursor 2} {590125000 ps} 0} | |||
|
|
9 | configure wave -namecolwidth 424 | |||
|
|
10 | configure wave -valuecolwidth 119 | |||
|
|
11 | configure wave -justifyvalue left | |||
|
|
12 | configure wave -signalnamewidth 0 | |||
|
|
13 | configure wave -snapdistance 10 | |||
|
|
14 | configure wave -datasetprefix 0 | |||
|
|
15 | configure wave -rowmargin 4 | |||
|
|
16 | configure wave -childrowmargin 2 | |||
|
|
17 | configure wave -gridoffset 0 | |||
|
|
18 | configure wave -gridperiod 1 | |||
|
|
19 | configure wave -griddelta 40 | |||
|
|
20 | configure wave -timeline 0 | |||
|
|
21 | configure wave -timelineunits ns | |||
|
|
22 | update | |||
|
|
23 | WaveRestoreZoom {0 ps} {2100026250 ps} | |||
| @@ -0,0 +1,50 | |||||
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1 | onerror {resume} | |||
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2 | quietly WaveActivateNextPane {} 0 | |||
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3 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in | |||
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4 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in_valid | |||
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5 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out | |||
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6 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out_valid | |||
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7 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_data | |||
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8 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_valid | |||
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9 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_data | |||
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10 | add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_valid | |||
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11 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in | |||
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12 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in_valid | |||
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13 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out | |||
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14 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out_valid | |||
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15 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-radix hexadecimal} /testbench/cic_1/I_data(2) {-radix hexadecimal} /testbench/cic_1/I_data(1) {-radix hexadecimal} /testbench/cic_1/I_data(0) {-radix hexadecimal}} /testbench/cic_1/I_data | |||
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16 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/I_valid | |||
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17 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} /testbench/cic_1/C_data(3)(30) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/C_data | |||
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18 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/C_valid | |||
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19 | add wave -noupdate -expand -group CIC_LFR -radix decimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in | |||
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20 | add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_in_valid | |||
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21 | add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}}} -expand -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16 | |||
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22 | add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_16_valid | |||
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23 | add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_256(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_256(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_256 | |||
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24 | add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_256_valid | |||
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25 | add wave -noupdate -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) | |||
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26 | add wave -noupdate -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out | |||
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27 | add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(0)(15) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-radix hexadecimal}} /testbench/cic_lfr_1/data_out_16(0) | |||
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28 | add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(5)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(4)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s | |||
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29 | add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg256_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg256_s(5) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(4) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(3) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(2) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(1) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(0) {-radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg256_s | |||
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30 | add wave -noupdate -group temp -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) | |||
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31 | add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out | |||
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32 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray | |||
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33 | TreeUpdate [SetDefaultTree] | |||
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34 | WaveRestoreCursors {{Cursor 1} {21545643925 ps} 0} {{Cursor 2} {514701877948 ps} 0} {{Cursor 3} {8443215000 ps} 0} | |||
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35 | quietly wave cursor active 3 | |||
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36 | configure wave -namecolwidth 299 | |||
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37 | configure wave -valuecolwidth 188 | |||
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38 | configure wave -justifyvalue left | |||
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39 | configure wave -signalnamewidth 0 | |||
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40 | configure wave -snapdistance 10 | |||
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41 | configure wave -datasetprefix 0 | |||
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42 | configure wave -rowmargin 4 | |||
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43 | configure wave -childrowmargin 2 | |||
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44 | configure wave -gridoffset 0 | |||
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45 | configure wave -gridperiod 1 | |||
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46 | configure wave -griddelta 40 | |||
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47 | configure wave -timeline 0 | |||
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48 | configure wave -timelineunits ns | |||
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49 | update | |||
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50 | WaveRestoreZoom {0 ps} {300136435256 ps} | |||
| @@ -0,0 +1,62 | |||||
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1 | onerror {resume} | |||
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2 | quietly virtual signal -install /testbench/cic_lfr_1 { /testbench/cic_lfr_1/OPERATION(12 downto 10)} SEL_ADRR_JUMP | |||
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3 | quietly WaveActivateNextPane {} 0 | |||
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4 | add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in | |||
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5 | add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in_valid | |||
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6 | add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out | |||
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7 | add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out_valid | |||
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8 | add wave -noupdate -expand -group CIC_256 -radix hexadecimal -childformat {{/testbench/cic_256/I_data(3) -radix hexadecimal} {/testbench/cic_256/I_data(2) -radix hexadecimal} {/testbench/cic_256/I_data(1) -radix hexadecimal} {/testbench/cic_256/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_256/I_data(3) {-radix hexadecimal} /testbench/cic_256/I_data(2) {-radix hexadecimal} /testbench/cic_256/I_data(1) {-radix hexadecimal} /testbench/cic_256/I_data(0) {-radix hexadecimal}} /testbench/cic_256/I_data | |||
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9 | add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/I_valid | |||
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10 | add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/C_data | |||
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11 | add wave -noupdate -expand -group CIC_256 -radix hexadecimal -childformat {{/testbench/cic_256/C_valid(3) -radix hexadecimal} {/testbench/cic_256/C_valid(2) -radix hexadecimal} {/testbench/cic_256/C_valid(1) -radix hexadecimal} {/testbench/cic_256/C_valid(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_256/C_valid(3) {-radix hexadecimal} /testbench/cic_256/C_valid(2) {-radix hexadecimal} /testbench/cic_256/C_valid(1) {-radix hexadecimal} /testbench/cic_256/C_valid(0) {-radix hexadecimal}} /testbench/cic_256/C_valid | |||
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12 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in | |||
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13 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in_valid | |||
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14 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out | |||
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15 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out_valid | |||
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16 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/I_data | |||
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17 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/I_valid | |||
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18 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} /testbench/cic_1/C_data(3)(30) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/C_data | |||
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19 | add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/C_valid | |||
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20 | add wave -noupdate -group CIC_LFR -radix decimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in | |||
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21 | add wave -noupdate -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_in_valid | |||
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22 | add wave -noupdate -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}}} -expand -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16 | |||
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23 | add wave -noupdate -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_16_valid | |||
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24 | add wave -noupdate -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_256(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_256(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_256 | |||
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25 | add wave -noupdate -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_256_valid | |||
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26 | add wave -noupdate -expand -group addr_gen /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_base | |||
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27 | add wave -noupdate -expand -group addr_gen /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_init | |||
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28 | add wave -noupdate -expand -group addr_gen /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_add_1 | |||
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29 | add wave -noupdate -expand -group addr_gen /testbench/cic_lfr_1/cic_lfr_address_gen_1/address_reg_s | |||
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30 | add wave -noupdate -expand -group addr_gen /testbench/cic_lfr_1/cic_lfr_address_gen_1/address_reg | |||
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31 | add wave -noupdate -expand -group addr_gen -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr | |||
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32 | add wave -noupdate /testbench/cic_lfr_1/cic_lfr_control_1/STATE_CIC_LFR | |||
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33 | add wave -noupdate -expand /testbench/cic_lfr_1/SEL_ADRR_JUMP | |||
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34 | add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RADDR | |||
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35 | add wave -noupdate /testbench/cic_lfr_1/cic_lfr_control_1/sample_16_odd | |||
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36 | add wave -noupdate /testbench/cic_lfr_1/cic_lfr_control_1/sample_256_odd | |||
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37 | add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16(0) | |||
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38 | add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(5)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(4)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s | |||
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39 | add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg256_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg256_s(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg256_s | |||
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40 | add wave -noupdate -group temp -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) | |||
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41 | add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out | |||
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42 | add wave -noupdate -group temp -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) | |||
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43 | add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out | |||
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44 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) -radix hexadecimal} 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/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray | |||
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45 | TreeUpdate [SetDefaultTree] | |||
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46 | WaveRestoreCursors {{Cursor 1} {20772435000 ps} 0} {{Cursor 2} {514701877948 ps} 0} {{Cursor 3} {10355795000 ps} 0} | |||
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47 | quietly wave cursor active 1 | |||
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48 | configure wave -namecolwidth 362 | |||
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49 | configure wave -valuecolwidth 188 | |||
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50 | configure wave -justifyvalue left | |||
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51 | configure wave -signalnamewidth 0 | |||
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52 | configure wave -snapdistance 10 | |||
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53 | configure wave -datasetprefix 0 | |||
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54 | configure wave -rowmargin 4 | |||
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55 | configure wave -childrowmargin 2 | |||
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56 | configure wave -gridoffset 0 | |||
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57 | configure wave -gridperiod 1 | |||
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58 | configure wave -griddelta 40 | |||
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59 | configure wave -timeline 0 | |||
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60 | configure wave -timelineunits ns | |||
|
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61 | update | |||
|
|
62 | WaveRestoreZoom {20772244241 ps} {20772735038 ps} | |||
| @@ -0,0 +1,441 | |||||
|
|
1 | VHDLIB=../.. | |||
|
|
2 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |||
|
|
3 | ||||
|
|
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |||
|
|
5 | TOP=TB | |||
|
|
6 | ||||
|
|
7 | CMD_VLIB=vlib | |||
|
|
8 | CMD_VMAP=vmap | |||
|
|
9 | CMD_VCOM=@vcom -quiet -93 -work | |||
|
|
10 | ||||
|
|
11 | ################## project specific targets ########################## | |||
|
|
12 | ||||
|
|
13 | all: | |||
|
|
14 | @echo "make vsim" | |||
|
|
15 | @echo "make libs" | |||
|
|
16 | @echo "make clean" | |||
|
|
17 | @echo "make vcom_grlib vcom_lpp vcom_tb" | |||
|
|
18 | ||||
|
|
19 | run: | |||
|
|
20 | @vsim lpp.top_ad_conv_RHF1401_withFilter_tb -do run.do | |||
|
|
21 | # @vsim work.TB | |||
|
|
22 | # @vsim lpp.lpp_lfr_ms | |||
|
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23 | ||||
|
|
24 | vsim: libs vcom run | |||
|
|
25 | ||||
|
|
26 | libs: | |||
|
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27 | @$(CMD_VLIB) modelsim | |||
|
|
28 | @$(CMD_VMAP) modelsim modelsim | |||
|
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29 | @$(CMD_VLIB) modelsim/techmap | |||
|
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30 | @$(CMD_VMAP) techmap modelsim/techmap | |||
|
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31 | @$(CMD_VLIB) modelsim/grlib | |||
|
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32 | @$(CMD_VMAP) grlib modelsim/grlib | |||
|
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33 | @$(CMD_VLIB) modelsim/gaisler | |||
|
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34 | @$(CMD_VMAP) gaisler modelsim/gaisler | |||
|
|
35 | @$(CMD_VLIB) modelsim/work | |||
|
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36 | @$(CMD_VMAP) work modelsim/work | |||
|
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37 | @$(CMD_VLIB) modelsim/lpp | |||
|
|
38 | @$(CMD_VMAP) lpp modelsim/lpp | |||
|
|
39 | @echo "libs done" | |||
|
|
40 | ||||
|
|
41 | ||||
|
|
42 | clean: | |||
|
|
43 | @rm -Rf modelsim | |||
|
|
44 | @rm -Rf modelsim.ini | |||
|
|
45 | @rm -Rf *~ | |||
|
|
46 | @rm -Rf transcript | |||
|
|
47 | @rm -Rf wlft* | |||
|
|
48 | @rm -Rf *.wlf | |||
|
|
49 | @rm -Rf vish_stacktrace.vstf | |||
|
|
50 | @rm -Rf libs.do | |||
|
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51 | ||||
|
|
52 | vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb | |||
|
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53 | ||||
|
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54 | ||||
|
|
55 | vcom_tb: | |||
|
|
56 | ## $(CMD_VCOM) lpp lpp_memory.vhd | |||
|
|
57 | ## $(CMD_VCOM) lpp lppFIFOxN.vhd | |||
|
|
58 | ## $(CMD_VCOM) lpp lpp_FIFO.vhd | |||
|
|
59 | ## $(CMD_VCOM) lpp lpp_lfr_ms.vhd | |||
|
|
60 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd | |||
|
|
61 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/verif/top_ad_conv_RHF1401_withFilter_tb.vhd | |||
|
|
62 | @echo "vcom done" | |||
|
|
63 | ||||
|
|
64 | vcom_grlib: | |||
|
|
65 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd | |||
|
|
66 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd | |||
|
|
67 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd | |||
|
|
68 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd | |||
|
|
69 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd | |||
|
|
70 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd | |||
|
|
71 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd | |||
|
|
72 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd | |||
|
|
73 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd | |||
|
|
74 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd | |||
|
|
75 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd | |||
|
|
76 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd | |||
|
|
77 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd | |||
|
|
78 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd | |||
|
|
79 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd | |||
|
|
80 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd | |||
|
|
81 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd | |||
|
|
82 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd | |||
|
|
83 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd | |||
|
|
84 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd | |||
|
|
85 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd | |||
|
|
86 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd | |||
|
|
87 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd | |||
|
|
88 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd | |||
|
|
89 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd | |||
|
|
90 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd | |||
|
|
91 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd | |||
|
|
92 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd | |||
|
|
93 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd | |||
|
|
94 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd | |||
|
|
95 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd | |||
|
|
96 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd | |||
|
|
97 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd | |||
|
|
98 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd | |||
|
|
99 | @echo "vcom grlib done" | |||
|
|
100 | ||||
|
|
101 | vcom_gaisler: | |||
|
|
102 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd | |||
|
|
103 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd | |||
|
|
104 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd | |||
|
|
105 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd | |||
|
|
106 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd | |||
|
|
107 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd | |||
|
|
108 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd | |||
|
|
109 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd | |||
|
|
110 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd | |||
|
|
111 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd | |||
|
|
112 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd | |||
|
|
113 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd | |||
|
|
114 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd | |||
|
|
115 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd | |||
|
|
116 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd | |||
|
|
117 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd | |||
|
|
118 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd | |||
|
|
119 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd | |||
|
|
120 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd | |||
|
|
121 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd | |||
|
|
122 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd | |||
|
|
123 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd | |||
|
|
124 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd | |||
|
|
125 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd | |||
|
|
126 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd | |||
|
|
127 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd | |||
|
|
128 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd | |||
|
|
129 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd | |||
|
|
130 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd | |||
|
|
131 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd | |||
|
|
132 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd | |||
|
|
133 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd | |||
|
|
134 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd | |||
|
|
135 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd | |||
|
|
136 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd | |||
|
|
137 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd | |||
|
|
138 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd | |||
|
|
139 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd | |||
|
|
140 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd | |||
|
|
141 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd | |||
|
|
142 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd | |||
|
|
143 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd | |||
|
|
144 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd | |||
|
|
145 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd | |||
|
|
146 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd | |||
|
|
147 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd | |||
|
|
148 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd | |||
|
|
149 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd | |||
|
|
150 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd | |||
|
|
151 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd | |||
|
|
152 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd | |||
|
|
153 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd | |||
|
|
154 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd | |||
|
|
155 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd | |||
|
|
156 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd | |||
|
|
157 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd | |||
|
|
158 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd | |||
|
|
159 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd | |||
|
|
160 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd | |||
|
|
161 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd | |||
|
|
162 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd | |||
|
|
163 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd | |||
|
|
164 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd | |||
|
|
165 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd | |||
|
|
166 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd | |||
|
|
167 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd | |||
|
|
168 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd | |||
|
|
169 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd | |||
|
|
170 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd | |||
|
|
171 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd | |||
|
|
172 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd | |||
|
|
173 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd | |||
|
|
174 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd | |||
|
|
175 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd | |||
|
|
176 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd | |||
|
|
177 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd | |||
|
|
178 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd | |||
|
|
179 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd | |||
|
|
180 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd | |||
|
|
181 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd | |||
|
|
182 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd | |||
|
|
183 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd | |||
|
|
184 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd | |||
|
|
185 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd | |||
|
|
186 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd | |||
|
|
187 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd | |||
|
|
188 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd | |||
|
|
189 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd | |||
|
|
190 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd | |||
|
|
191 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd | |||
|
|
192 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd | |||
|
|
193 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd | |||
|
|
194 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd | |||
|
|
195 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd | |||
|
|
196 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd | |||
|
|
197 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd | |||
|
|
198 | ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd | |||
|
|
199 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd | |||
|
|
200 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd | |||
|
|
201 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd | |||
|
|
202 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd | |||
|
|
203 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd | |||
|
|
204 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd | |||
|
|
205 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd | |||
|
|
206 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd | |||
|
|
207 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd | |||
|
|
208 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd | |||
|
|
209 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd | |||
|
|
210 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd | |||
|
|
211 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd | |||
|
|
212 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd | |||
|
|
213 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd | |||
|
|
214 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd | |||
|
|
215 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd | |||
|
|
216 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd | |||
|
|
217 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd | |||
|
|
218 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd | |||
|
|
219 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd | |||
|
|
220 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd | |||
|
|
221 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd | |||
|
|
222 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd | |||
|
|
223 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd | |||
|
|
224 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd | |||
|
|
225 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd | |||
|
|
226 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd | |||
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227 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd | |||
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228 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd | |||
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229 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd | |||
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230 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd | |||
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231 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd | |||
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232 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd | |||
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233 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd | |||
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234 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd | |||
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235 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd | |||
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236 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd | |||
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237 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd | |||
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238 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd | |||
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239 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd | |||
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240 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd | |||
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241 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd | |||
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242 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd | |||
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243 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd | |||
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244 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd | |||
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245 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd | |||
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246 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd | |||
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247 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd | |||
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248 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd | |||
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249 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd | |||
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250 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd | |||
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251 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd | |||
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252 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd | |||
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253 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd | |||
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254 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd | |||
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255 | @echo "vcom gaisler done" | |||
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256 | ||||
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257 | vcom_techmap: | |||
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258 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd | |||
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259 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd | |||
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260 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd | |||
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261 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd | |||
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262 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd | |||
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263 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd | |||
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264 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd | |||
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265 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd | |||
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266 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd | |||
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267 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd | |||
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268 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd | |||
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269 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd | |||
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270 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd | |||
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271 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd | |||
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272 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd | |||
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273 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd | |||
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274 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd | |||
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275 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd | |||
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276 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd | |||
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|
277 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd | |||
|
|
278 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd | |||
|
|
279 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd | |||
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280 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd | |||
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|
281 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd | |||
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|
282 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd | |||
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|
283 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd | |||
|
|
284 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd | |||
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|
285 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd | |||
|
|
286 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd | |||
|
|
287 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd | |||
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|
288 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd | |||
|
|
289 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd | |||
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290 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd | |||
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|
291 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd | |||
|
|
292 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd | |||
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|
293 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd | |||
|
|
294 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd | |||
|
|
295 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd | |||
|
|
296 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd | |||
|
|
297 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd | |||
|
|
298 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd | |||
|
|
299 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd | |||
|
|
300 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd | |||
|
|
301 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd | |||
|
|
302 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd | |||
|
|
303 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd | |||
|
|
304 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd | |||
|
|
305 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd | |||
|
|
306 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd | |||
|
|
307 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd | |||
|
|
308 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd | |||
|
|
309 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd | |||
|
|
310 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd | |||
|
|
311 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd | |||
|
|
312 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd | |||
|
|
313 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd | |||
|
|
314 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd | |||
|
|
315 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd | |||
|
|
316 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd | |||
|
|
317 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd | |||
|
|
318 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd | |||
|
|
319 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd | |||
|
|
320 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd | |||
|
|
321 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd | |||
|
|
322 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd | |||
|
|
323 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd | |||
|
|
324 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd | |||
|
|
325 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd | |||
|
|
326 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd | |||
|
|
327 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd | |||
|
|
328 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd | |||
|
|
329 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd | |||
|
|
330 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd | |||
|
|
331 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd | |||
|
|
332 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd | |||
|
|
333 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd | |||
|
|
334 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd | |||
|
|
335 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd | |||
|
|
336 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd | |||
|
|
337 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd | |||
|
|
338 | @echo "vcom techmap done" | |||
|
|
339 | ||||
|
|
340 | vcom_lpp: | |||
|
|
341 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd | |||
|
|
342 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd | |||
|
|
343 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd | |||
|
|
344 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd | |||
|
|
345 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd | |||
|
|
346 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd | |||
|
|
347 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |||
|
|
348 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |||
|
|
349 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |||
|
|
350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |||
|
|
351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |||
|
|
352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |||
|
|
353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |||
|
|
354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |||
|
|
355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |||
|
|
356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |||
|
|
357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |||
|
|
358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |||
|
|
359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |||
|
|
360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |||
|
|
361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |||
|
|
362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |||
|
|
363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |||
|
|
364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |||
|
|
365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |||
|
|
366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |||
|
|
367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |||
|
|
368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |||
|
|
369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |||
|
|
370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |||
|
|
371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |||
|
|
372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd | |||
|
|
373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |||
|
|
374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |||
|
|
375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |||
|
|
376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd | |||
|
|
377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |||
|
|
378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd | |||
|
|
379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd | |||
|
|
380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd | |||
|
|
381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd | |||
|
|
382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd | |||
|
|
383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |||
|
|
384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd | |||
|
|
385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd | |||
|
|
386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd | |||
|
|
387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd | |||
|
|
388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd | |||
|
|
389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd | |||
|
|
390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd | |||
|
|
391 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd | |||
|
|
392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd | |||
|
|
393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd | |||
|
|
394 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd | |||
|
|
395 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd | |||
|
|
396 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd | |||
|
|
397 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd | |||
|
|
398 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |||
|
|
399 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd | |||
|
|
400 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd | |||
|
|
401 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd | |||
|
|
402 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd | |||
|
|
403 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd | |||
|
|
404 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |||
|
|
405 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd | |||
|
|
406 | @echo "vcom lpp done" | |||
|
|
407 | ||||
|
|
408 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |||
|
|
409 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |||
|
|
410 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |||
|
|
411 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |||
|
|
412 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |||
|
|
413 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |||
|
|
414 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |||
|
|
415 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |||
|
|
416 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |||
|
|
417 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |||
|
|
418 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |||
|
|
419 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |||
|
|
420 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |||
|
|
421 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |||
|
|
422 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |||
|
|
423 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |||
|
|
424 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |||
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425 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |||
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426 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |||
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427 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |||
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428 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |||
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429 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |||
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430 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |||
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431 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |||
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432 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |||
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433 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |||
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434 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd | |||
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435 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd | |||
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436 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd | |||
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437 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd | |||
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438 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd | |||
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439 | # @echo "vcom lpp done" | |||
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440 | ||||
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441 | #include Makefile_vcom_lpp | |||
| @@ -0,0 +1,480 | |||||
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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
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6 | -- it under the terms of the GNU General Public License as published by | |||
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7 | -- the Free Software Foundation; either version 3 of the License, or | |||
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8 | -- (at your option) any later version. | |||
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9 | -- | |||
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10 | -- This program is distributed in the hope that it will be useful, | |||
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | -- GNU General Public License for more details. | |||
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14 | -- | |||
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15 | -- You should have received a copy of the GNU General Public License | |||
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16 | -- along with this program; if not, write to the Free Software | |||
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ------------------------------------------------------------------------------- | |||
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19 | -- Author : Jean-christophe Pellion | |||
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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21 | ------------------------------------------------------------------------------- | |||
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22 | ||||
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23 | LIBRARY IEEE; | |||
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24 | USE IEEE.STD_LOGIC_1164.ALL; | |||
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25 | USE IEEE.NUMERIC_STD.ALL; | |||
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26 | ||||
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27 | LIBRARY lpp; | |||
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28 | USE lpp.lpp_lfr_pkg.ALL; | |||
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29 | USE lpp.lpp_memory.ALL; | |||
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30 | USE lpp.iir_filter.ALL; | |||
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31 | USE lpp.spectral_matrix_package.ALL; | |||
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32 | use lpp.lpp_fft.all; | |||
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33 | use lpp.fft_components.all; | |||
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34 | ||||
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35 | LIBRARY grlib; | |||
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36 | USE grlib.amba.ALL; | |||
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37 | USE grlib.stdlib.ALL; | |||
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38 | USE grlib.devices.ALL; | |||
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39 | USE GRLIB.DMA2AHB_Package.ALL; | |||
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40 | ||||
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41 | ENTITY TB IS | |||
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42 | ||||
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43 | ||||
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44 | END TB; | |||
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45 | ||||
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46 | ||||
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47 | ARCHITECTURE beh OF TB IS | |||
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48 | ||||
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49 | ----------------------------------------------------------------------------- | |||
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50 | SIGNAL clk25MHz : STD_LOGIC := '0'; | |||
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51 | SIGNAL rstn : STD_LOGIC := '0'; | |||
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52 | ||||
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53 | ----------------------------------------------------------------------------- | |||
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54 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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55 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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56 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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57 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
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58 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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59 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
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60 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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61 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
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62 | SIGNAL dma_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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63 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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64 | SIGNAL dma_valid : STD_LOGIC; | |||
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65 | SIGNAL dma_valid_burst : STD_LOGIC; | |||
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66 | SIGNAL dma_ren : STD_LOGIC; | |||
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67 | SIGNAL dma_done : STD_LOGIC; | |||
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68 | SIGNAL ready_matrix_f0 : STD_LOGIC; | |||
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69 | -- SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |||
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70 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |||
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71 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |||
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72 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |||
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73 | SIGNAL error_bad_component_error : STD_LOGIC; | |||
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74 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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75 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; | |||
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76 | -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |||
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77 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |||
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78 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |||
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79 | -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |||
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80 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; | |||
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81 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |||
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82 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |||
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83 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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84 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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85 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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86 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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87 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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88 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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89 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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90 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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91 | ||||
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92 | ----------------------------------------------------------------------------- | |||
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93 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; | |||
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94 | SIGNAL sample_counter_24k : INTEGER; | |||
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95 | SIGNAL s_24576Hz : STD_LOGIC; | |||
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96 | ||||
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97 | SIGNAL s_24_sync_reg_0 : STD_LOGIC; | |||
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98 | SIGNAL s_24_sync_reg_1 : STD_LOGIC; | |||
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99 | ||||
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100 | SIGNAL s_24576Hz_sync : STD_LOGIC; | |||
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101 | ||||
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102 | SIGNAL sample_counter_f1 : INTEGER; | |||
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103 | SIGNAL sample_counter_f2 : INTEGER; | |||
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104 | -- | |||
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105 | SIGNAL sample_f0_val : STD_LOGIC; | |||
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106 | SIGNAL sample_f1_val : STD_LOGIC; | |||
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107 | SIGNAL sample_f2_val : STD_LOGIC; | |||
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108 | ||||
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109 | ----------------------------------------------------------------------------- | |||
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110 | SIGNAL ren_counter : INTEGER; | |||
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111 | ||||
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112 | SIGNAL error_buffer_full : STD_LOGIC; | |||
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113 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); | |||
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114 | ----------------------------------------------------------------------------- | |||
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115 | SIGNAL apbi : apb_slv_in_type; | |||
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116 | SIGNAL apbo : apb_slv_out_type; | |||
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117 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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118 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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119 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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120 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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121 | -- | |||
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122 | SIGNAL ready_reg : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
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123 | SIGNAL irq_ongoing : STD_LOGIC; | |||
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124 | -- | |||
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125 | SIGNAL read_status : STD_LOGIC; | |||
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126 | SIGNAL read_status_t : STD_LOGIC; | |||
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127 | ||||
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128 | ||||
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129 | SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0); | |||
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130 | SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0); | |||
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131 | ||||
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132 | BEGIN -- beh | |||
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133 | ||||
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134 | clk25MHz <= NOT clk25MHz AFTER 20 ns; | |||
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135 | clk25MHz <= NOT clk25MHz AFTER 20 ns; | |||
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136 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz | |||
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137 | ||||
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138 | PROCESS | |||
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139 | BEGIN -- PROCESS | |||
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140 | WAIT UNTIL clk25MHz = '1'; | |||
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141 | WAIT UNTIL clk25MHz = '1'; | |||
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142 | WAIT UNTIL clk25MHz = '1'; | |||
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143 | rstn <= '1'; | |||
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144 | WAIT UNTIL clk25MHz = '1'; | |||
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145 | ||||
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146 | ||||
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147 | WAIT FOR 100 ms; | |||
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148 | ||||
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149 | REPORT "*** END simulation ***" SEVERITY failure; | |||
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150 | WAIT; | |||
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151 | ||||
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152 | END PROCESS; | |||
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153 | ||||
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154 | ||||
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155 | ----------------------------------------------------------------------------- | |||
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156 | PROCESS (clk49_152MHz, rstn) | |||
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157 | BEGIN -- PROCESS | |||
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158 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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159 | sample_counter_24k <= 0; | |||
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160 | s_24576Hz <= '0'; | |||
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161 | ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge | |||
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162 | IF sample_counter_24k = 0 THEN | |||
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163 | sample_counter_24k <= 2000; | |||
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164 | s_24576Hz <= NOT s_24576Hz; | |||
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165 | ELSE | |||
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166 | sample_counter_24k <= sample_counter_24k - 1; | |||
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167 | END IF; | |||
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168 | END IF; | |||
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169 | END PROCESS; | |||
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170 | ||||
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171 | PROCESS (clk25MHz, rstn) | |||
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172 | BEGIN -- PROCESS | |||
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173 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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174 | s_24_sync_reg_0 <= '0'; | |||
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175 | s_24_sync_reg_1 <= '0'; | |||
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176 | s_24576Hz_sync <= '0'; | |||
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177 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge | |||
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178 | s_24_sync_reg_0 <= s_24576Hz; | |||
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179 | s_24_sync_reg_1 <= s_24_sync_reg_0; | |||
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180 | s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1; | |||
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181 | END IF; | |||
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182 | END PROCESS; | |||
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183 | ||||
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184 | PROCESS (clk25MHz, rstn) | |||
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185 | BEGIN -- PROCESS | |||
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186 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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187 | sample_f0_val <= '0'; | |||
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188 | sample_f1_val <= '0'; | |||
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189 | sample_f2_val <= '0'; | |||
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190 | ||||
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191 | sample_counter_f1 <= 0; | |||
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192 | sample_counter_f2 <= 0; | |||
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193 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge | |||
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194 | IF s_24576Hz_sync = '1' THEN | |||
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195 | sample_f0_val <= '1'; | |||
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196 | IF sample_counter_f1 = 0 THEN | |||
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197 | sample_f1_val <= '1'; | |||
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198 | sample_counter_f1 <= 5; | |||
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199 | ELSE | |||
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200 | sample_f1_val <= '0'; | |||
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201 | sample_counter_f1 <= sample_counter_f1 -1; | |||
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202 | END IF; | |||
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203 | IF sample_counter_f2 = 0 THEN | |||
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204 | sample_f2_val <= '1'; | |||
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205 | sample_counter_f2 <= 95; | |||
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206 | ELSE | |||
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207 | sample_f2_val <= '0'; | |||
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208 | sample_counter_f2 <= sample_counter_f2 -1; | |||
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209 | END IF; | |||
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210 | ELSE | |||
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211 | sample_f0_val <= '0'; | |||
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212 | sample_f1_val <= '0'; | |||
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213 | sample_f2_val <= '0'; | |||
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214 | END IF; | |||
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215 | END IF; | |||
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216 | END PROCESS; | |||
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217 | ||||
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218 | ||||
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219 | ||||
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220 | ----------------------------------------------------------------------------- | |||
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221 | coarse_time <= (OTHERS => '1'); | |||
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222 | ||||
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223 | PROCESS (clk25MHz, rstn) | |||
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224 | BEGIN | |||
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225 | IF rstn = '0' THEN | |||
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226 | fine_time <= (OTHERS => '0'); | |||
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227 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN | |||
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228 | fine_time <= fine_time + 1; | |||
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229 | END IF; | |||
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230 | END PROCESS; | |||
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231 | ||||
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232 | ||||
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233 | sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444"; | |||
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234 | sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444"; | |||
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235 | sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444"; | |||
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236 | ||||
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237 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val); | |||
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238 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val); | |||
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239 | sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val); | |||
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240 | ----------------------------------------------------------------------------- | |||
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241 | ||||
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242 | lpp_lfr_ms_1: lpp_lfr_ms | |||
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243 | GENERIC MAP ( | |||
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244 | Mem_use => use_CEL) | |||
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245 | PORT MAP ( | |||
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246 | clk => clk25MHz, | |||
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247 | rstn => rstn, | |||
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248 | -- | |||
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249 | coarse_time => coarse_time, | |||
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250 | fine_time => fine_time, | |||
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251 | -- | |||
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252 | sample_f0_wen => sample_f0_wen, | |||
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253 | sample_f0_wdata => sample_f0_wdata, | |||
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254 | sample_f1_wen => sample_f1_wen, | |||
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255 | sample_f1_wdata => sample_f1_wdata, | |||
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256 | sample_f2_wen => sample_f2_wen, | |||
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257 | sample_f2_wdata => sample_f2_wdata, | |||
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258 | -- | |||
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259 | dma_addr => dma_addr, | |||
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260 | dma_data => dma_data, | |||
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261 | dma_valid => dma_valid, | |||
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262 | dma_valid_burst => dma_valid_burst, | |||
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263 | dma_ren => dma_ren, | |||
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264 | dma_done => dma_done, | |||
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265 | ||||
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266 | ready_matrix_f0 => ready_matrix_f0, | |||
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267 | -- ready_matrix_f0_1 => ready_matrix_f0_1, | |||
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268 | ready_matrix_f1 => ready_matrix_f1, | |||
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269 | ready_matrix_f2 => ready_matrix_f2, | |||
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270 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |||
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271 | error_bad_component_error => error_bad_component_error, | |||
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272 | error_buffer_full => error_buffer_full, | |||
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273 | error_input_fifo_write => error_input_fifo_write, | |||
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|
274 | ||||
|
|
275 | debug_reg => debug_reg, | |||
|
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276 | ||||
|
|
277 | -- | |||
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|
278 | observation_vector_0 => observation_vector_0, | |||
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279 | observation_vector_1 => observation_vector_1, | |||
|
|
280 | -- | |||
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281 | status_ready_matrix_f0 => status_ready_matrix_f0, | |||
|
|
282 | -- status_ready_matrix_f0 => status_ready_matrix_f0_1, | |||
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283 | status_ready_matrix_f1 => status_ready_matrix_f1, | |||
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284 | status_ready_matrix_f2 => status_ready_matrix_f2, | |||
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285 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |||
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286 | -- status_error_bad_component_error => status_error_bad_component_error, | |||
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287 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |||
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288 | config_active_interruption_onError => config_active_interruption_onError, | |||
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289 | addr_matrix_f0 => addr_matrix_f0, | |||
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290 | -- addr_matrix_f0_1 => addr_matrix_f0_1, | |||
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291 | addr_matrix_f1 => addr_matrix_f1, | |||
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292 | addr_matrix_f2 => addr_matrix_f2, | |||
|
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293 | matrix_time_f0 => matrix_time_f0, | |||
|
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294 | -- matrix_time_f0_1 => matrix_time_f0_1, | |||
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295 | matrix_time_f1 => matrix_time_f1, | |||
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296 | matrix_time_f2 => matrix_time_f2); | |||
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297 | ||||
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298 | ||||
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299 | ||||
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300 | ||||
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301 | ||||
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302 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |||
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303 | GENERIC MAP ( | |||
|
|
304 | nb_data_by_buffer_size => 11, | |||
|
|
305 | nb_word_by_buffer_size => 11, | |||
|
|
306 | nb_snapshot_param_size => 11, | |||
|
|
307 | delta_vector_size => 20, | |||
|
|
308 | delta_vector_size_f0_2 => 7, | |||
|
|
309 | pindex => 4, | |||
|
|
310 | paddr => 4, | |||
|
|
311 | pmask => 16#fff#, | |||
|
|
312 | pirq_ms => 0, | |||
|
|
313 | pirq_wfp => 1, | |||
|
|
314 | top_lfr_version => (OTHERS => '0') | |||
|
|
315 | ) | |||
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|
316 | PORT MAP ( | |||
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317 | HCLK => clk25MHz, | |||
|
|
318 | HRESETn => rstn, | |||
|
|
319 | apbi => apbi, | |||
|
|
320 | apbo => apbo, | |||
|
|
321 | ||||
|
|
322 | run_ms => OPEN, | |||
|
|
323 | ||||
|
|
324 | ready_matrix_f0 => ready_matrix_f0, | |||
|
|
325 | ready_matrix_f1 => ready_matrix_f1, | |||
|
|
326 | ready_matrix_f2 => ready_matrix_f2, | |||
|
|
327 | error_bad_component_error => error_bad_component_error, | |||
|
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328 | error_buffer_full => error_buffer_full, -- TODO | |||
|
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329 | error_input_fifo_write => error_input_fifo_write, -- TODO | |||
|
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330 | status_ready_matrix_f0 => status_ready_matrix_f0, | |||
|
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331 | status_ready_matrix_f1 => status_ready_matrix_f1, | |||
|
|
332 | status_ready_matrix_f2 => status_ready_matrix_f2, | |||
|
|
333 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |||
|
|
334 | config_active_interruption_onError => config_active_interruption_onError, | |||
|
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335 | ||||
|
|
336 | matrix_time_f0 => matrix_time_f0, | |||
|
|
337 | matrix_time_f1 => matrix_time_f1, | |||
|
|
338 | matrix_time_f2 => matrix_time_f2, | |||
|
|
339 | ||||
|
|
340 | addr_matrix_f0 => addr_matrix_f0, | |||
|
|
341 | addr_matrix_f1 => addr_matrix_f1, | |||
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342 | addr_matrix_f2 => addr_matrix_f2, | |||
|
|
343 | ------------------------------------------------------------------------- | |||
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344 | status_full => status_full, | |||
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345 | status_full_ack => status_full_ack, | |||
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346 | status_full_err => status_full_err, | |||
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347 | status_new_err => status_new_err, | |||
|
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348 | data_shaping_BW => OPEN, | |||
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349 | data_shaping_SP0 => OPEN, | |||
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350 | data_shaping_SP1 => OPEN, | |||
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|
351 | data_shaping_R0 => OPEN, | |||
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|
352 | data_shaping_R1 => OPEN, | |||
|
|
353 | delta_snapshot => OPEN, | |||
|
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354 | delta_f0 => OPEN, | |||
|
|
355 | delta_f0_2 => OPEN, | |||
|
|
356 | delta_f1 => OPEN, | |||
|
|
357 | delta_f2 => OPEN, | |||
|
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358 | nb_data_by_buffer => OPEN, | |||
|
|
359 | nb_word_by_buffer => OPEN, | |||
|
|
360 | nb_snapshot_param => OPEN, | |||
|
|
361 | enable_f0 => OPEN, | |||
|
|
362 | enable_f1 => OPEN, | |||
|
|
363 | enable_f2 => OPEN, | |||
|
|
364 | enable_f3 => OPEN, | |||
|
|
365 | burst_f0 => OPEN, | |||
|
|
366 | burst_f1 => OPEN, | |||
|
|
367 | burst_f2 => OPEN, | |||
|
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368 | run => OPEN, | |||
|
|
369 | addr_data_f0 => OPEN, | |||
|
|
370 | addr_data_f1 => OPEN, | |||
|
|
371 | addr_data_f2 => OPEN, | |||
|
|
372 | addr_data_f3 => OPEN, | |||
|
|
373 | start_date => OPEN); | |||
|
|
374 | ||||
|
|
375 | ||||
|
|
376 | ||||
|
|
377 | ||||
|
|
378 | read_status_t <= TRANSPORT apbo.pirq(0) AFTER 200 us; | |||
|
|
379 | ||||
|
|
380 | PROCESS (clk25MHz, rstn) | |||
|
|
381 | BEGIN | |||
|
|
382 | IF rstn = '0' THEN | |||
|
|
383 | ready_reg <= (OTHERS => '0'); | |||
|
|
384 | --read_status <= '0'; | |||
|
|
385 | apbi.psel(4) <= '0'; | |||
|
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386 | apbi.pwrite <= '0'; | |||
|
|
387 | apbi.penable <= '0'; | |||
|
|
388 | apbi.paddr(7 DOWNTO 2) <= (OTHERS => '0'); | |||
|
|
389 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN | |||
|
|
390 | apbi.psel(4) <= '1'; | |||
|
|
391 | apbi.paddr(7 DOWNTO 2) <= "000001"; | |||
|
|
392 | apbi.penable <= '1'; | |||
|
|
393 | read_status <= apbo.pirq(0); | |||
|
|
394 | ||||
|
|
395 | IF read_status = '1' AND irq_ongoing = '0' THEN | |||
|
|
396 | ready_reg <= apbo.prdata(5 DOWNTO 0); | |||
|
|
397 | irq_ongoing <= '1'; | |||
|
|
398 | END IF; | |||
|
|
399 | ||||
|
|
400 | IF read_status_t = '0' THEN | |||
|
|
401 | apbi.pwrite <= '0'; | |||
|
|
402 | ELSE | |||
|
|
403 | irq_ongoing <= '0'; | |||
|
|
404 | apbi.pwrite <= '1'; | |||
|
|
405 | apbi.pwdata(31 DOWNTO 6) <= (OTHERS => '0'); | |||
|
|
406 | apbi.pwdata(5 DOWNTO 0) <= ready_reg; | |||
|
|
407 | ready_reg <= (OTHERS => '0'); | |||
|
|
408 | END IF; | |||
|
|
409 | ||||
|
|
410 | END IF; | |||
|
|
411 | END PROCESS; | |||
|
|
412 | ||||
|
|
413 | ||||
|
|
414 | ||||
|
|
415 | ||||
|
|
416 | ||||
|
|
417 | ||||
|
|
418 | ||||
|
|
419 | ||||
|
|
420 | ||||
|
|
421 | ||||
|
|
422 | -- PROCESS (clk25MHz, rstn) | |||
|
|
423 | -- BEGIN -- PROCESS | |||
|
|
424 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
425 | -- status_ready_matrix_f0 <= '0'; | |||
|
|
426 | ---- status_ready_matrix_f0_1 <= '0'; | |||
|
|
427 | -- status_ready_matrix_f1 <= '0'; | |||
|
|
428 | -- status_ready_matrix_f2 <= '0'; | |||
|
|
429 | -- ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge | |||
|
|
430 | -- status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0; | |||
|
|
431 | ---- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |||
|
|
432 | -- status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1; | |||
|
|
433 | -- status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2; | |||
|
|
434 | -- END IF; | |||
|
|
435 | -- END PROCESS; | |||
|
|
436 | ||||
|
|
437 | ||||
|
|
438 | ||||
|
|
439 | -- status_error_anticipating_empty_fifo <= '0'; | |||
|
|
440 | -- status_error_bad_component_error <= '0'; | |||
|
|
441 | ||||
|
|
442 | -- config_active_interruption_onNewMatrix <= '0'; | |||
|
|
443 | -- config_active_interruption_onError <= '0'; | |||
|
|
444 | -- addr_matrix_f0 <= (OTHERS => '0'); | |||
|
|
445 | -- addr_matrix_f0_1 <= (OTHERS => '0'); | |||
|
|
446 | -- addr_matrix_f1 <= (OTHERS => '0'); | |||
|
|
447 | -- addr_matrix_f2 <= (OTHERS => '0'); | |||
|
|
448 | ||||
|
|
449 | ||||
|
|
450 | PROCESS (clk25MHz, rstn) | |||
|
|
451 | BEGIN -- PROCESS | |||
|
|
452 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
453 | ||||
|
|
454 | dma_ren <= '1'; | |||
|
|
455 | dma_done <= '0'; | |||
|
|
456 | ren_counter <= 0; | |||
|
|
457 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge | |||
|
|
458 | dma_ren <= '1'; | |||
|
|
459 | dma_done <= '0'; | |||
|
|
460 | ||||
|
|
461 | IF dma_valid_burst = '1' THEN | |||
|
|
462 | ren_counter <= 17; | |||
|
|
463 | END IF; | |||
|
|
464 | ||||
|
|
465 | IF ren_counter > 1 THEN | |||
|
|
466 | ren_counter <= ren_counter - 1; | |||
|
|
467 | dma_ren <= '0'; | |||
|
|
468 | END IF; | |||
|
|
469 | ||||
|
|
470 | IF ren_counter = 1 THEN | |||
|
|
471 | ren_counter <= 0; | |||
|
|
472 | dma_done <= '1'; | |||
|
|
473 | END IF; | |||
|
|
474 | ||||
|
|
475 | END IF; | |||
|
|
476 | END PROCESS; | |||
|
|
477 | ||||
|
|
478 | ||||
|
|
479 | END beh; | |||
|
|
480 | ||||
| @@ -0,0 +1,41 | |||||
|
|
1 | onerror {resume} | |||
|
|
2 | quietly WaveActivateNextPane {} 0 | |||
|
|
3 | add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/cnv_clk | |||
|
|
4 | add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/cnv_rstn | |||
|
|
5 | add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/rstn | |||
|
|
6 | add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/adc_data | |||
|
|
7 | add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/clk | |||
|
|
8 | add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/adc_data_v | |||
|
|
9 | add wave -noupdate -expand -group CNV_GEN /top_ad_conv_rhf1401_withfilter_tb/dut/cnv_cycle_counter | |||
|
|
10 | add wave -noupdate -expand -group CNV_GEN /top_ad_conv_rhf1401_withfilter_tb/dut/cnv_s | |||
|
|
11 | add wave -noupdate -expand -group CNV_GEN /top_ad_conv_rhf1401_withfilter_tb/cnv | |||
|
|
12 | add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/dut/cnv_sync | |||
|
|
13 | add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/dut/cnv_sync_pre | |||
|
|
14 | add wave -noupdate -expand -group DATA_GEN_OutputEnable -radix hexadecimal /top_ad_conv_rhf1401_withfilter_tb/dut/adc_noe_reg | |||
|
|
15 | add wave -noupdate -expand -group DATA_GEN_OutputEnable /top_ad_conv_rhf1401_withfilter_tb/dut/enable_adc | |||
|
|
16 | add wave -noupdate -radix hexadecimal /top_ad_conv_rhf1401_withfilter_tb/adc_noe | |||
|
|
17 | add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/dut/channel_counter | |||
|
|
18 | add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/dut/sample_reg | |||
|
|
19 | add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/sample_val | |||
|
|
20 | add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/dut/sample_counter | |||
|
|
21 | add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/dut/adc_data_selected | |||
|
|
22 | add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/dut/adc_data_result | |||
|
|
23 | add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/sample_val | |||
|
|
24 | add wave -noupdate -radix hexadecimal /top_ad_conv_rhf1401_withfilter_tb/sample | |||
|
|
25 | TreeUpdate [SetDefaultTree] | |||
|
|
26 | WaveRestoreCursors {{Cursor 1} {875312 ps} 0} {{Cursor 2} {200000 ps} 0} | |||
|
|
27 | configure wave -namecolwidth 403 | |||
|
|
28 | configure wave -valuecolwidth 198 | |||
|
|
29 | configure wave -justifyvalue left | |||
|
|
30 | configure wave -signalnamewidth 0 | |||
|
|
31 | configure wave -snapdistance 10 | |||
|
|
32 | configure wave -datasetprefix 0 | |||
|
|
33 | configure wave -rowmargin 4 | |||
|
|
34 | configure wave -childrowmargin 2 | |||
|
|
35 | configure wave -gridoffset 0 | |||
|
|
36 | configure wave -gridperiod 1 | |||
|
|
37 | configure wave -griddelta 40 | |||
|
|
38 | configure wave -timeline 0 | |||
|
|
39 | configure wave -timelineunits ps | |||
|
|
40 | update | |||
|
|
41 | WaveRestoreZoom {0 ps} {1050 us} | |||
| @@ -0,0 +1,53 | |||||
|
|
1 | #GRLIB=../.. | |||
|
|
2 | VHDLIB=../.. | |||
|
|
3 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |||
|
|
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |||
|
|
5 | TOP=leon3mp | |||
|
|
6 | BOARD=em-LeonLPP-A3PE3kL-v3-core1 | |||
|
|
7 | include $(GRLIB)/boards/$(BOARD)/Makefile.inc | |||
|
|
8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |||
|
|
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |||
|
|
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |||
|
|
11 | EFFORT=high | |||
|
|
12 | XSTOPT= | |||
|
|
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |||
|
|
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |||
|
|
15 | VHDLSYNFILES= | |||
|
|
16 | VHDLSIMFILES= tb.vhd | |||
|
|
17 | SIMTOP=testbench | |||
|
|
18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |||
|
|
19 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc | |||
|
|
20 | PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc | |||
|
|
21 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut | |||
|
|
22 | CLEAN=soft-clean | |||
|
|
23 | ||||
|
|
24 | TECHLIBS = proasic3e | |||
|
|
25 | ||||
|
|
26 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |||
|
|
27 | tmtc openchip hynix ihp gleichmann micron usbhc | |||
|
|
28 | ||||
|
|
29 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |||
|
|
30 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ | |||
|
|
31 | ./amba_lcd_16x2_ctrlr \ | |||
|
|
32 | ./general_purpose/lpp_AMR \ | |||
|
|
33 | ./general_purpose/lpp_balise \ | |||
|
|
34 | ./general_purpose/lpp_delay \ | |||
|
|
35 | ./lpp_bootloader \ | |||
|
|
36 | ./lpp_cna \ | |||
|
|
37 | ./lpp_uart \ | |||
|
|
38 | ./lpp_usb \ | |||
|
|
39 | ./dsp/lpp_fft_rtax \ | |||
|
|
40 | ||||
|
|
41 | FILESKIP = i2cmst.vhd \ | |||
|
|
42 | APB_MULTI_DIODE.vhd \ | |||
|
|
43 | APB_MULTI_DIODE.vhd \ | |||
|
|
44 | Top_MatrixSpec.vhd \ | |||
|
|
45 | APB_FFT.vhd \ | |||
|
|
46 | lpp_lfr_apbreg.vhd \ | |||
|
|
47 | CoreFFT.vhd | |||
|
|
48 | ||||
|
|
49 | include $(GRLIB)/bin/Makefile | |||
|
|
50 | include $(GRLIB)/software/leon3/Makefile | |||
|
|
51 | ||||
|
|
52 | ################## project specific targets ########################## | |||
|
|
53 | ||||
| @@ -0,0 +1,9 | |||||
|
|
1 | vcom -quiet -93 -work work tb.vhd | |||
|
|
2 | ||||
|
|
3 | vsim work.testbench | |||
|
|
4 | ||||
|
|
5 | log -r * | |||
|
|
6 | ||||
|
|
7 | do wave.do | |||
|
|
8 | ||||
|
|
9 | run -all | |||
| This diff has been collapsed as it changes many lines, (507 lines changed) Show them Hide them | |||||
| @@ -0,0 +1,507 | |||||
|
|
1 | ||||
|
|
2 | LIBRARY ieee; | |||
|
|
3 | USE ieee.std_logic_1164.ALL; | |||
|
|
4 | USE IEEE.MATH_REAL.ALL; | |||
|
|
5 | USE ieee.numeric_std.ALL; | |||
|
|
6 | ||||
|
|
7 | LIBRARY lpp; | |||
|
|
8 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
|
9 | ||||
|
|
10 | ENTITY testbench IS | |||
|
|
11 | END; | |||
|
|
12 | ||||
|
|
13 | ARCHITECTURE behav OF testbench IS | |||
|
|
14 | ||||
|
|
15 | ----------------------------------------------------------------------------- | |||
|
|
16 | -- Common signal | |||
|
|
17 | SIGNAL clk : STD_LOGIC := '0'; | |||
|
|
18 | SIGNAL rstn : STD_LOGIC := '0'; | |||
|
|
19 | SIGNAL run : STD_LOGIC := '0'; | |||
|
|
20 | ||||
|
|
21 | ----------------------------------------------------------------------------- | |||
|
|
22 | TYPE DATA_FIFO_VECTOR IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
23 | SIGNAL data_out_obs : DATA_FIFO_VECTOR; | |||
|
|
24 | ||||
|
|
25 | SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
26 | SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
27 | SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
28 | SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
29 | ||||
|
|
30 | SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b | |||
|
|
31 | SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
32 | SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
33 | SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
34 | ||||
|
|
35 | SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
36 | SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
37 | SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
38 | SIGNAL data_out : DATA_FIFO_VECTOR; | |||
|
|
39 | ||||
|
|
40 | SIGNAL empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
41 | SIGNAL full_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
42 | ----------------------------------------------------------------------------- | |||
|
|
43 | TYPE DATA_CHANNEL IS ARRAY (0 TO 128/4-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
|
44 | TYPE DATA_ARRAY IS ARRAY (0 TO 3) OF DATA_CHANNEL; | |||
|
|
45 | SIGNAL data_in : DATA_ARRAY; | |||
|
|
46 | ||||
|
|
47 | ----------------------------------------------------------------------------- | |||
|
|
48 | CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1+2+2; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE | |||
|
|
49 | CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0; | |||
|
|
50 | SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
51 | -- | |||
|
|
52 | SIGNAL rand_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
53 | SIGNAL rand_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
54 | ||||
|
|
55 | TYPE POINTER IS ARRAY (0 TO 3) OF INTEGER; | |||
|
|
56 | SIGNAL pointer_read : POINTER; | |||
|
|
57 | SIGNAL pointer_write : POINTER := (0, 0, 0, 0); | |||
|
|
58 | ||||
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59 | --SIGNAL data_f0_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
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60 | --SIGNAL data_f0_data_out_obs : STD_LOGIC; | |||
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61 | --SIGNAL data_f1_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
62 | --SIGNAL data_f1_data_out_obs : STD_LOGIC; | |||
|
|
63 | --SIGNAL data_f2_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
|
64 | --SIGNAL data_f2_data_out_obs : STD_LOGIC; | |||
|
|
65 | --SIGNAL data_f3_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
|
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66 | --SIGNAL data_f3_data_out_obs : STD_LOGIC; | |||
|
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67 | SIGNAL error_now : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
|
68 | SIGNAL error_new : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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69 | ||||
|
|
70 | SIGNAL read_stop : STD_LOGIC; | |||
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71 | ||||
|
|
72 | -- SIGNAL empty_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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73 | ||||
|
|
74 | ----------------------------------------------------------------------------- | |||
|
|
75 | BEGIN | |||
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76 | ||||
|
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77 | all_I : FOR I IN 0 TO 3 GENERATE | |||
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78 | all_J : FOR J IN 0 TO 128/4-1 GENERATE | |||
|
|
79 | data_in(I)(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+I*(2**28)+1, 32)); | |||
|
|
80 | END GENERATE all_J; | |||
|
|
81 | END GENERATE all_I; | |||
|
|
82 | ||||
|
|
83 | ||||
|
|
84 | ----------------------------------------------------------------------------- | |||
|
|
85 | lpp_waveform_fifo_1 : lpp_waveform_fifo | |||
|
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86 | GENERIC MAP (tech => 0) | |||
|
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87 | PORT MAP ( | |||
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88 | clk => clk, | |||
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89 | rstn => rstn, | |||
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90 | run => run, | |||
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91 | ||||
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92 | empty => s_empty, | |||
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93 | empty_almost => s_empty_almost, | |||
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94 | data_ren => s_data_ren, | |||
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95 | rdata => s_rdata, | |||
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96 | ||||
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97 | full_almost => full_almost, | |||
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98 | full => full, | |||
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99 | data_wen => data_wen, | |||
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100 | wdata => wdata); | |||
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101 | ||||
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102 | lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg | |||
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103 | GENERIC MAP (tech => 0) | |||
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104 | PORT MAP ( | |||
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105 | clk => clk, | |||
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106 | rstn => rstn, | |||
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107 | run => run, | |||
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108 | o_empty_almost => empty_almost, | |||
|
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109 | o_empty => empty, | |||
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110 | ||||
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111 | o_data_ren => data_ren, | |||
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112 | o_rdata_0 => data_out(0), | |||
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113 | o_rdata_1 => data_out(1), | |||
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114 | o_rdata_2 => data_out(2), | |||
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115 | o_rdata_3 => data_out(3), | |||
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116 | ||||
|
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117 | i_empty_almost => s_empty_almost, | |||
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118 | i_empty => s_empty, | |||
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119 | i_data_ren => s_data_ren, | |||
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120 | i_rdata => s_rdata); | |||
|
|
121 | ----------------------------------------------------------------------------- | |||
|
|
122 | ||||
|
|
123 | ||||
|
|
124 | ||||
|
|
125 | ----------------------------------------------------------------------------- | |||
|
|
126 | all_data_channel: FOR I IN 0 TO 3 GENERATE | |||
|
|
127 | ----------------------------------------------------------------------------- | |||
|
|
128 | -- READ | |||
|
|
129 | ----------------------------------------------------------------------------- | |||
|
|
130 | ||||
|
|
131 | PROCESS (clk, rstn) | |||
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132 | BEGIN -- PROCESS | |||
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133 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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134 | empty_reg(I) <= '1'; | |||
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135 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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136 | empty_reg(I) <= empty(I); | |||
|
|
137 | END IF; | |||
|
|
138 | END PROCESS; | |||
|
|
139 | ||||
|
|
140 | PROCESS (clk, rstn) | |||
|
|
141 | BEGIN -- PROCESS | |||
|
|
142 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
143 | data_out_obs(I) <= (OTHERS => '0'); | |||
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|
144 | ||||
|
|
145 | pointer_read(I) <= 0; | |||
|
|
146 | error_now(I) <= '0'; | |||
|
|
147 | error_new(I) <= '0'; | |||
|
|
148 | ||||
|
|
149 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
150 | error_now(I) <= '0'; | |||
|
|
151 | IF empty_reg(I) = '0' THEN | |||
|
|
152 | IF data_ren(I) = '0' THEN | |||
|
|
153 | ||||
|
|
154 | error_new(I) <= '0'; | |||
|
|
155 | data_out_obs(I) <= data_out(I); | |||
|
|
156 | ||||
|
|
157 | IF pointer_read(I) < 128/4-1 THEN | |||
|
|
158 | pointer_read(I) <= pointer_read(I) + 1; | |||
|
|
159 | ELSE | |||
|
|
160 | pointer_read(I) <= 0; | |||
|
|
161 | END IF; | |||
|
|
162 | ||||
|
|
163 | IF data_out(I) /= data_in(I)(pointer_read(I)) THEN | |||
|
|
164 | error_now(I) <= '1'; | |||
|
|
165 | error_new(I) <= '1'; | |||
|
|
166 | END IF; | |||
|
|
167 | END IF; | |||
|
|
168 | ||||
|
|
169 | END IF; | |||
|
|
170 | END IF; | |||
|
|
171 | END PROCESS; | |||
|
|
172 | ||||
|
|
173 | ----------------------------------------------------------------------------- | |||
|
|
174 | -- WRITE | |||
|
|
175 | ----------------------------------------------------------------------------- | |||
|
|
176 | PROCESS (clk, rstn) | |||
|
|
177 | BEGIN -- PROCESS | |||
|
|
178 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
179 | full_reg(I) <= '0'; | |||
|
|
180 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
181 | full_reg(I) <= full(I); | |||
|
|
182 | END IF; | |||
|
|
183 | END PROCESS; | |||
|
|
184 | ||||
|
|
185 | PROCESS (clk, rstn) | |||
|
|
186 | BEGIN -- PROCESS proc_verif | |||
|
|
187 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
188 | pointer_write(I) <= 0; | |||
|
|
189 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
190 | IF data_wen(I) = '0' THEN | |||
|
|
191 | IF full_reg(I) = '0' THEN | |||
|
|
192 | IF pointer_write(I) < 128/4-1 THEN | |||
|
|
193 | pointer_write(I) <= pointer_write(I)+1; | |||
|
|
194 | ELSE | |||
|
|
195 | pointer_write(I) <= 0; | |||
|
|
196 | END IF; | |||
|
|
197 | END IF; | |||
|
|
198 | END IF; | |||
|
|
199 | END IF; | |||
|
|
200 | END PROCESS; | |||
|
|
201 | END GENERATE all_data_channel; | |||
|
|
202 | ||||
|
|
203 | wdata <= data_in(0)(pointer_write(0)) WHEN data_wen = "1110" ELSE | |||
|
|
204 | data_in(1)(pointer_write(1)) WHEN data_wen = "1101" ELSE | |||
|
|
205 | data_in(2)(pointer_write(2)) WHEN data_wen = "1011" ELSE | |||
|
|
206 | data_in(3)(pointer_write(3)) WHEN data_wen = "0111" ELSE | |||
|
|
207 | (OTHERS => 'X'); | |||
|
|
208 | ||||
|
|
209 | ----------------------------------------------------------------------------- | |||
|
|
210 | ||||
|
|
211 | ||||
|
|
212 | ||||
|
|
213 | ----------------------------------------------------------------------------- | |||
|
|
214 | clk <= NOT clk AFTER 5 ns; -- 100 MHz | |||
|
|
215 | ----------------------------------------------------------------------------- | |||
|
|
216 | WaveGen_Proc : PROCESS | |||
|
|
217 | BEGIN | |||
|
|
218 | -- insert signal assignments here | |||
|
|
219 | WAIT UNTIL clk = '1'; | |||
|
|
220 | read_stop <= '0'; | |||
|
|
221 | rstn <= '0'; | |||
|
|
222 | run <= '0'; | |||
|
|
223 | WAIT UNTIL clk = '1'; | |||
|
|
224 | WAIT UNTIL clk = '1'; | |||
|
|
225 | WAIT UNTIL clk = '1'; | |||
|
|
226 | rstn <= '1'; | |||
|
|
227 | WAIT UNTIL clk = '1'; | |||
|
|
228 | WAIT UNTIL clk = '1'; | |||
|
|
229 | WAIT UNTIL clk = '1'; | |||
|
|
230 | WAIT UNTIL clk = '1'; | |||
|
|
231 | WAIT UNTIL clk = '1'; | |||
|
|
232 | run <= '1'; | |||
|
|
233 | WAIT UNTIL clk = '1'; | |||
|
|
234 | WAIT UNTIL clk = '1'; | |||
|
|
235 | WAIT UNTIL clk = '1'; | |||
|
|
236 | WAIT UNTIL clk = '1'; | |||
|
|
237 | WAIT FOR 10 us; | |||
|
|
238 | read_stop <= '1'; | |||
|
|
239 | WAIT FOR 10 us; | |||
|
|
240 | read_stop <= '0'; | |||
|
|
241 | WAIT FOR 80 us; | |||
|
|
242 | REPORT "*** END simulation ***" SEVERITY failure; | |||
|
|
243 | WAIT; | |||
|
|
244 | END PROCESS WaveGen_Proc; | |||
|
|
245 | ----------------------------------------------------------------------------- | |||
|
|
246 | ||||
|
|
247 | ||||
|
|
248 | ||||
|
|
249 | ||||
|
|
250 | ||||
|
|
251 | ----------------------------------------------------------------------------- | |||
|
|
252 | -- RANDOM GENERATOR | |||
|
|
253 | ----------------------------------------------------------------------------- | |||
|
|
254 | PROCESS (clk, rstn) | |||
|
|
255 | VARIABLE seed1, seed2 : POSITIVE; | |||
|
|
256 | VARIABLE rand1 : REAL; | |||
|
|
257 | VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); | |||
|
|
258 | BEGIN -- PROCESS | |||
|
|
259 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
260 | random_vector <= (OTHERS => '0'); | |||
|
|
261 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
262 | UNIFORM(seed1, seed2, rand1); | |||
|
|
263 | RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR( | |||
|
|
264 | to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)), | |||
|
|
265 | RANDOM_VECTOR_VAR'LENGTH) | |||
|
|
266 | ); | |||
|
|
267 | ||||
|
|
268 | random_vector <= RANDOM_VECTOR_VAR; | |||
|
|
269 | END IF; | |||
|
|
270 | END PROCESS; | |||
|
|
271 | ----------------------------------------------------------------------------- | |||
|
|
272 | rand_ren <= "1111" WHEN random_vector(0) = '0' ELSE | |||
|
|
273 | "1110" WHEN random_vector(2 DOWNTO 1) = "00" ELSE | |||
|
|
274 | "1101" WHEN random_vector(2 DOWNTO 1) = "01" ELSE | |||
|
|
275 | "1011" WHEN random_vector(2 DOWNTO 1) = "10" ELSE | |||
|
|
276 | "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE | |||
|
|
277 | ||||
|
|
278 | rand_wen <= "1111" WHEN random_vector(3) = '0' ELSE | |||
|
|
279 | "1110" WHEN random_vector(5 DOWNTO 4) = "00" ELSE | |||
|
|
280 | "1101" WHEN random_vector(5 DOWNTO 4) = "01" ELSE | |||
|
|
281 | "1011" WHEN random_vector(5 DOWNTO 4) = "10" ELSE | |||
|
|
282 | "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE | |||
|
|
283 | ----------------------------------------------------------------------------- | |||
|
|
284 | PROCESS (clk, rstn) | |||
|
|
285 | BEGIN -- PROCESS | |||
|
|
286 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
287 | data_wen <= (OTHERS => '1'); | |||
|
|
288 | data_ren <= (OTHERS => '1'); | |||
|
|
289 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
290 | data_wen <= rand_wen; | |||
|
|
291 | IF read_stop = '0' THEN | |||
|
|
292 | all_ren_bits: FOR I IN 0 TO 3 LOOP | |||
|
|
293 | IF empty(I) = '1' THEN | |||
|
|
294 | data_ren(I) <= '1'; | |||
|
|
295 | ELSE | |||
|
|
296 | data_ren(I) <= rand_ren(I); | |||
|
|
297 | END IF; | |||
|
|
298 | END LOOP all_ren_bits; | |||
|
|
299 | ELSE | |||
|
|
300 | data_ren <= (OTHERS => '1') ; | |||
|
|
301 | END IF; | |||
|
|
302 | END IF; | |||
|
|
303 | END PROCESS; | |||
|
|
304 | ----------------------------------------------------------------------------- | |||
|
|
305 | ||||
|
|
306 | ||||
|
|
307 | --PROCESS (clk, rstn) | |||
|
|
308 | --BEGIN -- PROCESS | |||
|
|
309 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
310 | -- empty <= (OTHERS => '1'); | |||
|
|
311 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
312 | -- empty <= empty_s; | |||
|
|
313 | -- END IF; | |||
|
|
314 | --END PROCESS; | |||
|
|
315 | ||||
|
|
316 | ||||
|
|
317 | --PROCESS (clk, rstn) | |||
|
|
318 | --BEGIN -- PROCESS | |||
|
|
319 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
320 | -- data_f0_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
321 | -- data_f1_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
322 | -- data_f2_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
323 | -- data_f3_data_out_obs_data <= (OTHERS => '0'); | |||
|
|
324 | -- data_f0_data_out_obs <= '0'; | |||
|
|
325 | -- data_f1_data_out_obs <= '0'; | |||
|
|
326 | -- data_f2_data_out_obs <= '0'; | |||
|
|
327 | -- data_f3_data_out_obs <= '0'; | |||
|
|
328 | ||||
|
|
329 | -- pointer_read <= (0, 0, 0, 0); | |||
|
|
330 | -- error_now <= (OTHERS => '0'); | |||
|
|
331 | -- error_new <= (OTHERS => '0'); | |||
|
|
332 | ||||
|
|
333 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
|
334 | -- error_now <= (OTHERS => '0'); | |||
|
|
335 | -- CASE data_ren IS | |||
|
|
336 | -- WHEN "1110" => | |||
|
|
337 | -- IF empty(0) = '0' THEN | |||
|
|
338 | -- error_new(0) <= '0'; | |||
|
|
339 | -- data_f0_data_out_obs_data <= data_f0_data_out(5 DOWNTO 0); | |||
|
|
340 | -- IF pointer_read(0) < 31 THEN | |||
|
|
341 | -- pointer_read(0) <= pointer_read(0)+1; | |||
|
|
342 | -- ELSE | |||
|
|
343 | -- pointer_read(0) <= 0; | |||
|
|
344 | -- END IF; | |||
|
|
345 | -- IF data_f0_data_out /= data_in(0)(pointer_read(0)) THEN | |||
|
|
346 | -- error_now(0) <= '1'; | |||
|
|
347 | -- error_new(0) <= '1'; | |||
|
|
348 | -- data_f0_data_out_obs <= '1'; | |||
|
|
349 | -- END IF; | |||
|
|
350 | -- --IF data_f0_data_out(29 DOWNTO 28) /= "00" THEN | |||
|
|
351 | -- -- data_f0_data_out_obs <= '1'; | |||
|
|
352 | -- --END IF; | |||
|
|
353 | -- END IF; | |||
|
|
354 | ||||
|
|
355 | -- WHEN "1101" => | |||
|
|
356 | -- IF empty(1) = '0' THEN | |||
|
|
357 | -- error_new(1) <= '0'; | |||
|
|
358 | -- data_f1_data_out_obs_data <= data_f1_data_out(5 DOWNTO 0); | |||
|
|
359 | -- IF pointer_read(1) < 31 THEN | |||
|
|
360 | -- pointer_read(1) <= pointer_read(1)+1; | |||
|
|
361 | -- ELSE | |||
|
|
362 | -- pointer_read(1) <= 0; | |||
|
|
363 | -- END IF; | |||
|
|
364 | -- IF data_f1_data_out /= data_in(1)(pointer_read(1)) THEN | |||
|
|
365 | -- error_new(1) <= '1'; | |||
|
|
366 | -- error_now(1) <= '1'; | |||
|
|
367 | -- data_f1_data_out_obs <= '1'; | |||
|
|
368 | -- END IF; | |||
|
|
369 | -- END IF; | |||
|
|
370 | -- WHEN "1011" => | |||
|
|
371 | -- IF empty(2) = '0' THEN | |||
|
|
372 | -- error_new(2) <= '0'; | |||
|
|
373 | -- data_f2_data_out_obs_data <= data_f2_data_out(5 DOWNTO 0); | |||
|
|
374 | -- IF pointer_read(2) < 31 THEN | |||
|
|
375 | -- pointer_read(2) <= pointer_read(2)+1; | |||
|
|
376 | -- ELSE | |||
|
|
377 | -- pointer_read(2) <= 0; | |||
|
|
378 | -- END IF; | |||
|
|
379 | -- IF data_f2_data_out /= data_in(2)(pointer_read(2)) THEN | |||
|
|
380 | -- error_new(2) <= '1'; | |||
|
|
381 | -- error_now(2) <= '1'; | |||
|
|
382 | -- data_f2_data_out_obs <= '1'; | |||
|
|
383 | -- END IF; | |||
|
|
384 | -- END IF; | |||
|
|
385 | -- WHEN "0111" => | |||
|
|
386 | -- IF empty(3) = '0' THEN | |||
|
|
387 | -- error_new(3) <= '0'; | |||
|
|
388 | -- data_f3_data_out_obs_data <= data_f3_data_out(5 DOWNTO 0); | |||
|
|
389 | -- IF pointer_read(3) < 31 THEN | |||
|
|
390 | -- pointer_read(3) <= pointer_read(3)+1; | |||
|
|
391 | -- ELSE | |||
|
|
392 | -- pointer_read(3) <= 0; | |||
|
|
393 | -- END IF; | |||
|
|
394 | -- IF data_f3_data_out /= data_in(3)(pointer_read(3)) THEN | |||
|
|
395 | -- error_new(3) <= '1'; | |||
|
|
396 | -- error_now(3) <= '1'; | |||
|
|
397 | -- data_f3_data_out_obs <= '1'; | |||
|
|
398 | -- END IF; | |||
|
|
399 | -- END IF; | |||
|
|
400 | -- WHEN "1111" => | |||
|
|
401 | -- NULL; | |||
|
|
402 | ||||
|
|
403 | ||||
|
|
404 | -- WHEN OTHERS => | |||
|
|
405 | -- REPORT "*** ERROR_DATA_REN ***" SEVERITY failure; | |||
|
|
406 | -- NULL; | |||
|
|
407 | -- END CASE; | |||
|
|
408 | ||||
|
|
409 | -- END IF; | |||
|
|
410 | --END PROCESS; | |||
|
|
411 | ||||
|
|
412 | ||||
|
|
413 | ------------------------------------------------------------------------------- | |||
|
|
414 | --clk <= NOT clk AFTER 5 ns; -- 100 MHz | |||
|
|
415 | ||||
|
|
416 | ------------------------------------------------------------------------------- | |||
|
|
417 | --WaveGen_Proc : PROCESS | |||
|
|
418 | --BEGIN | |||
|
|
419 | ||||
|
|
420 | -- -- insert signal assignments here | |||
|
|
421 | -- WAIT UNTIL clk = '1'; | |||
|
|
422 | -- rstn <= '0'; | |||
|
|
423 | -- run <= '0'; | |||
|
|
424 | -- WAIT UNTIL clk = '1'; | |||
|
|
425 | -- WAIT UNTIL clk = '1'; | |||
|
|
426 | -- WAIT UNTIL clk = '1'; | |||
|
|
427 | -- rstn <= '1'; | |||
|
|
428 | -- WAIT UNTIL clk = '1'; | |||
|
|
429 | -- WAIT UNTIL clk = '1'; | |||
|
|
430 | -- WAIT UNTIL clk = '1'; | |||
|
|
431 | -- WAIT UNTIL clk = '1'; | |||
|
|
432 | -- WAIT UNTIL clk = '1'; | |||
|
|
433 | -- run <= '1'; | |||
|
|
434 | -- WAIT UNTIL clk = '1'; | |||
|
|
435 | -- WAIT UNTIL clk = '1'; | |||
|
|
436 | -- WAIT UNTIL clk = '1'; | |||
|
|
437 | -- WAIT UNTIL clk = '1'; | |||
|
|
438 | ||||
|
|
439 | -- WAIT FOR 100 us; | |||
|
|
440 | -- REPORT "*** END simulation ***" SEVERITY failure; | |||
|
|
441 | -- WAIT; | |||
|
|
442 | ||||
|
|
443 | --END PROCESS WaveGen_Proc; | |||
|
|
444 | ||||
|
|
445 | ------------------------------------------------------------------------------- | |||
|
|
446 | --proc_verif : PROCESS (clk, rstn) | |||
|
|
447 | --BEGIN -- PROCESS proc_verif | |||
|
|
448 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
|
449 | -- pointer_write <= (0, 0, 0, 0); | |||
|
|
450 | -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
|
451 | -- --IF rand_wen = "1111" THEN | |||
|
|
452 | -- CASE rand_wen IS | |||
|
|
453 | -- WHEN "1110" => | |||
|
|
454 | -- IF full(0) = '0' THEN | |||
|
|
455 | -- IF pointer_write(0) = 128/4-1 THEN | |||
|
|
456 | -- pointer_write(0) <= 0; | |||
|
|
457 | -- ELSE | |||
|
|
458 | -- pointer_write(0) <= pointer_write(0)+1; | |||
|
|
459 | -- END IF; | |||
|
|
460 | -- END IF; | |||
|
|
461 | ||||
|
|
462 | -- WHEN "1101" => | |||
|
|
463 | -- IF full(1) = '0' THEN | |||
|
|
464 | -- IF pointer_write(1) = 128/4-1 THEN | |||
|
|
465 | -- pointer_write(1) <= 0; | |||
|
|
466 | -- ELSE | |||
|
|
467 | -- pointer_write(1) <= pointer_write(1)+1; | |||
|
|
468 | -- END IF; | |||
|
|
469 | -- END IF; | |||
|
|
470 | ||||
|
|
471 | -- WHEN "1011" => | |||
|
|
472 | -- IF full(2) = '0' THEN | |||
|
|
473 | -- IF pointer_write(2) = 128/4-1 THEN | |||
|
|
474 | -- pointer_write(2) <= 0; | |||
|
|
475 | -- ELSE | |||
|
|
476 | -- pointer_write(2) <= pointer_write(2)+1; | |||
|
|
477 | -- END IF; | |||
|
|
478 | -- END IF; | |||
|
|
479 | -- WHEN "0111" => | |||
|
|
480 | -- IF full(3) = '0' THEN | |||
|
|
481 | -- IF pointer_write(3) = 128/4-1 THEN | |||
|
|
482 | -- pointer_write(3) <= 0; | |||
|
|
483 | -- ELSE | |||
|
|
484 | -- pointer_write(3) <= pointer_write(3)+1; | |||
|
|
485 | -- END IF; | |||
|
|
486 | -- END IF; | |||
|
|
487 | -- WHEN OTHERS => NULL; | |||
|
|
488 | -- END CASE; | |||
|
|
489 | ||||
|
|
490 | -- --END IF; | |||
|
|
491 | -- END IF; | |||
|
|
492 | --END PROCESS proc_verif; | |||
|
|
493 | ||||
|
|
494 | --wdata <= data_in(0)(pointer_write(0)) WHEN rand_wen(0) = '0' ELSE | |||
|
|
495 | -- data_in(1)(pointer_write(1)) WHEN rand_wen(1) = '0' ELSE | |||
|
|
496 | -- data_in(2)(pointer_write(2)) WHEN rand_wen(2) = '0' ELSE | |||
|
|
497 | -- data_in(3)(pointer_write(3)) WHEN rand_wen(3) = '0' ELSE | |||
|
|
498 | -- (OTHERS => '0'); | |||
|
|
499 | ||||
|
|
500 | --data_wen <= rand_wen; | |||
|
|
501 | ||||
|
|
502 | --data_ren <= rand_ren OR empty; | |||
|
|
503 | ||||
|
|
504 | ||||
|
|
505 | ||||
|
|
506 | ||||
|
|
507 | END; | |||
| @@ -0,0 +1,47 | |||||
|
|
1 | onerror {resume} | |||
|
|
2 | quietly WaveActivateNextPane {} 0 | |||
|
|
3 | add wave -noupdate /testbench/clk | |||
|
|
4 | add wave -noupdate /testbench/rstn | |||
|
|
5 | add wave -noupdate /testbench/run | |||
|
|
6 | add wave -noupdate -expand -group FIFO_IN /testbench/full_almost | |||
|
|
7 | add wave -noupdate -expand -group FIFO_IN /testbench/full | |||
|
|
8 | add wave -noupdate -expand -group FIFO_IN -expand /testbench/data_wen | |||
|
|
9 | add wave -noupdate -expand -group FIFO_IN -radix hexadecimal /testbench/wdata | |||
|
|
10 | add wave -noupdate -expand -group internal /testbench/s_empty_almost | |||
|
|
11 | add wave -noupdate -expand -group internal -expand /testbench/s_empty | |||
|
|
12 | add wave -noupdate -expand -group internal -expand /testbench/s_data_ren | |||
|
|
13 | add wave -noupdate -expand -group internal -radix hexadecimal /testbench/s_rdata | |||
|
|
14 | add wave -noupdate /testbench/pointer_write | |||
|
|
15 | add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty_almost | |||
|
|
16 | add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty | |||
|
|
17 | add wave -noupdate -expand -group FIFO_OUT -radix binary -expand /testbench/data_ren | |||
|
|
18 | add wave -noupdate -expand -group FIFO_OUT -radix hexadecimal -expand -subitemconfig {/testbench/data_out(0) {-radix hexadecimal} /testbench/data_out(1) {-radix hexadecimal} /testbench/data_out(2) {-radix hexadecimal} /testbench/data_out(3) {-radix hexadecimal}} /testbench/data_out | |||
|
|
19 | add wave -noupdate -expand /testbench/pointer_read | |||
|
|
20 | add wave -noupdate -format Analog-Step -height 74 -max 32.0 /testbench/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/space_busy | |||
|
|
21 | add wave -noupdate -format Analog-Step -height 74 -max 32.0 /testbench/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/space_busy | |||
|
|
22 | add wave -noupdate -format Analog-Step -height 74 -max 32.0 /testbench/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/space_busy | |||
|
|
23 | add wave -noupdate -format Analog-Step -height 74 -max 32.0 /testbench/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/space_busy | |||
|
|
24 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/error_now(3) {-radix hexadecimal} /testbench/error_now(2) {-radix hexadecimal} /testbench/error_now(1) {-radix hexadecimal} /testbench/error_now(0) {-radix hexadecimal}} /testbench/error_now | |||
|
|
25 | add wave -noupdate -radix hexadecimal /testbench/error_new | |||
|
|
26 | add wave -noupdate /testbench/read_stop | |||
|
|
27 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd | |||
|
|
28 | add wave -noupdate -expand /testbench/empty_reg | |||
|
|
29 | add wave -noupdate -expand /testbench/data_ren | |||
|
|
30 | add wave -noupdate /testbench/lpp_waveform_fifo_headreg_1/one_ren_and_notempty | |||
|
|
31 | TreeUpdate [SetDefaultTree] | |||
|
|
32 | WaveRestoreCursors {{Cursor 1} {125000 ps} 0} | |||
|
|
33 | configure wave -namecolwidth 341 | |||
|
|
34 | configure wave -valuecolwidth 172 | |||
|
|
35 | configure wave -justifyvalue left | |||
|
|
36 | configure wave -signalnamewidth 0 | |||
|
|
37 | configure wave -snapdistance 10 | |||
|
|
38 | configure wave -datasetprefix 0 | |||
|
|
39 | configure wave -rowmargin 4 | |||
|
|
40 | configure wave -childrowmargin 2 | |||
|
|
41 | configure wave -gridoffset 0 | |||
|
|
42 | configure wave -gridperiod 1 | |||
|
|
43 | configure wave -griddelta 40 | |||
|
|
44 | configure wave -timeline 0 | |||
|
|
45 | configure wave -timelineunits ns | |||
|
|
46 | update | |||
|
|
47 | WaveRestoreZoom {0 ps} {1025712 ps} | |||
| @@ -388,6 +388,7 BEGIN -- beh | |||||
| 388 | ------------------------------------------------------------------------------- |
|
388 | ------------------------------------------------------------------------------- | |
| 389 | apb_lfr_management_1 : apb_lfr_management |
|
389 | apb_lfr_management_1 : apb_lfr_management | |
| 390 | GENERIC MAP ( |
|
390 | GENERIC MAP ( | |
|
|
391 | tech => apa3e, | |||
| 391 | pindex => 6, |
|
392 | pindex => 6, | |
| 392 | paddr => 6, |
|
393 | paddr => 6, | |
| 393 | pmask => 16#fff#, |
|
394 | pmask => 16#fff#, | |
| @@ -402,7 +403,11 BEGIN -- beh | |||||
| 402 | apbo => apbo_ext(6), |
|
403 | apbo => apbo_ext(6), | |
| 403 | HK_sample => sample_hk, |
|
404 | HK_sample => sample_hk, | |
| 404 | HK_val => sample_val, |
|
405 | HK_val => sample_val, | |
| 405 |
HK_sel => HK_SEL, |
|
406 | HK_sel => HK_SEL, | |
|
|
407 | DAC_SDO => OPEN, | |||
|
|
408 | DAC_SCK => OPEN, | |||
|
|
409 | DAC_SYNC => OPEN, | |||
|
|
410 | DAC_CAL_EN => OPEN, | |||
| 406 | coarse_time => coarse_time, |
|
411 | coarse_time => coarse_time, | |
| 407 | fine_time => fine_time, |
|
412 | fine_time => fine_time, | |
| 408 | LFR_soft_rstn => LFR_soft_rstn |
|
413 | LFR_soft_rstn => LFR_soft_rstn | |
| @@ -517,7 +522,7 BEGIN -- beh | |||||
| 517 | pirq_ms => 6, |
|
522 | pirq_ms => 6, | |
| 518 | pirq_wfp => 14, |
|
523 | pirq_wfp => 14, | |
| 519 | hindex => 2, |
|
524 | hindex => 2, | |
| 520 |
top_lfr_version => X"00013 |
|
525 | top_lfr_version => X"00013F") -- aa.bb.cc version | |
| 521 | PORT MAP ( |
|
526 | PORT MAP ( | |
| 522 | clk => clk_25, |
|
527 | clk => clk_25, | |
| 523 | rstn => LFR_rstn, |
|
528 | rstn => LFR_rstn, | |
| @@ -32,7 +32,6 DIRSKIP = b1553 pcif leon2 leon2ft crypt | |||||
| 32 | ./general_purpose/lpp_balise \ |
|
32 | ./general_purpose/lpp_balise \ | |
| 33 | ./general_purpose/lpp_delay \ |
|
33 | ./general_purpose/lpp_delay \ | |
| 34 | ./lpp_bootloader \ |
|
34 | ./lpp_bootloader \ | |
| 35 | ./lpp_cna \ |
|
|||
| 36 | ./lpp_uart \ |
|
35 | ./lpp_uart \ | |
| 37 | ./lpp_usb \ |
|
36 | ./lpp_usb \ | |
| 38 | ./dsp/lpp_fft_rtax \ |
|
37 | ./dsp/lpp_fft_rtax \ | |
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