diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -388,6 +388,7 @@ BEGIN -- beh ------------------------------------------------------------------------------- apb_lfr_management_1 : apb_lfr_management GENERIC MAP ( + tech => apa3e, pindex => 6, paddr => 6, pmask => 16#fff#, @@ -402,7 +403,11 @@ BEGIN -- beh apbo => apbo_ext(6), HK_sample => sample_hk, HK_val => sample_val, - HK_sel => HK_SEL, + HK_sel => HK_SEL, + DAC_SDO => OPEN, + DAC_SCK => OPEN, + DAC_SYNC => OPEN, + DAC_CAL_EN => OPEN, coarse_time => coarse_time, fine_time => fine_time, LFR_soft_rstn => LFR_soft_rstn @@ -517,7 +522,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00013A") -- aa.bb.cc version + top_lfr_version => X"00013F") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, diff --git a/designs/MINI-LFR_WFP_MS/Makefile b/designs/MINI-LFR_WFP_MS/Makefile --- a/designs/MINI-LFR_WFP_MS/Makefile +++ b/designs/MINI-LFR_WFP_MS/Makefile @@ -32,7 +32,6 @@ DIRSKIP = b1553 pcif leon2 leon2ft crypt ./general_purpose/lpp_balise \ ./general_purpose/lpp_delay \ ./lpp_bootloader \ - ./lpp_cna \ ./lpp_uart \ ./lpp_usb \ ./dsp/lpp_fft_rtax \ diff --git a/designs/Validation_DMA_SubSystem/Makefile b/designs/Validation_DMA_SubSystem/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_DMA_SubSystem/Makefile @@ -0,0 +1,570 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ + +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=TB + +CMD_VLIB=vlib +CMD_VMAP=vmap +CMD_VCOM=@vcom -quiet -93 -work + +################## project specific targets ########################## + +all: + @echo "make vsim" + @echo "make libs" + @echo "make clean" + @echo "make vcom_grlib vcom_lpp vcom_tb" + +run: + @vsim work.TB -do run.do +# @vsim work.TB +# @vsim lpp.lpp_lfr_ms + +vsim: libs vcom run + +libs: + @$(CMD_VLIB) modelsim + @$(CMD_VMAP) modelsim modelsim + @$(CMD_VLIB) modelsim/techmap + @$(CMD_VMAP) techmap modelsim/techmap + @$(CMD_VLIB) modelsim/grlib + @$(CMD_VMAP) grlib modelsim/grlib + @$(CMD_VLIB) modelsim/gaisler + @$(CMD_VMAP) gaisler modelsim/gaisler + @$(CMD_VLIB) modelsim/work + @$(CMD_VMAP) work modelsim/work + @$(CMD_VLIB) modelsim/lpp + @$(CMD_VMAP) lpp modelsim/lpp + @$(CMD_VLIB) modelsim/esa + @$(CMD_VMAP) esa modelsim/esa + @echo "libs done" + + +clean: + @rm -Rf modelsim + @rm -Rf modelsim.ini + @rm -Rf *~ + @rm -Rf transcript + @rm -Rf wlft* + @rm -Rf *.wlf + @rm -Rf vish_stacktrace.vstf + @rm -Rf libs.do + +vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_esa vcom_tb + + +vcom_tb: +## $(CMD_VCOM) lpp lpp_memory.vhd +## $(CMD_VCOM) lpp lppFIFOxN.vhd +## $(CMD_VCOM) lpp lpp_FIFO.vhd +## $(CMD_VCOM) lpp lpp_lfr_ms.vhd + $(CMD_VCOM) lpp ../MINI-LFR_testdma/lpp_lfr_apbreg.vhd + $(CMD_VCOM) lpp testbench_package.vhd + $(CMD_VCOM) lpp testbench_package.vhd + $(CMD_VCOM) work TB.vhd + @echo "vcom done" + +vcom_esa: + $(CMD_VCOM) esa $(GRLIB)/lib/esa/memoryctrl/memoryctrl.vhd + $(CMD_VCOM) esa $(GRLIB)/lib/esa/memoryctrl/mctrl.vhd + @echo "lib esa done" + +vcom_grlib: + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd + @echo "vcom grlib done" + +vcom_gaisler: + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd +# # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd +# # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd +# # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd +## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd + @echo "vcom gaisler done" + +vcom_techmap: + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd + @echo "vcom techmap done" + +vcom_lpp: + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/apb_devices_list.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_control.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/general_purpose.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/ADDRcntr.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/ALU.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Adder.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clk_Divider2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clk_divider.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_CONTROLER.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_MUX.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_MUX2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MAC_REG.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MUX2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/MUXN.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Multiplier.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/REG.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/SYNC_FF.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Shifter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/TwoComplementer.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/Clock_Divider.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_to_level.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_detection.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/RR_Arbiter_4.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./general_purpose/general_counter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/apb_devices_list.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/lpp_lfr_time_management.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/apb_lfr_time_management.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/lfr_time_management.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/fine_time_counter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lfr_time_management/coarse_time_counter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/RHF1401.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/MS_control.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_demux/DEMUX.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_demux/lpp_demux.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/lpp_Header.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/HeaderBuilder.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/ALU_Driver.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/Dispatch.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/DriveInputs.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/GetResult.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/Matrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/SpectralMatrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_matrix/lpp_matrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lpp_memory.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lpp_FIFO.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_memory/lppFIFOxN.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/fifo_latency_correction.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_ip.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd +## $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd +## $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/lpp_Header.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_Header/HeaderBuilder.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +## $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/DMA_SubSystem.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/DMA_SubSystem_GestionBuffer.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/DMA_SubSystem_Arbiter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/DMA_SubSystem_MUX.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/package_utility.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/package_timing.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd + @echo "vcom lpp done" + +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd +# @echo "vcom lpp done" + +#include Makefile_vcom_lpp diff --git a/designs/Validation_DMA_SubSystem/TB.vhd b/designs/Validation_DMA_SubSystem/TB.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_DMA_SubSystem/TB.vhd @@ -0,0 +1,569 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.spectral_matrix_package.ALL; +USE lpp.lpp_fft.ALL; +USE lpp.fft_components.ALL; +USE lpp.CY7C1061DV33_pkg.ALL; +USE lpp.testbench_package.ALL; + + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.misc.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY esa; +USE esa.memoryctrl.ALL; + + +ENTITY TB IS +END TB; + + +ARCHITECTURE beh OF TB IS + + COMPONENT lpp_lfr_apbreg_tb + GENERIC ( + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + fifo_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_wdata : OUT STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + fifo_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_full_almost : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_empty_threshold : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_new : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_length : OUT STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); + buffer_addr : OUT STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + buffer_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_full_err : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + grant_error : IN STD_LOGIC); + END COMPONENT; + + COMPONENT DMA_SubSystem + GENERIC ( + hindex : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + ahbi : IN AHB_Mst_In_Type; + ahbo : OUT AHB_Mst_Out_Type; + fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); + buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + grant_error : OUT STD_LOGIC); + END COMPONENT; + + CONSTANT INDEX_DMA_SUBSYSTEM : INTEGER := 15; + CONSTANT ADDR_DMA_SUBSYSTEM : INTEGER := 15; + + + -- REG DMA_SubSystem + CONSTANT ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00"; + CONSTANT ADDR_DMA_SUBSYSTEM_F0_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; + CONSTANT ADDR_DMA_SUBSYSTEM_F0_LENGTH : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; + + CONSTANT ADDR_DMA_SUBSYSTEM_F1_wDATA_rSTATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; + CONSTANT ADDR_DMA_SUBSYSTEM_F1_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; + CONSTANT ADDR_DMA_SUBSYSTEM_F1_LENGTH : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; + + CONSTANT ADDR_DMA_SUBSYSTEM_F2_wDATA_rSTATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; + CONSTANT ADDR_DMA_SUBSYSTEM_F2_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; + CONSTANT ADDR_DMA_SUBSYSTEM_F2_LENGTH : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; + + CONSTANT ADDR_DMA_SUBSYSTEM_F3_wDATA_rSTATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; + CONSTANT ADDR_DMA_SUBSYSTEM_F3_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; + CONSTANT ADDR_DMA_SUBSYSTEM_F3_LENGTH : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; + + CONSTANT ADDR_DMA_SUBSYSTEM_F4_wDATA_rSTATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; + CONSTANT ADDR_DMA_SUBSYSTEM_F4_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; + CONSTANT ADDR_DMA_SUBSYSTEM_F4_LENGTH : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; + -- RAM ADDRESS + CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#000#; + CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; + CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; + CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; + + + -- Common signal + SIGNAL clk49_152MHz : STD_LOGIC := '0'; + SIGNAL clk25MHz : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + + -- ADC interface + SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT + SIGNAL ADC_smpclk : STD_LOGIC; -- OUT + SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN + + -- AD Converter RHF1401 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_s : Samples(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + + -- AHB/APB SIGNAL + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); + + SIGNAL bias_fail_bw : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- LPP_WAVEFORM + ----------------------------------------------------------------------------- + CONSTANT data_size : INTEGER := 96; + CONSTANT nb_burst_available_size : INTEGER := 50; + CONSTANT nb_snapshot_param_size : INTEGER := 2; + CONSTANT delta_vector_size : INTEGER := 2; + CONSTANT delta_vector_size_f0_2 : INTEGER := 2; + + SIGNAL reg_run : STD_LOGIC; + SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); + SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL enable_f0 : STD_LOGIC; + SIGNAL enable_f1 : STD_LOGIC; + SIGNAL enable_f2 : STD_LOGIC; + SIGNAL enable_f3 : STD_LOGIC; + SIGNAL burst_f0 : STD_LOGIC; + SIGNAL burst_f1 : STD_LOGIC; + SIGNAL burst_f2 : STD_LOGIC; + SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_in_valid : STD_LOGIC; + SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_in_valid : STD_LOGIC; + SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_in_valid : STD_LOGIC; + SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_in_valid : STD_LOGIC; + SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_data_out_valid : STD_LOGIC; + SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f0_data_out_ack : STD_LOGIC; + SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_data_out_valid : STD_LOGIC; + SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f1_data_out_ack : STD_LOGIC; + SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_data_out_valid : STD_LOGIC; + SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f2_data_out_ack : STD_LOGIC; + SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_data_out_valid : STD_LOGIC; + SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f3_data_out_ack : STD_LOGIC; + + --MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + + SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; + SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL nSRAM_BE0 : STD_LOGIC; + SIGNAL nSRAM_BE1 : STD_LOGIC; + SIGNAL nSRAM_BE2 : STD_LOGIC; + SIGNAL nSRAM_BE3 : STD_LOGIC; + SIGNAL nSRAM_WE : STD_LOGIC; + SIGNAL nSRAM_CE : STD_LOGIC; + SIGNAL nSRAM_OE : STD_LOGIC; + + CONSTANT padtech : INTEGER := inferred; + SIGNAL not_ramsn_0 : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL read_buffer : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; + SIGNAL state_read_buffer_on_going : STD_LOGIC; + CONSTANT hindex : INTEGER := 1; + SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0); + + SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + SIGNAL run : STD_LOGIC; + + SIGNAL fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_wdata : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + SIGNAL fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_rdata : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + + SIGNAL fifo_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_full_almost : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_empty_threshold : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0); + SIGNAL buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + SIGNAL buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL grant_error :STD_LOGIC; + +BEGIN + + ----------------------------------------------------------------------------- + + clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz + clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz + + + + ----------------------------------------------------------------------------- + -- DMA SUBSYSTEM + ----------------------------------------------------------------------------- + lpp_lfr_apbreg_tb_1: lpp_lfr_apbreg_tb + GENERIC MAP ( + pindex => INDEX_DMA_SUBSYSTEM, + paddr => ADDR_DMA_SUBSYSTEM, + pmask => 16#fff#) + PORT MAP ( + HCLK => clk25MHz, + HRESETn => rstn, + apbi => apbi, + apbo => apbo(INDEX_DMA_SUBSYSTEM), + + fifo_wen => fifo_wen, + fifo_wdata => fifo_wdata, + fifo_full => fifo_full, + fifo_full_almost => fifo_full_almost, + fifo_empty => fifo_empty, + fifo_empty_threshold => fifo_empty_threshold, + + buffer_new => buffer_new, + buffer_length => buffer_length, + buffer_addr => buffer_addr, + buffer_full => buffer_full, + buffer_full_err => buffer_full_err, + + grant_error => grant_error); + + all_fifo: FOR I IN 4 DOWNTO 0 GENERATE + lpp_fifo_I: lpp_fifo + GENERIC MAP ( + tech => inferred, + Mem_use => use_RAM, + EMPTY_THRESHOLD_LIMIT => 15, + FULL_THRESHOLD_LIMIT => 1, + DataSz => 32, + AddrSz => 7) + PORT MAP ( + clk => clk25MHz, + rstn => rstn, + reUse => '0', + run => run, + + ren => fifo_ren(I), + rdata => fifo_rdata(32*(I+1)-1 DOWNTO 32*i), + + wen => fifo_wen(I), + wdata => fifo_wdata(32*(I+1)-1 DOWNTO 32*i), + + empty => fifo_empty(I), + full => fifo_full(I), + full_almost => fifo_full_almost(I), + empty_threshold => fifo_empty_threshold(I), + + full_threshold => OPEN); + + fifo_burst_valid(I) <= NOT fifo_empty_threshold(I); + + END GENERATE all_fifo; + + + + DMA_SubSystem_1: DMA_SubSystem + GENERIC MAP ( + hindex => 0) + PORT MAP ( + clk => clk25MHz, + rstn => rstn, + run => run, + ahbi => ahbmi, + ahbo => ahbmo(0), + + fifo_burst_valid => fifo_burst_valid, + fifo_data => fifo_rdata, + fifo_ren => fifo_ren, + buffer_new => buffer_new, + buffer_addr => buffer_addr, + buffer_length => buffer_length, + buffer_full => buffer_full, + buffer_full_err => buffer_full_err, + grant_error => grant_error); + + + ----------------------------------------------------------------------------- + --- AHB CONTROLLER ------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => 0, split => 0, + rrobin => 1, ioaddr => 16#FFF#, + ioen => 0, nahbm => 2, nahbs => 1) + PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); + + + + --- AHB RAM ---------------------------------------------------------- + --ahbram0 : ahbram + -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); + --ahbram1 : ahbram + -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); + --ahbram2 : ahbram + -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); + --ahbram3 : ahbram + -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); + + ----------------------------------------------------------------------------- + ---------------------------------------------------------------------- + --- Memory controllers --------------------------------------------- + ---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + + not_ramsn_0 <= NOT(memo.ramsn(0)); + + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + + async_1Mx16_0 : CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 20, + DATA_BITS => 16, + depth => 1048576, + MEM_ARRAY_DEBUG => 32, + TimingInfo => true, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_WE, + OE_b => nSRAM_OE, + BHE_b => nSRAM_BE1, + BLE_b => nSRAM_BE0, + A => address, + DQ => data(15 DOWNTO 0)); + + async_1Mx16_1 : CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 20, + DATA_BITS => 16, + depth => 1048576, + MEM_ARRAY_DEBUG => 32, + TimingInfo => true, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_WE, + OE_b => nSRAM_OE, + BHE_b => nSRAM_BE3, + BLE_b => nSRAM_BE2, + A => address, + DQ => data(31 DOWNTO 16)); + + + ----------------------------------------------------------------------------- + + WaveGen_Proc : PROCESS + BEGIN + + -- insert signal assignments here + WAIT UNTIL clk25MHz = '1'; + run <= '0'; + rstn <= '0'; + apbi.psel(15) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + fine_time <= (OTHERS => '0'); + coarse_time <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; + + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + rstn <= '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + run <= '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + + WAIT UNTIL clk25MHz = '1'; + + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_ADDR , X"40000000"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_LENGTH , X"00000002"); + + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000001"); --1 + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000002"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000003"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000004"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000005"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000006"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000007"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000008"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000009"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000A"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000B"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000C"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000D"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000E"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000000F"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000010"); --16 + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000011"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000012"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000013"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000014"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000015"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000016"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000017"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000018"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000019"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001A"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001B"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001C"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001D"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001E"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"0000001F"); + APB_WRITE(clk25MHz, INDEX_DMA_SUBSYSTEM, apbi, ADDR_DMA_SUBSYSTEM_F0_wDATA_rSTATUS , X"00000020"); --32 + + + WAIT FOR 1 ms; + REPORT "*** END simulation ***" SEVERITY failure; + + + WAIT; + + END PROCESS WaveGen_Proc; + ----------------------------------------------------------------------------- + +END beh; + diff --git a/designs/Validation_DMA_SubSystem/run.do b/designs/Validation_DMA_SubSystem/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_DMA_SubSystem/run.do @@ -0,0 +1,3 @@ +log -R * +do wave.do +run -all \ No newline at end of file diff --git a/designs/Validation_DMA_SubSystem/testbench_package.vhd b/designs/Validation_DMA_SubSystem/testbench_package.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_DMA_SubSystem/testbench_package.vhd @@ -0,0 +1,136 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +--LIBRARY gaisler; +--USE gaisler.libdcom.ALL; +--USE gaisler.sim.ALL; +--USE gaisler.jtagtst.ALL; +--LIBRARY techmap; +--USE techmap.gencomp.ALL; + + +PACKAGE testbench_package IS + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END testbench_package; + +PACKAGE BODY testbench_package IS + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + apbi.pwdata <= pwdata; + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + + END APB_WRITE; + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '0'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + prdata <= apbo.prdata; + END APB_READ; + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + WAIT UNTIL clk = '1'; + ahbmo.HADDR <= haddr; + ahbmo.HPROT <= "0011"; + ahbmo.HIRQ <= (OTHERS => '0'); + ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); + ahbmo.HINDEX <= hindex; + ahbmo.HBUSREQ <= '1'; + ahbmo.HLOCK <= '1'; + ahbmo.HSIZE <= HSIZE_WORD; + ahbmo.HBURST <= HBURST_SINGLE; + ahbmo.HTRANS <= HTRANS_NONSEQ; + ahbmo.HWRITE <= '0'; + WHILE ahbmi.HREADY = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + ahbmo.HBUSREQ <= '0'; + ahbmo.HLOCK <= '0'; + ahbmo.HTRANS <= HTRANS_IDLE; + WHILE ahbmi.HREADY = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + hrdata <= ahbmi.HRDATA; + --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + ahbmo.HLOCK <= '0'; + WAIT UNTIL clk = '1'; + + END AHB_READ; + +END testbench_package; diff --git a/designs/Validation_DMA_SubSystem/wave.do b/designs/Validation_DMA_SubSystem/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_DMA_SubSystem/wave.do @@ -0,0 +1,46 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group APB_REG -expand -group BUFFER_CONFIG /tb/lpp_lfr_apbreg_tb_1/buffer_new +add wave -noupdate -expand -group APB_REG -expand -group BUFFER_CONFIG /tb/lpp_lfr_apbreg_tb_1/buffer_length +add wave -noupdate -expand -group APB_REG -expand -group BUFFER_CONFIG /tb/lpp_lfr_apbreg_tb_1/buffer_addr +add wave -noupdate -expand -group APB_REG /tb/lpp_lfr_apbreg_tb_1/buffer_full +add wave -noupdate -expand -group APB_REG /tb/lpp_lfr_apbreg_tb_1/buffer_full_err +add wave -noupdate -expand -group APB_REG /tb/lpp_lfr_apbreg_tb_1/grant_error +add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_wen +add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_wdata +add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_full +add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_full_almost +add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_empty +add wave -noupdate -expand -group APB_REG -expand -group FIFO_WRITE&STATUS /tb/lpp_lfr_apbreg_tb_1/fifo_empty_threshold +add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group AHB /tb/dma_subsystem_1/ahbi +add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group AHB /tb/dma_subsystem_1/ahbo +add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group FIFO_READ /tb/dma_subsystem_1/fifo_burst_valid +add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group FIFO_READ /tb/dma_subsystem_1/fifo_data +add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group FIFO_READ /tb/dma_subsystem_1/fifo_ren +add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group BUFFER_CONFIG&STATUS /tb/dma_subsystem_1/buffer_new +add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group BUFFER_CONFIG&STATUS /tb/dma_subsystem_1/buffer_addr +add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group BUFFER_CONFIG&STATUS /tb/dma_subsystem_1/buffer_length +add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group BUFFER_CONFIG&STATUS /tb/dma_subsystem_1/buffer_full +add wave -noupdate -expand -group DMA_SUBSYSTEM -expand -group BUFFER_CONFIG&STATUS /tb/dma_subsystem_1/buffer_full_err +add wave -noupdate -expand -group DMA_SUBSYSTEM /tb/dma_subsystem_1/grant_error +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_0/mem_array_0(31) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(30) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(29) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(28) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(27) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(26) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(25) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(24) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(23) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(22) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(21) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(20) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(19) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(18) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(17) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(16) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(15) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(14) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(13) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(12) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(11) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(10) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(9) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(8) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(7) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(6) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(5) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(4) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(3) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(2) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(1) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_0(0) {-radix hexadecimal}} /tb/async_1mx16_0/mem_array_0 +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_1/mem_array_0(31) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(30) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(29) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(28) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(27) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(26) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(25) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(24) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(23) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(22) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(21) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(20) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(19) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(18) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(17) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(16) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(15) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(14) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(13) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(12) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(11) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(10) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(9) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(8) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(7) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(6) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(5) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(4) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(3) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(2) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(1) {-radix hexadecimal} /tb/async_1mx16_1/mem_array_0(0) {-radix hexadecimal}} /tb/async_1mx16_1/mem_array_0 +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {1151509 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {27526990683 ps} 0} +configure wave -namecolwidth 618 +configure wave -valuecolwidth 472 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {2011303 ps} +bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 +bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 diff --git a/designs/Validation_DMA_SubSystem/wave_temp.do b/designs/Validation_DMA_SubSystem/wave_temp.do new file mode 100644 --- /dev/null +++ b/designs/Validation_DMA_SubSystem/wave_temp.do @@ -0,0 +1,80 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val +add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/enable +add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/burst_enable +add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/start_snapshot +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/state_on +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on_s +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0_pre +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_decount +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_init +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_f0 +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/send_start_snapshot_f0 +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f0_valid +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f2_valid +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0 +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f1 +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f2 +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in +add wave -noupdate -group temp -subitemconfig {/tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.haddr {-height 15 -radix hexadecimal} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hwdata {-height 15 -radix hexadecimal}} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/send +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/done +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ren +add wave -noupdate -group temp -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/address +add wave -noupdate -group temp -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/data +add wave -noupdate -group temp /tb/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay +add wave -noupdate -group temp /tb/async_1mx16_0/ce1_b +add wave -noupdate -group temp /tb/async_1mx16_0/ce2 +add wave -noupdate -group temp /tb/async_1mx16_0/we_b +add wave -noupdate -group temp /tb/async_1mx16_0/oe_b +add wave -noupdate -group temp /tb/async_1mx16_0/bhe_b +add wave -noupdate -group temp /tb/async_1mx16_0/ble_b +add wave -noupdate -group temp /tb/async_1mx16_0/a +add wave -noupdate -group temp /tb/async_1mx16_0/dq +add wave -noupdate -radix hexadecimal -subitemconfig {/tb/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /tb/async_1mx16_0/mem_array_0 +add wave -noupdate -radix hexadecimal -subitemconfig {/tb/async_1mx16_0/mem_array_1(31) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(30) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(29) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(28) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(27) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(26) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(25) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(24) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(23) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(22) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(21) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(20) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(19) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(18) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(17) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(16) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(15) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(14) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(13) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(12) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(11) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(10) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(9) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(8) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(7) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(6) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(5) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(4) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(3) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(2) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(1) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_1(0) {-height 15 -radix hexadecimal}} /tb/async_1mx16_0/mem_array_1 +add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_2 +add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_3 +add wave -noupdate -format Analog-Step -height 70 -max 256.0 -radix unsigned /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect +add wave -noupdate -radix hexadecimal -subitemconfig {/tb/ahbmi.hirq(31) {-radix hexadecimal} /tb/ahbmi.hirq(30) {-radix hexadecimal} /tb/ahbmi.hirq(29) {-radix hexadecimal} /tb/ahbmi.hirq(28) {-radix hexadecimal} /tb/ahbmi.hirq(27) {-radix hexadecimal} /tb/ahbmi.hirq(26) {-radix hexadecimal} /tb/ahbmi.hirq(25) {-radix hexadecimal} /tb/ahbmi.hirq(24) {-radix hexadecimal} /tb/ahbmi.hirq(23) {-radix hexadecimal} /tb/ahbmi.hirq(22) {-radix hexadecimal} /tb/ahbmi.hirq(21) {-radix hexadecimal} /tb/ahbmi.hirq(20) {-radix hexadecimal} /tb/ahbmi.hirq(19) {-radix hexadecimal} /tb/ahbmi.hirq(18) {-radix hexadecimal} /tb/ahbmi.hirq(17) {-radix hexadecimal} /tb/ahbmi.hirq(16) {-radix hexadecimal} /tb/ahbmi.hirq(15) {-radix hexadecimal} /tb/ahbmi.hirq(14) {-radix hexadecimal} /tb/ahbmi.hirq(13) {-radix hexadecimal} /tb/ahbmi.hirq(12) {-radix hexadecimal} /tb/ahbmi.hirq(11) {-radix hexadecimal} /tb/ahbmi.hirq(10) {-radix hexadecimal} /tb/ahbmi.hirq(9) {-radix hexadecimal} /tb/ahbmi.hirq(8) {-radix hexadecimal} /tb/ahbmi.hirq(7) {-radix hexadecimal} /tb/ahbmi.hirq(6) {-radix hexadecimal} /tb/ahbmi.hirq(5) {-radix hexadecimal} /tb/ahbmi.hirq(4) {-radix hexadecimal} /tb/ahbmi.hirq(3) {-radix hexadecimal} /tb/ahbmi.hirq(2) {-radix hexadecimal} /tb/ahbmi.hirq(1) {-radix hexadecimal} /tb/ahbmi.hirq(0) {-radix hexadecimal}} /tb/ahbmi.hirq +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/status_full +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/status_full_ack +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/status_full_err +add wave -noupdate -radix unsigned /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/nb_data_by_buffer +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_p(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_p(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_p(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_p(0) {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_p +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_b(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_b(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_b(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_b(0) {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_v_b +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_data_f0 +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_data_f1 +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_data_f2 +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/addr_data_f3 +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_gen_address_1/run +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {265000 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {27526990683 ps} 0} +configure wave -namecolwidth 518 +configure wave -valuecolwidth 227 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {966012 ps} +bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 +bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 diff --git a/designs/Validation_FFT_auto/Makefile b/designs/Validation_FFT_auto/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_FFT_auto/Makefile @@ -0,0 +1,54 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES= +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft_rtax \ + ./lpp_sim/CY7C1061DV33 \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + CoreFFT_simu.vhd \ + lpp_lfr_apbreg_simu.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/Validation_FFT_auto/run.do b/designs/Validation_FFT_auto/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_FFT_auto/run.do @@ -0,0 +1,9 @@ +vcom -quiet -93 -work work tb.vhd + +vsim work.testbench + +log -r * + +do wave.do + +run -all diff --git a/designs/Validation_FFT_auto/run_nowindow.do b/designs/Validation_FFT_auto/run_nowindow.do new file mode 100644 --- /dev/null +++ b/designs/Validation_FFT_auto/run_nowindow.do @@ -0,0 +1,33 @@ +#vsim -c -do "run_nowindow.do" -goutput_file_name="output_data.txt" -ginput_file_name="input_data.txt" + +quietly set args [ split $argv {\ } ] +set argc [ llength $args ] + +set outputfile "output\_data\.txt" +set inputfile "input\_data\.txt" + +#puts "there are $argc arguments to this script" +#puts "The name of this script is $argv0" + +#foreach arg $::argv {puts $arg} + +#puts [ lindex $args 4 ] + +for { set i 0 } { $i < $argc } { incr i 1 } { + puts "$i : [ lindex $args $i ]" + if { [ string match -goutput_file_name=* [ lindex $args $i ] ] } { + set outputfile [ lindex [ split [ lindex $args $i ] {=} ] 1 ] + #set outputfile [ lindex [ split $argv {=} ] 1 ] + puts "OUTPUT_FILE : $outputfile" + } + if { [ string match -ginput_file_name=* [ lindex $args $i ] ] } { + set inputfile [ lindex [ split [ lindex $args $i ] {=} ] 1 ] + #set inputfile [ lindex [ split $argv {=} ] 1 ] + puts "INPUT_FILE : $inputfile" + } +} + +vsim work.testbench -goutput_file_name=$outputfile -ginput_file_name=$inputfile +when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation"; exit ;} +run -all +exit diff --git a/designs/Validation_FFT_auto/script_run.sh b/designs/Validation_FFT_auto/script_run.sh new file mode 100644 --- /dev/null +++ b/designs/Validation_FFT_auto/script_run.sh @@ -0,0 +1,10 @@ +#!/bin/sh + +for FILE_NAME in "$@" +do + vsim -c -do "run_nowindow.do" -goutput_file_name=$FILE_NAME".FFT_output" -ginput_file_name=$FILE_NAME +done + + + + diff --git a/designs/Validation_FFT_auto/tb.vhd b/designs/Validation_FFT_auto/tb.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_FFT_auto/tb.vhd @@ -0,0 +1,186 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY std; +use std.textio.all; + +LIBRARY lpp; +USE lpp.cic_pkg.ALL; +USE lpp.chirp_pkg.ALL; +USE lpp.lpp_fft.ALL; +USE lpp.lpp_lfr_pkg.ALL; + +ENTITY testbench IS + GENERIC ( + input_file_name : STRING := "input_data_2.txt"; + output_file_name : STRING := "output_data.txt"); +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + + -- IN + SIGNAL sample_valid : STD_LOGIC; + SIGNAL fft_read : STD_LOGIC; + SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL sample_load : STD_LOGIC; + -- OUT + SIGNAL fft_pong : STD_LOGIC; + SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fft_data_valid : STD_LOGIC; + SIGNAL fft_ready : STD_LOGIC; + SIGNAL fft_component_number : INTEGER; + + SIGNAL end_of_sim : STD_LOGIC := '0'; + +BEGIN + + clk <= NOT clk AFTER 5 ns; + + PROCESS + FILE file_pointer : TEXT; + VARIABLE line_read : LINE; + VARIABLE line_content : STRING(1 TO 4); + VARIABLE line_write : LINE; + VARIABLE line_content_write : STRING(1 TO 8); + VARIABLE char_read : CHARACTER; + VARIABLE data_read : STD_LOGIC_VECTOR(15 DOWNTO 0); + VARIABLE signal_part : STD_LOGIC_VECTOR(3 DOWNTO 0); + + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + rstn <= '0'; + fft_read <= '0'; + sample_valid <= '0'; + fft_component_number <= 0; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + + WHILE sample_load = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + + file_open(file_pointer,input_file_name,READ_MODE); + WHILE NOT endfile(file_pointer) LOOP + readline(file_pointer, line_read); + read(line_read,line_content); + FOR i IN 1 TO 4 LOOP + char_read := line_content(5-i); + CASE char_read IS + WHEN '0' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0000"; + WHEN '1' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0001"; + WHEN '2' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0010"; + WHEN '3' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0011"; + WHEN '4' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0100"; + WHEN '5' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0101"; + WHEN '6' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0110"; + WHEN '7' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0111"; + WHEN '8' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1000"; + WHEN '9' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1001"; + WHEN 'a' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1010"; + WHEN 'b' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1011"; + WHEN 'c' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1100"; + WHEN 'd' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1101"; + WHEN 'e' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1110"; + WHEN 'f' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1111"; + WHEN OTHERS => NULL; + END CASE; + END LOOP; + sample_data <= data_read; + sample_valid <= '1'; + WAIT UNTIL clk = '1'; + END LOOP; + file_close(file_pointer); + sample_valid <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WHILE fft_ready = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + + + file_open(file_pointer,output_file_name,WRITE_MODE); + WHILE fft_ready = '1' LOOP + IF fft_data_valid = '1' THEN + FOR j IN 0 TO 1 LOOP + FOR i IN 1 TO 4 LOOP + IF j = 0 THEN + signal_part := fft_data_im(i*4-1 DOWNTO (i-1)*4); + ELSE + signal_part := fft_data_re(i*4-1 DOWNTO (i-1)*4); + END IF; + CASE signal_part IS + WHEN "0000" => line_content(i) := '0'; + WHEN "0001" => line_content(i) := '1'; + WHEN "0010" => line_content(i) := '2'; + WHEN "0011" => line_content(i) := '3'; + WHEN "0100" => line_content(i) := '4'; + WHEN "0101" => line_content(i) := '5'; + WHEN "0110" => line_content(i) := '6'; + WHEN "0111" => line_content(i) := '7'; + WHEN "1000" => line_content(i) := '8'; + WHEN "1001" => line_content(i) := '9'; + WHEN "1010" => line_content(i) := 'a'; + WHEN "1011" => line_content(i) := 'b'; + WHEN "1100" => line_content(i) := 'c'; + WHEN "1101" => line_content(i) := 'd'; + WHEN "1110" => line_content(i) := 'e'; + WHEN "1111" => line_content(i) := 'f'; + WHEN OTHERS => NULL; + END CASE; + END LOOP; -- i + line_content_write(j*4+1) := line_content(4); + line_content_write(j*4+2) := line_content(3); + line_content_write(j*4+3) := line_content(2); + line_content_write(j*4+4) := line_content(1); + END LOOP; -- j + write(line_write,line_content_write); + writeline(file_pointer,line_write); + fft_component_number <= fft_component_number + 1; + END IF; + fft_read <= '1'; + WAIT UNTIL clk = '1'; + END LOOP; + file_close(file_pointer); + + fft_read <= '0'; + WAIT UNTIL clk = '1'; + + + WAIT FOR 1 us; + end_of_sim <= '1'; + WAIT FOR 100 ns; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS; + ----------------------------------------------------------------------------- + + lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT + PORT MAP ( + clk => clk, + rstn => rstn, + -- IN + sample_valid => sample_valid, -- in + fft_read => fft_read, -- in + sample_data => sample_data, -- in + sample_load => sample_load, -- out + -- OUT + fft_pong => fft_pong, -- out + fft_data_im => fft_data_im, -- out + fft_data_re => fft_data_re, -- out + fft_data_valid => fft_data_valid, -- out + fft_ready => fft_ready); -- out + +END; diff --git a/designs/Validation_FFT_auto/wave.do b/designs/Validation_FFT_auto/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_FFT_auto/wave.do @@ -0,0 +1,46 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/message_simu +add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp +add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp +add wave -noupdate /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/ongoing +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_full +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_write_error +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_data +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/fsm_state +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data2 +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full_s +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen_s +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_empty +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_data +add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_wen +add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/rdata +add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/almost_full +add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/full +add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/empty +add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/ren +add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/wdata +add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/wen +add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/run +add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/ReUse +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {48603668788 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 539 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {84406089600 ps} diff --git a/designs/Validation_FIFO_Shared/Makefile b/designs/Validation_FIFO_Shared/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO_Shared/Makefile @@ -0,0 +1,53 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES= +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft_rtax \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_apbreg.vhd \ + CoreFFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/Validation_FIFO_Shared/run.do b/designs/Validation_FIFO_Shared/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO_Shared/run.do @@ -0,0 +1,9 @@ +vcom -quiet -93 -work work tb.vhd + +vsim work.testbench + +log -r * + +do wave.do + +run -all diff --git a/designs/Validation_FIFO_Shared/run_with_head_reg_lantency_0.do b/designs/Validation_FIFO_Shared/run_with_head_reg_lantency_0.do new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO_Shared/run_with_head_reg_lantency_0.do @@ -0,0 +1,9 @@ +vcom -quiet -93 -work work tb_with_head_reg_latency_0.vhd + +vsim work.testbench + +log -r * + +do wave_head_reg_latency_0.do + +run -all diff --git a/designs/Validation_FIFO_Shared/run_with_head_reg_lantency_1.do b/designs/Validation_FIFO_Shared/run_with_head_reg_lantency_1.do new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO_Shared/run_with_head_reg_lantency_1.do @@ -0,0 +1,9 @@ +vcom -quiet -93 -work work tb_with_head_reg_latency_1.vhd + +vsim work.testbench + +log -r * + +do wave_head_reg_latency_1.do + +run -all diff --git a/designs/Validation_FIFO_Shared/tb.vhd b/designs/Validation_FIFO_Shared/tb.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO_Shared/tb.vhd @@ -0,0 +1,608 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + ----------------------------------------------------------------------------- + -- Common signal + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + SIGNAL run : STD_LOGIC := '0'; + + ----------------------------------------------------------------------------- + TYPE DATA_FIFO_VECTOR IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_obs : DATA_FIFO_VECTOR; + SIGNAL data_out_obs_read : DATA_FIFO_VECTOR; + SIGNAL data_out_obs_1 : DATA_FIFO_VECTOR; + SIGNAL data_out_obs_2 : DATA_FIFO_VECTOR; + + SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '1'); + SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_out : DATA_FIFO_VECTOR; + + SIGNAL empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty_reg_2 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL full_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + ----------------------------------------------------------------------------- + TYPE DATA_CHANNEL IS ARRAY (0 TO 128/4-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + TYPE DATA_ARRAY IS ARRAY (0 TO 3) OF DATA_CHANNEL; + SIGNAL data_in : DATA_ARRAY; + + ----------------------------------------------------------------------------- + CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1+2+2; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE + CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0; + SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + -- + SIGNAL rand_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rand_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + + TYPE POINTER IS ARRAY (0 TO 3) OF INTEGER; + SIGNAL pointer_read : POINTER; + SIGNAL pointer_write : POINTER := (0, 0, 0, 0); + + --SIGNAL data_f0_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f0_data_out_obs : STD_LOGIC; + --SIGNAL data_f1_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f1_data_out_obs : STD_LOGIC; + --SIGNAL data_f2_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f2_data_out_obs : STD_LOGIC; + --SIGNAL data_f3_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f3_data_out_obs : STD_LOGIC; + SIGNAL error_now : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL error_new : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL WARNING_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0); + + + SIGNAL read_stop : STD_LOGIC; + SIGNAL write_stop : STD_LOGIC; + +-- SIGNAL empty_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + + ----------------------------------------------------------------------------- +BEGIN + + all_I : FOR I IN 0 TO 3 GENERATE + all_J : FOR J IN 0 TO 128/4-1 GENERATE + data_in(I)(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+I*(2**28)+1, 32)); + END GENERATE all_J; + END GENERATE all_I; + + + ----------------------------------------------------------------------------- + --lpp_waveform_fifo_1 : lpp_waveform_fifo + -- GENERIC MAP (tech => 0) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + + -- empty => s_empty, + -- empty_almost => s_empty_almost, + -- data_ren => s_data_ren, + -- rdata => s_rdata, + + -- full_almost => full_almost, + -- full => full, + -- data_wen => data_wen, + -- wdata => wdata); + + lpp_fifo_4_shared_1 : lpp_fifo_4_shared + GENERIC MAP ( + tech => 0, + Mem_use => use_RAM, + EMPTY_ALMOST_LIMIT => 16, + FULL_ALMOST_LIMIT => 5, + DataSz => 32, + AddrSz => 7) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + empty_almost => s_empty_almost, + empty => s_empty, + r_en => s_data_ren, + r_data => s_rdata, + + full_almost => full_almost, + full => full, + w_en => data_wen, + w_data => wdata); + + + empty_almost <= s_empty_almost; + empty <= s_empty; + + s_data_ren <= data_ren; + data_out(0) <= s_rdata; + data_out(1) <= s_rdata; + data_out(2) <= s_rdata; + data_out(3) <= s_rdata; + + + + --lpp_fifo_4_shared_headreg_1: lpp_fifo_4_shared_headreg + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + + -- o_empty_almost => empty_almost, + -- o_empty => empty, + + -- o_data_ren => data_ren, + -- o_rdata_0 => data_out(0), + -- o_rdata_1 => data_out(1), + -- o_rdata_2 => data_out(2), + -- o_rdata_3 => data_out(3), + + -- i_empty_almost => s_empty_almost, + -- i_empty => s_empty, + -- i_data_ren => s_data_ren, + -- i_rdata => s_rdata); + + --lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg + -- GENERIC MAP (tech => 0) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + -- o_empty_almost => empty_almost, + -- o_empty => empty, + + -- o_data_ren => data_ren, + -- o_rdata_0 => data_out(0), + -- o_rdata_1 => data_out(1), + -- o_rdata_2 => data_out(2), + -- o_rdata_3 => data_out(3), + + -- i_empty_almost => s_empty_almost, + -- i_empty => s_empty, + -- i_data_ren => s_data_ren, + -- i_rdata => s_rdata); + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + all_data_channel : FOR I IN 0 TO 3 GENERATE + ----------------------------------------------------------------------------- + -- READ + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + empty_reg(I) <= '1'; + empty_reg_2(I) <= '1'; + data_ren_reg(I) <= '1'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + empty_reg(I) <= empty(I); + empty_reg_2(I) <= empty_reg(I); + + data_ren_reg(I) <= data_ren(I); + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_out_obs(I) <= (OTHERS => '0'); + + pointer_read(I) <= 0; + error_now(I) <= '0'; + error_new(I) <= '0'; + + WARNING_DATA(I) <= '0'; + + data_out_obs(I) <= data_in(I)(0); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF data_out(I) = data_out_obs(I) THEN + WARNING_DATA(I) <= '0'; + ELSE + WARNING_DATA(I) <= '1'; + END IF; + + error_now(I) <= '0'; + IF empty_reg_2(I) = '0' THEN + IF data_ren_reg(I) = '0' THEN + + error_new(I) <= '0'; + --data_out_obs(I) <= data_out(I); + data_out_obs(I) <= data_in(I)(pointer_read(I)); + + + IF pointer_read(I) < 128/4-1 THEN + pointer_read(I) <= pointer_read(I) + 1; + ELSE + pointer_read(I) <= 0; + END IF; + + IF data_out(I) /= data_in(I)(pointer_read(I)) THEN + data_out_obs_1(I) <= data_out(I); + data_out_obs_2(I) <= data_in(I)(pointer_read(I)); + error_now(I) <= '1'; + error_new(I) <= '1'; + END IF; + END IF; + + END IF; + END IF; + END PROCESS; + + + + ----------------------------------------------------------------------------- + -- WRITE + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + full_reg(I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + full_reg(I) <= full(I); + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS proc_verif + IF rstn = '0' THEN -- asynchronous reset (active low) + pointer_write(I) <= 0; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF data_wen(I) = '0' THEN + IF full_reg(I) = '0' THEN + IF pointer_write(I) < 128/4-1 THEN + pointer_write(I) <= pointer_write(I)+1; + ELSE + pointer_write(I) <= 0; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE all_data_channel; + + wdata <= data_in(0)(pointer_write(0)) WHEN data_wen = "1110" ELSE + data_in(1)(pointer_write(1)) WHEN data_wen = "1101" ELSE + data_in(2)(pointer_write(2)) WHEN data_wen = "1011" ELSE + data_in(3)(pointer_write(3)) WHEN data_wen = "0111" ELSE + (OTHERS => 'X'); + + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + clk <= NOT clk AFTER 5 ns; -- 100 MHz + ----------------------------------------------------------------------------- + WaveGen_Proc : PROCESS + BEGIN + -- insert signal assignments here + WAIT UNTIL clk = '1'; + rstn <= '0'; + run <= '0'; + read_stop <= '1'; + write_stop <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + run <= '1'; + WAIT UNTIL clk = '1'; + WAIT FOR 10 us; + read_stop <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT FOR 10 us; + read_stop <= '1'; + WAIT FOR 10 us; + read_stop <= '0'; + WAIT FOR 1 us; + write_stop <= '1'; + WAIT FOR 10 us; + write_stop <= '0'; + WAIT FOR 80 us; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS WaveGen_Proc; + ----------------------------------------------------------------------------- + + + + + + ----------------------------------------------------------------------------- + -- RANDOM GENERATOR + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + VARIABLE seed1, seed2 : POSITIVE; + VARIABLE rand1 : REAL; + VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + random_vector <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + UNIFORM(seed1, seed2, rand1); + RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR( + to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)), + RANDOM_VECTOR_VAR'LENGTH) + ); + + random_vector <= RANDOM_VECTOR_VAR; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + rand_ren <= "1111" WHEN random_vector(0) = '0' ELSE + "1110" WHEN random_vector(2 DOWNTO 1) = "00" ELSE + "1101" WHEN random_vector(2 DOWNTO 1) = "01" ELSE + "1011" WHEN random_vector(2 DOWNTO 1) = "10" ELSE + "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE + + rand_wen <= "1111" WHEN random_vector(3) = '0' ELSE + "1110" WHEN random_vector(5 DOWNTO 4) = "00" ELSE + "1101" WHEN random_vector(5 DOWNTO 4) = "01" ELSE + "1011" WHEN random_vector(5 DOWNTO 4) = "10" ELSE + "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_wen <= (OTHERS => '1'); + data_ren <= (OTHERS => '1'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + + IF write_stop = '0' THEN + data_wen <= rand_ren; + ELSE + data_ren <= (OTHERS => '1'); + END IF; + + IF read_stop = '0' THEN + all_ren_bits : FOR I IN 0 TO 3 LOOP + IF empty(I) = '1' THEN + data_ren(I) <= '1'; + ELSE + data_ren(I) <= rand_ren(I); + END IF; + END LOOP all_ren_bits; + ELSE + data_ren <= (OTHERS => '1'); + END IF; + + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- empty <= (OTHERS => '1'); + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- empty <= empty_s; + -- END IF; + --END PROCESS; + + + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- data_f0_data_out_obs_data <= (OTHERS => '0'); + -- data_f1_data_out_obs_data <= (OTHERS => '0'); + -- data_f2_data_out_obs_data <= (OTHERS => '0'); + -- data_f3_data_out_obs_data <= (OTHERS => '0'); + -- data_f0_data_out_obs <= '0'; + -- data_f1_data_out_obs <= '0'; + -- data_f2_data_out_obs <= '0'; + -- data_f3_data_out_obs <= '0'; + + -- pointer_read <= (0, 0, 0, 0); + -- error_now <= (OTHERS => '0'); + -- error_new <= (OTHERS => '0'); + + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- error_now <= (OTHERS => '0'); + -- CASE data_ren IS + -- WHEN "1110" => + -- IF empty(0) = '0' THEN + -- error_new(0) <= '0'; + -- data_f0_data_out_obs_data <= data_f0_data_out(5 DOWNTO 0); + -- IF pointer_read(0) < 31 THEN + -- pointer_read(0) <= pointer_read(0)+1; + -- ELSE + -- pointer_read(0) <= 0; + -- END IF; + -- IF data_f0_data_out /= data_in(0)(pointer_read(0)) THEN + -- error_now(0) <= '1'; + -- error_new(0) <= '1'; + -- data_f0_data_out_obs <= '1'; + -- END IF; + -- --IF data_f0_data_out(29 DOWNTO 28) /= "00" THEN + -- -- data_f0_data_out_obs <= '1'; + -- --END IF; + -- END IF; + + -- WHEN "1101" => + -- IF empty(1) = '0' THEN + -- error_new(1) <= '0'; + -- data_f1_data_out_obs_data <= data_f1_data_out(5 DOWNTO 0); + -- IF pointer_read(1) < 31 THEN + -- pointer_read(1) <= pointer_read(1)+1; + -- ELSE + -- pointer_read(1) <= 0; + -- END IF; + -- IF data_f1_data_out /= data_in(1)(pointer_read(1)) THEN + -- error_new(1) <= '1'; + -- error_now(1) <= '1'; + -- data_f1_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "1011" => + -- IF empty(2) = '0' THEN + -- error_new(2) <= '0'; + -- data_f2_data_out_obs_data <= data_f2_data_out(5 DOWNTO 0); + -- IF pointer_read(2) < 31 THEN + -- pointer_read(2) <= pointer_read(2)+1; + -- ELSE + -- pointer_read(2) <= 0; + -- END IF; + -- IF data_f2_data_out /= data_in(2)(pointer_read(2)) THEN + -- error_new(2) <= '1'; + -- error_now(2) <= '1'; + -- data_f2_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "0111" => + -- IF empty(3) = '0' THEN + -- error_new(3) <= '0'; + -- data_f3_data_out_obs_data <= data_f3_data_out(5 DOWNTO 0); + -- IF pointer_read(3) < 31 THEN + -- pointer_read(3) <= pointer_read(3)+1; + -- ELSE + -- pointer_read(3) <= 0; + -- END IF; + -- IF data_f3_data_out /= data_in(3)(pointer_read(3)) THEN + -- error_new(3) <= '1'; + -- error_now(3) <= '1'; + -- data_f3_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "1111" => + -- NULL; + + + -- WHEN OTHERS => + -- REPORT "*** ERROR_DATA_REN ***" SEVERITY failure; + -- NULL; + -- END CASE; + + -- END IF; + --END PROCESS; + + + ------------------------------------------------------------------------------- + --clk <= NOT clk AFTER 5 ns; -- 100 MHz + + ------------------------------------------------------------------------------- + --WaveGen_Proc : PROCESS + --BEGIN + + -- -- insert signal assignments here + -- WAIT UNTIL clk = '1'; + -- rstn <= '0'; + -- run <= '0'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- rstn <= '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- run <= '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + + -- WAIT FOR 100 us; + -- REPORT "*** END simulation ***" SEVERITY failure; + -- WAIT; + + --END PROCESS WaveGen_Proc; + + ------------------------------------------------------------------------------- + --proc_verif : PROCESS (clk, rstn) + --BEGIN -- PROCESS proc_verif + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- pointer_write <= (0, 0, 0, 0); + -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + -- --IF rand_wen = "1111" THEN + -- CASE rand_wen IS + -- WHEN "1110" => + -- IF full(0) = '0' THEN + -- IF pointer_write(0) = 128/4-1 THEN + -- pointer_write(0) <= 0; + -- ELSE + -- pointer_write(0) <= pointer_write(0)+1; + -- END IF; + -- END IF; + + -- WHEN "1101" => + -- IF full(1) = '0' THEN + -- IF pointer_write(1) = 128/4-1 THEN + -- pointer_write(1) <= 0; + -- ELSE + -- pointer_write(1) <= pointer_write(1)+1; + -- END IF; + -- END IF; + + -- WHEN "1011" => + -- IF full(2) = '0' THEN + -- IF pointer_write(2) = 128/4-1 THEN + -- pointer_write(2) <= 0; + -- ELSE + -- pointer_write(2) <= pointer_write(2)+1; + -- END IF; + -- END IF; + -- WHEN "0111" => + -- IF full(3) = '0' THEN + -- IF pointer_write(3) = 128/4-1 THEN + -- pointer_write(3) <= 0; + -- ELSE + -- pointer_write(3) <= pointer_write(3)+1; + -- END IF; + -- END IF; + -- WHEN OTHERS => NULL; + -- END CASE; + + -- --END IF; + -- END IF; + --END PROCESS proc_verif; + + --wdata <= data_in(0)(pointer_write(0)) WHEN rand_wen(0) = '0' ELSE + -- data_in(1)(pointer_write(1)) WHEN rand_wen(1) = '0' ELSE + -- data_in(2)(pointer_write(2)) WHEN rand_wen(2) = '0' ELSE + -- data_in(3)(pointer_write(3)) WHEN rand_wen(3) = '0' ELSE + -- (OTHERS => '0'); + + --data_wen <= rand_wen; + + --data_ren <= rand_ren OR empty; + + + + +END; diff --git a/designs/Validation_FIFO_Shared/tb_with_head_reg_latency_0.vhd b/designs/Validation_FIFO_Shared/tb_with_head_reg_latency_0.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO_Shared/tb_with_head_reg_latency_0.vhd @@ -0,0 +1,595 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + COMPONENT lpp_fifo_4_shared_headreg_latency_0 + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + -- Common signal + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + SIGNAL run : STD_LOGIC := '0'; + + ----------------------------------------------------------------------------- + TYPE DATA_FIFO_VECTOR IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_obs : DATA_FIFO_VECTOR; + SIGNAL data_out_obs_1 : DATA_FIFO_VECTOR; + SIGNAL data_out_obs_2 : DATA_FIFO_VECTOR; + + SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '1'); + SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_out : DATA_FIFO_VECTOR; + + SIGNAL empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty_reg_2 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL full_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + ----------------------------------------------------------------------------- + TYPE DATA_CHANNEL IS ARRAY (0 TO 128/4-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + TYPE DATA_ARRAY IS ARRAY (0 TO 3) OF DATA_CHANNEL; + SIGNAL data_in : DATA_ARRAY; + + ----------------------------------------------------------------------------- + CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1+2+2; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE + CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0; + SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + -- + SIGNAL rand_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rand_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + + TYPE POINTER IS ARRAY (0 TO 3) OF INTEGER; + SIGNAL pointer_read : POINTER; + SIGNAL pointer_write : POINTER := (0, 0, 0, 0); + + --SIGNAL data_f0_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f0_data_out_obs : STD_LOGIC; + --SIGNAL data_f1_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f1_data_out_obs : STD_LOGIC; + --SIGNAL data_f2_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f2_data_out_obs : STD_LOGIC; + --SIGNAL data_f3_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f3_data_out_obs : STD_LOGIC; + SIGNAL error_now : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL error_new : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL read_stop : STD_LOGIC; + +-- SIGNAL empty_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + + ----------------------------------------------------------------------------- +BEGIN + + all_I : FOR I IN 0 TO 3 GENERATE + all_J : FOR J IN 0 TO 128/4-1 GENERATE + data_in(I)(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+I*(2**28)+1, 32)); + END GENERATE all_J; + END GENERATE all_I; + + + ----------------------------------------------------------------------------- + --lpp_waveform_fifo_1 : lpp_waveform_fifo + -- GENERIC MAP (tech => 0) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + + -- empty => s_empty, + -- empty_almost => s_empty_almost, + -- data_ren => s_data_ren, + -- rdata => s_rdata, + + -- full_almost => full_almost, + -- full => full, + -- data_wen => data_wen, + -- wdata => wdata); + + lpp_fifo_4_shared_1 : lpp_fifo_4_shared + GENERIC MAP ( + tech => 0, + Mem_use => use_RAM, + EMPTY_ALMOST_LIMIT => 16, + FULL_ALMOST_LIMIT => 5, + DataSz => 32, + AddrSz => 7) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + empty_almost => s_empty_almost, + empty => s_empty, + r_en => s_data_ren, + r_data => s_rdata, + + full_almost => full_almost, + full => full, + w_en => data_wen, + w_data => wdata); + + + --empty_almost <= s_empty_almost; + --empty <= s_empty; + + --s_data_ren <= data_ren; + --data_out(0) <= s_rdata; + --data_out(1) <= s_rdata; + --data_out(2) <= s_rdata; + --data_out(3) <= s_rdata; + + + + lpp_fifo_4_shared_headreg_1: lpp_fifo_4_shared_headreg_latency_0 + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + o_empty_almost => empty_almost, + o_empty => empty, + + o_data_ren => data_ren, + o_rdata_0 => data_out(0), + o_rdata_1 => data_out(1), + o_rdata_2 => data_out(2), + o_rdata_3 => data_out(3), + + i_empty_almost => s_empty_almost, + i_empty => s_empty, + i_data_ren => s_data_ren, + i_rdata => s_rdata); + + --lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg + -- GENERIC MAP (tech => 0) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + -- o_empty_almost => empty_almost, + -- o_empty => empty, + + -- o_data_ren => data_ren, + -- o_rdata_0 => data_out(0), + -- o_rdata_1 => data_out(1), + -- o_rdata_2 => data_out(2), + -- o_rdata_3 => data_out(3), + + -- i_empty_almost => s_empty_almost, + -- i_empty => s_empty, + -- i_data_ren => s_data_ren, + -- i_rdata => s_rdata); + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + all_data_channel : FOR I IN 0 TO 3 GENERATE + ----------------------------------------------------------------------------- + -- READ + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + empty_reg(I) <= '1'; + empty_reg_2(I) <= '1'; + data_ren_reg(I) <= '1'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + empty_reg(I) <= empty(I); + empty_reg_2(I) <= empty_reg(I); + + data_ren_reg(I) <= data_ren(I); + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_out_obs(I) <= (OTHERS => '0'); + + pointer_read(I) <= 0; + error_now(I) <= '0'; + error_new(I) <= '0'; + + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + error_now(I) <= '0'; + IF empty(I) = '0' THEN + IF data_ren(I) = '0' THEN + + error_new(I) <= '0'; + data_out_obs(I) <= data_out(I); + + IF pointer_read(I) < 128/4-1 THEN + pointer_read(I) <= pointer_read(I) + 1; + ELSE + pointer_read(I) <= 0; + END IF; + + IF data_out(I) /= data_in(I)(pointer_read(I)) THEN + data_out_obs_1(I) <= data_out(I); + data_out_obs_2(I) <= data_in(I)(pointer_read(I)); + error_now(I) <= '1'; + error_new(I) <= '1'; + END IF; + END IF; + + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- WRITE + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + full_reg(I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + full_reg(I) <= full(I); + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS proc_verif + IF rstn = '0' THEN -- asynchronous reset (active low) + pointer_write(I) <= 0; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF data_wen(I) = '0' THEN + IF full_reg(I) = '0' THEN + IF pointer_write(I) < 128/4-1 THEN + pointer_write(I) <= pointer_write(I)+1; + ELSE + pointer_write(I) <= 0; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE all_data_channel; + + wdata <= data_in(0)(pointer_write(0)) WHEN data_wen = "1110" ELSE + data_in(1)(pointer_write(1)) WHEN data_wen = "1101" ELSE + data_in(2)(pointer_write(2)) WHEN data_wen = "1011" ELSE + data_in(3)(pointer_write(3)) WHEN data_wen = "0111" ELSE + (OTHERS => 'X'); + + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + clk <= NOT clk AFTER 5 ns; -- 100 MHz + ----------------------------------------------------------------------------- + WaveGen_Proc : PROCESS + BEGIN + -- insert signal assignments here + WAIT UNTIL clk = '1'; + read_stop <= '0'; + rstn <= '0'; + run <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + run <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT FOR 10 us; + read_stop <= '1'; + WAIT FOR 10 us; + read_stop <= '0'; + WAIT FOR 80 us; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS WaveGen_Proc; + ----------------------------------------------------------------------------- + + + + + + ----------------------------------------------------------------------------- + -- RANDOM GENERATOR + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + VARIABLE seed1, seed2 : POSITIVE; + VARIABLE rand1 : REAL; + VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + random_vector <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + UNIFORM(seed1, seed2, rand1); + RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR( + to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)), + RANDOM_VECTOR_VAR'LENGTH) + ); + + random_vector <= RANDOM_VECTOR_VAR; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + rand_ren <= "1111" WHEN random_vector(0) = '0' ELSE + "1110" WHEN random_vector(2 DOWNTO 1) = "00" ELSE + "1101" WHEN random_vector(2 DOWNTO 1) = "01" ELSE + "1011" WHEN random_vector(2 DOWNTO 1) = "10" ELSE + "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE + + rand_wen <= "1111" WHEN random_vector(3) = '0' ELSE + "1110" WHEN random_vector(5 DOWNTO 4) = "00" ELSE + "1101" WHEN random_vector(5 DOWNTO 4) = "01" ELSE + "1011" WHEN random_vector(5 DOWNTO 4) = "10" ELSE + "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_wen <= (OTHERS => '1'); + data_ren <= (OTHERS => '1'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + data_wen <= rand_wen; + IF read_stop = '0' THEN + all_ren_bits : FOR I IN 0 TO 3 LOOP + IF empty(I) = '1' THEN + data_ren(I) <= '1'; + ELSE + data_ren(I) <= rand_ren(I); + END IF; + END LOOP all_ren_bits; + ELSE + data_ren <= (OTHERS => '1'); + END IF; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- empty <= (OTHERS => '1'); + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- empty <= empty_s; + -- END IF; + --END PROCESS; + + + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- data_f0_data_out_obs_data <= (OTHERS => '0'); + -- data_f1_data_out_obs_data <= (OTHERS => '0'); + -- data_f2_data_out_obs_data <= (OTHERS => '0'); + -- data_f3_data_out_obs_data <= (OTHERS => '0'); + -- data_f0_data_out_obs <= '0'; + -- data_f1_data_out_obs <= '0'; + -- data_f2_data_out_obs <= '0'; + -- data_f3_data_out_obs <= '0'; + + -- pointer_read <= (0, 0, 0, 0); + -- error_now <= (OTHERS => '0'); + -- error_new <= (OTHERS => '0'); + + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- error_now <= (OTHERS => '0'); + -- CASE data_ren IS + -- WHEN "1110" => + -- IF empty(0) = '0' THEN + -- error_new(0) <= '0'; + -- data_f0_data_out_obs_data <= data_f0_data_out(5 DOWNTO 0); + -- IF pointer_read(0) < 31 THEN + -- pointer_read(0) <= pointer_read(0)+1; + -- ELSE + -- pointer_read(0) <= 0; + -- END IF; + -- IF data_f0_data_out /= data_in(0)(pointer_read(0)) THEN + -- error_now(0) <= '1'; + -- error_new(0) <= '1'; + -- data_f0_data_out_obs <= '1'; + -- END IF; + -- --IF data_f0_data_out(29 DOWNTO 28) /= "00" THEN + -- -- data_f0_data_out_obs <= '1'; + -- --END IF; + -- END IF; + + -- WHEN "1101" => + -- IF empty(1) = '0' THEN + -- error_new(1) <= '0'; + -- data_f1_data_out_obs_data <= data_f1_data_out(5 DOWNTO 0); + -- IF pointer_read(1) < 31 THEN + -- pointer_read(1) <= pointer_read(1)+1; + -- ELSE + -- pointer_read(1) <= 0; + -- END IF; + -- IF data_f1_data_out /= data_in(1)(pointer_read(1)) THEN + -- error_new(1) <= '1'; + -- error_now(1) <= '1'; + -- data_f1_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "1011" => + -- IF empty(2) = '0' THEN + -- error_new(2) <= '0'; + -- data_f2_data_out_obs_data <= data_f2_data_out(5 DOWNTO 0); + -- IF pointer_read(2) < 31 THEN + -- pointer_read(2) <= pointer_read(2)+1; + -- ELSE + -- pointer_read(2) <= 0; + -- END IF; + -- IF data_f2_data_out /= data_in(2)(pointer_read(2)) THEN + -- error_new(2) <= '1'; + -- error_now(2) <= '1'; + -- data_f2_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "0111" => + -- IF empty(3) = '0' THEN + -- error_new(3) <= '0'; + -- data_f3_data_out_obs_data <= data_f3_data_out(5 DOWNTO 0); + -- IF pointer_read(3) < 31 THEN + -- pointer_read(3) <= pointer_read(3)+1; + -- ELSE + -- pointer_read(3) <= 0; + -- END IF; + -- IF data_f3_data_out /= data_in(3)(pointer_read(3)) THEN + -- error_new(3) <= '1'; + -- error_now(3) <= '1'; + -- data_f3_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "1111" => + -- NULL; + + + -- WHEN OTHERS => + -- REPORT "*** ERROR_DATA_REN ***" SEVERITY failure; + -- NULL; + -- END CASE; + + -- END IF; + --END PROCESS; + + + ------------------------------------------------------------------------------- + --clk <= NOT clk AFTER 5 ns; -- 100 MHz + + ------------------------------------------------------------------------------- + --WaveGen_Proc : PROCESS + --BEGIN + + -- -- insert signal assignments here + -- WAIT UNTIL clk = '1'; + -- rstn <= '0'; + -- run <= '0'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- rstn <= '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- run <= '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + + -- WAIT FOR 100 us; + -- REPORT "*** END simulation ***" SEVERITY failure; + -- WAIT; + + --END PROCESS WaveGen_Proc; + + ------------------------------------------------------------------------------- + --proc_verif : PROCESS (clk, rstn) + --BEGIN -- PROCESS proc_verif + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- pointer_write <= (0, 0, 0, 0); + -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + -- --IF rand_wen = "1111" THEN + -- CASE rand_wen IS + -- WHEN "1110" => + -- IF full(0) = '0' THEN + -- IF pointer_write(0) = 128/4-1 THEN + -- pointer_write(0) <= 0; + -- ELSE + -- pointer_write(0) <= pointer_write(0)+1; + -- END IF; + -- END IF; + + -- WHEN "1101" => + -- IF full(1) = '0' THEN + -- IF pointer_write(1) = 128/4-1 THEN + -- pointer_write(1) <= 0; + -- ELSE + -- pointer_write(1) <= pointer_write(1)+1; + -- END IF; + -- END IF; + + -- WHEN "1011" => + -- IF full(2) = '0' THEN + -- IF pointer_write(2) = 128/4-1 THEN + -- pointer_write(2) <= 0; + -- ELSE + -- pointer_write(2) <= pointer_write(2)+1; + -- END IF; + -- END IF; + -- WHEN "0111" => + -- IF full(3) = '0' THEN + -- IF pointer_write(3) = 128/4-1 THEN + -- pointer_write(3) <= 0; + -- ELSE + -- pointer_write(3) <= pointer_write(3)+1; + -- END IF; + -- END IF; + -- WHEN OTHERS => NULL; + -- END CASE; + + -- --END IF; + -- END IF; + --END PROCESS proc_verif; + + --wdata <= data_in(0)(pointer_write(0)) WHEN rand_wen(0) = '0' ELSE + -- data_in(1)(pointer_write(1)) WHEN rand_wen(1) = '0' ELSE + -- data_in(2)(pointer_write(2)) WHEN rand_wen(2) = '0' ELSE + -- data_in(3)(pointer_write(3)) WHEN rand_wen(3) = '0' ELSE + -- (OTHERS => '0'); + + --data_wen <= rand_wen; + + --data_ren <= rand_ren OR empty; + + + + +END; diff --git a/designs/Validation_FIFO_Shared/tb_with_head_reg_latency_1.vhd b/designs/Validation_FIFO_Shared/tb_with_head_reg_latency_1.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO_Shared/tb_with_head_reg_latency_1.vhd @@ -0,0 +1,610 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + COMPONENT lpp_fifo_4_shared_headreg_latency_1 + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + -- Common signal + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + SIGNAL run : STD_LOGIC := '0'; + + ----------------------------------------------------------------------------- + TYPE DATA_FIFO_VECTOR IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_obs : DATA_FIFO_VECTOR; + SIGNAL data_out_obs_1 : DATA_FIFO_VECTOR; + SIGNAL data_out_obs_2 : DATA_FIFO_VECTOR; + + SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '1'); + SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_out : DATA_FIFO_VECTOR; + + SIGNAL empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty_reg_2 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL full_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + ----------------------------------------------------------------------------- + TYPE DATA_CHANNEL IS ARRAY (0 TO 128/4-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + TYPE DATA_ARRAY IS ARRAY (0 TO 3) OF DATA_CHANNEL; + SIGNAL data_in : DATA_ARRAY; + + ----------------------------------------------------------------------------- + CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1+2+2; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE + CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0; + SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + -- + SIGNAL rand_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rand_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + + TYPE POINTER IS ARRAY (0 TO 3) OF INTEGER; + SIGNAL pointer_read : POINTER; + SIGNAL pointer_write : POINTER := (0, 0, 0, 0); + + --SIGNAL data_f0_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f0_data_out_obs : STD_LOGIC; + --SIGNAL data_f1_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f1_data_out_obs : STD_LOGIC; + --SIGNAL data_f2_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f2_data_out_obs : STD_LOGIC; + --SIGNAL data_f3_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f3_data_out_obs : STD_LOGIC; + SIGNAL error_now : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL error_new : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL WARNING_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL read_stop : STD_LOGIC; + SIGNAL write_stop : STD_LOGIC; + +-- SIGNAL empty_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + + ----------------------------------------------------------------------------- +BEGIN + + all_I : FOR I IN 0 TO 3 GENERATE + all_J : FOR J IN 0 TO 128/4-1 GENERATE + data_in(I)(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+I*(2**28)+1, 32)); + END GENERATE all_J; + END GENERATE all_I; + + + ----------------------------------------------------------------------------- + --lpp_waveform_fifo_1 : lpp_waveform_fifo + -- GENERIC MAP (tech => 0) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + + -- empty => s_empty, + -- empty_almost => s_empty_almost, + -- data_ren => s_data_ren, + -- rdata => s_rdata, + + -- full_almost => full_almost, + -- full => full, + -- data_wen => data_wen, + -- wdata => wdata); + + lpp_fifo_4_shared_1 : lpp_fifo_4_shared + GENERIC MAP ( + tech => 0, + Mem_use => use_RAM, + EMPTY_ALMOST_LIMIT => 16, + FULL_ALMOST_LIMIT => 5, + DataSz => 32, + AddrSz => 7) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + empty_almost => s_empty_almost, + empty => s_empty, + r_en => s_data_ren, + r_data => s_rdata, + + full_almost => full_almost, + full => full, + w_en => data_wen, + w_data => wdata); + + + + lpp_fifo_4_shared_headreg_1: lpp_fifo_4_shared_headreg_latency_1 + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + o_empty_almost => empty_almost, + o_empty => empty, + + o_data_ren => data_ren, + o_rdata_0 => data_out(0), + o_rdata_1 => data_out(1), + o_rdata_2 => data_out(2), + o_rdata_3 => data_out(3), + + i_empty_almost => s_empty_almost, + i_empty => s_empty, + i_data_ren => s_data_ren, + i_rdata => s_rdata); + + --lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg + -- GENERIC MAP (tech => 0) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + -- o_empty_almost => empty_almost, + -- o_empty => empty, + + -- o_data_ren => data_ren, + -- o_rdata_0 => data_out(0), + -- o_rdata_1 => data_out(1), + -- o_rdata_2 => data_out(2), + -- o_rdata_3 => data_out(3), + + -- i_empty_almost => s_empty_almost, + -- i_empty => s_empty, + -- i_data_ren => s_data_ren, + -- i_rdata => s_rdata); + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + all_data_channel : FOR I IN 0 TO 3 GENERATE + ----------------------------------------------------------------------------- + -- READ + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + empty_reg(I) <= '1'; + empty_reg_2(I) <= '1'; + data_ren_reg(I) <= '1'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + empty_reg(I) <= empty(I); + empty_reg_2(I) <= empty_reg(I); + + data_ren_reg(I) <= data_ren(I); + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_out_obs(I) <= (OTHERS => '0'); + + pointer_read(I) <= 0; + error_now(I) <= '0'; + error_new(I) <= '0'; + + WARNING_DATA(I) <= '0'; + + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF data_out_obs(I) = data_in(I)(pointer_read(I)) THEN + WARNING_DATA(I) <= '0'; + ELSE + WARNING_DATA(I) <= '1'; + END IF; + + error_now(I) <= '0'; + IF empty_reg_2(I) = '0' THEN + IF data_ren_reg(I) = '0' THEN + + error_new(I) <= '0'; + data_out_obs(I) <= data_out(I); + + IF pointer_read(I) < 128/4-1 THEN + pointer_read(I) <= pointer_read(I) + 1; + ELSE + pointer_read(I) <= 0; + END IF; + + IF data_out(I) /= data_in(I)(pointer_read(I)) THEN + data_out_obs_1(I) <= data_out(I); + data_out_obs_2(I) <= data_in(I)(pointer_read(I)); + error_now(I) <= '1'; + error_new(I) <= '1'; + END IF; + END IF; + + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- WRITE + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + full_reg(I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + full_reg(I) <= full(I); + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS proc_verif + IF rstn = '0' THEN -- asynchronous reset (active low) + pointer_write(I) <= 0; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF data_wen(I) = '0' THEN + IF full_reg(I) = '0' THEN + IF pointer_write(I) < 128/4-1 THEN + pointer_write(I) <= pointer_write(I)+1; + ELSE + pointer_write(I) <= 0; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE all_data_channel; + + wdata <= data_in(0)(pointer_write(0)) WHEN data_wen = "1110" ELSE + data_in(1)(pointer_write(1)) WHEN data_wen = "1101" ELSE + data_in(2)(pointer_write(2)) WHEN data_wen = "1011" ELSE + data_in(3)(pointer_write(3)) WHEN data_wen = "0111" ELSE + (OTHERS => 'X'); + + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + clk <= NOT clk AFTER 5 ns; -- 100 MHz + ----------------------------------------------------------------------------- + WaveGen_Proc : PROCESS + BEGIN + -- insert signal assignments here + WAIT UNTIL clk = '1'; + rstn <= '0'; + run <= '0'; + read_stop <= '1'; + write_stop <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + run <= '1'; + WAIT UNTIL clk = '1'; + WAIT FOR 10 us; + read_stop <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT FOR 10 us; + read_stop <= '1'; + WAIT FOR 10 us; + read_stop <= '0'; + WAIT FOR 1 us; + write_stop <= '1'; + WAIT FOR 10 us; + write_stop <= '0'; + WAIT FOR 80 us; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS WaveGen_Proc; + ----------------------------------------------------------------------------- + + + + + + ----------------------------------------------------------------------------- + -- RANDOM GENERATOR + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + VARIABLE seed1, seed2 : POSITIVE; + VARIABLE rand1 : REAL; + VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + random_vector <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + UNIFORM(seed1, seed2, rand1); + RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR( + to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)), + RANDOM_VECTOR_VAR'LENGTH) + ); + + random_vector <= RANDOM_VECTOR_VAR; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + rand_ren <= "1111" WHEN random_vector(0) = '0' ELSE + "1110" WHEN random_vector(2 DOWNTO 1) = "00" ELSE + "1101" WHEN random_vector(2 DOWNTO 1) = "01" ELSE + "1011" WHEN random_vector(2 DOWNTO 1) = "10" ELSE + "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE + + rand_wen <= "1111" WHEN random_vector(3) = '0' ELSE + "1110" WHEN random_vector(5 DOWNTO 4) = "00" ELSE + "1101" WHEN random_vector(5 DOWNTO 4) = "01" ELSE + "1011" WHEN random_vector(5 DOWNTO 4) = "10" ELSE + "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_wen <= (OTHERS => '1'); + data_ren <= (OTHERS => '1'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + + IF write_stop = '0' THEN + data_wen <= rand_ren; + ELSE + data_ren <= (OTHERS => '1'); + END IF; + + IF read_stop = '0' THEN + all_ren_bits : FOR I IN 0 TO 3 LOOP + IF empty(I) = '1' THEN + data_ren(I) <= '1'; + ELSE + data_ren(I) <= rand_ren(I); + END IF; + END LOOP all_ren_bits; + ELSE + data_ren <= (OTHERS => '1'); + END IF; + + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- empty <= (OTHERS => '1'); + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- empty <= empty_s; + -- END IF; + --END PROCESS; + + + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- data_f0_data_out_obs_data <= (OTHERS => '0'); + -- data_f1_data_out_obs_data <= (OTHERS => '0'); + -- data_f2_data_out_obs_data <= (OTHERS => '0'); + -- data_f3_data_out_obs_data <= (OTHERS => '0'); + -- data_f0_data_out_obs <= '0'; + -- data_f1_data_out_obs <= '0'; + -- data_f2_data_out_obs <= '0'; + -- data_f3_data_out_obs <= '0'; + + -- pointer_read <= (0, 0, 0, 0); + -- error_now <= (OTHERS => '0'); + -- error_new <= (OTHERS => '0'); + + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- error_now <= (OTHERS => '0'); + -- CASE data_ren IS + -- WHEN "1110" => + -- IF empty(0) = '0' THEN + -- error_new(0) <= '0'; + -- data_f0_data_out_obs_data <= data_f0_data_out(5 DOWNTO 0); + -- IF pointer_read(0) < 31 THEN + -- pointer_read(0) <= pointer_read(0)+1; + -- ELSE + -- pointer_read(0) <= 0; + -- END IF; + -- IF data_f0_data_out /= data_in(0)(pointer_read(0)) THEN + -- error_now(0) <= '1'; + -- error_new(0) <= '1'; + -- data_f0_data_out_obs <= '1'; + -- END IF; + -- --IF data_f0_data_out(29 DOWNTO 28) /= "00" THEN + -- -- data_f0_data_out_obs <= '1'; + -- --END IF; + -- END IF; + + -- WHEN "1101" => + -- IF empty(1) = '0' THEN + -- error_new(1) <= '0'; + -- data_f1_data_out_obs_data <= data_f1_data_out(5 DOWNTO 0); + -- IF pointer_read(1) < 31 THEN + -- pointer_read(1) <= pointer_read(1)+1; + -- ELSE + -- pointer_read(1) <= 0; + -- END IF; + -- IF data_f1_data_out /= data_in(1)(pointer_read(1)) THEN + -- error_new(1) <= '1'; + -- error_now(1) <= '1'; + -- data_f1_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "1011" => + -- IF empty(2) = '0' THEN + -- error_new(2) <= '0'; + -- data_f2_data_out_obs_data <= data_f2_data_out(5 DOWNTO 0); + -- IF pointer_read(2) < 31 THEN + -- pointer_read(2) <= pointer_read(2)+1; + -- ELSE + -- pointer_read(2) <= 0; + -- END IF; + -- IF data_f2_data_out /= data_in(2)(pointer_read(2)) THEN + -- error_new(2) <= '1'; + -- error_now(2) <= '1'; + -- data_f2_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "0111" => + -- IF empty(3) = '0' THEN + -- error_new(3) <= '0'; + -- data_f3_data_out_obs_data <= data_f3_data_out(5 DOWNTO 0); + -- IF pointer_read(3) < 31 THEN + -- pointer_read(3) <= pointer_read(3)+1; + -- ELSE + -- pointer_read(3) <= 0; + -- END IF; + -- IF data_f3_data_out /= data_in(3)(pointer_read(3)) THEN + -- error_new(3) <= '1'; + -- error_now(3) <= '1'; + -- data_f3_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "1111" => + -- NULL; + + + -- WHEN OTHERS => + -- REPORT "*** ERROR_DATA_REN ***" SEVERITY failure; + -- NULL; + -- END CASE; + + -- END IF; + --END PROCESS; + + + ------------------------------------------------------------------------------- + --clk <= NOT clk AFTER 5 ns; -- 100 MHz + + ------------------------------------------------------------------------------- + --WaveGen_Proc : PROCESS + --BEGIN + + -- -- insert signal assignments here + -- WAIT UNTIL clk = '1'; + -- rstn <= '0'; + -- run <= '0'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- rstn <= '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- run <= '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + + -- WAIT FOR 100 us; + -- REPORT "*** END simulation ***" SEVERITY failure; + -- WAIT; + + --END PROCESS WaveGen_Proc; + + ------------------------------------------------------------------------------- + --proc_verif : PROCESS (clk, rstn) + --BEGIN -- PROCESS proc_verif + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- pointer_write <= (0, 0, 0, 0); + -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + -- --IF rand_wen = "1111" THEN + -- CASE rand_wen IS + -- WHEN "1110" => + -- IF full(0) = '0' THEN + -- IF pointer_write(0) = 128/4-1 THEN + -- pointer_write(0) <= 0; + -- ELSE + -- pointer_write(0) <= pointer_write(0)+1; + -- END IF; + -- END IF; + + -- WHEN "1101" => + -- IF full(1) = '0' THEN + -- IF pointer_write(1) = 128/4-1 THEN + -- pointer_write(1) <= 0; + -- ELSE + -- pointer_write(1) <= pointer_write(1)+1; + -- END IF; + -- END IF; + + -- WHEN "1011" => + -- IF full(2) = '0' THEN + -- IF pointer_write(2) = 128/4-1 THEN + -- pointer_write(2) <= 0; + -- ELSE + -- pointer_write(2) <= pointer_write(2)+1; + -- END IF; + -- END IF; + -- WHEN "0111" => + -- IF full(3) = '0' THEN + -- IF pointer_write(3) = 128/4-1 THEN + -- pointer_write(3) <= 0; + -- ELSE + -- pointer_write(3) <= pointer_write(3)+1; + -- END IF; + -- END IF; + -- WHEN OTHERS => NULL; + -- END CASE; + + -- --END IF; + -- END IF; + --END PROCESS proc_verif; + + --wdata <= data_in(0)(pointer_write(0)) WHEN rand_wen(0) = '0' ELSE + -- data_in(1)(pointer_write(1)) WHEN rand_wen(1) = '0' ELSE + -- data_in(2)(pointer_write(2)) WHEN rand_wen(2) = '0' ELSE + -- data_in(3)(pointer_write(3)) WHEN rand_wen(3) = '0' ELSE + -- (OTHERS => '0'); + + --data_wen <= rand_wen; + + --data_ren <= rand_ren OR empty; + + + + +END; diff --git a/designs/Validation_FIFO_Shared/testbench_package.vhd b/designs/Validation_FIFO_Shared/testbench_package.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO_Shared/testbench_package.vhd @@ -0,0 +1,136 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +--LIBRARY gaisler; +--USE gaisler.libdcom.ALL; +--USE gaisler.sim.ALL; +--USE gaisler.jtagtst.ALL; +--LIBRARY techmap; +--USE techmap.gencomp.ALL; + + +PACKAGE testbench_package IS + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END testbench_package; + +PACKAGE BODY testbench_package IS + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + apbi.pwdata <= pwdata; + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + + END APB_WRITE; + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '0'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + prdata <= apbo.prdata; + END APB_READ; + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + WAIT UNTIL clk = '1'; + ahbmo.HADDR <= haddr; + ahbmo.HPROT <= "0011"; + ahbmo.HIRQ <= (OTHERS => '0'); + ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); + ahbmo.HINDEX <= hindex; + ahbmo.HBUSREQ <= '1'; + ahbmo.HLOCK <= '1'; + ahbmo.HSIZE <= HSIZE_WORD; + ahbmo.HBURST <= HBURST_SINGLE; + ahbmo.HTRANS <= HTRANS_NONSEQ; + ahbmo.HWRITE <= '0'; + WHILE ahbmi.HREADY = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + ahbmo.HBUSREQ <= '0'; + ahbmo.HLOCK <= '0'; + ahbmo.HTRANS <= HTRANS_IDLE; + WHILE ahbmi.HREADY = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + hrdata <= ahbmi.HRDATA; + --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + ahbmo.HLOCK <= '0'; + WAIT UNTIL clk = '1'; + + END AHB_READ; + +END testbench_package; diff --git a/designs/Validation_FIFO_Shared/wave.do b/designs/Validation_FIFO_Shared/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO_Shared/wave.do @@ -0,0 +1,27 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/clk +add wave -noupdate /testbench/rstn +add wave -noupdate /testbench/run +add wave -noupdate /testbench/read_stop +add wave -noupdate /testbench/write_stop +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/error_now(3) {-height 15 -radix hexadecimal} /testbench/error_now(2) {-height 15 -radix hexadecimal} /testbench/error_now(1) {-height 15 -radix hexadecimal} /testbench/error_now(0) {-height 15 -radix hexadecimal}} /testbench/error_now +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/error_new(3) {-height 15 -radix hexadecimal} /testbench/error_new(2) {-height 15 -radix hexadecimal} /testbench/error_new(1) {-height 15 -radix hexadecimal} /testbench/error_new(0) {-height 15 -radix hexadecimal}} /testbench/error_new +add wave -noupdate /testbench/warning_data +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {41355000 ps} 0} +configure wave -namecolwidth 341 +configure wave -valuecolwidth 172 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {699496876 ps} diff --git a/designs/Validation_FIFO_Shared/wave_head_reg_latency_0.do b/designs/Validation_FIFO_Shared/wave_head_reg_latency_0.do new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO_Shared/wave_head_reg_latency_0.do @@ -0,0 +1,59 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/clk +add wave -noupdate /testbench/rstn +add wave -noupdate /testbench/run +add wave -noupdate -expand -group FIFO_IN /testbench/full_almost +add wave -noupdate -expand -group FIFO_IN /testbench/full +add wave -noupdate -expand -group FIFO_IN -expand /testbench/data_wen +add wave -noupdate -expand -group FIFO_IN -radix hexadecimal /testbench/wdata +add wave -noupdate -expand -group internal /testbench/s_empty_almost +add wave -noupdate -expand -group internal -expand /testbench/s_empty +add wave -noupdate -expand -group internal -expand /testbench/s_data_ren +add wave -noupdate -expand -group internal -radix hexadecimal /testbench/s_rdata +add wave -noupdate /testbench/pointer_write +add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty_almost +add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty +add wave -noupdate -expand -group FIFO_OUT -radix binary -expand -subitemconfig {/testbench/data_ren(3) {-radix binary} /testbench/data_ren(2) {-radix binary} /testbench/data_ren(1) {-radix binary} /testbench/data_ren(0) {-radix binary}} /testbench/data_ren +add wave -noupdate -expand -group FIFO_OUT -radix hexadecimal -expand -subitemconfig {/testbench/data_out(0) {-height 15 -radix hexadecimal} /testbench/data_out(1) {-height 15 -radix hexadecimal} /testbench/data_out(2) {-height 15 -radix hexadecimal} /testbench/data_out(3) {-height 15 -radix hexadecimal}} /testbench/data_out +add wave -noupdate -expand /testbench/pointer_read +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/error_now(3) {-height 15 -radix hexadecimal} /testbench/error_now(2) {-height 15 -radix hexadecimal} /testbench/error_now(1) {-height 15 -radix hexadecimal} /testbench/error_now(0) {-height 15 -radix hexadecimal}} /testbench/error_now +add wave -noupdate -radix hexadecimal /testbench/error_new +add wave -noupdate /testbench/read_stop +add wave -noupdate -expand /testbench/empty_reg +add wave -noupdate -expand /testbench/data_ren +add wave -noupdate -expand -group Head_REG /testbench/lpp_fifo_4_shared_headreg_1/o_empty_almost +add wave -noupdate -expand -group Head_REG /testbench/lpp_fifo_4_shared_headreg_1/o_empty +add wave -noupdate -expand -group Head_REG /testbench/lpp_fifo_4_shared_headreg_1/o_data_ren +add wave -noupdate -expand -group Head_REG -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/o_rdata_0 +add wave -noupdate -expand -group Head_REG -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/o_rdata_1 +add wave -noupdate -expand -group Head_REG -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/o_rdata_2 +add wave -noupdate -expand -group Head_REG -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/o_rdata_3 +add wave -noupdate -expand -group {HEAD_REG - FIFO_Shared} /testbench/lpp_fifo_4_shared_headreg_1/i_empty_almost +add wave -noupdate -expand -group {HEAD_REG - FIFO_Shared} /testbench/lpp_fifo_4_shared_headreg_1/i_empty +add wave -noupdate -expand -group {HEAD_REG - FIFO_Shared} /testbench/lpp_fifo_4_shared_headreg_1/i_data_ren +add wave -noupdate -expand -group {HEAD_REG - FIFO_Shared} -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/i_rdata +add wave -noupdate -radix hexadecimal /testbench/lpp_fifo_4_shared_headreg_1/reg_head_data +add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/reg_head_full +add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/i_data_ren_pre +add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/o_data_ren_pre +add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/i_data_ren_s_temp +add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/i_data_ren_s +add wave -noupdate /testbench/lpp_fifo_4_shared_headreg_1/i_empty_reg +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {75000 ps} 0} +configure wave -namecolwidth 341 +configure wave -valuecolwidth 172 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {215438 ps} diff --git a/designs/Validation_FIFO_Shared/wave_head_reg_latency_1.do b/designs/Validation_FIFO_Shared/wave_head_reg_latency_1.do new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO_Shared/wave_head_reg_latency_1.do @@ -0,0 +1,41 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/clk +add wave -noupdate /testbench/rstn +add wave -noupdate /testbench/run +add wave -noupdate -expand /testbench/empty +add wave -noupdate /testbench/full +add wave -noupdate /testbench/read_stop +add wave -noupdate /testbench/write_stop +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/error_now(3) {-height 15 -radix hexadecimal} /testbench/error_now(2) {-height 15 -radix hexadecimal} /testbench/error_now(1) {-height 15 -radix hexadecimal} /testbench/error_now(0) {-height 15 -radix hexadecimal}} /testbench/error_now +add wave -noupdate -radix hexadecimal /testbench/error_new +add wave -noupdate -expand -group FIFO_IN /testbench/full_almost +add wave -noupdate -expand -group FIFO_IN /testbench/full +add wave -noupdate -expand -group FIFO_IN /testbench/data_wen +add wave -noupdate -expand -group FIFO_IN -radix hexadecimal /testbench/wdata +add wave -noupdate -group internal /testbench/s_empty_almost +add wave -noupdate -group internal -expand /testbench/s_empty +add wave -noupdate -group internal -expand /testbench/s_data_ren +add wave -noupdate -group internal -radix hexadecimal /testbench/s_rdata +add wave -noupdate /testbench/pointer_write +add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty_almost +add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty +add wave -noupdate -expand -group FIFO_OUT -radix binary -expand -subitemconfig {/testbench/data_ren(3) {-height 15 -radix binary} /testbench/data_ren(2) {-height 15 -radix binary} /testbench/data_ren(1) {-height 15 -radix binary} /testbench/data_ren(0) {-height 15 -radix binary}} /testbench/data_ren +add wave -noupdate -expand -group FIFO_OUT -radix hexadecimal -expand -subitemconfig {/testbench/data_out(0) {-height 15 -radix hexadecimal} /testbench/data_out(1) {-height 15 -radix hexadecimal} /testbench/data_out(2) {-height 15 -radix hexadecimal} /testbench/data_out(3) {-height 15 -radix hexadecimal}} /testbench/data_out +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {41365000 ps} 0} +configure wave -namecolwidth 341 +configure wave -valuecolwidth 172 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {40912888 ps} {42319723 ps} diff --git a/designs/Validation_IIR_LFR/IIR_CEL_TEST.vhd b/designs/Validation_IIR_LFR/IIR_CEL_TEST.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/IIR_CEL_TEST.vhd @@ -0,0 +1,128 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_lfr_filter_coeff.ALL; +USE lpp.general_purpose.ALL; + +ENTITY IIR_CEL_TEST IS + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + sample_in_val : IN STD_LOGIC; + sample_in : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); + + sample_out_val : OUT STD_LOGIC; + sample_out : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0)); +END IIR_CEL_TEST; + +ARCHITECTURE beh OF IIR_CEL_TEST IS + CONSTANT ChanelCount : INTEGER := 8; + CONSTANT Coef_SZ : INTEGER := 9; + CONSTANT CoefCntPerCel : INTEGER := 6; + CONSTANT CoefPerCel : INTEGER := 5; + CONSTANT Cels_count : INTEGER := 5; + + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + + + ----------------------------------------------------------------------------- + CONSTANT CEL_NUMBER : INTEGER := 5; + CONSTANT COEFFICIENT_SIZE : INTEGER := 9; + CONSTANT POINT_POSITION : INTEGER := 7; + CONSTANT COEFFICIENT_PER_CEL : INTEGER := 5; + SIGNAL coeff_test : STD_LOGIC_VECTOR((CEL_NUMBER * 5 * COEFFICIENT_SIZE)-1 DOWNTO 0); + SIGNAL f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := + ( + (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), + (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), + (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), + (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), + (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) + ); + SIGNAL f0_to_f1_gain : COEFF_CEL_REAL := + ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); + + SUBTYPE COEFFICIENT IS STD_LOGIC_VECTOR(COEFFICIENT_SIZE-1 DOWNTO 0); + TYPE COEFFICIENT_CEL IS ARRAY (1 TO 5) OF COEFFICIENT; + TYPE COEFFICIENT_GLOBAL IS ARRAY (INTEGER RANGE <>) OF COEFFICIENT_CEL; + + SIGNAL coeff_test_2 : COEFFICIENT_GLOBAL(1 TO 5); + ----------------------------------------------------------------------------- + SIGNAL f_to_f0_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := + ( + (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), + (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), + (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), + (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), + (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) + ); + SIGNAL f_to_f0_gain : COEFF_CEL_REAL := + ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); + +BEGIN -- beh + + coeff_test <= + get_IIR_CEL_FILTER_CONFIG( + COEFFICIENT_SIZE, POINT_POSITION, CEL_NUMBER, + f0_to_f1_sos, f0_to_f1_gain); + + all_cel: FOR I IN 0 TO 4 GENERATE + all_coeff: FOR J IN 0 TO 4 GENERATE + coeff_test_2(I+1)(J+1) <= + coeff_test((I*5+J+1)*COEFFICIENT_SIZE-1 DOWNTO (I*5+J)*COEFFICIENT_SIZE); + END GENERATE all_coeff; + END GENERATE all_cel; + + + coefs_v2 <= CoefsInitValCst_v2; + + IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 + GENERIC MAP ( + tech => 0, + Mem_use => use_CEL, -- use_RAM + Sample_SZ => 18, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, + Coef_sel_SZ => 5, + Cels_count => Cels_count, + ChanelsCount => ChanelCount) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => 7, + coefs => coefs_v2, + sample_in_val => sample_in_val, + sample_in => sample_in, + sample_out_val => sample_out_val, + sample_out => sample_out); + +END beh; diff --git a/designs/Validation_IIR_LFR/IIR_CEL_TEST_v3.vhd b/designs/Validation_IIR_LFR/IIR_CEL_TEST_v3.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/IIR_CEL_TEST_v3.vhd @@ -0,0 +1,157 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_lfr_filter_coeff.ALL; +USE lpp.general_purpose.ALL; + +ENTITY IIR_CEL_TEST_v3 IS + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + sample_in1_val : IN STD_LOGIC; + sample_in1 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); + sample_in2_val : IN STD_LOGIC; + sample_in2 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); + + sample_out1_val : OUT STD_LOGIC; + sample_out1 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0); + sample_out2_val : OUT STD_LOGIC; + sample_out2 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0) + ); +END IIR_CEL_TEST_v3; + +ARCHITECTURE beh OF IIR_CEL_TEST_v3 IS + CONSTANT ChanelCount : INTEGER := 8; + CONSTANT Coef_SZ : INTEGER := 9; + CONSTANT CoefCntPerCel : INTEGER := 6; + CONSTANT CoefPerCel : INTEGER := 5; + CONSTANT Cels_count : INTEGER := 5; + + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + + + ----------------------------------------------------------------------------- + CONSTANT CEL_NUMBER : INTEGER := 5; + CONSTANT COEFFICIENT_SIZE : INTEGER := 9; + CONSTANT POINT_POSITION : INTEGER := 7; + CONSTANT COEFFICIENT_PER_CEL : INTEGER := 5; + SIGNAL coeff_test : STD_LOGIC_VECTOR((CEL_NUMBER * 5 * COEFFICIENT_SIZE)-1 DOWNTO 0); + SIGNAL f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := + ( + (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), + (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), + (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), + (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), + (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) + ); + SIGNAL f0_to_f1_gain : COEFF_CEL_REAL := + ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); + + SUBTYPE COEFFICIENT IS STD_LOGIC_VECTOR(COEFFICIENT_SIZE-1 DOWNTO 0); + TYPE COEFFICIENT_CEL IS ARRAY (1 TO 5) OF COEFFICIENT; + TYPE COEFFICIENT_GLOBAL IS ARRAY (INTEGER RANGE <>) OF COEFFICIENT_CEL; + + SIGNAL coeff_test_2 : COEFFICIENT_GLOBAL(1 TO 5); + ----------------------------------------------------------------------------- + SIGNAL f_to_f0_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) := + ( + (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583), + (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351), + (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102), + (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464), + (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691) + ); + SIGNAL f_to_f0_gain : COEFF_CEL_REAL := + ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0); + +BEGIN -- beh + + coeff_test <= + get_IIR_CEL_FILTER_CONFIG( + COEFFICIENT_SIZE, POINT_POSITION, CEL_NUMBER, + f0_to_f1_sos, f0_to_f1_gain); + + all_cel: FOR I IN 0 TO 4 GENERATE + all_coeff: FOR J IN 0 TO 4 GENERATE + coeff_test_2(I+1)(J+1) <= + coeff_test((I*5+J+1)*COEFFICIENT_SIZE-1 DOWNTO (I*5+J)*COEFFICIENT_SIZE); + END GENERATE all_coeff; + END GENERATE all_cel; + + + coefs_v2 <= CoefsInitValCst_v2; + + --IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 + -- GENERIC MAP ( + -- tech => 0, + -- Mem_use => use_CEL, -- use_RAM + -- Sample_SZ => 18, + -- Coef_SZ => Coef_SZ, + -- Coef_Nb => 25, + -- Coef_sel_SZ => 5, + -- Cels_count => Cels_count, + -- ChanelsCount => ChanelCount) + -- PORT MAP ( + -- rstn => rstn, + -- clk => clk, + -- virg_pos => 7, + -- coefs => coefs_v2, + -- sample_in_val => sample_in_val, + -- sample_in => sample_in, + -- sample_out_val => sample_out_val, + -- sample_out => sample_out); + + IIR_CEL_CTRLR_v3_1: IIR_CEL_CTRLR_v3 + GENERIC MAP ( + tech => 0, + Mem_use => use_CEL, + Sample_SZ => 18, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, + Coef_sel_SZ => 5, + Cels_count => Cels_count, + ChanelsCount => ChanelCount) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => 7, + coefs => coefs_v2, + sample_in1_val => sample_in1_val, + sample_in1 => sample_in1, + sample_in2_val => sample_in2_val, + sample_in2 => sample_in2, + sample_out1_val => sample_out1_val, + sample_out1 => sample_out1, + sample_out2_val => sample_out2_val, + sample_out2 => sample_out2); + +END beh; diff --git a/designs/Validation_IIR_LFR/Makefile b/designs/Validation_IIR_LFR/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/Makefile @@ -0,0 +1,53 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES= +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft_rtax \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_apbreg.vhd \ + CoreFFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/Validation_IIR_LFR/run.do b/designs/Validation_IIR_LFR/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/run.do @@ -0,0 +1,20 @@ +vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/iir_filter.vhd + +vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd +vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd + +vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd +vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd + +vcom -quiet -93 -work work IIR_CEL_TEST.vhd +vcom -quiet -93 -work work IIR_CEL_TEST_v3.vhd +vcom -quiet -93 -work work tb.vhd + +vsim work.testbench + +log -r * + +do wave.do + +run -all + diff --git a/designs/Validation_IIR_LFR/run_add_sub.do b/designs/Validation_IIR_LFR/run_add_sub.do new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/run_add_sub.do @@ -0,0 +1,12 @@ +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd + +vcom -quiet -93 -work work tb_cic_lfr_add_sub.vhd + +vsim work.testbench + +log -r * + +do wave_add_sub.do + +run -all diff --git a/designs/Validation_IIR_LFR/run_calc.do b/designs/Validation_IIR_LFR/run_calc.do new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/run_calc.do @@ -0,0 +1,10 @@ +vcom -quiet -93 -work work tb_calc.vhd + +vsim work.testbench + +log -r * + +do wave_calc.do + +run -all + diff --git a/designs/Validation_IIR_LFR/run_calc.vhd b/designs/Validation_IIR_LFR/run_calc.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/run_calc.vhd @@ -0,0 +1,10 @@ +vcom -quiet -93 -work work tb_calc.vhd + +vsim work.testbench + +log -r * + +do wave_calc.do + +run -all + diff --git a/designs/Validation_IIR_LFR/tb.vhd b/designs/Validation_IIR_LFR/tb.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/tb.vhd @@ -0,0 +1,262 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_lfr_filter_coeff.ALL; +USE lpp.general_purpose.ALL; +USE lpp.data_type_pkg.ALL; +USE lpp.chirp_pkg.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.general_purpose.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + COMPONENT IIR_CEL_TEST + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + sample_in_val : IN STD_LOGIC; + sample_in : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); + sample_out_val : OUT STD_LOGIC; + sample_out : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0)); + END COMPONENT; + + COMPONENT IIR_CEL_TEST_v3 + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + sample_in1_val : IN STD_LOGIC; + sample_in1 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); + sample_in2_val : IN STD_LOGIC; + sample_in2 : IN samplT(7 DOWNTO 0, 17 DOWNTO 0); + sample_out1_val : OUT STD_LOGIC; + sample_out1 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0); + sample_out2_val : OUT STD_LOGIC; + sample_out2 : OUT samplT(7 DOWNTO 0, 17 DOWNTO 0)); + END COMPONENT; + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL clk_24k : STD_LOGIC := '0'; + SIGNAL clk_24k_r : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + + SIGNAL sample : Samples(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL sample_val_2 : STD_LOGIC; + + SIGNAL data_chirp : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_chirp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL sample_s : samplT(7 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_out_s : samplT(7 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_out_s2 : samplT(7 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_out_val : STD_LOGIC; + + + SIGNAL sample_out1_val : STD_LOGIC; + SIGNAL sample_out2_val : STD_LOGIC; + SIGNAL sample_out1 : samplT(7 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_out2 : samplT(7 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_out1_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_out2_reg : samplT(7 DOWNTO 0, 17 DOWNTO 0); + + SIGNAL sample_s_v3 : samplT(7 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_val_v3 : STD_LOGIC; + SIGNAL sample_val_v3_2 : STD_LOGIC; + + SIGNAL temp : STD_LOGIC; +BEGIN + + ----------------------------------------------------------------------------- + -- CLOCK and RESET + ----------------------------------------------------------------------------- + clk <= NOT clk AFTER 5 ns; + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + rstn <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT FOR 30 ms; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS; + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- LPP_LFR_FILTER + ----------------------------------------------------------------------------- + lpp_lfr_filter_1: lpp_lfr_filter + GENERIC MAP ( + Mem_use => use_CEL) + PORT MAP ( + sample => sample, + sample_val => sample_val, + + clk => clk, + rstn => rstn, + + data_shaping_SP0 => '0', + data_shaping_SP1 => '0', + data_shaping_R0 => '0', + data_shaping_R1 => '0', + data_shaping_R2 => '0', + + sample_f0_val => OPEN, + sample_f1_val => OPEN, + sample_f2_val => OPEN, + sample_f3_val => OPEN, + sample_f0_wdata => OPEN, + sample_f1_wdata => OPEN, + sample_f2_wdata => OPEN, + sample_f3_wdata => OPEN); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- SAMPLE GENERATION + ----------------------------------------------------------------------------- + clk_24k <= NOT clk_24k AFTER 20345 ns; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_val <= '0'; + sample_val_2 <= '0'; + clk_24k_r <= '0'; + temp <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + clk_24k_r <= clk_24k; + IF clk_24k = '1' AND clk_24k_r = '0' THEN + sample_val <= '1'; + sample_val_2 <= temp; + temp <= NOT temp; + ELSE + sample_val <= '0'; + sample_val_2 <= '0'; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + chirp_1: chirp + GENERIC MAP ( + LOW_FREQUENCY_LIMIT => 0, + HIGH_FREQUENCY_LIMIT => 2000, + NB_POINT_TO_GEN => 10000, + AMPLITUDE => 100, + NB_BITS => 16) + PORT MAP ( + clk => clk, + rstn => rstn, + run => '1', + data_ack => sample_val, + data => data_chirp); + + chirp_2: chirp + GENERIC MAP ( + LOW_FREQUENCY_LIMIT => 0, + HIGH_FREQUENCY_LIMIT => 2000, + NB_POINT_TO_GEN => 100000, + AMPLITUDE => 200, + NB_BITS => 16) + PORT MAP ( + clk => clk, + rstn => rstn, + run => '1', + data_ack => sample_val, + data => data_chirp_2); + + all_channel: FOR I IN 0 TO 3 GENERATE + sample(2*I) <= data_chirp; + sample(2*I+1) <= data_chirp_2; + END GENERATE all_channel; + ----------------------------------------------------------------------------- + + all_channel_test: FOR I IN 0 TO 3 GENERATE + all_bit_test: FOR J IN 0 TO 15 GENERATE + sample_s(2*I ,J) <= data_chirp(J); + sample_s(2*I+1,J) <= data_chirp_2(J); + END GENERATE all_bit_test; + sample_s(2*I,16) <= data_chirp(15); + sample_s(2*I,17) <= data_chirp(15); + sample_s(2*I+1,16) <= data_chirp_2(15); + sample_s(2*I+1,17) <= data_chirp_2(15); + END GENERATE all_channel_test; + + IIR_CEL_TEST_1: IIR_CEL_TEST + PORT MAP ( + rstn => rstn, + clk => clk, + sample_in_val => sample_val, + sample_in => sample_s, + sample_out_val => sample_out_val, + sample_out => sample_out_s); + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + all_channel: FOR I IN 0 TO 7 LOOP + all_bit: FOR J IN 0 TO 17 LOOP + sample_out_s2(I,J) <= '0'; + END LOOP all_bit; + END LOOP all_channel; + + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF sample_out_val = '1' THEN + sample_out_s2 <= sample_out_s; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + IIR_CEL_TEST_v3_1: IIR_CEL_TEST_v3 + PORT MAP ( + rstn => rstn, + clk => clk, + sample_in1_val => sample_val_v3, + sample_in1 => sample_s_v3, + sample_in2_val => sample_val_v3_2, + sample_in2 => sample_s_v3, + sample_out1_val => sample_out1_val, + sample_out1 => sample_out1, + sample_out2_val => sample_out2_val, + sample_out2 => sample_out2); + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF sample_val = '1' THEN + sample_s_v3 <= sample_s; + END IF; + sample_val_v3 <= sample_val; + sample_val_v3_2 <= sample_val_2; + + IF sample_out1_val = '1' THEN + sample_out1_reg <= sample_out1; + END IF; + IF sample_out2_val = '1' THEN + sample_out2_reg <= sample_out2; + END IF; + END IF; + + END PROCESS; + + + +END; diff --git a/designs/Validation_IIR_LFR/tb_calc.vhd b/designs/Validation_IIR_LFR/tb_calc.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/tb_calc.vhd @@ -0,0 +1,124 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.cic_pkg.ALL; +USE lpp.data_type_pkg.ALL; +USE lpp.chirp_pkg.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + + CONSTANT VECTOR_SIZE : INTEGER := 4*2; + SIGNAL VECTOR_1 : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + SIGNAL VECTOR_MIN : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + SIGNAL VECTOR_MAX : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + + SIGNAL all_done : STD_LOGIC; + SIGNAL all_ok : STD_LOGIC; + SIGNAL all_ok_E : STD_LOGIC; + + SIGNAL A : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + SIGNAL B : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + + SIGNAL C : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + + SIGNAL D_0 : STD_LOGIC_VECTOR(VECTOR_SIZE/2 DOWNTO 0); + SIGNAL D_1 : STD_LOGIC_VECTOR(VECTOR_SIZE/2-1 DOWNTO 0); + SIGNAL D : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + + SIGNAL E : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + + +BEGIN + VECTOR_1(0) <= '1'; + VECTOR_1(VECTOR_SIZE-1 DOWNTO 1) <= (OTHERS => '0') ; + + VECTOR_MIN(VECTOR_SIZE-1) <= '1'; + VECTOR_MIN(VECTOR_SIZE-2 DOWNTO 0) <= (OTHERS => '0') ; + VECTOR_MAX(VECTOR_SIZE-1) <= '0'; + VECTOR_MAX(VECTOR_SIZE-2 DOWNTO 0) <= (OTHERS => '1') ; + + clk <= NOT clk AFTER 5 ns; + + PROCESSD_0(VECTOR_SIZE/2) + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + rstn <= '0'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + + + WAIT FOR 2 ms; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + A <= VECTOR_MIN; + B <= VECTOR_MIN; + all_done <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + all_done <= '0'; + IF A = VECTOR_MAX THEN + A <= VECTOR_MIN; + IF B = VECTOR_MAX THEN + B <= VECTOR_MIN; + all_done <= '1'; + ELSE + B <= STD_LOGIC_VECTOR(signed(B) + signed(VECTOR_1)); + END IF; + ELSE + A <= STD_LOGIC_VECTOR(signed(A) + signed(VECTOR_1)); + END IF; + END IF; + END PROCESS; + + + C <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B)); + + E <= STD_LOGIC_VECTOR(UNSIGNED(A) - UNSIGNED(B)); + + + + + D_0 <= STD_LOGIC_VECTOR(SIGNED('0'&A(VECTOR_SIZE/2-1 DOWNTO 0)) - SIGNED('0' & B(VECTOR_SIZE/2-1 DOWNTO 0))); + + D_1 <= STD_LOGIC_VECTOR( SIGNED(A(VECTOR_SIZE-1 DOWNTO VECTOR_SIZE/2)) + - SIGNED(B(VECTOR_SIZE-1 DOWNTO VECTOR_SIZE/2)) + - SIGNED(VECTOR_1(VECTOR_SIZE/2-1 DOWNTO 1) & D_0(VECTOR_SIZE/2) )); + + D <= D_1(VECTOR_SIZE/2-1 DOWNTO 0) & D_0(VECTOR_SIZE/2-1 DOWNTO 0); + + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + all_ok <= '1'; + all_ok_E <= '1'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF D = C THEN + all_ok <= '1'; + ELSE + all_ok <= '0'; + END IF; + + IF E = C THEN + all_ok_E <= '1'; + ELSE + all_ok_E <= '0'; + END IF; + END IF; + END PROCESS; + +END; + diff --git a/designs/Validation_IIR_LFR/tb_cic_lfr_add_sub.vhd b/designs/Validation_IIR_LFR/tb_cic_lfr_add_sub.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/tb_cic_lfr_add_sub.vhd @@ -0,0 +1,173 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.cic_pkg.ALL; +USE lpp.data_type_pkg.ALL; +USE lpp.chirp_pkg.ALL; + +ENTITY testbench IS + +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL clk_24k : STD_LOGIC := '0'; + SIGNAL clk_24k_r : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + SIGNAL run : STD_LOGIC; + SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_v : sample_vector(5 DOWNTO 0,15 DOWNTO 0); + SIGNAL data_in_valid : STD_LOGIC; + ----------------------------------------------------------------------------- + CONSTANT CARRY : STD_LOGIC := '1'; + CONSTANT CARRY_NO : STD_LOGIC := '0'; + CONSTANT ADD : STD_LOGIC := '0'; + CONSTANT SUB : STD_LOGIC := '1'; + SIGNAL OP : STD_LOGIC; + SIGNAL OP_0 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL OP_1 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL data_out_verif : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_verif_s : STD_LOGIC_VECTOR(32 DOWNTO 0); + SIGNAL data_in_A_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_in_B_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_in_A : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_in_B : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_pre : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_diff : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_Carry : STD_LOGIC; + + SIGNAL COUNTER_A : INTEGER; + SIGNAL COUNTER_B : INTEGER; + CONSTANT COUNTER_MIN : INTEGER := INTEGER'LOW; + CONSTANT COUNTER_MAX : INTEGER := INTEGER'HIGH; + CONSTANT COUNTER_STEP : INTEGER := INTEGER'HIGH/100; + + SIGNAL ALL_is_OK : STD_LOGIC; +BEGIN + + clk <= NOT clk AFTER 5 ns; + + ----------------------------------------------------------------------------- + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + rstn <= '0'; + run <= '0'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + run <= '1'; + WAIT UNTIL clk = '1'; + OP <= ADD; + WAIT FOR 500 us; + OP <= SUB; + WAIT FOR 500 us; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + COUNTER_A <= COUNTER_MIN; + COUNTER_B <= COUNTER_MIN; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF COUNTER_A < COUNTER_MAX - COUNTER_STEP THEN + COUNTER_A <= COUNTER_A + COUNTER_STEP; + ELSE + COUNTER_A <= COUNTER_MIN; + IF COUNTER_B < COUNTER_MAX - COUNTER_STEP THEN + COUNTER_B <= COUNTER_B + COUNTER_STEP; + ELSE + COUNTER_B <= COUNTER_MIN; + END IF; + END IF; + END IF; + END PROCESS; + + data_in_A <= STD_LOGIC_VECTOR(to_signed(COUNTER_A,32)); + data_in_B <= STD_LOGIC_VECTOR(to_signed(COUNTER_B,32)); + + ----------------------------------------------------------------------------- + OP_0 <= CARRY_NO & OP; + OP_1 <= CARRY & OP; + cic_lfr_add_sub_1: cic_lfr_add_sub + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + OP => OP_0, + data_in_A => data_in_A(15 DOWNTO 0), + data_in_B => data_in_B(15 DOWNTO 0), + data_in_Carry => '0', + data_out => data_out_s, + data_out_Carry => data_out_Carry); + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_in_A_reg <= (OTHERS => '0'); + data_in_B_reg <= (OTHERS => '0'); + data_out(15 DOWNTO 0) <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + data_in_A_reg <= data_in_A; + data_in_B_reg <= data_in_B; + data_out(15 DOWNTO 0) <= data_out_s; + END IF; + END PROCESS; + + cic_lfr_add_sub_2: cic_lfr_add_sub + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + OP => OP_1, + data_in_A => data_in_A_reg(31 DOWNTO 16), + data_in_B => data_in_B_reg(31 DOWNTO 16), + data_in_Carry => data_out_Carry, + data_out => data_out(31 DOWNTO 16), + data_out_Carry => OPEN); + ----------------------------------------------------------------------------- + data_out_verif_s <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_in_A_reg)) + to_integer(SIGNED(data_in_B_reg)),33)) WHEN OP = ADD ELSE + STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_in_A_reg)) - to_integer(SIGNED(data_in_B_reg)),33)); + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_out_verif <= (OTHERS => '0'); + ALL_is_OK <= '0'; + data_out_pre <= (OTHERS => '0'); + data_out_diff <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + data_out_verif <= data_out_verif_s(31 DOWNTO 0); + IF data_out_verif = data_out THEN + ALL_is_OK <= '1'; + ELSE + ALL_is_OK <= '0'; + END IF; + ------------------------------------------------------------------------- + data_out_pre <= data_out; + IF OP = ADD THEN + data_out_diff <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_out)) - to_integer(SIGNED(data_out_pre) ),32)); + ELSE + data_out_diff <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_out)) - to_integer(SIGNED(data_out_pre) ),32)); + END IF; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + + + + + + + +END; diff --git a/designs/Validation_IIR_LFR/wave.do b/designs/Validation_IIR_LFR/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/wave.do @@ -0,0 +1,77 @@ +onerror {resume} +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(15 downto 0)} DATA_F0_0 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(31 downto 16)} dATa_F0_1 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(47 downto 32)} DATA_F0_2 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(63 downto 48)} DATA_F0_3 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(79 downto 63)} DATA_F0_4 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(95 downto 80)} DATA_F0_5 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f0_wdata(79 downto 64)} DATA_F0_4001 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(15 downto 0)} DATA_F1_0 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(31 downto 16)} DATA_F1_1 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(47 downto 31)} DATA_F1_2 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(63 downto 48)} DATA_F1_3 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(79 downto 64)} DATA_F1_4 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(95 downto 81)} DATA_F1_5 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(95 downto 80)} DATA_F1_5001 +quietly virtual signal -install /testbench/lpp_lfr_filter_1 { /testbench/lpp_lfr_filter_1/sample_f1_wdata(47 downto 32)} DATA_F1_2001 +quietly virtual signal -install /testbench/IIR_CEL_TEST_1 { /testbench/IIR_CEL_TEST_1/coeff_test(9 downto 0)} b0_2 +quietly virtual signal -install /testbench/IIR_CEL_TEST_1 { /testbench/IIR_CEL_TEST_1/coeff_test(19 downto 10)} b0_1 +quietly virtual signal -install /testbench/IIR_CEL_TEST_1 { /testbench/IIR_CEL_TEST_1/coeff_test(29 downto 20)} b0_0 +quietly virtual signal -install /testbench/IIR_CEL_TEST_1 { /testbench/IIR_CEL_TEST_1/coeff_test(39 downto 30)} a0_2 +quietly virtual signal -install /testbench/IIR_CEL_TEST_1 { /testbench/IIR_CEL_TEST_1/coeff_test(49 downto 40)} a0_1 +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group INPUT /testbench/lpp_lfr_filter_1/sample +add wave -noupdate -group INPUT /testbench/lpp_lfr_filter_1/sample_val +add wave -noupdate -group OUTPUT /testbench/lpp_lfr_filter_1/sample_f2_wdata +add wave -noupdate -group OUTPUT /testbench/lpp_lfr_filter_1/sample_f2_val +add wave -noupdate -group OUTPUT /testbench/lpp_lfr_filter_1/sample_f3_wdata +add wave -noupdate -group OUTPUT /testbench/lpp_lfr_filter_1/sample_f3_val +add wave -noupdate -group OUTPUT -group F0 /testbench/lpp_lfr_filter_1/sample_f0_val +add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_0 -max 84.0 -min -97.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F0_0 +add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_1 -max 172.00000000000003 -min -183.0 -radix decimal /testbench/lpp_lfr_filter_1/dATa_F0_1 +add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_2 -max 84.0 -min -97.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F0_2 +add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_3 -max 172.00000000000003 -min -183.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F0_3 +add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_4 -max 84.0 -min -97.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F0_4001 +add wave -noupdate -group OUTPUT -group F0 -format Analog-Step -height 74 -label DATA_F0_5 -max 172.00000000000003 -min -183.0 -radix decimal /testbench/lpp_lfr_filter_1/DATA_F0_5 +add wave -noupdate -group OUTPUT -group F1 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decimal /testbench/lpp_lfr_filter_1/DATA_F1_5001 +add wave -noupdate /testbench/sample_out_s2 +add wave -noupdate -radix decimal -childformat {{/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(5) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(4) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(3) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(2) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(1) -radix decimal} {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(0) -radix decimal}} -subitemconfig {/testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(5) {-format Analog-Step -height 74 -max 172.00000000000003 -min -183.0 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(4) {-format Analog-Step -height 74 -max 84.0 -min -97.0 -radix decimal} /testbench/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/sample_in(3) {-format Analog-Step -height 74 -max 172.00000000000003 -min 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{-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(90) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(89) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(88) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(87) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(86) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(85) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(84) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(83) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(82) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(81) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(80) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(79) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(78) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(77) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(76) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(75) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(74) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(73) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(72) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(71) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(70) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(69) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(68) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(67) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(66) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(65) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(64) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(63) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(62) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(61) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(60) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(59) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(58) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(57) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(56) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(55) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(54) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(53) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(52) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(51) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(50) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(49) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(48) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(47) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(46) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(45) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(44) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(43) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(42) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(41) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(40) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(39) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(38) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(37) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(36) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(35) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(34) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(33) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(32) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(31) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(30) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(29) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(28) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(27) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(26) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(25) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(24) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(23) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(22) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(21) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(20) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(19) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(18) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(17) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(16) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(15) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(14) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(13) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(12) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(11) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(10) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(9) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(8) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(7) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(6) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(5) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(4) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(3) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(2) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(1) {-height 15 -radix binary} /testbench/IIR_CEL_TEST_1/coeff_test(0) {-height 15 -radix binary}} /testbench/IIR_CEL_TEST_1/coeff_test +add wave -noupdate -radix decimal -childformat {{/testbench/sample_out1_reg(7) -radix decimal} {/testbench/sample_out1_reg(6) -radix decimal} {/testbench/sample_out1_reg(5) -radix decimal} {/testbench/sample_out1_reg(4) -radix decimal} {/testbench/sample_out1_reg(3) -radix decimal} {/testbench/sample_out1_reg(2) -radix decimal} {/testbench/sample_out1_reg(1) -radix decimal} {/testbench/sample_out1_reg(0) -radix decimal}} -expand -subitemconfig {/testbench/sample_out1_reg(7) {-radix decimal} /testbench/sample_out1_reg(6) {-radix decimal} /testbench/sample_out1_reg(5) {-radix decimal} /testbench/sample_out1_reg(4) {-radix decimal} /testbench/sample_out1_reg(3) {-radix decimal} /testbench/sample_out1_reg(2) {-radix decimal} /testbench/sample_out1_reg(1) {-format Analog-Step -height 74 -max 200.0 -min -200.0 -radix decimal} /testbench/sample_out1_reg(0) {-format Analog-Step -height 74 -max 100.0 -min -100.0 -radix decimal}} /testbench/sample_out1_reg +add wave -noupdate -radix decimal -childformat {{/testbench/sample_out2_reg(7) -radix decimal} {/testbench/sample_out2_reg(6) -radix decimal} {/testbench/sample_out2_reg(5) -radix decimal} {/testbench/sample_out2_reg(4) -radix decimal} {/testbench/sample_out2_reg(3) -radix decimal} {/testbench/sample_out2_reg(2) -radix decimal} {/testbench/sample_out2_reg(1) -radix decimal} {/testbench/sample_out2_reg(0) -radix decimal}} -expand -subitemconfig {/testbench/sample_out2_reg(7) {-radix decimal} /testbench/sample_out2_reg(6) {-radix decimal} /testbench/sample_out2_reg(5) {-radix decimal} /testbench/sample_out2_reg(4) {-radix decimal} /testbench/sample_out2_reg(3) {-radix decimal} /testbench/sample_out2_reg(2) {-radix decimal} /testbench/sample_out2_reg(1) {-format Analog-Step -height 74 -max 200.0 -min -200.0 -radix decimal} /testbench/sample_out2_reg(0) {-format Analog-Step -height 74 -max 100.0 -min -100.0 -radix decimal}} /testbench/sample_out2_reg +add wave -noupdate /testbench/IIR_CEL_TEST_v3_1/sample_out1_val +add wave -noupdate /testbench/IIR_CEL_TEST_v3_1/sample_out2_val +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 4} {0 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 377 +configure wave -valuecolwidth 254 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {5127439409 ps} {5439678593 ps} diff --git a/designs/Validation_IIR_LFR/wave_add_sub.do b/designs/Validation_IIR_LFR/wave_add_sub.do new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/wave_add_sub.do @@ -0,0 +1,27 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_in_a +add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_in_b +add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_out +add wave -noupdate /testbench/data_out_carry +add wave -noupdate /testbench/all_is_ok +add wave -noupdate -radix hexadecimal /testbench/data_out +add wave -noupdate -radix hexadecimal /testbench/data_out_pre +add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/data_out_diff(31) {-radix hexadecimal} /testbench/data_out_diff(30) {-radix hexadecimal} /testbench/data_out_diff(29) {-radix hexadecimal} /testbench/data_out_diff(28) {-radix hexadecimal} /testbench/data_out_diff(27) {-radix hexadecimal} /testbench/data_out_diff(26) {-radix hexadecimal} /testbench/data_out_diff(25) {-radix hexadecimal} /testbench/data_out_diff(24) {-radix hexadecimal} /testbench/data_out_diff(23) {-radix hexadecimal} /testbench/data_out_diff(22) {-radix hexadecimal} /testbench/data_out_diff(21) {-radix hexadecimal} /testbench/data_out_diff(20) {-radix hexadecimal} /testbench/data_out_diff(19) {-radix hexadecimal} /testbench/data_out_diff(18) {-radix hexadecimal} /testbench/data_out_diff(17) {-radix hexadecimal} /testbench/data_out_diff(16) {-radix hexadecimal} /testbench/data_out_diff(15) {-radix hexadecimal} /testbench/data_out_diff(14) {-radix hexadecimal} /testbench/data_out_diff(13) {-radix hexadecimal} /testbench/data_out_diff(12) {-radix hexadecimal} /testbench/data_out_diff(11) {-radix hexadecimal} /testbench/data_out_diff(10) {-radix hexadecimal} /testbench/data_out_diff(9) {-radix hexadecimal} /testbench/data_out_diff(8) {-radix hexadecimal} /testbench/data_out_diff(7) {-radix hexadecimal} /testbench/data_out_diff(6) {-radix hexadecimal} /testbench/data_out_diff(5) {-radix hexadecimal} /testbench/data_out_diff(4) {-radix hexadecimal} /testbench/data_out_diff(3) {-radix hexadecimal} /testbench/data_out_diff(2) {-radix hexadecimal} /testbench/data_out_diff(1) {-radix hexadecimal} /testbench/data_out_diff(0) {-radix hexadecimal}} /testbench/data_out_diff +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {55000 ps} 0} +configure wave -namecolwidth 182 +configure wave -valuecolwidth 97 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {424577 ps} diff --git a/designs/Validation_IIR_LFR/wave_calc.do b/designs/Validation_IIR_LFR/wave_calc.do new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/wave_calc.do @@ -0,0 +1,23 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/a +add wave -noupdate /testbench/b +add wave -noupdate /testbench/c +add wave -noupdate /testbench/all_done +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {631245000 ps} 1} {{Cursor 2} {590125000 ps} 0} +configure wave -namecolwidth 424 +configure wave -valuecolwidth 119 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {2100026250 ps} diff --git a/designs/Validation_IIR_LFR/wave_inout.do b/designs/Validation_IIR_LFR/wave_inout.do new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/wave_inout.do @@ -0,0 +1,50 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in_valid +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out_valid +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_data +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_valid +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_data +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-radix hexadecimal} /testbench/cic_1/I_data(2) {-radix hexadecimal} /testbench/cic_1/I_data(1) {-radix hexadecimal} /testbench/cic_1/I_data(0) {-radix hexadecimal}} /testbench/cic_1/I_data +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/I_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} /testbench/cic_1/C_data(3)(30) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/C_data +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/C_valid +add wave -noupdate -expand -group CIC_LFR -radix decimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in +add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_in_valid +add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}}} -expand -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16 +add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_16_valid +add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_256(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_256(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_256 +add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_256_valid +add wave -noupdate -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) +add wave -noupdate -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out +add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(0)(15) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-radix hexadecimal}} /testbench/cic_lfr_1/data_out_16(0) +add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(5)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(4)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s +add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg256_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg256_s(5) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(4) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(3) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(2) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(1) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(0) {-radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg256_s +add wave -noupdate -group temp -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) +add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out +add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} 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{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {21545643925 ps} 0} {{Cursor 2} {514701877948 ps} 0} {{Cursor 3} {8443215000 ps} 0} +quietly wave cursor active 3 +configure wave -namecolwidth 299 +configure wave -valuecolwidth 188 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {300136435256 ps} diff --git a/designs/Validation_IIR_LFR/wave_temp.do b/designs/Validation_IIR_LFR/wave_temp.do new file mode 100644 --- /dev/null +++ b/designs/Validation_IIR_LFR/wave_temp.do @@ -0,0 +1,62 @@ +onerror {resume} +quietly virtual signal -install /testbench/cic_lfr_1 { /testbench/cic_lfr_1/OPERATION(12 downto 10)} SEL_ADRR_JUMP +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in +add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in_valid +add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out +add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out_valid +add wave -noupdate -expand -group CIC_256 -radix hexadecimal -childformat {{/testbench/cic_256/I_data(3) -radix hexadecimal} {/testbench/cic_256/I_data(2) -radix hexadecimal} {/testbench/cic_256/I_data(1) -radix hexadecimal} {/testbench/cic_256/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_256/I_data(3) {-radix hexadecimal} /testbench/cic_256/I_data(2) {-radix hexadecimal} /testbench/cic_256/I_data(1) {-radix hexadecimal} /testbench/cic_256/I_data(0) {-radix hexadecimal}} /testbench/cic_256/I_data +add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/I_valid +add wave -noupdate -expand -group CIC_256 -radix hexadecimal /testbench/cic_256/C_data +add wave -noupdate -expand -group CIC_256 -radix hexadecimal -childformat {{/testbench/cic_256/C_valid(3) -radix hexadecimal} {/testbench/cic_256/C_valid(2) -radix hexadecimal} {/testbench/cic_256/C_valid(1) -radix hexadecimal} {/testbench/cic_256/C_valid(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_256/C_valid(3) {-radix hexadecimal} /testbench/cic_256/C_valid(2) {-radix hexadecimal} /testbench/cic_256/C_valid(1) {-radix hexadecimal} /testbench/cic_256/C_valid(0) {-radix hexadecimal}} /testbench/cic_256/C_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/I_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/I_data +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/I_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} /testbench/cic_1/C_data(3)(30) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/C_data +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/C_valid +add wave -noupdate -group CIC_LFR -radix decimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in +add wave -noupdate -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_in_valid +add wave -noupdate -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}}} -expand -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16 +add wave -noupdate -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_16_valid +add wave -noupdate -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_256(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_256(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_256 +add wave -noupdate -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_256_valid +add wave -noupdate -expand -group addr_gen /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_base +add wave -noupdate -expand -group addr_gen /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_init +add wave -noupdate -expand -group addr_gen /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_add_1 +add wave -noupdate -expand -group addr_gen /testbench/cic_lfr_1/cic_lfr_address_gen_1/address_reg_s +add wave -noupdate -expand -group addr_gen /testbench/cic_lfr_1/cic_lfr_address_gen_1/address_reg +add wave -noupdate -expand -group addr_gen -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr +add wave -noupdate /testbench/cic_lfr_1/cic_lfr_control_1/STATE_CIC_LFR +add wave -noupdate -expand /testbench/cic_lfr_1/SEL_ADRR_JUMP +add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RADDR +add wave -noupdate /testbench/cic_lfr_1/cic_lfr_control_1/sample_16_odd +add wave -noupdate /testbench/cic_lfr_1/cic_lfr_control_1/sample_256_odd +add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16(0) +add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(5)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(4)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s +add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg256_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg256_s(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg256_s +add wave -noupdate -group temp -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) +add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out +add wave -noupdate -group temp -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) +add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out +add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) -radix hexadecimal} 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/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {20772435000 ps} 0} {{Cursor 2} {514701877948 ps} 0} {{Cursor 3} {10355795000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 362 +configure wave -valuecolwidth 188 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {20772244241 ps} {20772735038 ps} diff --git a/designs/Validation_LFR_ADCONV/Makefile b/designs/Validation_LFR_ADCONV/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_ADCONV/Makefile @@ -0,0 +1,441 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ + +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=TB + +CMD_VLIB=vlib +CMD_VMAP=vmap +CMD_VCOM=@vcom -quiet -93 -work + +################## project specific targets ########################## + +all: + @echo "make vsim" + @echo "make libs" + @echo "make clean" + @echo "make vcom_grlib vcom_lpp vcom_tb" + +run: + @vsim lpp.top_ad_conv_RHF1401_withFilter_tb -do run.do +# @vsim work.TB +# @vsim lpp.lpp_lfr_ms + +vsim: libs vcom run + +libs: + @$(CMD_VLIB) modelsim + @$(CMD_VMAP) modelsim modelsim + @$(CMD_VLIB) modelsim/techmap + @$(CMD_VMAP) techmap modelsim/techmap + @$(CMD_VLIB) modelsim/grlib + @$(CMD_VMAP) grlib modelsim/grlib + @$(CMD_VLIB) modelsim/gaisler + @$(CMD_VMAP) gaisler modelsim/gaisler + @$(CMD_VLIB) modelsim/work + @$(CMD_VMAP) work modelsim/work + @$(CMD_VLIB) modelsim/lpp + @$(CMD_VMAP) lpp modelsim/lpp + @echo "libs done" + + +clean: + @rm -Rf modelsim + @rm -Rf modelsim.ini + @rm -Rf *~ + @rm -Rf transcript + @rm -Rf wlft* + @rm -Rf *.wlf + @rm -Rf vish_stacktrace.vstf + @rm -Rf libs.do + +vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb + + +vcom_tb: +## $(CMD_VCOM) lpp lpp_memory.vhd +## $(CMD_VCOM) lpp lppFIFOxN.vhd +## $(CMD_VCOM) lpp lpp_FIFO.vhd +## $(CMD_VCOM) lpp lpp_lfr_ms.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/verif/top_ad_conv_RHF1401_withFilter_tb.vhd + @echo "vcom done" + +vcom_grlib: + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd + @echo "vcom grlib done" + +vcom_gaisler: + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd +# # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd +# # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd +# # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd +## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd + @echo "vcom gaisler done" + +vcom_techmap: + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd + @echo "vcom techmap done" + +vcom_lpp: + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd + @echo "vcom lpp done" + +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd +# @echo "vcom lpp done" + +#include Makefile_vcom_lpp diff --git a/designs/Validation_LFR_ADCONV/TB.vhd b/designs/Validation_LFR_ADCONV/TB.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_ADCONV/TB.vhd @@ -0,0 +1,480 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +LIBRARY lpp; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.spectral_matrix_package.ALL; +use lpp.lpp_fft.all; +use lpp.fft_components.all; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY TB IS + + +END TB; + + +ARCHITECTURE beh OF TB IS + + ----------------------------------------------------------------------------- + SIGNAL clk25MHz : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL dma_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL dma_valid : STD_LOGIC; + SIGNAL dma_valid_burst : STD_LOGIC; + SIGNAL dma_ren : STD_LOGIC; + SIGNAL dma_done : STD_LOGIC; + SIGNAL ready_matrix_f0 : STD_LOGIC; +-- SIGNAL ready_matrix_f0_1 : STD_LOGIC; + SIGNAL ready_matrix_f1 : STD_LOGIC; + SIGNAL ready_matrix_f2 : STD_LOGIC; +-- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL error_bad_component_error : STD_LOGIC; + SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL status_ready_matrix_f0 : STD_LOGIC; +-- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; + SIGNAL status_ready_matrix_f1 : STD_LOGIC; + SIGNAL status_ready_matrix_f2 : STD_LOGIC; +-- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; +-- SIGNAL status_error_bad_component_error : STD_LOGIC; + SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; + SIGNAL config_active_interruption_onError : STD_LOGIC; + SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); +-- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); +-- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL clk49_152MHz : STD_LOGIC := '0'; + SIGNAL sample_counter_24k : INTEGER; + SIGNAL s_24576Hz : STD_LOGIC; + + SIGNAL s_24_sync_reg_0 : STD_LOGIC; + SIGNAL s_24_sync_reg_1 : STD_LOGIC; + + SIGNAL s_24576Hz_sync : STD_LOGIC; + + SIGNAL sample_counter_f1 : INTEGER; + SIGNAL sample_counter_f2 : INTEGER; + -- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f2_val : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL ren_counter : INTEGER; + + SIGNAL error_buffer_full : STD_LOGIC; + SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_type; + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + -- + SIGNAL ready_reg : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL irq_ongoing : STD_LOGIC; + -- + SIGNAL read_status : STD_LOGIC; + SIGNAL read_status_t : STD_LOGIC; + + + SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0); + +BEGIN -- beh + + clk25MHz <= NOT clk25MHz AFTER 20 ns; + clk25MHz <= NOT clk25MHz AFTER 20 ns; + clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz + + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + rstn <= '1'; + WAIT UNTIL clk25MHz = '1'; + + + WAIT FOR 100 ms; + + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + + END PROCESS; + + + ----------------------------------------------------------------------------- + PROCESS (clk49_152MHz, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_counter_24k <= 0; + s_24576Hz <= '0'; + ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge + IF sample_counter_24k = 0 THEN + sample_counter_24k <= 2000; + s_24576Hz <= NOT s_24576Hz; + ELSE + sample_counter_24k <= sample_counter_24k - 1; + END IF; + END IF; + END PROCESS; + + PROCESS (clk25MHz, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + s_24_sync_reg_0 <= '0'; + s_24_sync_reg_1 <= '0'; + s_24576Hz_sync <= '0'; + ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + s_24_sync_reg_0 <= s_24576Hz; + s_24_sync_reg_1 <= s_24_sync_reg_0; + s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1; + END IF; + END PROCESS; + + PROCESS (clk25MHz, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_f0_val <= '0'; + sample_f1_val <= '0'; + sample_f2_val <= '0'; + + sample_counter_f1 <= 0; + sample_counter_f2 <= 0; + ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + IF s_24576Hz_sync = '1' THEN + sample_f0_val <= '1'; + IF sample_counter_f1 = 0 THEN + sample_f1_val <= '1'; + sample_counter_f1 <= 5; + ELSE + sample_f1_val <= '0'; + sample_counter_f1 <= sample_counter_f1 -1; + END IF; + IF sample_counter_f2 = 0 THEN + sample_f2_val <= '1'; + sample_counter_f2 <= 95; + ELSE + sample_f2_val <= '0'; + sample_counter_f2 <= sample_counter_f2 -1; + END IF; + ELSE + sample_f0_val <= '0'; + sample_f1_val <= '0'; + sample_f2_val <= '0'; + END IF; + END IF; + END PROCESS; + + + + ----------------------------------------------------------------------------- + coarse_time <= (OTHERS => '1'); + + PROCESS (clk25MHz, rstn) + BEGIN + IF rstn = '0' THEN + fine_time <= (OTHERS => '0'); + ELSIF clk25MHz'event AND clk25MHz = '1' THEN + fine_time <= fine_time + 1; + END IF; + END PROCESS; + + + sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444"; + sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444"; + sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444"; + + sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val); + sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val); + sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val); + ----------------------------------------------------------------------------- + + lpp_lfr_ms_1: lpp_lfr_ms + GENERIC MAP ( + Mem_use => use_CEL) + PORT MAP ( + clk => clk25MHz, + rstn => rstn, + -- + coarse_time => coarse_time, + fine_time => fine_time, + -- + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, + -- + dma_addr => dma_addr, + dma_data => dma_data, + dma_valid => dma_valid, + dma_valid_burst => dma_valid_burst, + dma_ren => dma_ren, + dma_done => dma_done, + + ready_matrix_f0 => ready_matrix_f0, +-- ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, +-- error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + error_buffer_full => error_buffer_full, + error_input_fifo_write => error_input_fifo_write, + + debug_reg => debug_reg, + + -- + observation_vector_0 => observation_vector_0, + observation_vector_1 => observation_vector_1, + -- + status_ready_matrix_f0 => status_ready_matrix_f0, +-- status_ready_matrix_f0 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, +-- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, +-- status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0 => addr_matrix_f0, +-- addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + matrix_time_f0 => matrix_time_f0, +-- matrix_time_f0_1 => matrix_time_f0_1, + matrix_time_f1 => matrix_time_f1, + matrix_time_f2 => matrix_time_f2); + + + + + + lpp_lfr_apbreg_1 : lpp_lfr_apbreg + GENERIC MAP ( + nb_data_by_buffer_size => 11, + nb_word_by_buffer_size => 11, + nb_snapshot_param_size => 11, + delta_vector_size => 20, + delta_vector_size_f0_2 => 7, + pindex => 4, + paddr => 4, + pmask => 16#fff#, + pirq_ms => 0, + pirq_wfp => 1, + top_lfr_version => (OTHERS => '0') + ) + PORT MAP ( + HCLK => clk25MHz, + HRESETn => rstn, + apbi => apbi, + apbo => apbo, + + run_ms => OPEN, + + ready_matrix_f0 => ready_matrix_f0, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_bad_component_error => error_bad_component_error, + error_buffer_full => error_buffer_full, -- TODO + error_input_fifo_write => error_input_fifo_write, -- TODO + status_ready_matrix_f0 => status_ready_matrix_f0, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + + matrix_time_f0 => matrix_time_f0, + matrix_time_f1 => matrix_time_f1, + matrix_time_f2 => matrix_time_f2, + + addr_matrix_f0 => addr_matrix_f0, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + ------------------------------------------------------------------------- + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + data_shaping_BW => OPEN, + data_shaping_SP0 => OPEN, + data_shaping_SP1 => OPEN, + data_shaping_R0 => OPEN, + data_shaping_R1 => OPEN, + delta_snapshot => OPEN, + delta_f0 => OPEN, + delta_f0_2 => OPEN, + delta_f1 => OPEN, + delta_f2 => OPEN, + nb_data_by_buffer => OPEN, + nb_word_by_buffer => OPEN, + nb_snapshot_param => OPEN, + enable_f0 => OPEN, + enable_f1 => OPEN, + enable_f2 => OPEN, + enable_f3 => OPEN, + burst_f0 => OPEN, + burst_f1 => OPEN, + burst_f2 => OPEN, + run => OPEN, + addr_data_f0 => OPEN, + addr_data_f1 => OPEN, + addr_data_f2 => OPEN, + addr_data_f3 => OPEN, + start_date => OPEN); + + + + + read_status_t <= TRANSPORT apbo.pirq(0) AFTER 200 us; + + PROCESS (clk25MHz, rstn) + BEGIN + IF rstn = '0' THEN + ready_reg <= (OTHERS => '0'); + --read_status <= '0'; + apbi.psel(4) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr(7 DOWNTO 2) <= (OTHERS => '0'); + ELSIF clk25MHz'event AND clk25MHz = '1' THEN + apbi.psel(4) <= '1'; + apbi.paddr(7 DOWNTO 2) <= "000001"; + apbi.penable <= '1'; + read_status <= apbo.pirq(0); + + IF read_status = '1' AND irq_ongoing = '0' THEN + ready_reg <= apbo.prdata(5 DOWNTO 0); + irq_ongoing <= '1'; + END IF; + + IF read_status_t = '0' THEN + apbi.pwrite <= '0'; + ELSE + irq_ongoing <= '0'; + apbi.pwrite <= '1'; + apbi.pwdata(31 DOWNTO 6) <= (OTHERS => '0'); + apbi.pwdata(5 DOWNTO 0) <= ready_reg; + ready_reg <= (OTHERS => '0'); + END IF; + + END IF; + END PROCESS; + + + + + + + + + + +-- PROCESS (clk25MHz, rstn) +-- BEGIN -- PROCESS +-- IF rstn = '0' THEN -- asynchronous reset (active low) +-- status_ready_matrix_f0 <= '0'; +---- status_ready_matrix_f0_1 <= '0'; +-- status_ready_matrix_f1 <= '0'; +-- status_ready_matrix_f2 <= '0'; +-- ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge +-- status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0; +---- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1; +-- status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1; +-- status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2; +-- END IF; +-- END PROCESS; + + + +-- status_error_anticipating_empty_fifo <= '0'; +-- status_error_bad_component_error <= '0'; + +-- config_active_interruption_onNewMatrix <= '0'; +-- config_active_interruption_onError <= '0'; +-- addr_matrix_f0 <= (OTHERS => '0'); +-- addr_matrix_f0_1 <= (OTHERS => '0'); +-- addr_matrix_f1 <= (OTHERS => '0'); +-- addr_matrix_f2 <= (OTHERS => '0'); + + + PROCESS (clk25MHz, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + + dma_ren <= '1'; + dma_done <= '0'; + ren_counter <= 0; + ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + dma_ren <= '1'; + dma_done <= '0'; + + IF dma_valid_burst = '1' THEN + ren_counter <= 17; + END IF; + + IF ren_counter > 1 THEN + ren_counter <= ren_counter - 1; + dma_ren <= '0'; + END IF; + + IF ren_counter = 1 THEN + ren_counter <= 0; + dma_done <= '1'; + END IF; + + END IF; + END PROCESS; + + +END beh; + diff --git a/designs/Validation_LFR_ADCONV/run.do b/designs/Validation_LFR_ADCONV/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_ADCONV/run.do @@ -0,0 +1,3 @@ +log -R * +do wave.do +run 10 ms \ No newline at end of file diff --git a/designs/Validation_LFR_ADCONV/wave.do b/designs/Validation_LFR_ADCONV/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_ADCONV/wave.do @@ -0,0 +1,41 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/cnv_clk +add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/cnv_rstn +add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/rstn +add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/adc_data +add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/clk +add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/adc_data_v +add wave -noupdate -expand -group CNV_GEN /top_ad_conv_rhf1401_withfilter_tb/dut/cnv_cycle_counter +add wave -noupdate -expand -group CNV_GEN /top_ad_conv_rhf1401_withfilter_tb/dut/cnv_s +add wave -noupdate -expand -group CNV_GEN /top_ad_conv_rhf1401_withfilter_tb/cnv +add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/dut/cnv_sync +add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/dut/cnv_sync_pre +add wave -noupdate -expand -group DATA_GEN_OutputEnable -radix hexadecimal /top_ad_conv_rhf1401_withfilter_tb/dut/adc_noe_reg +add wave -noupdate -expand -group DATA_GEN_OutputEnable /top_ad_conv_rhf1401_withfilter_tb/dut/enable_adc +add wave -noupdate -radix hexadecimal /top_ad_conv_rhf1401_withfilter_tb/adc_noe +add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/dut/channel_counter +add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/dut/sample_reg +add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/sample_val +add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/dut/sample_counter +add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/dut/adc_data_selected +add wave -noupdate -expand -group ADC_READ_DATA /top_ad_conv_rhf1401_withfilter_tb/dut/adc_data_result +add wave -noupdate /top_ad_conv_rhf1401_withfilter_tb/sample_val +add wave -noupdate -radix hexadecimal /top_ad_conv_rhf1401_withfilter_tb/sample +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {875312 ps} 0} {{Cursor 2} {200000 ps} 0} +configure wave -namecolwidth 403 +configure wave -valuecolwidth 198 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {1050 us} diff --git a/designs/Validation_WFP_FIFO/Makefile b/designs/Validation_WFP_FIFO/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_WFP_FIFO/Makefile @@ -0,0 +1,53 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES= +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft_rtax \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_apbreg.vhd \ + CoreFFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/Validation_WFP_FIFO/run.do b/designs/Validation_WFP_FIFO/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_WFP_FIFO/run.do @@ -0,0 +1,9 @@ +vcom -quiet -93 -work work tb.vhd + +vsim work.testbench + +log -r * + +do wave.do + +run -all diff --git a/designs/Validation_WFP_FIFO/tb.vhd b/designs/Validation_WFP_FIFO/tb.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_WFP_FIFO/tb.vhd @@ -0,0 +1,507 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + ----------------------------------------------------------------------------- + -- Common signal + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + SIGNAL run : STD_LOGIC := '0'; + + ----------------------------------------------------------------------------- + TYPE DATA_FIFO_VECTOR IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_obs : DATA_FIFO_VECTOR; + + SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_out : DATA_FIFO_VECTOR; + + SIGNAL empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL full_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + ----------------------------------------------------------------------------- + TYPE DATA_CHANNEL IS ARRAY (0 TO 128/4-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + TYPE DATA_ARRAY IS ARRAY (0 TO 3) OF DATA_CHANNEL; + SIGNAL data_in : DATA_ARRAY; + + ----------------------------------------------------------------------------- + CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1+2+2; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE + CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0; + SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + -- + SIGNAL rand_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rand_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + + TYPE POINTER IS ARRAY (0 TO 3) OF INTEGER; + SIGNAL pointer_read : POINTER; + SIGNAL pointer_write : POINTER := (0, 0, 0, 0); + + --SIGNAL data_f0_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f0_data_out_obs : STD_LOGIC; + --SIGNAL data_f1_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f1_data_out_obs : STD_LOGIC; + --SIGNAL data_f2_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f2_data_out_obs : STD_LOGIC; + --SIGNAL data_f3_data_out_obs_data : STD_LOGIC_VECTOR(5 DOWNTO 0); + --SIGNAL data_f3_data_out_obs : STD_LOGIC; + SIGNAL error_now : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL error_new : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL read_stop : STD_LOGIC; + +-- SIGNAL empty_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + + ----------------------------------------------------------------------------- +BEGIN + + all_I : FOR I IN 0 TO 3 GENERATE + all_J : FOR J IN 0 TO 128/4-1 GENERATE + data_in(I)(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+I*(2**28)+1, 32)); + END GENERATE all_J; + END GENERATE all_I; + + + ----------------------------------------------------------------------------- + lpp_waveform_fifo_1 : lpp_waveform_fifo + GENERIC MAP (tech => 0) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + empty => s_empty, + empty_almost => s_empty_almost, + data_ren => s_data_ren, + rdata => s_rdata, + + full_almost => full_almost, + full => full, + data_wen => data_wen, + wdata => wdata); + + lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg + GENERIC MAP (tech => 0) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + o_empty_almost => empty_almost, + o_empty => empty, + + o_data_ren => data_ren, + o_rdata_0 => data_out(0), + o_rdata_1 => data_out(1), + o_rdata_2 => data_out(2), + o_rdata_3 => data_out(3), + + i_empty_almost => s_empty_almost, + i_empty => s_empty, + i_data_ren => s_data_ren, + i_rdata => s_rdata); + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + all_data_channel: FOR I IN 0 TO 3 GENERATE + ----------------------------------------------------------------------------- + -- READ + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + empty_reg(I) <= '1'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + empty_reg(I) <= empty(I); + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_out_obs(I) <= (OTHERS => '0'); + + pointer_read(I) <= 0; + error_now(I) <= '0'; + error_new(I) <= '0'; + + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + error_now(I) <= '0'; + IF empty_reg(I) = '0' THEN + IF data_ren(I) = '0' THEN + + error_new(I) <= '0'; + data_out_obs(I) <= data_out(I); + + IF pointer_read(I) < 128/4-1 THEN + pointer_read(I) <= pointer_read(I) + 1; + ELSE + pointer_read(I) <= 0; + END IF; + + IF data_out(I) /= data_in(I)(pointer_read(I)) THEN + error_now(I) <= '1'; + error_new(I) <= '1'; + END IF; + END IF; + + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- WRITE + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + full_reg(I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + full_reg(I) <= full(I); + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS proc_verif + IF rstn = '0' THEN -- asynchronous reset (active low) + pointer_write(I) <= 0; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF data_wen(I) = '0' THEN + IF full_reg(I) = '0' THEN + IF pointer_write(I) < 128/4-1 THEN + pointer_write(I) <= pointer_write(I)+1; + ELSE + pointer_write(I) <= 0; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE all_data_channel; + + wdata <= data_in(0)(pointer_write(0)) WHEN data_wen = "1110" ELSE + data_in(1)(pointer_write(1)) WHEN data_wen = "1101" ELSE + data_in(2)(pointer_write(2)) WHEN data_wen = "1011" ELSE + data_in(3)(pointer_write(3)) WHEN data_wen = "0111" ELSE + (OTHERS => 'X'); + + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + clk <= NOT clk AFTER 5 ns; -- 100 MHz + ----------------------------------------------------------------------------- + WaveGen_Proc : PROCESS + BEGIN + -- insert signal assignments here + WAIT UNTIL clk = '1'; + read_stop <= '0'; + rstn <= '0'; + run <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + run <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT FOR 10 us; + read_stop <= '1'; + WAIT FOR 10 us; + read_stop <= '0'; + WAIT FOR 80 us; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS WaveGen_Proc; + ----------------------------------------------------------------------------- + + + + + + ----------------------------------------------------------------------------- + -- RANDOM GENERATOR + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + VARIABLE seed1, seed2 : POSITIVE; + VARIABLE rand1 : REAL; + VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + random_vector <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + UNIFORM(seed1, seed2, rand1); + RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR( + to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)), + RANDOM_VECTOR_VAR'LENGTH) + ); + + random_vector <= RANDOM_VECTOR_VAR; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + rand_ren <= "1111" WHEN random_vector(0) = '0' ELSE + "1110" WHEN random_vector(2 DOWNTO 1) = "00" ELSE + "1101" WHEN random_vector(2 DOWNTO 1) = "01" ELSE + "1011" WHEN random_vector(2 DOWNTO 1) = "10" ELSE + "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE + + rand_wen <= "1111" WHEN random_vector(3) = '0' ELSE + "1110" WHEN random_vector(5 DOWNTO 4) = "00" ELSE + "1101" WHEN random_vector(5 DOWNTO 4) = "01" ELSE + "1011" WHEN random_vector(5 DOWNTO 4) = "10" ELSE + "0111"; -- WHEN random_vector(3 DOWNTO 1) = "11" ELSE + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_wen <= (OTHERS => '1'); + data_ren <= (OTHERS => '1'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + data_wen <= rand_wen; + IF read_stop = '0' THEN + all_ren_bits: FOR I IN 0 TO 3 LOOP + IF empty(I) = '1' THEN + data_ren(I) <= '1'; + ELSE + data_ren(I) <= rand_ren(I); + END IF; + END LOOP all_ren_bits; + ELSE + data_ren <= (OTHERS => '1') ; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- empty <= (OTHERS => '1'); + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- empty <= empty_s; + -- END IF; + --END PROCESS; + + + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- data_f0_data_out_obs_data <= (OTHERS => '0'); + -- data_f1_data_out_obs_data <= (OTHERS => '0'); + -- data_f2_data_out_obs_data <= (OTHERS => '0'); + -- data_f3_data_out_obs_data <= (OTHERS => '0'); + -- data_f0_data_out_obs <= '0'; + -- data_f1_data_out_obs <= '0'; + -- data_f2_data_out_obs <= '0'; + -- data_f3_data_out_obs <= '0'; + + -- pointer_read <= (0, 0, 0, 0); + -- error_now <= (OTHERS => '0'); + -- error_new <= (OTHERS => '0'); + + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- error_now <= (OTHERS => '0'); + -- CASE data_ren IS + -- WHEN "1110" => + -- IF empty(0) = '0' THEN + -- error_new(0) <= '0'; + -- data_f0_data_out_obs_data <= data_f0_data_out(5 DOWNTO 0); + -- IF pointer_read(0) < 31 THEN + -- pointer_read(0) <= pointer_read(0)+1; + -- ELSE + -- pointer_read(0) <= 0; + -- END IF; + -- IF data_f0_data_out /= data_in(0)(pointer_read(0)) THEN + -- error_now(0) <= '1'; + -- error_new(0) <= '1'; + -- data_f0_data_out_obs <= '1'; + -- END IF; + -- --IF data_f0_data_out(29 DOWNTO 28) /= "00" THEN + -- -- data_f0_data_out_obs <= '1'; + -- --END IF; + -- END IF; + + -- WHEN "1101" => + -- IF empty(1) = '0' THEN + -- error_new(1) <= '0'; + -- data_f1_data_out_obs_data <= data_f1_data_out(5 DOWNTO 0); + -- IF pointer_read(1) < 31 THEN + -- pointer_read(1) <= pointer_read(1)+1; + -- ELSE + -- pointer_read(1) <= 0; + -- END IF; + -- IF data_f1_data_out /= data_in(1)(pointer_read(1)) THEN + -- error_new(1) <= '1'; + -- error_now(1) <= '1'; + -- data_f1_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "1011" => + -- IF empty(2) = '0' THEN + -- error_new(2) <= '0'; + -- data_f2_data_out_obs_data <= data_f2_data_out(5 DOWNTO 0); + -- IF pointer_read(2) < 31 THEN + -- pointer_read(2) <= pointer_read(2)+1; + -- ELSE + -- pointer_read(2) <= 0; + -- END IF; + -- IF data_f2_data_out /= data_in(2)(pointer_read(2)) THEN + -- error_new(2) <= '1'; + -- error_now(2) <= '1'; + -- data_f2_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "0111" => + -- IF empty(3) = '0' THEN + -- error_new(3) <= '0'; + -- data_f3_data_out_obs_data <= data_f3_data_out(5 DOWNTO 0); + -- IF pointer_read(3) < 31 THEN + -- pointer_read(3) <= pointer_read(3)+1; + -- ELSE + -- pointer_read(3) <= 0; + -- END IF; + -- IF data_f3_data_out /= data_in(3)(pointer_read(3)) THEN + -- error_new(3) <= '1'; + -- error_now(3) <= '1'; + -- data_f3_data_out_obs <= '1'; + -- END IF; + -- END IF; + -- WHEN "1111" => + -- NULL; + + + -- WHEN OTHERS => + -- REPORT "*** ERROR_DATA_REN ***" SEVERITY failure; + -- NULL; + -- END CASE; + + -- END IF; + --END PROCESS; + + + ------------------------------------------------------------------------------- + --clk <= NOT clk AFTER 5 ns; -- 100 MHz + + ------------------------------------------------------------------------------- + --WaveGen_Proc : PROCESS + --BEGIN + + -- -- insert signal assignments here + -- WAIT UNTIL clk = '1'; + -- rstn <= '0'; + -- run <= '0'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- rstn <= '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- run <= '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + -- WAIT UNTIL clk = '1'; + + -- WAIT FOR 100 us; + -- REPORT "*** END simulation ***" SEVERITY failure; + -- WAIT; + + --END PROCESS WaveGen_Proc; + + ------------------------------------------------------------------------------- + --proc_verif : PROCESS (clk, rstn) + --BEGIN -- PROCESS proc_verif + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- pointer_write <= (0, 0, 0, 0); + -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + -- --IF rand_wen = "1111" THEN + -- CASE rand_wen IS + -- WHEN "1110" => + -- IF full(0) = '0' THEN + -- IF pointer_write(0) = 128/4-1 THEN + -- pointer_write(0) <= 0; + -- ELSE + -- pointer_write(0) <= pointer_write(0)+1; + -- END IF; + -- END IF; + + -- WHEN "1101" => + -- IF full(1) = '0' THEN + -- IF pointer_write(1) = 128/4-1 THEN + -- pointer_write(1) <= 0; + -- ELSE + -- pointer_write(1) <= pointer_write(1)+1; + -- END IF; + -- END IF; + + -- WHEN "1011" => + -- IF full(2) = '0' THEN + -- IF pointer_write(2) = 128/4-1 THEN + -- pointer_write(2) <= 0; + -- ELSE + -- pointer_write(2) <= pointer_write(2)+1; + -- END IF; + -- END IF; + -- WHEN "0111" => + -- IF full(3) = '0' THEN + -- IF pointer_write(3) = 128/4-1 THEN + -- pointer_write(3) <= 0; + -- ELSE + -- pointer_write(3) <= pointer_write(3)+1; + -- END IF; + -- END IF; + -- WHEN OTHERS => NULL; + -- END CASE; + + -- --END IF; + -- END IF; + --END PROCESS proc_verif; + + --wdata <= data_in(0)(pointer_write(0)) WHEN rand_wen(0) = '0' ELSE + -- data_in(1)(pointer_write(1)) WHEN rand_wen(1) = '0' ELSE + -- data_in(2)(pointer_write(2)) WHEN rand_wen(2) = '0' ELSE + -- data_in(3)(pointer_write(3)) WHEN rand_wen(3) = '0' ELSE + -- (OTHERS => '0'); + + --data_wen <= rand_wen; + + --data_ren <= rand_ren OR empty; + + + + +END; diff --git a/designs/Validation_WFP_FIFO/wave.do b/designs/Validation_WFP_FIFO/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_WFP_FIFO/wave.do @@ -0,0 +1,47 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/clk +add wave -noupdate /testbench/rstn +add wave -noupdate /testbench/run +add wave -noupdate -expand -group FIFO_IN /testbench/full_almost +add wave -noupdate -expand -group FIFO_IN /testbench/full +add wave -noupdate -expand -group FIFO_IN -expand /testbench/data_wen +add wave -noupdate -expand -group FIFO_IN -radix hexadecimal /testbench/wdata +add wave -noupdate -expand -group internal /testbench/s_empty_almost +add wave -noupdate -expand -group internal -expand /testbench/s_empty +add wave -noupdate -expand -group internal -expand /testbench/s_data_ren +add wave -noupdate -expand -group internal -radix hexadecimal /testbench/s_rdata +add wave -noupdate /testbench/pointer_write +add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty_almost +add wave -noupdate -expand -group FIFO_OUT -expand /testbench/empty +add wave -noupdate -expand -group FIFO_OUT -radix binary -expand /testbench/data_ren +add wave -noupdate -expand -group FIFO_OUT -radix hexadecimal -expand -subitemconfig {/testbench/data_out(0) {-radix hexadecimal} /testbench/data_out(1) {-radix hexadecimal} /testbench/data_out(2) {-radix hexadecimal} /testbench/data_out(3) {-radix hexadecimal}} /testbench/data_out +add wave -noupdate -expand /testbench/pointer_read +add wave -noupdate -format Analog-Step -height 74 -max 32.0 /testbench/lpp_waveform_fifo_1/gen_fifo_ctrl_data(0)/lpp_waveform_fifo_ctrl_data/space_busy +add wave -noupdate -format Analog-Step -height 74 -max 32.0 /testbench/lpp_waveform_fifo_1/gen_fifo_ctrl_data(1)/lpp_waveform_fifo_ctrl_data/space_busy +add wave -noupdate -format Analog-Step -height 74 -max 32.0 /testbench/lpp_waveform_fifo_1/gen_fifo_ctrl_data(2)/lpp_waveform_fifo_ctrl_data/space_busy +add wave -noupdate -format Analog-Step -height 74 -max 32.0 /testbench/lpp_waveform_fifo_1/gen_fifo_ctrl_data(3)/lpp_waveform_fifo_ctrl_data/space_busy +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/error_now(3) {-radix hexadecimal} /testbench/error_now(2) {-radix hexadecimal} /testbench/error_now(1) {-radix hexadecimal} /testbench/error_now(0) {-radix hexadecimal}} /testbench/error_now +add wave -noupdate -radix hexadecimal /testbench/error_new +add wave -noupdate /testbench/read_stop +add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_waveform_fifo_1/sram/inf/x0/rfd +add wave -noupdate -expand /testbench/empty_reg +add wave -noupdate -expand /testbench/data_ren +add wave -noupdate /testbench/lpp_waveform_fifo_headreg_1/one_ren_and_notempty +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {125000 ps} 0} +configure wave -namecolwidth 341 +configure wave -valuecolwidth 172 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {1025712 ps}