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add TestBench designs
add TestBench designs

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r543:cacd7252f42c JC
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run_with_head_reg_lantency_0.do
9 lines | 132 B | text/x-stata | StataLexer
vcom -quiet -93 -work work tb_with_head_reg_latency_0.vhd
vsim work.testbench
log -r *
do wave_head_reg_latency_0.do
run -all