@@ -19,3 +19,4 | |||||
19 | ./lpp_usb |
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19 | ./lpp_usb | |
20 | ./lpp_waveform |
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20 | ./lpp_waveform | |
21 | ./lpp_top_lfr |
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21 | ./lpp_top_lfr | |
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22 | ./lpp_Header |
@@ -72,6 +72,7 BEGIN | |||||
72 | memCEL : IF Mem_use = use_CEL GENERATE |
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72 | memCEL : IF Mem_use = use_CEL GENERATE | |
73 | WEN <= NOT ram_write; |
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73 | WEN <= NOT ram_write; | |
74 | REN <= NOT ram_read; |
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74 | REN <= NOT ram_read; | |
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75 | -- RAMblk : RAM_CEL_N | |||
75 | RAMblk : RAM_CEL_N |
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76 | RAMblk : RAM_CEL_N | |
76 | GENERIC MAP(Input_SZ_1) |
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77 | GENERIC MAP(Input_SZ_1) | |
77 | PORT MAP( |
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78 | PORT MAP( |
@@ -1,3 +1,4 | |||||
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1 | lpp_fft.vhd | |||
1 | APB_FFT.vhd |
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2 | APB_FFT.vhd | |
2 | APB_FFT_half.vhd |
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3 | APB_FFT_half.vhd | |
3 | Driver_FFT.vhd |
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4 | Driver_FFT.vhd | |
@@ -6,4 +7,3 FFTamont.vhd | |||||
6 | FFTaval.vhd |
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7 | FFTaval.vhd | |
7 | Flag_Extremum.vhd |
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8 | Flag_Extremum.vhd | |
8 | Linker_FFT.vhd |
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9 | Linker_FFT.vhd | |
9 | lpp_fft.vhd |
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@@ -146,7 +146,8 PACKAGE lpp_top_lfr_pkg IS | |||||
146 | delta_snapshot_size : INTEGER; |
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146 | delta_snapshot_size : INTEGER; | |
147 | delta_f2_f0_size : INTEGER; |
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147 | delta_f2_f0_size : INTEGER; | |
148 | delta_f2_f1_size : INTEGER; |
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148 | delta_f2_f1_size : INTEGER; | |
149 |
tech : INTEGER |
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149 | tech : INTEGER; | |
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150 | Mem_use : INTEGER); | |||
150 | PORT ( |
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151 | PORT ( | |
151 | cnv_run : IN STD_LOGIC; |
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152 | cnv_run : IN STD_LOGIC; | |
152 | cnv : OUT STD_LOGIC; |
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153 | cnv : OUT STD_LOGIC; |
@@ -193,7 +193,9 BEGIN | |||||
193 | delta_snapshot_size => delta_snapshot_size, |
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193 | delta_snapshot_size => delta_snapshot_size, | |
194 | delta_f2_f0_size => delta_f2_f0_size, |
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194 | delta_f2_f0_size => delta_f2_f0_size, | |
195 | delta_f2_f1_size => delta_f2_f1_size, |
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195 | delta_f2_f1_size => delta_f2_f1_size, | |
196 |
tech => tech |
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196 | tech => tech, | |
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197 | Mem_use => use_RAM | |||
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198 | ) | |||
197 | PORT MAP ( |
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199 | PORT MAP ( | |
198 | cnv_run => cnv_run, |
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200 | cnv_run => cnv_run, | |
199 | cnv => cnv, |
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201 | cnv => cnv, |
@@ -26,7 +26,8 ENTITY lpp_top_lfr_wf_picker_ip IS | |||||
26 | delta_snapshot_size : INTEGER := 16; |
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26 | delta_snapshot_size : INTEGER := 16; | |
27 | delta_f2_f0_size : INTEGER := 10; |
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27 | delta_f2_f0_size : INTEGER := 10; | |
28 | delta_f2_f1_size : INTEGER := 10; |
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28 | delta_f2_f1_size : INTEGER := 10; | |
29 | tech : INTEGER := 0 |
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29 | tech : INTEGER := 0; | |
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30 | Mem_use : INTEGER := use_RAM | |||
30 | ); |
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31 | ); | |
31 | PORT ( |
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32 | PORT ( | |
32 | -- ADS7886 |
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33 | -- ADS7886 | |
@@ -214,7 +215,7 BEGIN | |||||
214 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 |
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215 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
215 | GENERIC MAP ( |
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216 | GENERIC MAP ( | |
216 | tech => 0, |
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217 | tech => 0, | |
217 |
Mem_use => use |
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218 | Mem_use => Mem_use, -- use_RAM | |
218 | Sample_SZ => 18, |
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219 | Sample_SZ => 18, | |
219 | Coef_SZ => Coef_SZ, |
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220 | Coef_SZ => Coef_SZ, | |
220 | Coef_Nb => 25, |
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221 | Coef_Nb => 25, | |
@@ -480,6 +481,7 BEGIN | |||||
480 | data_f1_in => data_f1_in_valid, |
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481 | data_f1_in => data_f1_in_valid, | |
481 | data_f2_in => data_f2_in_valid, |
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482 | data_f2_in => data_f2_in_valid, | |
482 | data_f3_in => data_f3_in_valid, |
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483 | data_f3_in => data_f3_in_valid, | |
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484 | ||||
483 |
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485 | data_f0_in_valid => sample_f0_val, | |
484 | data_f1_in_valid => sample_f1_val, |
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486 | data_f1_in_valid => sample_f1_val, | |
485 | data_f2_in_valid => sample_f2_val, |
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487 | data_f2_in_valid => sample_f2_val, | |
@@ -489,6 +491,7 BEGIN | |||||
489 | data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); |
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491 | data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
490 | data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); |
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492 | data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
491 | data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); |
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493 | data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
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494 | ||||
492 |
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495 | data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; | |
493 | data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; |
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496 | data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; | |
494 | data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; |
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497 | data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; | |
@@ -499,4 +502,4 BEGIN | |||||
499 | sample_f2_wdata <= sample_f2_wdata_s; |
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502 | sample_f2_wdata <= sample_f2_wdata_s; | |
500 | sample_f3_wdata <= sample_f3_wdata_s; |
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503 | sample_f3_wdata <= sample_f3_wdata_s; | |
501 |
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504 | |||
502 | END tb; No newline at end of file |
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505 | END tb; |
@@ -117,7 +117,10 ARCHITECTURE Behavioral OF lpp_waveform_ | |||||
117 | SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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117 | SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
118 | SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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118 | SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
119 | ----------------------------------------------------------------------------- |
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119 | ----------------------------------------------------------------------------- | |
120 |
SIGNAL send_16_3_time : STD_LOGIC_VECTOR( |
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120 | SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0); | |
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121 | SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0); | |||
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122 | ----------------------------------------------------------------------------- | |||
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123 | SIGNAL send_16_3_time : STD_LOGIC; | |||
121 | SIGNAL count_send_time : INTEGER; |
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124 | SIGNAL count_send_time : INTEGER; | |
122 | BEGIN |
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125 | BEGIN | |
123 |
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126 | |||
@@ -158,6 +161,8 BEGIN | |||||
158 | END PROCESS; |
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161 | END PROCESS; | |
159 | END GENERATE all_time_write; |
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162 | END GENERATE all_time_write; | |
160 |
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163 | |||
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164 | ||||
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165 | ||||
161 | ----------------------------------------------------------------------------- |
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166 | ----------------------------------------------------------------------------- | |
162 | sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE |
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167 | sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE | |
163 | "01" WHEN data_ready(1) = '1' ELSE |
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168 | "01" WHEN data_ready(1) = '1' ELSE | |
@@ -169,6 +174,18 BEGIN | |||||
169 | time_already_send(2) WHEN data_ready(2) = '1' ELSE |
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174 | time_already_send(2) WHEN data_ready(2) = '1' ELSE | |
170 | time_already_send(3); |
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175 | time_already_send(3); | |
171 |
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176 | |||
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177 | ||||
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178 | send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE | |||
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179 | send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE | |||
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180 | send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE | |||
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181 | send_16_3_time_reg(9) ; | |||
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182 | ||||
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183 | all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE | |||
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184 | send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <= | |||
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185 | send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE | |||
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186 | send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1); | |||
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187 | END GENERATE all_send_16_3; | |||
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188 | ||||
172 |
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189 | -- DMA control | |
173 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
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190 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
174 | BEGIN -- PROCESS DMAWriteBurst_p |
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191 | BEGIN -- PROCESS DMAWriteBurst_p | |
@@ -182,7 +199,11 BEGIN | |||||
182 | data_send <= '0'; |
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199 | data_send <= '0'; | |
183 | time_send <= '0'; |
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200 | time_send <= '0'; | |
184 | time_write <= '0'; |
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201 | time_write <= '0'; | |
185 | send_16_3_time <= "001"; |
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202 | --send_16_3_time <= "001"; | |
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203 | send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001"; | |||
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204 | send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001"; | |||
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205 | send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001"; | |||
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206 | send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001"; | |||
186 |
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207 | |||
187 | ELSIF HCLK'EVENT AND HCLK = '1' THEN |
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208 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |
188 |
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209 | |||
@@ -201,8 +222,8 BEGIN | |||||
201 |
state |
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222 | state <= IDLE; | |
202 | ELSE |
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223 | ELSE | |
203 | sel_data <= sel_data_s; |
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224 | sel_data <= sel_data_s; | |
204 |
send_16_3_time <= send_16_3_time |
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225 | send_16_3_time_reg <= send_16_3_time_reg_s; | |
205 |
IF send_16_3_time |
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226 | IF send_16_3_time = '1' THEN | |
206 |
state |
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227 | state <= SEND_TIME_0; | |
207 | ELSE |
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228 | ELSE | |
208 |
state |
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229 | state <= SEND_5_TIME; |
@@ -65,7 +65,7 BEGIN -- beh | |||||
65 | END IF; |
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65 | END IF; | |
66 | ------------------------------------------------------------------------- |
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66 | ------------------------------------------------------------------------- | |
67 | coarse_time_0_r <= coarse_time_0; |
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67 | coarse_time_0_r <= coarse_time_0; | |
68 |
IF coarse_time_0 = NOT coarse_time_0_r |
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68 | IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN | |
69 | IF counter_delta_snapshot = 0 THEN |
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69 | IF counter_delta_snapshot = 0 THEN | |
70 | counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); |
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70 | counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); | |
71 | ELSE |
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71 | ELSE |
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