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pellion -
r180:b44cc8ef726a JC
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@@ -19,3 +19,4
19 ./lpp_usb
19 ./lpp_usb
20 ./lpp_waveform
20 ./lpp_waveform
21 ./lpp_top_lfr
21 ./lpp_top_lfr
22 ./lpp_Header
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@@ -72,6 +72,7 BEGIN
72 memCEL : IF Mem_use = use_CEL GENERATE
72 memCEL : IF Mem_use = use_CEL GENERATE
73 WEN <= NOT ram_write;
73 WEN <= NOT ram_write;
74 REN <= NOT ram_read;
74 REN <= NOT ram_read;
75 -- RAMblk : RAM_CEL_N
75 RAMblk : RAM_CEL_N
76 RAMblk : RAM_CEL_N
76 GENERIC MAP(Input_SZ_1)
77 GENERIC MAP(Input_SZ_1)
77 PORT MAP(
78 PORT MAP(
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@@ -1,3 +1,4
1 lpp_fft.vhd
1 APB_FFT.vhd
2 APB_FFT.vhd
2 APB_FFT_half.vhd
3 APB_FFT_half.vhd
3 Driver_FFT.vhd
4 Driver_FFT.vhd
@@ -6,4 +7,3 FFTamont.vhd
6 FFTaval.vhd
7 FFTaval.vhd
7 Flag_Extremum.vhd
8 Flag_Extremum.vhd
8 Linker_FFT.vhd
9 Linker_FFT.vhd
9 lpp_fft.vhd
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@@ -277,9 +277,9 BEGIN -- beh
277 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
277 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
278 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
278 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
279
279
280 reg_wp.status_full <= reg_wp.status_full OR status_full;
280 reg_wp.status_full <= reg_wp.status_full OR status_full;
281 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
281 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
282 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
282 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
283
283
284 paddr := "000000";
284 paddr := "000000";
285 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
285 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
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@@ -146,7 +146,8 PACKAGE lpp_top_lfr_pkg IS
146 delta_snapshot_size : INTEGER;
146 delta_snapshot_size : INTEGER;
147 delta_f2_f0_size : INTEGER;
147 delta_f2_f0_size : INTEGER;
148 delta_f2_f1_size : INTEGER;
148 delta_f2_f1_size : INTEGER;
149 tech : INTEGER);
149 tech : INTEGER;
150 Mem_use : INTEGER);
150 PORT (
151 PORT (
151 cnv_run : IN STD_LOGIC;
152 cnv_run : IN STD_LOGIC;
152 cnv : OUT STD_LOGIC;
153 cnv : OUT STD_LOGIC;
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@@ -193,7 +193,9 BEGIN
193 delta_snapshot_size => delta_snapshot_size,
193 delta_snapshot_size => delta_snapshot_size,
194 delta_f2_f0_size => delta_f2_f0_size,
194 delta_f2_f0_size => delta_f2_f0_size,
195 delta_f2_f1_size => delta_f2_f1_size,
195 delta_f2_f1_size => delta_f2_f1_size,
196 tech => tech)
196 tech => tech,
197 Mem_use => use_RAM
198 )
197 PORT MAP (
199 PORT MAP (
198 cnv_run => cnv_run,
200 cnv_run => cnv_run,
199 cnv => cnv,
201 cnv => cnv,
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@@ -26,7 +26,8 ENTITY lpp_top_lfr_wf_picker_ip IS
26 delta_snapshot_size : INTEGER := 16;
26 delta_snapshot_size : INTEGER := 16;
27 delta_f2_f0_size : INTEGER := 10;
27 delta_f2_f0_size : INTEGER := 10;
28 delta_f2_f1_size : INTEGER := 10;
28 delta_f2_f1_size : INTEGER := 10;
29 tech : INTEGER := 0
29 tech : INTEGER := 0;
30 Mem_use : INTEGER := use_RAM
30 );
31 );
31 PORT (
32 PORT (
32 -- ADS7886
33 -- ADS7886
@@ -214,7 +215,7 BEGIN
214 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
215 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
215 GENERIC MAP (
216 GENERIC MAP (
216 tech => 0,
217 tech => 0,
217 Mem_use => use_RAM, -- use_RAM
218 Mem_use => Mem_use, -- use_RAM
218 Sample_SZ => 18,
219 Sample_SZ => 18,
219 Coef_SZ => Coef_SZ,
220 Coef_SZ => Coef_SZ,
220 Coef_Nb => 25,
221 Coef_Nb => 25,
@@ -480,6 +481,7 BEGIN
480 data_f1_in => data_f1_in_valid,
481 data_f1_in => data_f1_in_valid,
481 data_f2_in => data_f2_in_valid,
482 data_f2_in => data_f2_in_valid,
482 data_f3_in => data_f3_in_valid,
483 data_f3_in => data_f3_in_valid,
484
483 data_f0_in_valid => sample_f0_val,
485 data_f0_in_valid => sample_f0_val,
484 data_f1_in_valid => sample_f1_val,
486 data_f1_in_valid => sample_f1_val,
485 data_f2_in_valid => sample_f2_val,
487 data_f2_in_valid => sample_f2_val,
@@ -489,6 +491,7 BEGIN
489 data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
491 data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
490 data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
492 data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
491 data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
493 data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
494
492 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
495 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
493 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
496 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
494 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
497 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
@@ -499,4 +502,4 BEGIN
499 sample_f2_wdata <= sample_f2_wdata_s;
502 sample_f2_wdata <= sample_f2_wdata_s;
500 sample_f3_wdata <= sample_f3_wdata_s;
503 sample_f3_wdata <= sample_f3_wdata_s;
501
504
502 END tb; No newline at end of file
505 END tb;
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@@ -76,10 +76,10 END;
76
76
77 ARCHITECTURE Behavioral OF lpp_waveform_dma IS
77 ARCHITECTURE Behavioral OF lpp_waveform_dma IS
78 -----------------------------------------------------------------------------
78 -----------------------------------------------------------------------------
79 SIGNAL DMAIn : DMA_In_Type;
79 SIGNAL DMAIn : DMA_In_Type;
80 SIGNAL DMAOut : DMA_OUt_Type;
80 SIGNAL DMAOut : DMA_OUt_Type;
81 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
82 TYPE state_DMAWriteBurst IS (IDLE,
82 TYPE state_DMAWriteBurst IS (IDLE,
83 SEND_TIME_0, WAIT_TIME_0,
83 SEND_TIME_0, WAIT_TIME_0,
84 SEND_TIME_1, WAIT_TIME_1,
84 SEND_TIME_1, WAIT_TIME_1,
85 SEND_5_TIME,
85 SEND_5_TIME,
@@ -92,8 +92,8 ARCHITECTURE Behavioral OF lpp_waveform_
92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 SIGNAL time_select : STD_LOGIC;
93 SIGNAL time_select : STD_LOGIC;
94 SIGNAL time_write : STD_LOGIC;
94 SIGNAL time_write : STD_LOGIC;
95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL time_already_send_s : STD_LOGIC;
96 SIGNAL time_already_send_s : STD_LOGIC;
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 -- SEND TIME MODULE
98 -- SEND TIME MODULE
99 SIGNAL time_dmai : DMA_In_Type;
99 SIGNAL time_dmai : DMA_In_Type;
@@ -117,8 +117,11 ARCHITECTURE Behavioral OF lpp_waveform_
117 SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
117 SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
118 SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
118 SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL send_16_3_time : STD_LOGIC_VECTOR(2 DOWNTO 0);
120 SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
121 SIGNAL count_send_time : INTEGER;
121 SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
122 -----------------------------------------------------------------------------
123 SIGNAL send_16_3_time : STD_LOGIC;
124 SIGNAL count_send_time : INTEGER;
122 BEGIN
125 BEGIN
123
126
124 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
@@ -143,10 +146,10 BEGIN
143 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
144 -- This module memorises when the Times info are write. When FSM send
147 -- This module memorises when the Times info are write. When FSM send
145 -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
148 -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
146 all_time_write: FOR I IN 3 DOWNTO 0 GENERATE
149 all_time_write : FOR I IN 3 DOWNTO 0 GENERATE
147 PROCESS (HCLK, HRESETn)
150 PROCESS (HCLK, HRESETn)
148 BEGIN -- PROCESS
151 BEGIN -- PROCESS
149 IF HRESETn = '0' THEN -- asynchronous reset (active low)
152 IF HRESETn = '0' THEN -- asynchronous reset (active low)
150 time_already_send(I) <= '0';
153 time_already_send(I) <= '0';
151 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
154 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
152 IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
155 IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
@@ -157,7 +160,9 BEGIN
157 END IF;
160 END IF;
158 END PROCESS;
161 END PROCESS;
159 END GENERATE all_time_write;
162 END GENERATE all_time_write;
163
160
164
165
161 -----------------------------------------------------------------------------
166 -----------------------------------------------------------------------------
162 sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
167 sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
163 "01" WHEN data_ready(1) = '1' ELSE
168 "01" WHEN data_ready(1) = '1' ELSE
@@ -169,68 +174,84 BEGIN
169 time_already_send(2) WHEN data_ready(2) = '1' ELSE
174 time_already_send(2) WHEN data_ready(2) = '1' ELSE
170 time_already_send(3);
175 time_already_send(3);
171
176
177
178 send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE
179 send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE
180 send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE
181 send_16_3_time_reg(9) ;
182
183 all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE
184 send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <=
185 send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE
186 send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1);
187 END GENERATE all_send_16_3;
188
172 -- DMA control
189 -- DMA control
173 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
190 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
174 BEGIN -- PROCESS DMAWriteBurst_p
191 BEGIN -- PROCESS DMAWriteBurst_p
175 IF HRESETn = '0' THEN
192 IF HRESETn = '0' THEN
176 state <= IDLE;
193 state <= IDLE;
177
194
178 sel_data <= "00";
195 sel_data <= "00";
179 update <= "00";
196 update <= "00";
180 time_select <= '0';
197 time_select <= '0';
181 time_fifo_ren <= '1';
198 time_fifo_ren <= '1';
182 data_send <= '0';
199 data_send <= '0';
183 time_send <= '0';
200 time_send <= '0';
184 time_write <= '0';
201 time_write <= '0';
185 send_16_3_time <= "001";
202 --send_16_3_time <= "001";
203 send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001";
204 send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001";
205 send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001";
206 send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001";
186
207
187 ELSIF HCLK'EVENT AND HCLK = '1' THEN
208 ELSIF HCLK'EVENT AND HCLK = '1' THEN
188
209
189 CASE state IS
210 CASE state IS
190 WHEN IDLE =>
211 WHEN IDLE =>
191 count_send_time <= 0;
212 count_send_time <= 0;
192 sel_data <= "00";
213 sel_data <= "00";
193 update <= "00";
214 update <= "00";
194 time_select <= '0';
215 time_select <= '0';
195 time_fifo_ren <= '1';
216 time_fifo_ren <= '1';
196 data_send <= '0';
217 data_send <= '0';
197 time_send <= '0';
218 time_send <= '0';
198 time_write <= '0';
219 time_write <= '0';
199
220
200 IF data_ready = "0000" THEN
221 IF data_ready = "0000" THEN
201 state <= IDLE;
222 state <= IDLE;
202 ELSE
223 ELSE
203 sel_data <= sel_data_s;
224 sel_data <= sel_data_s;
204 send_16_3_time <= send_16_3_time(1 DOWNTO 0) & send_16_3_time(2);
225 send_16_3_time_reg <= send_16_3_time_reg_s;
205 IF send_16_3_time(0) = '1' THEN
226 IF send_16_3_time = '1' THEN
206 state <= SEND_TIME_0;
227 state <= SEND_TIME_0;
207 ELSE
228 ELSE
208 state <= SEND_5_TIME;
229 state <= SEND_5_TIME;
209 END IF;
230 END IF;
210 END IF;
231 END IF;
211
232
212 WHEN SEND_TIME_0 =>
233 WHEN SEND_TIME_0 =>
213 time_select <= '1';
234 time_select <= '1';
214 IF time_already_send_s = '0' THEN
235 IF time_already_send_s = '0' THEN
215 time_send <= '1';
236 time_send <= '1';
216 state <= WAIT_TIME_0;
237 state <= WAIT_TIME_0;
217 ELSE
238 ELSE
218 time_send <= '0';
239 time_send <= '0';
219 state <= SEND_TIME_1;
240 state <= SEND_TIME_1;
220 END IF;
241 END IF;
221 time_fifo_ren <= '0';
242 time_fifo_ren <= '0';
222
243
223 WHEN WAIT_TIME_0 =>
244 WHEN WAIT_TIME_0 =>
224 time_fifo_ren <= '1';
245 time_fifo_ren <= '1';
225 update <= "00";
246 update <= "00";
226 time_send <= '0';
247 time_send <= '0';
227 IF time_send_ok = '1' OR time_send_ko = '1' THEN
248 IF time_send_ok = '1' OR time_send_ko = '1' THEN
228 update <= "01";
249 update <= "01";
229 state <= SEND_TIME_1;
250 state <= SEND_TIME_1;
230 END IF;
251 END IF;
231
252
232 WHEN SEND_TIME_1 =>
253 WHEN SEND_TIME_1 =>
233 time_select <= '1';
254 time_select <= '1';
234 IF time_already_send_s = '0' THEN
255 IF time_already_send_s = '0' THEN
235 time_send <= '1';
256 time_send <= '1';
236 state <= WAIT_TIME_1;
257 state <= WAIT_TIME_1;
@@ -242,36 +263,36 BEGIN
242
263
243 WHEN WAIT_TIME_1 =>
264 WHEN WAIT_TIME_1 =>
244 time_fifo_ren <= '1';
265 time_fifo_ren <= '1';
245 update <= "00";
266 update <= "00";
246 time_send <= '0';
267 time_send <= '0';
247 IF time_send_ok = '1' OR time_send_ko = '1' THEN
268 IF time_send_ok = '1' OR time_send_ko = '1' THEN
248 time_write <= '1';
269 time_write <= '1';
249 update <= "01";
270 update <= "01";
250 state <= SEND_5_TIME;
271 state <= SEND_5_TIME;
251 END IF;
272 END IF;
252
273
253 WHEN SEND_5_TIME =>
274 WHEN SEND_5_TIME =>
254 update <= "00";
275 update <= "00";
255 time_select <= '1';
276 time_select <= '1';
256 time_fifo_ren <= '0';
277 time_fifo_ren <= '0';
257 count_send_time <= count_send_time + 1;
278 count_send_time <= count_send_time + 1;
258 IF count_send_time = 10 THEN
279 IF count_send_time = 10 THEN
259 state <= SEND_DATA;
280 state <= SEND_DATA;
260 END IF;
281 END IF;
261
282
262 WHEN SEND_DATA =>
283 WHEN SEND_DATA =>
263 time_fifo_ren <= '1';
284 time_fifo_ren <= '1';
264 time_write <= '0';
285 time_write <= '0';
265 time_send <= '0';
286 time_send <= '0';
266
287
267 time_select <= '0';
288 time_select <= '0';
268 data_send <= '1';
289 data_send <= '1';
269 update <= "00";
290 update <= "00";
270 state <= WAIT_DATA;
291 state <= WAIT_DATA;
271
292
272 WHEN WAIT_DATA =>
293 WHEN WAIT_DATA =>
273 data_send <= '0';
294 data_send <= '0';
274
295
275 IF data_send_ok = '1' OR data_send_ko = '1' THEN
296 IF data_send_ok = '1' OR data_send_ko = '1' THEN
276 state <= IDLE;
297 state <= IDLE;
277 update <= "10";
298 update <= "10";
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@@ -65,7 +65,7 BEGIN -- beh
65 END IF;
65 END IF;
66 -------------------------------------------------------------------------
66 -------------------------------------------------------------------------
67 coarse_time_0_r <= coarse_time_0;
67 coarse_time_0_r <= coarse_time_0;
68 IF coarse_time_0 = NOT coarse_time_0_r AND coarse_time_0 = '1' THEN
68 IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN
69 IF counter_delta_snapshot = 0 THEN
69 IF counter_delta_snapshot = 0 THEN
70 counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot));
70 counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot));
71 ELSE
71 ELSE
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