diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt --- a/lib/lpp/dirs.txt +++ b/lib/lpp/dirs.txt @@ -19,3 +19,4 @@ ./lpp_usb ./lpp_waveform ./lpp_top_lfr +./lpp_Header diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd --- a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd @@ -72,6 +72,7 @@ BEGIN memCEL : IF Mem_use = use_CEL GENERATE WEN <= NOT ram_write; REN <= NOT ram_read; +-- RAMblk : RAM_CEL_N RAMblk : RAM_CEL_N GENERIC MAP(Input_SZ_1) PORT MAP( diff --git a/lib/lpp/dsp/lpp_fft/vhdlsyn.txt b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt --- a/lib/lpp/dsp/lpp_fft/vhdlsyn.txt +++ b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt @@ -1,3 +1,4 @@ +lpp_fft.vhd APB_FFT.vhd APB_FFT_half.vhd Driver_FFT.vhd @@ -6,4 +7,3 @@ FFTamont.vhd FFTaval.vhd Flag_Extremum.vhd Linker_FFT.vhd -lpp_fft.vhd diff --git a/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd @@ -277,9 +277,9 @@ BEGIN -- beh reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; - reg_wp.status_full <= reg_wp.status_full OR status_full; + reg_wp.status_full <= reg_wp.status_full OR status_full; reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err; - reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err; + reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err; paddr := "000000"; paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd @@ -146,7 +146,8 @@ PACKAGE lpp_top_lfr_pkg IS delta_snapshot_size : INTEGER; delta_f2_f0_size : INTEGER; delta_f2_f1_size : INTEGER; - tech : INTEGER); + tech : INTEGER; + Mem_use : INTEGER); PORT ( cnv_run : IN STD_LOGIC; cnv : OUT STD_LOGIC; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd @@ -193,7 +193,9 @@ BEGIN delta_snapshot_size => delta_snapshot_size, delta_f2_f0_size => delta_f2_f0_size, delta_f2_f1_size => delta_f2_f1_size, - tech => tech) + tech => tech, + Mem_use => use_RAM + ) PORT MAP ( cnv_run => cnv_run, cnv => cnv, diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd @@ -26,7 +26,8 @@ ENTITY lpp_top_lfr_wf_picker_ip IS delta_snapshot_size : INTEGER := 16; delta_f2_f0_size : INTEGER := 10; delta_f2_f1_size : INTEGER := 10; - tech : INTEGER := 0 + tech : INTEGER := 0; + Mem_use : INTEGER := use_RAM ); PORT ( -- ADS7886 @@ -214,7 +215,7 @@ BEGIN IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 GENERIC MAP ( tech => 0, - Mem_use => use_RAM, -- use_RAM + Mem_use => Mem_use, -- use_RAM Sample_SZ => 18, Coef_SZ => Coef_SZ, Coef_Nb => 25, @@ -480,6 +481,7 @@ BEGIN data_f1_in => data_f1_in_valid, data_f2_in => data_f2_in_valid, data_f3_in => data_f3_in_valid, + data_f0_in_valid => sample_f0_val, data_f1_in_valid => sample_f1_val, data_f2_in_valid => sample_f2_val, @@ -489,6 +491,7 @@ BEGIN data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); + data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; @@ -499,4 +502,4 @@ BEGIN sample_f2_wdata <= sample_f2_wdata_s; sample_f3_wdata <= sample_f3_wdata_s; -END tb; \ No newline at end of file +END tb; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd @@ -76,10 +76,10 @@ END; ARCHITECTURE Behavioral OF lpp_waveform_dma IS ----------------------------------------------------------------------------- - SIGNAL DMAIn : DMA_In_Type; - SIGNAL DMAOut : DMA_OUt_Type; + SIGNAL DMAIn : DMA_In_Type; + SIGNAL DMAOut : DMA_OUt_Type; ----------------------------------------------------------------------------- - TYPE state_DMAWriteBurst IS (IDLE, + TYPE state_DMAWriteBurst IS (IDLE, SEND_TIME_0, WAIT_TIME_0, SEND_TIME_1, WAIT_TIME_1, SEND_5_TIME, @@ -92,8 +92,8 @@ ARCHITECTURE Behavioral OF lpp_waveform_ SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL time_select : STD_LOGIC; SIGNAL time_write : STD_LOGIC; - SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_already_send_s : STD_LOGIC; + SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_already_send_s : STD_LOGIC; ----------------------------------------------------------------------------- -- SEND TIME MODULE SIGNAL time_dmai : DMA_In_Type; @@ -117,8 +117,11 @@ ARCHITECTURE Behavioral OF lpp_waveform_ SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); ----------------------------------------------------------------------------- - SIGNAL send_16_3_time : STD_LOGIC_VECTOR(2 DOWNTO 0); - SIGNAL count_send_time : INTEGER; + SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0); + SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL send_16_3_time : STD_LOGIC; + SIGNAL count_send_time : INTEGER; BEGIN ----------------------------------------------------------------------------- @@ -143,10 +146,10 @@ BEGIN ----------------------------------------------------------------------------- -- This module memorises when the Times info are write. When FSM send -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset. - all_time_write: FOR I IN 3 DOWNTO 0 GENERATE + all_time_write : FOR I IN 3 DOWNTO 0 GENERATE PROCESS (HCLK, HRESETn) BEGIN -- PROCESS - IF HRESETn = '0' THEN -- asynchronous reset (active low) + IF HRESETn = '0' THEN -- asynchronous reset (active low) time_already_send(I) <= '0'; ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge IF time_write = '1' AND UNSIGNED(sel_data) = I THEN @@ -157,7 +160,9 @@ BEGIN END IF; END PROCESS; END GENERATE all_time_write; + + ----------------------------------------------------------------------------- sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE "01" WHEN data_ready(1) = '1' ELSE @@ -169,68 +174,84 @@ BEGIN time_already_send(2) WHEN data_ready(2) = '1' ELSE time_already_send(3); + + send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE + send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE + send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE + send_16_3_time_reg(9) ; + + all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE + send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <= + send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE + send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1); + END GENERATE all_send_16_3; + -- DMA control DMAWriteFSM_p : PROCESS (HCLK, HRESETn) BEGIN -- PROCESS DMAWriteBurst_p IF HRESETn = '0' THEN - state <= IDLE; - - sel_data <= "00"; - update <= "00"; - time_select <= '0'; - time_fifo_ren <= '1'; - data_send <= '0'; - time_send <= '0'; - time_write <= '0'; - send_16_3_time <= "001"; + state <= IDLE; + + sel_data <= "00"; + update <= "00"; + time_select <= '0'; + time_fifo_ren <= '1'; + data_send <= '0'; + time_send <= '0'; + time_write <= '0'; + --send_16_3_time <= "001"; + send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001"; + send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001"; + send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001"; + send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001"; ELSIF HCLK'EVENT AND HCLK = '1' THEN CASE state IS WHEN IDLE => count_send_time <= 0; - sel_data <= "00"; - update <= "00"; - time_select <= '0'; - time_fifo_ren <= '1'; - data_send <= '0'; - time_send <= '0'; - time_write <= '0'; - + sel_data <= "00"; + update <= "00"; + time_select <= '0'; + time_fifo_ren <= '1'; + data_send <= '0'; + time_send <= '0'; + time_write <= '0'; + IF data_ready = "0000" THEN - state <= IDLE; + state <= IDLE; ELSE - sel_data <= sel_data_s; - send_16_3_time <= send_16_3_time(1 DOWNTO 0) & send_16_3_time(2); - IF send_16_3_time(0) = '1' THEN - state <= SEND_TIME_0; + sel_data <= sel_data_s; + send_16_3_time_reg <= send_16_3_time_reg_s; + IF send_16_3_time = '1' THEN + state <= SEND_TIME_0; ELSE - state <= SEND_5_TIME; + state <= SEND_5_TIME; END IF; END IF; WHEN SEND_TIME_0 => - time_select <= '1'; + time_select <= '1'; IF time_already_send_s = '0' THEN time_send <= '1'; state <= WAIT_TIME_0; ELSE time_send <= '0'; state <= SEND_TIME_1; - END IF; + END IF; time_fifo_ren <= '0'; WHEN WAIT_TIME_0 => time_fifo_ren <= '1'; - update <= "00"; - time_send <= '0'; + update <= "00"; + time_send <= '0'; IF time_send_ok = '1' OR time_send_ko = '1' THEN - update <= "01"; - state <= SEND_TIME_1; + update <= "01"; + state <= SEND_TIME_1; END IF; WHEN SEND_TIME_1 => - time_select <= '1'; + time_select <= '1'; IF time_already_send_s = '0' THEN time_send <= '1'; state <= WAIT_TIME_1; @@ -242,36 +263,36 @@ BEGIN WHEN WAIT_TIME_1 => time_fifo_ren <= '1'; - update <= "00"; - time_send <= '0'; + update <= "00"; + time_send <= '0'; IF time_send_ok = '1' OR time_send_ko = '1' THEN - time_write <= '1'; - update <= "01"; - state <= SEND_5_TIME; + time_write <= '1'; + update <= "01"; + state <= SEND_5_TIME; END IF; WHEN SEND_5_TIME => - update <= "00"; - time_select <= '1'; - time_fifo_ren <= '0'; + update <= "00"; + time_select <= '1'; + time_fifo_ren <= '0'; count_send_time <= count_send_time + 1; IF count_send_time = 10 THEN - state <= SEND_DATA; - END IF; + state <= SEND_DATA; + END IF; WHEN SEND_DATA => time_fifo_ren <= '1'; time_write <= '0'; time_send <= '0'; - - time_select <= '0'; - data_send <= '1'; - update <= "00"; - state <= WAIT_DATA; + + time_select <= '0'; + data_send <= '1'; + update <= "00"; + state <= WAIT_DATA; WHEN WAIT_DATA => - data_send <= '0'; - + data_send <= '0'; + IF data_send_ok = '1' OR data_send_ko = '1' THEN state <= IDLE; update <= "10"; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd b/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd @@ -65,7 +65,7 @@ BEGIN -- beh END IF; ------------------------------------------------------------------------- coarse_time_0_r <= coarse_time_0; - IF coarse_time_0 = NOT coarse_time_0_r AND coarse_time_0 = '1' THEN + IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN IF counter_delta_snapshot = 0 THEN counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); ELSE