HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r222:b37e19fe4c0b

Fixed bug, now minor and major frame pulses have the good width....

Alexis Jeandet -

r222:b37e19fe4c0b alexis

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Context file:

r222:b37e19fe4c0b

designs/EGSE_ICI/EGSE_ICI.vhd +7 -4

             SCLK    <=  Sclkint;
             Major_Frame <=  MajF;
-            --Minor_Frame <=  MinF;
+            Minor_Frame <=  MinF;
-            Minor_Frame <=  MinFclk;
+            --Minor_Frame <=  MinFclk;
             gateint <=  GateDC or GateLF or GateHF;
             Gate    <=  gateint;
             BUS0  <= WordClk;
             BUS12 <= MinFVector(0);
-            BUS13 <= MinFclk;
+            --BUS13 <= MinFclk;
-            BUS14 <= '1' when WordCount = 0 else '0';
+            --BUS14 <= '1' when WordCount = 0 else '0';
+            BUS13 <= MinF;
+            BUS14 <= MajF;
             MinFVector    <= std_logic_vector(TO_UNSIGNED(MinfCnt,WordSize));

designs/EGSE_ICI/MajF_Gen.vhd +8 -1

             architecture arMajF_Gen of MajF_Gen is
+            signal monostable : std_logic := '0';
             begin
             begin
                 if reset = '0' then
                     MajF_Clk    <=  '0';
+                    monostable  <=  '1';
                 elsif clk'event and clk = '0' then
-                    if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' then
+                    if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' and monostable = '1' then
                         MajF_Clk    <=  '1';
                     else
                         MajF_Clk    <=  '0';
                     end if;
+                    if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' and monostable = '1' then
+                        monostable  <=  '0';
+                    elsif WordCnt_in /= 0  and monostable = '0' then
+                        monostable  <=  '1';
+                    end if;
                 end if;
             end process;

designs/EGSE_ICI/MinF_Gen.vhd +8 -2

             architecture arMinF_Gen of MinF_Gen is
+            signal monostable : std_logic := '0';
             begin
             process(clk)
             begin
                 if reset = '0' then
                     MinF_Clk    <=  '0';
+                    monostable  <=  '1';
                 elsif clk'event and clk = '0' then
-                    if WordCnt_in = 0 and WordClk = '1' then
+                    if WordCnt_in = 0 and WordClk = '1' and monostable = '1' then
                         MinF_Clk    <=  '1';
                     else
                         MinF_Clk    <=  '0';
                     end if;
+                    if WordCnt_in = 0 and WordClk = '1' and monostable = '1' then
+                        monostable  <=  '0';
+                    elsif WordCnt_in /= 0  and monostable = '0' then
+                        monostable  <=  '1';
+                    end if;
                 end if;
             end process;

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