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MINI_LFR-WFP_MS-0.1.31.pdb :...
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r451:af05753380a8 (MINI-LFR) WFP_MS-0-1-31 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 BEGIN -- beh
180 180
181 181 -----------------------------------------------------------------------------
182 182 -- CLK
183 183 -----------------------------------------------------------------------------
184 184
185 185 PROCESS(clk_50)
186 186 BEGIN
187 187 IF clk_50'EVENT AND clk_50 = '1' THEN
188 188 clk_50_s <= NOT clk_50_s;
189 189 END IF;
190 190 END PROCESS;
191 191
192 192 PROCESS(clk_50_s)
193 193 BEGIN
194 194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 195 clk_25 <= NOT clk_25;
196 196 END IF;
197 197 END PROCESS;
198 198
199 199 PROCESS(clk_49)
200 200 BEGIN
201 201 IF clk_49'EVENT AND clk_49 = '1' THEN
202 202 clk_24 <= NOT clk_24;
203 203 END IF;
204 204 END PROCESS;
205 205
206 206 -----------------------------------------------------------------------------
207 207
208 208 PROCESS (clk_25, reset)
209 209 BEGIN -- PROCESS
210 210 IF reset = '0' THEN -- asynchronous reset (active low)
211 211 LED0 <= '0';
212 212 LED1 <= '0';
213 213 LED2 <= '0';
214 214 --IO1 <= '0';
215 215 --IO2 <= '1';
216 216 --IO3 <= '0';
217 217 --IO4 <= '0';
218 218 --IO5 <= '0';
219 219 --IO6 <= '0';
220 220 --IO7 <= '0';
221 221 --IO8 <= '0';
222 222 --IO9 <= '0';
223 223 --IO10 <= '0';
224 224 --IO11 <= '0';
225 225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 226 LED0 <= '0';
227 227 LED1 <= '1';
228 228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 229 --IO1 <= '1';
230 230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 231 --IO3 <= ADC_SDO(0);
232 232 --IO4 <= ADC_SDO(1);
233 233 --IO5 <= ADC_SDO(2);
234 234 --IO6 <= ADC_SDO(3);
235 235 --IO7 <= ADC_SDO(4);
236 236 --IO8 <= ADC_SDO(5);
237 237 --IO9 <= ADC_SDO(6);
238 238 --IO10 <= ADC_SDO(7);
239 239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 240 END IF;
241 241 END PROCESS;
242 242
243 243 PROCESS (clk_24, reset)
244 244 BEGIN -- PROCESS
245 245 IF reset = '0' THEN -- asynchronous reset (active low)
246 246 I00_s <= '0';
247 247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 248 I00_s <= NOT I00_s ;
249 249 END IF;
250 250 END PROCESS;
251 251 -- IO0 <= I00_s;
252 252
253 253 --UARTs
254 254 nCTS1 <= '1';
255 255 nCTS2 <= '1';
256 256 nDCD2 <= '1';
257 257
258 258 --EXT CONNECTOR
259 259
260 260 --SPACE WIRE
261 261
262 262 leon3_soc_1 : leon3_soc
263 263 GENERIC MAP (
264 264 fabtech => apa3e,
265 265 memtech => apa3e,
266 266 padtech => inferred,
267 267 clktech => inferred,
268 268 disas => 0,
269 269 dbguart => 0,
270 270 pclow => 2,
271 271 clk_freq => 25000,
272 272 NB_CPU => 1,
273 273 ENABLE_FPU => 1,
274 274 FPU_NETLIST => 0,
275 275 ENABLE_DSU => 1,
276 276 ENABLE_AHB_UART => 1,
277 277 ENABLE_APB_UART => 1,
278 278 ENABLE_IRQMP => 1,
279 279 ENABLE_GPT => 1,
280 280 NB_AHB_MASTER => NB_AHB_MASTER,
281 281 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 282 NB_APB_SLAVE => NB_APB_SLAVE)
283 283 PORT MAP (
284 284 clk => clk_25,
285 285 reset => reset,
286 286 errorn => errorn,
287 287 ahbrxd => TXD1,
288 288 ahbtxd => RXD1,
289 289 urxd1 => TXD2,
290 290 utxd1 => RXD2,
291 291 address => SRAM_A,
292 292 data => SRAM_DQ,
293 293 nSRAM_BE0 => SRAM_nBE(0),
294 294 nSRAM_BE1 => SRAM_nBE(1),
295 295 nSRAM_BE2 => SRAM_nBE(2),
296 296 nSRAM_BE3 => SRAM_nBE(3),
297 297 nSRAM_WE => SRAM_nWE,
298 298 nSRAM_CE => SRAM_CE,
299 299 nSRAM_OE => SRAM_nOE,
300 300
301 301 apbi_ext => apbi_ext,
302 302 apbo_ext => apbo_ext,
303 303 ahbi_s_ext => ahbi_s_ext,
304 304 ahbo_s_ext => ahbo_s_ext,
305 305 ahbi_m_ext => ahbi_m_ext,
306 306 ahbo_m_ext => ahbo_m_ext);
307 307
308 308 -------------------------------------------------------------------------------
309 309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 310 -------------------------------------------------------------------------------
311 311 apb_lfr_time_management_1 : apb_lfr_time_management
312 312 GENERIC MAP (
313 313 pindex => 6,
314 314 paddr => 6,
315 315 pmask => 16#fff#,
316 316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 318 PORT MAP (
319 319 clk25MHz => clk_25,
320 320 clk24_576MHz => clk_24, -- 49.152MHz/2
321 321 resetn => reset,
322 322 grspw_tick => swno.tickout,
323 323 apbi => apbi_ext,
324 324 apbo => apbo_ext(6),
325 325 coarse_time => coarse_time,
326 326 fine_time => fine_time);
327 327
328 328 -----------------------------------------------------------------------
329 329 --- SpaceWire --------------------------------------------------------
330 330 -----------------------------------------------------------------------
331 331
332 332 SPW_EN <= '1';
333 333
334 334 spw_clk <= clk_50_s;
335 335 spw_rxtxclk <= spw_clk;
336 336 spw_rxclkn <= NOT spw_rxtxclk;
337 337
338 338 -- PADS for SPW1
339 339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 340 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 342 PORT MAP (SPW_NOM_SIN, stmp(0));
343 343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 347 -- PADS FOR SPW2
348 348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 349 PORT MAP (SPW_RED_SIN, dtmp(1));
350 350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 351 PORT MAP (SPW_RED_DIN, stmp(1));
352 352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 353 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 355 PORT MAP (SPW_RED_SOUT, swno.s(1));
356 356
357 357 -- GRSPW PHY
358 358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 360 spw_phy0 : grspw_phy
361 361 GENERIC MAP(
362 362 tech => apa3e,
363 363 rxclkbuftype => 1,
364 364 scantest => 0)
365 365 PORT MAP(
366 366 rxrst => swno.rxrst,
367 367 di => dtmp(j),
368 368 si => stmp(j),
369 369 rxclko => spw_rxclk(j),
370 370 do => swni.d(j),
371 371 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 373 END GENERATE spw_inputloop;
374 374
375 375 -- SPW core
376 376 sw0 : grspwm GENERIC MAP(
377 377 tech => apa3e,
378 378 hindex => 1,
379 379 pindex => 5,
380 380 paddr => 5,
381 381 pirq => 11,
382 382 sysfreq => 25000, -- CPU_FREQ
383 383 rmap => 1,
384 384 rmapcrc => 1,
385 385 fifosize1 => 16,
386 386 fifosize2 => 16,
387 387 rxclkbuftype => 1,
388 388 rxunaligned => 0,
389 389 rmapbufs => 4,
390 390 ft => 0,
391 391 netlist => 0,
392 392 ports => 2,
393 393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 394 memtech => apa3e,
395 395 destkey => 2,
396 396 spwcore => 1
397 397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 400 )
401 401 PORT MAP(reset, clk_25, spw_rxclk(0),
402 402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 404 swni, swno);
405 405
406 406 swni.tickin <= '0';
407 407 swni.rmapen <= '1';
408 408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 409 swni.tickinraw <= '0';
410 410 swni.timein <= (OTHERS => '0');
411 411 swni.dcrstval <= (OTHERS => '0');
412 412 swni.timerrstval <= (OTHERS => '0');
413 413
414 414 -------------------------------------------------------------------------------
415 415 -- LFR ------------------------------------------------------------------------
416 416 -------------------------------------------------------------------------------
417 417 lpp_lfr_1 : lpp_lfr
418 418 GENERIC MAP (
419 419 Mem_use => use_RAM,
420 420 nb_data_by_buffer_size => 32,
421 421 -- nb_word_by_buffer_size => 30,
422 422 nb_snapshot_param_size => 32,
423 423 delta_vector_size => 32,
424 424 delta_vector_size_f0_2 => 7, -- log2(96)
425 425 pindex => 15,
426 426 paddr => 15,
427 427 pmask => 16#fff#,
428 428 pirq_ms => 6,
429 429 pirq_wfp => 14,
430 430 hindex => 2,
431 top_lfr_version => X"00011E") -- aa.bb.cc version
431 top_lfr_version => X"00011F") -- aa.bb.cc version
432 432 PORT MAP (
433 433 clk => clk_25,
434 434 rstn => reset,
435 435 sample_B => sample_s(2 DOWNTO 0),
436 436 sample_E => sample_s(7 DOWNTO 3),
437 437 sample_val => sample_val,
438 438 apbi => apbi_ext,
439 439 apbo => apbo_ext(15),
440 440 ahbi => ahbi_m_ext,
441 441 ahbo => ahbo_m_ext(2),
442 442 coarse_time => coarse_time,
443 443 fine_time => fine_time,
444 444 data_shaping_BW => bias_fail_sw_sig);
445 445
446 446 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
447 447 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
448 448 END GENERATE all_sample;
449 449
450 450
451 451
452 452 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
453 453 GENERIC MAP(
454 454 ChannelCount => 8,
455 455 SampleNbBits => 14,
456 456 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
457 457 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
458 458 PORT MAP (
459 459 -- CONV
460 460 cnv_clk => clk_24,
461 461 cnv_rstn => reset,
462 462 cnv => ADC_nCS_sig,
463 463 -- DATA
464 464 clk => clk_25,
465 465 rstn => reset,
466 466 sck => ADC_CLK_sig,
467 467 sdo => ADC_SDO_sig,
468 468 -- SAMPLE
469 469 sample => sample,
470 470 sample_val => sample_val);
471 471
472 472 --IO10 <= ADC_SDO_sig(5);
473 473 --IO9 <= ADC_SDO_sig(4);
474 474 --IO8 <= ADC_SDO_sig(3);
475 475
476 476 ADC_nCS <= ADC_nCS_sig;
477 477 ADC_CLK <= ADC_CLK_sig;
478 478 ADC_SDO_sig <= ADC_SDO;
479 479
480 480 ----------------------------------------------------------------------
481 481 --- GPIO -----------------------------------------------------------
482 482 ----------------------------------------------------------------------
483 483
484 484 grgpio0 : grgpio
485 485 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
486 486 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
487 487
488 488 --pio_pad_0 : iopad
489 489 -- GENERIC MAP (tech => CFG_PADTECH)
490 490 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
491 491 --pio_pad_1 : iopad
492 492 -- GENERIC MAP (tech => CFG_PADTECH)
493 493 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
494 494 --pio_pad_2 : iopad
495 495 -- GENERIC MAP (tech => CFG_PADTECH)
496 496 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
497 497 --pio_pad_3 : iopad
498 498 -- GENERIC MAP (tech => CFG_PADTECH)
499 499 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
500 500 --pio_pad_4 : iopad
501 501 -- GENERIC MAP (tech => CFG_PADTECH)
502 502 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
503 503 --pio_pad_5 : iopad
504 504 -- GENERIC MAP (tech => CFG_PADTECH)
505 505 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
506 506 --pio_pad_6 : iopad
507 507 -- GENERIC MAP (tech => CFG_PADTECH)
508 508 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
509 509 --pio_pad_7 : iopad
510 510 -- GENERIC MAP (tech => CFG_PADTECH)
511 511 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
512 512
513 513 PROCESS (clk_25, reset)
514 514 BEGIN -- PROCESS
515 515 IF reset = '0' THEN -- asynchronous reset (active low)
516 516 IO0 <= '0';
517 517 IO1 <= '0';
518 518 IO2 <= '0';
519 519 IO3 <= '0';
520 520 IO4 <= '0';
521 521 IO5 <= '0';
522 522 IO6 <= '0';
523 523 IO7 <= '0';
524 524 IO8 <= '0';
525 525 IO9 <= '0';
526 526 IO10 <= '0';
527 527 IO11 <= '0';
528 528 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
529 529 CASE gpioo.dout(2 DOWNTO 0) IS
530 530 WHEN "011" =>
531 531 IO0 <= observation_reg(0 );
532 532 IO1 <= observation_reg(1 );
533 533 IO2 <= observation_reg(2 );
534 534 IO3 <= observation_reg(3 );
535 535 IO4 <= observation_reg(4 );
536 536 IO5 <= observation_reg(5 );
537 537 IO6 <= observation_reg(6 );
538 538 IO7 <= observation_reg(7 );
539 539 IO8 <= observation_reg(8 );
540 540 IO9 <= observation_reg(9 );
541 541 IO10 <= observation_reg(10);
542 542 IO11 <= observation_reg(11);
543 543 WHEN "001" =>
544 544 IO0 <= observation_reg(0 + 12);
545 545 IO1 <= observation_reg(1 + 12);
546 546 IO2 <= observation_reg(2 + 12);
547 547 IO3 <= observation_reg(3 + 12);
548 548 IO4 <= observation_reg(4 + 12);
549 549 IO5 <= observation_reg(5 + 12);
550 550 IO6 <= observation_reg(6 + 12);
551 551 IO7 <= observation_reg(7 + 12);
552 552 IO8 <= observation_reg(8 + 12);
553 553 IO9 <= observation_reg(9 + 12);
554 554 IO10 <= observation_reg(10 + 12);
555 555 IO11 <= observation_reg(11 + 12);
556 556 WHEN "010" =>
557 557 IO0 <= observation_reg(0 + 12 + 12);
558 558 IO1 <= observation_reg(1 + 12 + 12);
559 559 IO2 <= observation_reg(2 + 12 + 12);
560 560 IO3 <= observation_reg(3 + 12 + 12);
561 561 IO4 <= observation_reg(4 + 12 + 12);
562 562 IO5 <= observation_reg(5 + 12 + 12);
563 563 IO6 <= observation_reg(6 + 12 + 12);
564 564 IO7 <= observation_reg(7 + 12 + 12);
565 565 IO8 <= '0';
566 566 IO9 <= '0';
567 567 IO10 <= '0';
568 568 IO11 <= '0';
569 569 WHEN "000" =>
570 570 IO0 <= observation_vector_0(0 );
571 571 IO1 <= observation_vector_0(1 );
572 572 IO2 <= observation_vector_0(2 );
573 573 IO3 <= observation_vector_0(3 );
574 574 IO4 <= observation_vector_0(4 );
575 575 IO5 <= observation_vector_0(5 );
576 576 IO6 <= observation_vector_0(6 );
577 577 IO7 <= observation_vector_0(7 );
578 578 IO8 <= observation_vector_0(8 );
579 579 IO9 <= observation_vector_0(9 );
580 580 IO10 <= observation_vector_0(10);
581 581 IO11 <= observation_vector_0(11);
582 582 WHEN "100" =>
583 583 IO0 <= observation_vector_1(0 );
584 584 IO1 <= observation_vector_1(1 );
585 585 IO2 <= observation_vector_1(2 );
586 586 IO3 <= observation_vector_1(3 );
587 587 IO4 <= observation_vector_1(4 );
588 588 IO5 <= observation_vector_1(5 );
589 589 IO6 <= observation_vector_1(6 );
590 590 IO7 <= observation_vector_1(7 );
591 591 IO8 <= observation_vector_1(8 );
592 592 IO9 <= observation_vector_1(9 );
593 593 IO10 <= observation_vector_1(10);
594 594 IO11 <= observation_vector_1(11);
595 595 WHEN OTHERS => NULL;
596 596 END CASE;
597 597
598 598 END IF;
599 599 END PROCESS;
600 600
601 601 END beh;
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@@ -1,265 +1,281
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26 USE ieee.numeric_std.ALL;
27 27
28 28
29 29 LIBRARY lpp;
30 30 USE lpp.cic_pkg.ALL;
31 31 USE lpp.data_type_pkg.ALL;
32 32
33 33 ENTITY cic_lfr_control IS
34 34 PORT (
35 35 clk : IN STD_LOGIC;
36 36 rstn : IN STD_LOGIC;
37 37 run : IN STD_LOGIC;
38 38 --
39 39 data_in_valid : IN STD_LOGIC;
40 40 data_out_16_valid : OUT STD_LOGIC;
41 41 data_out_256_valid : OUT STD_LOGIC;
42 42 -- dataflow
43 43 sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
44 44 --
45 45 op_valid : OUT STD_LOGIC;
46 46 op_ADD_SUBn : OUT STD_LOGIC;
47 47 --
48 48 r_addr_init : OUT STD_LOGIC;
49 49 r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
50 50 r_addr_add1 : OUT STD_LOGIC;
51 51 --
52 52 w_en : OUT STD_LOGIC;
53 53 w_addr_init : OUT STD_LOGIC;
54 54 w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
55 55 w_addr_add1 : OUT STD_LOGIC
56 56 );
57 57
58 58 END cic_lfr_control;
59 59
60 60 ARCHITECTURE beh OF cic_lfr_control IS
61 61
62 62 TYPE STATE_CIC_LFR_TYPE IS (IDLE,
63 63
64 64 INT_0_d0, INT_1_d0, INT_2_d0,
65 65 INT_0_d1, INT_1_d1, INT_2_d1,
66 66 INT_0_d2, INT_1_d2, INT_2_d2,
67 67
68 68 WAIT_INT_to_COMB_16,
69 69
70 70 COMB_0_16_d0, COMB_1_16_d0, COMB_2_16_d0,
71 71 COMB_0_16_d1, COMB_1_16_d1, COMB_2_16_d1,
72 72
73 73 COMB_0_256_d0, COMB_1_256_d0, COMB_2_256_d0,
74 74 COMB_0_256_d1, COMB_1_256_d1, COMB_2_256_d1,
75 75 COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2,
76 76
77 77 READ_INT_2_d0,
78 READ_INT_2_d1
78 READ_INT_2_d1,
79
80 Wait_step,
81
82 INT_0, INT_1, INT_2
79 83 );
80 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
84 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
85 SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE;
81 86
82 87 SIGNAL nb_data_receipt : INTEGER;
83 88 SIGNAL current_channel : INTEGER;
84 89
85 90 TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
86 91
87 92 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
88 93 CONSTANT base_addr_delta : INTEGER := 40;
94
95 CONSTANT SEL_OUT : INTEGER := 6;
96
97 signal nb_cycle_wait : integer;
89 98 BEGIN
90 99
91 100 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
92 101 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
93 102 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
94 103 END GENERATE all_bit;
95 104 END GENERATE all_channel;
96 105
97 106 PROCESS (clk, rstn)
98 107 BEGIN -- PROCESS
99 108 IF rstn = '0' THEN -- asynchronous reset (active low)
100 109 STATE_CIC_LFR <= IDLE;
101 110 --
102 111 data_out_16_valid <= '0';
103 112 data_out_256_valid <= '0';
104 113 --
105 114 sel_sample <= (OTHERS => '0');
106 115 --
107 116 op_valid <= '0';
108 117 op_ADD_SUBn <= '0';
109 118 --
110 119 r_addr_init <= '0';
111 120 r_addr_base <= (OTHERS => '0');
112 121 r_addr_add1 <= '0';
113 122 --
114 123 w_en <= '1';
115 124 w_addr_init <= '0';
116 125 w_addr_base <= (OTHERS => '0');
117 126 w_addr_add1 <= '0';
118 127 --
119 128 nb_data_receipt <= 0;
120 129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
121 130 data_out_16_valid <= '0';
122 131 data_out_256_valid <= '0';
123 132 op_valid <= '0';
124 133 op_ADD_SUBn <= '0';
125 134 r_addr_init <= '0';
126 135 r_addr_base <= (OTHERS => '0');
127 136 r_addr_add1 <= '0';
128 137 w_en <= '1';
129 138 w_addr_init <= '0';
130 139 w_addr_base <= (OTHERS => '0');
131 140 w_addr_add1 <= '0';
132 141
133 142 IF run = '0' THEN
134 143 STATE_CIC_LFR <= IDLE;
135 144 --
136 145 data_out_16_valid <= '0';
137 146 data_out_256_valid <= '0';
138 147 --
139 148 sel_sample <= (OTHERS => '0');
140 149 --
141 150 op_valid <= '0';
142 151 op_ADD_SUBn <= '0';
143 152 --
144 153 r_addr_init <= '0';
145 154 r_addr_base <= (OTHERS => '0');
146 155 r_addr_add1 <= '0';
147 156 --
148 157 w_en <= '1';
149 158 w_addr_init <= '0';
150 159 w_addr_base <= (OTHERS => '0');
151 160 w_addr_add1 <= '0';
152 161 --
153 162 nb_data_receipt <= 0;
154 163 current_channel <= 0;
155 164 ELSE
156 165 CASE STATE_CIC_LFR IS
157 166 WHEN IDLE =>
158 167 data_out_16_valid <= '0';
159 168 data_out_256_valid <= '0';
160 169 --
161 170 sel_sample <= (OTHERS => '0');
162 171 --
163 172 op_valid <= '0';
164 173 op_ADD_SUBn <= '0';
165 174 --
166 175 r_addr_init <= '0';
167 176 r_addr_base <= (OTHERS => '0');
168 177 r_addr_add1 <= '0';
169 178 --
170 179 w_en <= '1';
171 180 w_addr_init <= '0';
172 181 w_addr_base <= (OTHERS => '0');
173 182 w_addr_add1 <= '0';
174 183 --
175 184 IF data_in_valid = '1' THEN
176 185 nb_data_receipt <= nb_data_receipt+1;
177 186 current_channel <= 0;
178 187 STATE_CIC_LFR <= INT_0_d0;
179 188 END IF;
180 189
181 -------------------------------------------------------------------
182 WHEN INT_0_d0 =>
183 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
184 STATE_CIC_LFR <= INT_0_d1;
185 r_addr_init <= '1';
186 r_addr_base <= base_addr_INT(current_channel);
190
191 WHEN WAIT_step => ---------------------------------------------------
192 IF nb_cycle_wait > 0 THEN
193 nb_cycle_wait <= nb_cycle_wait -1;
194 ELSE
195 STATE_CIC_LFR <= STATE_CIC_LFR_pre;
196 END IF;
187 197
188 198
189 WHEN INT_0_d1 =>
190 STATE_CIC_LFR <= INT_0_d2;
199 WHEN INT_0 => -------------------------------------------------------
200 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
201 r_addr_init <= '1';
202 r_addr_base <= base_addr_INT(current_channel);
203 nb_cycle_wait <= 1;
204 op_ADD_SUBn <= '1';
205 op_valid <= '1';
206 STATE_CIC_LFR <= WAIT_step;
207 STATE_CIC_LFR_pre <= INT_1;
208
209 WHEN INT_1 =>
210 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
191 211 r_addr_add1 <= '1';
192
193 WHEN INT_0_d2 =>
194 STATE_CIC_LFR <= INT_1_d0;
195 r_addr_add1 <= '1';
212 nb_cycle_wait <= 3;
196 213 op_ADD_SUBn <= '1';
197 214 op_valid <= '1';
198
199 WHEN INT_1_d0 => STATE_CIC_LFR <= INT_1_d1;
200 WHEN INT_1_d1 => STATE_CIC_LFR <= INT_1_d2;
201 WHEN INT_1_d2 => STATE_CIC_LFR <= INT_2_d0;
215 STATE_CIC_LFR <= INT_2;
202 216
203 WHEN INT_2_d0 => STATE_CIC_LFR <= INT_2_d1;
204 WHEN INT_2_d1 => STATE_CIC_LFR <= INT_2_d2;
205 WHEN INT_2_d2 =>
217 WHEN INT_2 =>
218 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
219 r_addr_add1 <= '1';
220 nb_cycle_wait <= 3;
221 op_ADD_SUBn <= '1';
222 op_valid <= '1';
206 223 IF nb_data_receipt = 256 THEN
207 224 STATE_CIC_LFR <= COMB_0_256_d0;
208 225 ELSIF (nb_data_receipt mod 16) = 0 THEN
209 226 STATE_CIC_LFR <= WAIT_INT_to_COMB_16;
210 227 ELSE
211 228 IF current_channel = 5 THEN
212 229 STATE_CIC_LFR <= IDLE;
213 230 ELSE
214 231 current_channel <= current_channel +1;
215 STATE_CIC_LFR <= INT_0_d0;
232 STATE_CIC_LFR <= INT_0;
216 233 END IF;
217 234 END IF;
218 235
219 236 -------------------------------------------------------------------
220 237 WHEN WAIT_INT_to_COMB_16 =>
221 238 STATE_CIC_LFR <= COMB_0_16_d0;
222 239
223 240 WHEN COMB_0_16_d0 => STATE_CIC_LFR <= COMB_0_16_d1;
224 241 WHEN COMB_0_16_d1 => STATE_CIC_LFR <= COMB_1_16_d0;
225 242
226 243 WHEN COMB_1_16_d0 => STATE_CIC_LFR <= COMB_1_16_d1;
227 244 WHEN COMB_1_16_d1 => STATE_CIC_LFR <= COMB_2_16_d0;
228 245
229 246 WHEN COMB_2_16_d0 => STATE_CIC_LFR <= COMB_2_16_d1;
230 247 WHEN COMB_2_16_d1 =>
231 248 IF current_channel = 5 THEN
232 249 STATE_CIC_LFR <= IDLE;
233 250 IF nb_data_receipt = 256 THEN
234 251 nb_data_receipt <= 0;
235 252 END IF;
236 253 ELSE
237 254 current_channel <= current_channel +1;
238 255 STATE_CIC_LFR <= INT_0_d0;
239 256 END IF;
240 257
241 258 -------------------------------------------------------------------
242 259 WHEN COMB_0_256_d0 => STATE_CIC_LFR <= COMB_0_256_d1;
243 260 WHEN COMB_0_256_d1 => STATE_CIC_LFR <= COMB_0_256_d2;
244 261 WHEN COMB_0_256_d2 => STATE_CIC_LFR <= COMB_1_256_d0;
245 262
246 263 WHEN COMB_1_256_d0 => STATE_CIC_LFR <= COMB_1_256_d1;
247 264 WHEN COMB_1_256_d1 => STATE_CIC_LFR <= COMB_1_256_d2;
248 265 WHEN COMB_1_256_d2 => STATE_CIC_LFR <= COMB_2_256_d0;
249 266
250 267 WHEN COMB_2_256_d0 => STATE_CIC_LFR <= COMB_2_256_d1;
251 268 WHEN COMB_2_256_d1 => STATE_CIC_LFR <= COMB_2_256_d2;
252 269 WHEN COMB_2_256_d2 => STATE_CIC_LFR <= READ_INT_2_d0;
253 270
254 271 -------------------------------------------------------------------
255 272 WHEN READ_INT_2_d0 => STATE_CIC_LFR <= READ_INT_2_d1;
256 273 WHEN READ_INT_2_d1 => STATE_CIC_LFR <= COMB_0_16_d0;
257 274
258 275 WHEN OTHERS => NULL;
259 276 END CASE;
260 277 END IF;
261 278 END IF;
262 279 END PROCESS;
263 280
264 281 END beh;
265
Show file before | Show file after | Hide comments
@@ -1,776 +1,784
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_lfr_pkg.ALL;
32 32 --USE lpp.lpp_amba.ALL;
33 33 USE lpp.apb_devices_list.ALL;
34 34 USE lpp.lpp_memory.ALL;
35 35 LIBRARY techmap;
36 36 USE techmap.gencomp.ALL;
37 37
38 38 ENTITY lpp_lfr_apbreg IS
39 39 GENERIC (
40 40 nb_data_by_buffer_size : INTEGER := 11;
41 41 -- nb_word_by_buffer_size : INTEGER := 11;
42 42 nb_snapshot_param_size : INTEGER := 11;
43 43 delta_vector_size : INTEGER := 20;
44 44 delta_vector_size_f0_2 : INTEGER := 3;
45 45
46 46 pindex : INTEGER := 4;
47 47 paddr : INTEGER := 4;
48 48 pmask : INTEGER := 16#fff#;
49 49 pirq_ms : INTEGER := 0;
50 50 pirq_wfp : INTEGER := 1;
51 51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
52 52 PORT (
53 53 -- AMBA AHB system signals
54 54 HCLK : IN STD_ULOGIC;
55 55 HRESETn : IN STD_ULOGIC;
56 56
57 57 -- AMBA APB Slave Interface
58 58 apbi : IN apb_slv_in_type;
59 59 apbo : OUT apb_slv_out_type;
60 60
61 61 ---------------------------------------------------------------------------
62 62 -- Spectral Matrix Reg
63 63 run_ms : OUT STD_LOGIC;
64 64 -- IN
65 65 ready_matrix_f0 : IN STD_LOGIC;
66 66 ready_matrix_f1 : IN STD_LOGIC;
67 67 ready_matrix_f2 : IN STD_LOGIC;
68 68
69 69 -- error_bad_component_error : IN STD_LOGIC;
70 70 error_buffer_full : IN STD_LOGIC; -- TODO
71 71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72 72
73 73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74
75 75 -- OUT
76 76 status_ready_matrix_f0 : OUT STD_LOGIC;
77 77 status_ready_matrix_f1 : OUT STD_LOGIC;
78 78 status_ready_matrix_f2 : OUT STD_LOGIC;
79 79
80 80 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 81 --config_active_interruption_onError : OUT STD_LOGIC;
82 82
83 83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86
87 87 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
88 88 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 89 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 90
91 91 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92 92 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 93 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 94
95 95 ---------------------------------------------------------------------------
96 96 ---------------------------------------------------------------------------
97 97 -- WaveForm picker Reg
98 98 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
99 99 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
100 100 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 101 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
102 102
103 103 -- OUT
104 104 data_shaping_BW : OUT STD_LOGIC;
105 105 data_shaping_SP0 : OUT STD_LOGIC;
106 106 data_shaping_SP1 : OUT STD_LOGIC;
107 107 data_shaping_R0 : OUT STD_LOGIC;
108 108 data_shaping_R1 : OUT STD_LOGIC;
109 109 data_shaping_R2 : OUT STD_LOGIC;
110 110
111 111 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 112 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 113 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
114 114 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 115 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 116 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
117 117 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
118 118 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
119 119
120 120 enable_f0 : OUT STD_LOGIC;
121 121 enable_f1 : OUT STD_LOGIC;
122 122 enable_f2 : OUT STD_LOGIC;
123 123 enable_f3 : OUT STD_LOGIC;
124 124
125 125 burst_f0 : OUT STD_LOGIC;
126 126 burst_f1 : OUT STD_LOGIC;
127 127 burst_f2 : OUT STD_LOGIC;
128 128
129 129 run : OUT STD_LOGIC;
130 130
131 131 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
132 132
133 133 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
134 134 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
135 135 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
136 136 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
137 137 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
138 138 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
139 139
140 140 );
141 141
142 142 END lpp_lfr_apbreg;
143 143
144 144 ARCHITECTURE beh OF lpp_lfr_apbreg IS
145 145
146 146 CONSTANT REVISION : INTEGER := 1;
147 147
148 148 CONSTANT pconfig : apb_config_type := (
149 149 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
150 150 1 => apb_iobar(paddr, pmask));
151 151
152 152 TYPE lpp_SpectralMatrix_regs IS RECORD
153 153 config_active_interruption_onNewMatrix : STD_LOGIC;
154 154 config_active_interruption_onError : STD_LOGIC;
155 155 config_ms_run : STD_LOGIC;
156 156 status_ready_matrix_f0_0 : STD_LOGIC;
157 157 status_ready_matrix_f1_0 : STD_LOGIC;
158 158 status_ready_matrix_f2_0 : STD_LOGIC;
159 159 status_ready_matrix_f0_1 : STD_LOGIC;
160 160 status_ready_matrix_f1_1 : STD_LOGIC;
161 161 status_ready_matrix_f2_1 : STD_LOGIC;
162 162 -- status_error_bad_component_error : STD_LOGIC;
163 163 status_error_buffer_full : STD_LOGIC;
164 164 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
165 165
166 166 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 168 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 169 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 170 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 171 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 172
173 173 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
174 174
175 175 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 176 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 177 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 178 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 179 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 180 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
181 181 END RECORD;
182 182 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
183 183
184 184 TYPE lpp_WaveformPicker_regs IS RECORD
185 185 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 186 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 187 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 188 data_shaping_BW : STD_LOGIC;
189 189 data_shaping_SP0 : STD_LOGIC;
190 190 data_shaping_SP1 : STD_LOGIC;
191 191 data_shaping_R0 : STD_LOGIC;
192 192 data_shaping_R1 : STD_LOGIC;
193 193 data_shaping_R2 : STD_LOGIC;
194 194 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 195 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196 196 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
197 197 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
198 198 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
199 199 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
200 200 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
201 201 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
202 202 enable_f0 : STD_LOGIC;
203 203 enable_f1 : STD_LOGIC;
204 204 enable_f2 : STD_LOGIC;
205 205 enable_f3 : STD_LOGIC;
206 206 burst_f0 : STD_LOGIC;
207 207 burst_f1 : STD_LOGIC;
208 208 burst_f2 : STD_LOGIC;
209 209 run : STD_LOGIC;
210 210 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
211 211 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
212 212 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
213 213 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
214 214 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 215 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
216 216 END RECORD;
217 217 SIGNAL reg_wp : lpp_WaveformPicker_regs;
218 218
219 219 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 220
221 221 -----------------------------------------------------------------------------
222 222 -- IRQ
223 223 -----------------------------------------------------------------------------
224 224 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
225 225 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 226 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
227 227 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
228 228 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
229 229 SIGNAL ored_irq_wfp : STD_LOGIC;
230 230
231 231 -----------------------------------------------------------------------------
232 232 --
233 233 -----------------------------------------------------------------------------
234 234 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
235 235 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 236 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
237 237
238 238 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
239 239 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 240 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
241 241
242 242 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
243 243 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 244 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
245 245
246 246 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
247 247 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 248 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
249 249
250 250 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
251 251 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 252 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
253 253
254 254 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
255 255 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
256 256 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
257 257 SIGNAL apbo_irq_ms : STD_LOGIC;
258 258 SIGNAL apbo_irq_wfp : STD_LOGIC;
259 259 -----------------------------------------------------------------------------
260 260 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
261 261
262 262 BEGIN -- beh
263 263
264 264 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
265 265 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
266 266 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
267 267
268 268 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
269 269 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
270 270
271 271
272 272 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
273 273 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
274 274 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
275 275
276 276
277 277 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
278 278 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
279 279 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
280 280 data_shaping_R0 <= reg_wp.data_shaping_R0;
281 281 data_shaping_R1 <= reg_wp.data_shaping_R1;
282 282 data_shaping_R2 <= reg_wp.data_shaping_R2;
283 283
284 284 delta_snapshot <= reg_wp.delta_snapshot;
285 285 delta_f0 <= reg_wp.delta_f0;
286 286 delta_f0_2 <= reg_wp.delta_f0_2;
287 287 delta_f1 <= reg_wp.delta_f1;
288 288 delta_f2 <= reg_wp.delta_f2;
289 289 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
290 290 nb_snapshot_param <= reg_wp.nb_snapshot_param;
291 291
292 292 enable_f0 <= reg_wp.enable_f0;
293 293 enable_f1 <= reg_wp.enable_f1;
294 294 enable_f2 <= reg_wp.enable_f2;
295 295 enable_f3 <= reg_wp.enable_f3;
296 296
297 297 burst_f0 <= reg_wp.burst_f0;
298 298 burst_f1 <= reg_wp.burst_f1;
299 299 burst_f2 <= reg_wp.burst_f2;
300 300
301 301 run <= reg_wp.run;
302 302
303 303 --addr_data_f0 <= reg_wp.addr_data_f0;
304 304 --addr_data_f1 <= reg_wp.addr_data_f1;
305 305 --addr_data_f2 <= reg_wp.addr_data_f2;
306 306 --addr_data_f3 <= reg_wp.addr_data_f3;
307 307
308 308 start_date <= reg_wp.start_date;
309 309
310 310 length_matrix_f0 <= reg_sp.length_matrix;
311 311 length_matrix_f1 <= reg_sp.length_matrix;
312 312 length_matrix_f2 <= reg_sp.length_matrix;
313 313 wfp_length_buffer <= reg_wp.length_buffer;
314 314
315 315
316 316 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
317 317 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
318 318 BEGIN -- PROCESS lpp_dma_top
319 319 IF HRESETn = '0' THEN -- asynchronous reset (active low)
320 320 reg_sp.config_active_interruption_onNewMatrix <= '0';
321 321 reg_sp.config_active_interruption_onError <= '0';
322 322 reg_sp.config_ms_run <= '0';
323 323 reg_sp.status_ready_matrix_f0_0 <= '0';
324 324 reg_sp.status_ready_matrix_f1_0 <= '0';
325 325 reg_sp.status_ready_matrix_f2_0 <= '0';
326 326 reg_sp.status_ready_matrix_f0_1 <= '0';
327 327 reg_sp.status_ready_matrix_f1_1 <= '0';
328 328 reg_sp.status_ready_matrix_f2_1 <= '0';
329 329 reg_sp.status_error_buffer_full <= '0';
330 330 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
331 331
332 332 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
333 333 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
334 334 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
335 335
336 336 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
337 337 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
338 338 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
339 339
340 340 reg_sp.length_matrix <= (OTHERS => '0');
341 341
342 342 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
343 343 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
344 344 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
345 345
346 346 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
347 347 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
348 348 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
349 349
350 350 prdata <= (OTHERS => '0');
351 351
352 352
353 353 apbo_irq_ms <= '0';
354 354 apbo_irq_wfp <= '0';
355 355
356 356
357 357 -- status_full_ack <= (OTHERS => '0');
358 358
359 359 reg_wp.data_shaping_BW <= '0';
360 360 reg_wp.data_shaping_SP0 <= '0';
361 361 reg_wp.data_shaping_SP1 <= '0';
362 362 reg_wp.data_shaping_R0 <= '0';
363 363 reg_wp.data_shaping_R1 <= '0';
364 364 reg_wp.data_shaping_R2 <= '0';
365 365 reg_wp.enable_f0 <= '0';
366 366 reg_wp.enable_f1 <= '0';
367 367 reg_wp.enable_f2 <= '0';
368 368 reg_wp.enable_f3 <= '0';
369 369 reg_wp.burst_f0 <= '0';
370 370 reg_wp.burst_f1 <= '0';
371 371 reg_wp.burst_f2 <= '0';
372 372 reg_wp.run <= '0';
373 373 -- reg_wp.status_full <= (OTHERS => '0');
374 374 -- reg_wp.status_full_err <= (OTHERS => '0');
375 375 reg_wp.status_new_err <= (OTHERS => '0');
376 376 reg_wp.error_buffer_full <= (OTHERS => '0');
377 377 reg_wp.delta_snapshot <= (OTHERS => '0');
378 378 reg_wp.delta_f0 <= (OTHERS => '0');
379 379 reg_wp.delta_f0_2 <= (OTHERS => '0');
380 380 reg_wp.delta_f1 <= (OTHERS => '0');
381 381 reg_wp.delta_f2 <= (OTHERS => '0');
382 382 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
383 383 reg_wp.nb_snapshot_param <= (OTHERS => '0');
384 384 reg_wp.start_date <= (OTHERS => '0');
385 385
386 386 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
387 387 reg_wp.length_buffer <= (OTHERS => '0');
388 388 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
389 389
390 390 -- status_full_ack <= (OTHERS => '0');
391 391
392 392 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
393 393 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
394 394 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
395 395
396 396 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
397 397 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
398 398 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
399 399
400 400 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
401 401 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
402 402 END LOOP all_status_ready_buffer_bit;
403 403
404 404
405 405 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
406 406 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
407 407 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
408 408 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
409 409
410 410
411 411
412 412 all_status : FOR I IN 3 DOWNTO 0 LOOP
413 413 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
414 414 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
415 415 END LOOP all_status;
416 416
417 417 paddr := "000000";
418 418 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
419 419 prdata <= (OTHERS => '0');
420 420 IF apbi.psel(pindex) = '1' THEN
421 421 -- APB DMA READ --
422 422 CASE paddr(7 DOWNTO 2) IS
423 423 --0
424 424 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
425 425 prdata(1) <= reg_sp.config_active_interruption_onError;
426 426 prdata(2) <= reg_sp.config_ms_run;
427 427 --1
428 428 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
429 429 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
430 430 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
431 431 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
432 432 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
433 433 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
434 434 -- prdata(6) <= reg_sp.status_error_bad_component_error;
435 435 prdata(7) <= reg_sp.status_error_buffer_full;
436 436 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
437 437 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
438 438 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
439 439 --2
440 440 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
441 441 --3
442 442 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
443 443 --4
444 444 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
445 445 --5
446 446 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
447 447 --6
448 448 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
449 449 --7
450 450 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
451 451 --8
452 452 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
453 453 --9
454 454 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
455 455 --10
456 456 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
457 457 --11
458 458 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
459 459 --12
460 460 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
461 461 --13
462 462 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
463 463 --14
464 464 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
465 465 --15
466 466 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
467 467 --16
468 468 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
469 469 --17
470 470 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
471 471 --18
472 472 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
473 473 --19
474 474 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
475 475 --20
476 476 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
477 477 ---------------------------------------------------------------------
478 478 --20
479 479 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
480 480 prdata(1) <= reg_wp.data_shaping_SP0;
481 481 prdata(2) <= reg_wp.data_shaping_SP1;
482 482 prdata(3) <= reg_wp.data_shaping_R0;
483 483 prdata(4) <= reg_wp.data_shaping_R1;
484 484 prdata(5) <= reg_wp.data_shaping_R2;
485 485 --21
486 486 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
487 487 prdata(1) <= reg_wp.enable_f1;
488 488 prdata(2) <= reg_wp.enable_f2;
489 489 prdata(3) <= reg_wp.enable_f3;
490 490 prdata(4) <= reg_wp.burst_f0;
491 491 prdata(5) <= reg_wp.burst_f1;
492 492 prdata(6) <= reg_wp.burst_f2;
493 493 prdata(7) <= reg_wp.run;
494 494 --22
495 495 --ON GOING \/
496 496 WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
497 497 WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
498 498 WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
499 499 WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
500 500 WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
501 501 WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
502 502 WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
503 503 WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
504 504 --ON GOING /\
505 505 WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
506 506 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
507 507 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
508 508 --prdata(3 DOWNTO 0) <= reg_wp.status_full;
509 509 -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
510 510 --27
511 511 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
512 512 --28
513 513 WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
514 514 --29
515 515 WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
516 516 --30
517 517 WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
518 518 --31
519 519 WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
520 520 --32
521 521 WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
522 522 --33
523 523 WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
524 524 --34
525 525 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
526 526 --35
527 527 WHEN "101000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); --reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0);
528 528 WHEN "101001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); --reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16);
529 529 WHEN "101010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
530 530 WHEN "101011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
531 531
532 532 WHEN "101100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
533 533 WHEN "101101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
534 534 WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
535 535 WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
536 536
537 537 WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
538 538 WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
539 539 WHEN "110010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
540 540 WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
541 541
542 542 WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
543 543 WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
544 544 WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
545 545 WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
546 546
547 547 WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
548 548
549 549 -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
550 550 ----------------------------------------------------
551 551 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
552 552 WHEN OTHERS => NULL;
553 553
554 554 END CASE;
555 555 IF (apbi.pwrite AND apbi.penable) = '1' THEN
556 556 -- APB DMA WRITE --
557 557 CASE paddr(7 DOWNTO 2) IS
558 558 --
559 559 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
560 560 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
561 561 reg_sp.config_ms_run <= apbi.pwdata(2);
562 562
563 563 WHEN "000001" =>
564 564 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
565 565 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
566 566 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
567 567 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
568 568 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
569 569 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
570 570 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
571 571 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
572 572 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
573 573 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
574 574 --2
575 575 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
576 576 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
577 577 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
578 578 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
579 579 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
580 580 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
581 581 --8 to 19
582 582 --20
583 583 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
584 584 --20
585 585 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
586 586 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
587 587 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
588 588 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
589 589 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
590 590 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
591 591 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
592 592 reg_wp.enable_f1 <= apbi.pwdata(1);
593 593 reg_wp.enable_f2 <= apbi.pwdata(2);
594 594 reg_wp.enable_f3 <= apbi.pwdata(3);
595 595 reg_wp.burst_f0 <= apbi.pwdata(4);
596 596 reg_wp.burst_f1 <= apbi.pwdata(5);
597 597 reg_wp.burst_f2 <= apbi.pwdata(6);
598 598 reg_wp.run <= apbi.pwdata(7);
599 599 --22
600 600 WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
601 601 WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
602 602 WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
603 603 WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
604 604 WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
605 605 WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
606 606 WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
607 607 WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
608 608 --26
609 609 WHEN "011111" =>
610 610 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
611 611 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
612 612 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
613 613 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
614 614 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
615 615 END LOOP all_reg_wp_status_bit;
616 616
617 617 WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
618 618 WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
619 619 WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
620 620 WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
621 621 WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
622 622 WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
623 623 WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
624 624 WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
625 625
626 626 WHEN "111000" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
627 627
628 628
629 629
630 630
631 631
632 632 -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
633 633 --
634 634 WHEN OTHERS => NULL;
635 635 END CASE;
636 636 END IF;
637 637 END IF;
638 638 --apbo.pirq(pirq_ms) <=
639 639 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
640 640 ready_matrix_f1 OR
641 641 ready_matrix_f2)
642 642 )
643 643 OR
644 644 (reg_sp.config_active_interruption_onError AND (
645 645 -- error_bad_component_error OR
646 646 error_buffer_full
647 647 OR error_input_fifo_write(0)
648 648 OR error_input_fifo_write(1)
649 649 OR error_input_fifo_write(2))
650 650 ));
651 651 -- apbo.pirq(pirq_wfp)
652 652 apbo_irq_wfp<= ored_irq_wfp;
653 653
654 654 END IF;
655 655 END PROCESS lpp_lfr_apbreg;
656 656
657 657 apbo.pirq(pirq_ms) <= apbo_irq_ms;
658 658 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
659 659
660 660 apbo.pindex <= pindex;
661 661 apbo.pconfig <= pconfig;
662 662 apbo.prdata <= prdata;
663 663
664 664 -----------------------------------------------------------------------------
665 665 -- IRQ
666 666 -----------------------------------------------------------------------------
667 667 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
668 668
669 669 PROCESS (HCLK, HRESETn)
670 670 BEGIN -- PROCESS
671 671 IF HRESETn = '0' THEN -- asynchronous reset (active low)
672 672 irq_wfp_reg <= (OTHERS => '0');
673 673 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
674 674 irq_wfp_reg <= irq_wfp_reg_s;
675 675 END IF;
676 676 END PROCESS;
677 677
678 678 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
679 679 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
680 680 END GENERATE all_irq_wfp;
681 681
682 682 irq_wfp_ZERO <= (OTHERS => '0');
683 683 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
684 684
685 685 run_ms <= reg_sp.config_ms_run;
686 686
687 687 -----------------------------------------------------------------------------
688 688 --
689 689 -----------------------------------------------------------------------------
690 690 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
691 691 PORT MAP (
692 692 clk => HCLK,
693 693 rstn => HRESETn,
694 694
695 run => reg_sp.config_ms_run,
696
695 697 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
696 698 reg0_ready_matrix => reg0_ready_matrix_f0,
697 699 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
698 700 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
699 701
700 702 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
701 703 reg1_ready_matrix => reg1_ready_matrix_f0,
702 704 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
703 705 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
704 706
705 707 ready_matrix => ready_matrix_f0,
706 708 status_ready_matrix => status_ready_matrix_f0,
707 709 addr_matrix => addr_matrix_f0,
708 710 matrix_time => matrix_time_f0);
709 711
710 712 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
711 713 PORT MAP (
712 714 clk => HCLK,
713 715 rstn => HRESETn,
714 716
717 run => reg_sp.config_ms_run,
718
715 719 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
716 720 reg0_ready_matrix => reg0_ready_matrix_f1,
717 721 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
718 722 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
719 723
720 724 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
721 725 reg1_ready_matrix => reg1_ready_matrix_f1,
722 726 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
723 727 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
724 728
725 729 ready_matrix => ready_matrix_f1,
726 730 status_ready_matrix => status_ready_matrix_f1,
727 731 addr_matrix => addr_matrix_f1,
728 732 matrix_time => matrix_time_f1);
729 733
730 734 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
731 735 PORT MAP (
732 736 clk => HCLK,
733 737 rstn => HRESETn,
734 738
739 run => reg_sp.config_ms_run,
740
735 741 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
736 742 reg0_ready_matrix => reg0_ready_matrix_f2,
737 743 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
738 744 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
739 745
740 746 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
741 747 reg1_ready_matrix => reg1_ready_matrix_f2,
742 748 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
743 749 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
744 750
745 751 ready_matrix => ready_matrix_f2,
746 752 status_ready_matrix => status_ready_matrix_f2,
747 753 addr_matrix => addr_matrix_f2,
748 754 matrix_time => matrix_time_f2);
749 755
750 756 -----------------------------------------------------------------------------
751 757 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
752 758 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
753 759 PORT MAP (
754 760 clk => HCLK,
755 761 rstn => HRESETn,
756 762
763 run => reg_wp.run,
764
757 765 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
758 766 reg0_ready_matrix => reg_ready_buffer_f(2*I),
759 767 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
760 768 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
761 769
762 770 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
763 771 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
764 772 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
765 773 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
766 774
767 775 ready_matrix => wfp_ready_buffer(I),
768 776 status_ready_matrix => wfp_status_buffer_ready(I),
769 777 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
770 778 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
771 779 );
772 780
773 781 END GENERATE all_wfp_pointer;
774 782 -----------------------------------------------------------------------------
775 783
776 END beh; No newline at end of file
784 END beh;
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@@ -1,96 +1,103
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26
27 27 ENTITY lpp_apbreg_ms_pointer IS
28 28
29 29 PORT (
30 30 clk : IN STD_LOGIC;
31 31 rstn : IN STD_LOGIC;
32 run : IN STD_LOGIC;
32 33
33 34 -- REG 0
34 35 reg0_status_ready_matrix : IN STD_LOGIC;
35 36 reg0_ready_matrix : OUT STD_LOGIC;
36 37 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
37 38 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
38 39
39 40 -- REG 1
40 41 reg1_status_ready_matrix : IN STD_LOGIC;
41 42 reg1_ready_matrix : OUT STD_LOGIC;
42 43 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
43 44 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
44 45
45 46 -- SpectralMatrix
46 47 ready_matrix : IN STD_LOGIC;
47 48 status_ready_matrix : OUT STD_LOGIC;
48 49 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49 50 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
50 51 );
51 52
52 53 END lpp_apbreg_ms_pointer;
53 54
54 55 ARCHITECTURE beh OF lpp_apbreg_ms_pointer IS
55 56
56 57 SIGNAL current_reg : STD_LOGIC;
57 58
58 59 BEGIN -- beh
59 60
60 61 PROCESS (clk, rstn)
61 62 BEGIN -- PROCESS
62 63 IF rstn = '0' THEN -- asynchronous reset (active low)
63 current_reg <= '0';
64 current_reg <= '0';
64 65 reg0_matrix_time <= (OTHERS => '0');
65 66 reg1_matrix_time <= (OTHERS => '0');
66 67
67 68 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
68 IF ready_matrix = '1' THEN
69 current_reg <= NOT current_reg;
70
71 IF current_reg = '0' THEN
72 reg0_matrix_time <= matrix_time;
69 IF run = '0' THEN
70 current_reg <= '0';
71 reg0_matrix_time <= (OTHERS => '0');
72 reg1_matrix_time <= (OTHERS => '0');
73 ELSE
74 IF ready_matrix = '1' THEN
75 current_reg <= NOT current_reg;
76
77 IF current_reg = '0' THEN
78 reg0_matrix_time <= matrix_time;
79 END IF;
80
81 IF current_reg = '1' THEN
82 reg1_matrix_time <= matrix_time;
83 END IF;
84
73 85 END IF;
74
75 IF current_reg = '1' THEN
76 reg1_matrix_time <= matrix_time;
77 END IF;
78
79 86 END IF;
80 87
81 88 END IF;
82 89 END PROCESS;
83 90
84 91 addr_matrix <= reg0_addr_matrix WHEN current_reg = '0' ELSE
85 92 reg1_addr_matrix;
86 93
87 94 status_ready_matrix <= reg0_status_ready_matrix WHEN current_reg = '0' ELSE
88 95 reg1_status_ready_matrix;
89 96
90 97 reg0_ready_matrix <= ready_matrix WHEN current_reg = '0' ELSE '0';
91 98 reg1_ready_matrix <= ready_matrix WHEN current_reg = '1' ELSE '0';
92 99
93 100
94 101
95 102
96 103 END beh;
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@@ -1,385 +1,385
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_lfr_pkg IS
16 16 -----------------------------------------------------------------------------
17 17 -- TEMP
18 18 -----------------------------------------------------------------------------
19 19 COMPONENT lpp_lfr_ms_test
20 20 GENERIC (
21 21 Mem_use : INTEGER);
22 22 PORT (
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 25
26 26 -- TIME
27 27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 29 --
30 30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 32 --
33 33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 35 --
36 36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38 38
39 39
40 40
41 41 ---------------------------------------------------------------------------
42 42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43 43
44 44 --
45 45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49 49
50 50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51 51
52 52 -- IN
53 53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54 54
55 55 -----------------------------------------------------------------------------
56 56
57 57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61 61
62 62 SM_correlation_start : OUT STD_LOGIC;
63 63 SM_correlation_auto : OUT STD_LOGIC;
64 64 SM_correlation_done : IN STD_LOGIC
65 65 );
66 66 END COMPONENT;
67 67
68 68
69 69 -----------------------------------------------------------------------------
70 70 COMPONENT lpp_lfr_ms
71 71 GENERIC (
72 72 Mem_use : INTEGER);
73 73 PORT (
74 74 clk : IN STD_LOGIC;
75 75 rstn : IN STD_LOGIC;
76 76 run : IN STD_LOGIC;
77 77 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 78 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
79 79 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 80 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 81 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 82 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 83 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 84 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 85 dma_fifo_burst_valid : OUT STD_LOGIC;
86 86 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 87 dma_fifo_ren : IN STD_LOGIC;
88 88 dma_buffer_new : OUT STD_LOGIC;
89 89 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 91 dma_buffer_full : IN STD_LOGIC;
92 92 dma_buffer_full_err : IN STD_LOGIC;
93 93 ready_matrix_f0 : OUT STD_LOGIC;
94 94 ready_matrix_f1 : OUT STD_LOGIC;
95 95 ready_matrix_f2 : OUT STD_LOGIC;
96 96 error_buffer_full : OUT STD_LOGIC;
97 97 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
98 98 status_ready_matrix_f0 : IN STD_LOGIC;
99 99 status_ready_matrix_f1 : IN STD_LOGIC;
100 100 status_ready_matrix_f2 : IN STD_LOGIC;
101 101 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
105 105 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 106 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 107 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 108 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 109 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
110 110 END COMPONENT;
111 111
112 112 COMPONENT lpp_lfr_ms_fsmdma
113 113 PORT (
114 114 clk : IN STD_ULOGIC;
115 115 rstn : IN STD_ULOGIC;
116 116 run : IN STD_LOGIC;
117 117 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
118 118 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
119 119 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 120 fifo_empty : IN STD_LOGIC;
121 121 fifo_empty_threshold : IN STD_LOGIC;
122 122 fifo_ren : OUT STD_LOGIC;
123 123 dma_fifo_valid_burst : OUT STD_LOGIC;
124 124 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
125 125 dma_fifo_ren : IN STD_LOGIC;
126 126 dma_buffer_new : OUT STD_LOGIC;
127 127 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 128 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
129 129 dma_buffer_full : IN STD_LOGIC;
130 130 dma_buffer_full_err : IN STD_LOGIC;
131 131 status_ready_matrix_f0 : IN STD_LOGIC;
132 132 status_ready_matrix_f1 : IN STD_LOGIC;
133 133 status_ready_matrix_f2 : IN STD_LOGIC;
134 134 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 135 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 136 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 137 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
138 138 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 139 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 140 ready_matrix_f0 : OUT STD_LOGIC;
141 141 ready_matrix_f1 : OUT STD_LOGIC;
142 142 ready_matrix_f2 : OUT STD_LOGIC;
143 143 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
144 144 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 145 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 146 error_buffer_full : OUT STD_LOGIC);
147 147 END COMPONENT;
148 148
149 149 COMPONENT lpp_lfr_ms_FFT
150 150 PORT (
151 151 clk : IN STD_LOGIC;
152 152 rstn : IN STD_LOGIC;
153 153 sample_valid : IN STD_LOGIC;
154 154 fft_read : IN STD_LOGIC;
155 155 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
156 156 sample_load : OUT STD_LOGIC;
157 157 fft_pong : OUT STD_LOGIC;
158 158 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
159 159 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
160 160 fft_data_valid : OUT STD_LOGIC;
161 161 fft_ready : OUT STD_LOGIC);
162 162 END COMPONENT;
163 163
164 164 COMPONENT lpp_lfr_filter
165 165 GENERIC (
166 166 Mem_use : INTEGER);
167 167 PORT (
168 168 sample : IN Samples(7 DOWNTO 0);
169 169 sample_val : IN STD_LOGIC;
170 170 clk : IN STD_LOGIC;
171 171 rstn : IN STD_LOGIC;
172 172 data_shaping_SP0 : IN STD_LOGIC;
173 173 data_shaping_SP1 : IN STD_LOGIC;
174 174 data_shaping_R0 : IN STD_LOGIC;
175 175 data_shaping_R1 : IN STD_LOGIC;
176 176 data_shaping_R2 : IN STD_LOGIC;
177 177 sample_f0_val : OUT STD_LOGIC;
178 178 sample_f1_val : OUT STD_LOGIC;
179 179 sample_f2_val : OUT STD_LOGIC;
180 180 sample_f3_val : OUT STD_LOGIC;
181 181 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
182 182 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 183 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 184 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
185 185 END COMPONENT;
186 186
187 187 COMPONENT lpp_lfr
188 188 GENERIC (
189 189 Mem_use : INTEGER;
190 190 nb_data_by_buffer_size : INTEGER;
191 191 -- nb_word_by_buffer_size : INTEGER;
192 192 nb_snapshot_param_size : INTEGER;
193 193 delta_vector_size : INTEGER;
194 194 delta_vector_size_f0_2 : INTEGER;
195 195 pindex : INTEGER;
196 196 paddr : INTEGER;
197 197 pmask : INTEGER;
198 198 pirq_ms : INTEGER;
199 199 pirq_wfp : INTEGER;
200 200 hindex : INTEGER;
201 201 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
202 202 );
203 203 PORT (
204 204 clk : IN STD_LOGIC;
205 205 rstn : IN STD_LOGIC;
206 206 sample_B : IN Samples(2 DOWNTO 0);
207 207 sample_E : IN Samples(4 DOWNTO 0);
208 208 sample_val : IN STD_LOGIC;
209 209 apbi : IN apb_slv_in_type;
210 210 apbo : OUT apb_slv_out_type;
211 211 ahbi : IN AHB_Mst_In_Type;
212 212 ahbo : OUT AHB_Mst_Out_Type;
213 213 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
214 214 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
215 215 data_shaping_BW : OUT STD_LOGIC
216 216 );
217 217 END COMPONENT;
218 218
219 219 -----------------------------------------------------------------------------
220 220 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
221 221 -----------------------------------------------------------------------------
222 222 COMPONENT lpp_lfr_WFP_nMS
223 223 GENERIC (
224 224 Mem_use : INTEGER;
225 225 nb_data_by_buffer_size : INTEGER;
226 226 nb_word_by_buffer_size : INTEGER;
227 227 nb_snapshot_param_size : INTEGER;
228 228 delta_vector_size : INTEGER;
229 229 delta_vector_size_f0_2 : INTEGER;
230 230 pindex : INTEGER;
231 231 paddr : INTEGER;
232 232 pmask : INTEGER;
233 233 pirq_ms : INTEGER;
234 234 pirq_wfp : INTEGER;
235 235 hindex : INTEGER;
236 236 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
237 237 PORT (
238 238 clk : IN STD_LOGIC;
239 239 rstn : IN STD_LOGIC;
240 240 sample_B : IN Samples(2 DOWNTO 0);
241 241 sample_E : IN Samples(4 DOWNTO 0);
242 242 sample_val : IN STD_LOGIC;
243 243 apbi : IN apb_slv_in_type;
244 244 apbo : OUT apb_slv_out_type;
245 245 ahbi : IN AHB_Mst_In_Type;
246 246 ahbo : OUT AHB_Mst_Out_Type;
247 247 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
248 248 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
249 249 data_shaping_BW : OUT STD_LOGIC;
250 250 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
251 251 END COMPONENT;
252 252 -----------------------------------------------------------------------------
253 253
254 254 COMPONENT lpp_lfr_apbreg
255 255 GENERIC (
256 256 nb_data_by_buffer_size : INTEGER;
257 257 nb_snapshot_param_size : INTEGER;
258 258 delta_vector_size : INTEGER;
259 259 delta_vector_size_f0_2 : INTEGER;
260 260 pindex : INTEGER;
261 261 paddr : INTEGER;
262 262 pmask : INTEGER;
263 263 pirq_ms : INTEGER;
264 264 pirq_wfp : INTEGER;
265 265 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
266 266 PORT (
267 267 HCLK : IN STD_ULOGIC;
268 268 HRESETn : IN STD_ULOGIC;
269 269 apbi : IN apb_slv_in_type;
270 270 apbo : OUT apb_slv_out_type;
271 271 run_ms : OUT STD_LOGIC;
272 272 ready_matrix_f0 : IN STD_LOGIC;
273 273 ready_matrix_f1 : IN STD_LOGIC;
274 274 ready_matrix_f2 : IN STD_LOGIC;
275 275 error_buffer_full : IN STD_LOGIC;
276 276 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
277 277 status_ready_matrix_f0 : OUT STD_LOGIC;
278 278 status_ready_matrix_f1 : OUT STD_LOGIC;
279 279 status_ready_matrix_f2 : OUT STD_LOGIC;
280 280 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
281 281 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
282 282 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 283 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
284 284 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
285 285 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
286 286 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
287 287 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
288 288 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
289 289 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
290 290 data_shaping_BW : OUT STD_LOGIC;
291 291 data_shaping_SP0 : OUT STD_LOGIC;
292 292 data_shaping_SP1 : OUT STD_LOGIC;
293 293 data_shaping_R0 : OUT STD_LOGIC;
294 294 data_shaping_R1 : OUT STD_LOGIC;
295 295 data_shaping_R2 : OUT STD_LOGIC;
296 296 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
297 297 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
298 298 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
299 299 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
300 300 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
301 301 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
302 302 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
303 303 enable_f0 : OUT STD_LOGIC;
304 304 enable_f1 : OUT STD_LOGIC;
305 305 enable_f2 : OUT STD_LOGIC;
306 306 enable_f3 : OUT STD_LOGIC;
307 307 burst_f0 : OUT STD_LOGIC;
308 308 burst_f1 : OUT STD_LOGIC;
309 309 burst_f2 : OUT STD_LOGIC;
310 310 run : OUT STD_LOGIC;
311 311 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
312 312 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
313 313 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
314 314 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
315 315 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
316 316 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
317 317 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
318 318 END COMPONENT;
319 319
320 320 COMPONENT lpp_top_ms
321 321 GENERIC (
322 322 Mem_use : INTEGER;
323 323 nb_burst_available_size : INTEGER;
324 324 nb_snapshot_param_size : INTEGER;
325 325 delta_snapshot_size : INTEGER;
326 326 delta_f2_f0_size : INTEGER;
327 327 delta_f2_f1_size : INTEGER;
328 328 pindex : INTEGER;
329 329 paddr : INTEGER;
330 330 pmask : INTEGER;
331 331 pirq_ms : INTEGER;
332 332 pirq_wfp : INTEGER;
333 333 hindex_wfp : INTEGER;
334 334 hindex_ms : INTEGER);
335 335 PORT (
336 336 clk : IN STD_LOGIC;
337 337 rstn : IN STD_LOGIC;
338 338 sample_B : IN Samples14v(2 DOWNTO 0);
339 339 sample_E : IN Samples14v(4 DOWNTO 0);
340 340 sample_val : IN STD_LOGIC;
341 341 apbi : IN apb_slv_in_type;
342 342 apbo : OUT apb_slv_out_type;
343 343 ahbi_ms : IN AHB_Mst_In_Type;
344 344 ahbo_ms : OUT AHB_Mst_Out_Type;
345 345 data_shaping_BW : OUT STD_LOGIC;
346 346 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
347 347 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
348 348 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
349 349 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
350
351 350 );
352 351 END COMPONENT;
353 352
354 353 COMPONENT lpp_apbreg_ms_pointer
355 354 PORT (
356 355 clk : IN STD_LOGIC;
357 356 rstn : IN STD_LOGIC;
357 run : IN STD_LOGIC;
358 358 reg0_status_ready_matrix : IN STD_LOGIC;
359 359 reg0_ready_matrix : OUT STD_LOGIC;
360 360 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
361 361 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
362 362 reg1_status_ready_matrix : IN STD_LOGIC;
363 363 reg1_ready_matrix : OUT STD_LOGIC;
364 364 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
365 365 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
366 366 ready_matrix : IN STD_LOGIC;
367 367 status_ready_matrix : OUT STD_LOGIC;
368 368 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
369 369 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
370 370 END COMPONENT;
371 371
372 372 COMPONENT lpp_lfr_ms_reg_head
373 373 PORT (
374 374 clk : IN STD_LOGIC;
375 375 rstn : IN STD_LOGIC;
376 376 in_wen : IN STD_LOGIC;
377 377 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
378 378 in_full : IN STD_LOGIC;
379 379 in_empty : IN STD_LOGIC;
380 380 out_wen : OUT STD_LOGIC;
381 381 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
382 382 out_full : OUT STD_LOGIC);
383 383 END COMPONENT;
384 384
385 385 END lpp_lfr_pkg;
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@@ -1,265 +1,270
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.std_logic_1164.ALL;
24 24 USE IEEE.numeric_std.ALL;
25 25
26 26 LIBRARY lpp;
27 27 USE lpp.lpp_waveform_pkg.ALL;
28 28 USE lpp.general_purpose.ALL;
29 29
30 30 ENTITY lpp_waveform_fifo_arbiter IS
31 31 GENERIC(
32 32 tech : INTEGER := 0;
33 33 nb_data_by_buffer_size : INTEGER := 11
34 34 );
35 35 PORT(
36 36 clk : IN STD_LOGIC;
37 37 rstn : IN STD_LOGIC;
38 38 ---------------------------------------------------------------------------
39 39 run : IN STD_LOGIC;
40 40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
41 41 ---------------------------------------------------------------------------
42 42 -- SNAPSHOT INTERFACE (INPUT)
43 43 ---------------------------------------------------------------------------
44 44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
46 46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
47 47
48 48 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
49 49
50 50 ---------------------------------------------------------------------------
51 51 -- FIFO INTERFACE (OUTPUT)
52 52 ---------------------------------------------------------------------------
53 53 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
54 54 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
55 55 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
56 56 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57 57
58 58 ---------------------------------------------------------------------------
59 59 -- TIME INTERFACE (OUTPUT)
60 60 ---------------------------------------------------------------------------
61 61 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
62 62 time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
63 63
64 64 );
65 65 END ENTITY;
66 66
67 67
68 68 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
69 69 TYPE state_type_fifo_arbiter IS (IDLE,DATA1,DATA2,DATA3,LAST);
70 70 SIGNAL state : state_type_fifo_arbiter;
71 71
72 72 -----------------------------------------------------------------------------
73 73 -- DATA MUX
74 74 -----------------------------------------------------------------------------
75 75 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
76 76 SIGNAL data_0 : WORD_VECTOR(3 DOWNTO 0);
77 77 SIGNAL data_1 : WORD_VECTOR(3 DOWNTO 0);
78 78 SIGNAL data_2 : WORD_VECTOR(3 DOWNTO 0);
79 79 SIGNAL data_3 : WORD_VECTOR(3 DOWNTO 0);
80 80 SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0);
81 81
82 82 -----------------------------------------------------------------------------
83 83 -- RR and SELECTION
84 84 -----------------------------------------------------------------------------
85 85 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
86 86 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
87 87 SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
88 88 SIGNAL sel_reg : STD_LOGIC;
89 89 SIGNAL sel_ack : STD_LOGIC;
90 90 SIGNAL no_sel : STD_LOGIC;
91 91
92 92 -----------------------------------------------------------------------------
93 93 -- REG
94 94 -----------------------------------------------------------------------------
95 95 SIGNAL count_enable : STD_LOGIC;
96 96 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
97 97 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
98 98
99 99 SIGNAL time_sel : STD_LOGIC_VECTOR(47 DOWNTO 0);
100 100
101 101 BEGIN
102 102
103 103 -----------------------------------------------------------------------------
104 104 -- CONTROL
105 105 -----------------------------------------------------------------------------
106 106 PROCESS (clk, rstn)
107 107 BEGIN -- PROCESS
108 108 IF rstn = '0' THEN -- asynchronous reset (active low)
109 109 count_enable <= '0';
110 110 data_in_ack <= (OTHERS => '0');
111 111 data_out_wen <= (OTHERS => '1');
112 112 sel_ack <= '0';
113 113 state <= IDLE;
114 114 time_out <= (OTHERS => '0');
115 115 time_out_new <= (OTHERS => '0');
116 116 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
117 117 count_enable <= '0';
118 118 data_in_ack <= (OTHERS => '0');
119 119 data_out_wen <= (OTHERS => '1');
120 120 sel_ack <= '0';
121 121 time_out_new <= (OTHERS => '0');
122 122 IF run = '0' THEN
123 123 state <= IDLE;
124 124 time_out <= (OTHERS => '0');
125 125 ELSE
126 126 CASE state IS
127 127 WHEN IDLE =>
128 128 IF no_sel = '0' THEN
129 129 state <= DATA1;
130 130 END IF;
131 131 WHEN DATA1 =>
132 132 count_enable <= '1';
133 133 IF UNSIGNED(count) = 0 THEN
134 134 time_out <= time_sel;
135 135 time_out_new <= sel;
136 136 END IF;
137 137 data_out_wen <= NOT sel;
138 138 data_out <= data_sel(0);
139 139 state <= DATA2;
140 140 WHEN DATA2 =>
141 141 data_out_wen <= NOT sel;
142 142 data_out <= data_sel(1);
143 143 state <= DATA3;
144 144 WHEN DATA3 =>
145 145 data_out_wen <= NOT sel;
146 146 data_out <= data_sel(2);
147 147 state <= LAST;
148 148 data_in_ack <= sel;
149 149 WHEN LAST =>
150 150 state <= IDLE;
151 151 sel_ack <= '1';
152 152
153 153 WHEN OTHERS => NULL;
154 154 END CASE;
155 155 END IF;
156 156 END IF;
157 157 END PROCESS;
158 158 -----------------------------------------------------------------------------
159 159
160 160 -----------------------------------------------------------------------------
161 161 -- DATA MUX
162 162 -----------------------------------------------------------------------------
163 163
164 164 all_word: FOR J IN 2 DOWNTO 0 GENERATE
165 165 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
166 166 data_0(J)(I) <= data_in(0,I+32*J);
167 167 data_1(J)(I) <= data_in(1,I+32*J);
168 168 data_2(J)(I) <= data_in(2,I+32*J);
169 169 data_3(J)(I) <= data_in(3,I+32*J);
170 170 END GENERATE all_data_bit;
171 171 END GENERATE all_word;
172 172
173 173 data_sel <= data_0 WHEN sel(0) = '1' ELSE
174 174 data_1 WHEN sel(1) = '1' ELSE
175 175 data_2 WHEN sel(2) = '1' ELSE
176 176 data_3;
177 177
178 178 all_time_bit: FOR I IN 47 DOWNTO 0 GENERATE
179 179
180 180 time_sel(I) <= time_in(0,I) WHEN sel(0) = '1' ELSE
181 181 time_in(1,I) WHEN sel(1) = '1' ELSE
182 182 time_in(2,I) WHEN sel(2) = '1' ELSE
183 183 time_in(3,I);
184 184 END GENERATE all_time_bit;
185 185
186 186
187 187 -----------------------------------------------------------------------------
188 188 -- RR and SELECTION
189 189 -----------------------------------------------------------------------------
190 190 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
191 191 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
192 192 END GENERATE all_input_rr;
193 193
194 194 RR_Arbiter_4_1 : RR_Arbiter_4
195 195 PORT MAP (
196 196 clk => clk,
197 197 rstn => rstn,
198 198 in_valid => valid_in_rr,
199 199 out_grant => sel_s);
200 200
201 201 PROCESS (clk, rstn)
202 202 BEGIN -- PROCESS
203 203 IF rstn = '0' THEN -- asynchronous reset (active low)
204 204 sel <= "0000";
205 205 sel_reg <= '0';
206 206 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
207 IF sel_reg = '0' OR sel_ack = '1' THEN
208 sel <= sel_s;
209 IF sel_s = "0000" THEN
210 sel_reg <= '0';
211 ELSE
212 sel_reg <= '1';
207 IF run = '0' THEN
208 sel <= "0000";
209 sel_reg <= '0';
210 ELSE
211 IF sel_reg = '0' OR sel_ack = '1' THEN
212 sel <= sel_s;
213 IF sel_s = "0000" THEN
214 sel_reg <= '0';
215 ELSE
216 sel_reg <= '1';
217 END IF;
213 218 END IF;
214 219 END IF;
215 220 END IF;
216 221 END PROCESS;
217 222
218 223 no_sel <= '1' WHEN sel = "0000" ELSE '0';
219 224
220 225 -----------------------------------------------------------------------------
221 226 -- REG
222 227 -----------------------------------------------------------------------------
223 228 reg_count_i: lpp_waveform_fifo_arbiter_reg
224 229 GENERIC MAP (
225 230 data_size => nb_data_by_buffer_size,
226 231 data_nb => 4)
227 232 PORT MAP (
228 233 clk => clk,
229 234 rstn => rstn,
230 235 run => run,
231 236 max_count => nb_data_by_buffer,
232 237 enable => count_enable,
233 238 sel => sel,
234 239 data => count,
235 240 data_s => count_s);
236 241
237 242
238 243
239 244
240 245 END ARCHITECTURE;
241 246
242 247
243 248
244 249
245 250
246 251
247 252
248 253
249 254
250 255
251 256
252 257
253 258
254 259
255 260
256 261
257 262
258 263
259 264
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