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MINI_LFR-WFP_MS-0.1.31.pdb :...
pellion -
r451:af05753380a8 (MINI-LFR) WFP_MS-0-1-31 JC
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@@ -428,7 +428,7 BEGIN -- beh
428 pirq_ms => 6,
428 pirq_ms => 6,
429 pirq_wfp => 14,
429 pirq_wfp => 14,
430 hindex => 2,
430 hindex => 2,
431 top_lfr_version => X"00011E") -- aa.bb.cc version
431 top_lfr_version => X"00011F") -- aa.bb.cc version
432 PORT MAP (
432 PORT MAP (
433 clk => clk_25,
433 clk => clk_25,
434 rstn => reset,
434 rstn => reset,
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@@ -75,9 +75,14 ARCHITECTURE beh OF cic_lfr_control IS
75 COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2,
75 COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2,
76
76
77 READ_INT_2_d0,
77 READ_INT_2_d0,
78 READ_INT_2_d1
78 READ_INT_2_d1,
79
80 Wait_step,
81
82 INT_0, INT_1, INT_2
79 );
83 );
80 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
84 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
85 SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE;
81
86
82 SIGNAL nb_data_receipt : INTEGER;
87 SIGNAL nb_data_receipt : INTEGER;
83 SIGNAL current_channel : INTEGER;
88 SIGNAL current_channel : INTEGER;
@@ -86,6 +91,10 ARCHITECTURE beh OF cic_lfr_control IS
86
91
87 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
92 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
88 CONSTANT base_addr_delta : INTEGER := 40;
93 CONSTANT base_addr_delta : INTEGER := 40;
94
95 CONSTANT SEL_OUT : INTEGER := 6;
96
97 signal nb_cycle_wait : integer;
89 BEGIN
98 BEGIN
90
99
91 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
100 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
@@ -178,31 +187,39 BEGIN
178 STATE_CIC_LFR <= INT_0_d0;
187 STATE_CIC_LFR <= INT_0_d0;
179 END IF;
188 END IF;
180
189
181 -------------------------------------------------------------------
190
182 WHEN INT_0_d0 =>
191 WHEN WAIT_step => ---------------------------------------------------
183 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
192 IF nb_cycle_wait > 0 THEN
184 STATE_CIC_LFR <= INT_0_d1;
193 nb_cycle_wait <= nb_cycle_wait -1;
185 r_addr_init <= '1';
194 ELSE
186 r_addr_base <= base_addr_INT(current_channel);
195 STATE_CIC_LFR <= STATE_CIC_LFR_pre;
196 END IF;
187
197
188
198
189 WHEN INT_0_d1 =>
199 WHEN INT_0 => -------------------------------------------------------
190 STATE_CIC_LFR <= INT_0_d2;
200 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
201 r_addr_init <= '1';
202 r_addr_base <= base_addr_INT(current_channel);
203 nb_cycle_wait <= 1;
204 op_ADD_SUBn <= '1';
205 op_valid <= '1';
206 STATE_CIC_LFR <= WAIT_step;
207 STATE_CIC_LFR_pre <= INT_1;
208
209 WHEN INT_1 =>
210 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
191 r_addr_add1 <= '1';
211 r_addr_add1 <= '1';
192
212 nb_cycle_wait <= 3;
193 WHEN INT_0_d2 =>
194 STATE_CIC_LFR <= INT_1_d0;
195 r_addr_add1 <= '1';
196 op_ADD_SUBn <= '1';
213 op_ADD_SUBn <= '1';
197 op_valid <= '1';
214 op_valid <= '1';
198
215 STATE_CIC_LFR <= INT_2;
199 WHEN INT_1_d0 => STATE_CIC_LFR <= INT_1_d1;
200 WHEN INT_1_d1 => STATE_CIC_LFR <= INT_1_d2;
201 WHEN INT_1_d2 => STATE_CIC_LFR <= INT_2_d0;
202
216
203 WHEN INT_2_d0 => STATE_CIC_LFR <= INT_2_d1;
217 WHEN INT_2 =>
204 WHEN INT_2_d1 => STATE_CIC_LFR <= INT_2_d2;
218 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
205 WHEN INT_2_d2 =>
219 r_addr_add1 <= '1';
220 nb_cycle_wait <= 3;
221 op_ADD_SUBn <= '1';
222 op_valid <= '1';
206 IF nb_data_receipt = 256 THEN
223 IF nb_data_receipt = 256 THEN
207 STATE_CIC_LFR <= COMB_0_256_d0;
224 STATE_CIC_LFR <= COMB_0_256_d0;
208 ELSIF (nb_data_receipt mod 16) = 0 THEN
225 ELSIF (nb_data_receipt mod 16) = 0 THEN
@@ -212,7 +229,7 BEGIN
212 STATE_CIC_LFR <= IDLE;
229 STATE_CIC_LFR <= IDLE;
213 ELSE
230 ELSE
214 current_channel <= current_channel +1;
231 current_channel <= current_channel +1;
215 STATE_CIC_LFR <= INT_0_d0;
232 STATE_CIC_LFR <= INT_0;
216 END IF;
233 END IF;
217 END IF;
234 END IF;
218
235
@@ -262,4 +279,3 BEGIN
262 END PROCESS;
279 END PROCESS;
263
280
264 END beh;
281 END beh;
265
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@@ -692,6 +692,8 BEGIN -- beh
692 clk => HCLK,
692 clk => HCLK,
693 rstn => HRESETn,
693 rstn => HRESETn,
694
694
695 run => reg_sp.config_ms_run,
696
695 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
697 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
696 reg0_ready_matrix => reg0_ready_matrix_f0,
698 reg0_ready_matrix => reg0_ready_matrix_f0,
697 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
699 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
@@ -712,6 +714,8 BEGIN -- beh
712 clk => HCLK,
714 clk => HCLK,
713 rstn => HRESETn,
715 rstn => HRESETn,
714
716
717 run => reg_sp.config_ms_run,
718
715 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
719 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
716 reg0_ready_matrix => reg0_ready_matrix_f1,
720 reg0_ready_matrix => reg0_ready_matrix_f1,
717 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
721 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
@@ -732,6 +736,8 BEGIN -- beh
732 clk => HCLK,
736 clk => HCLK,
733 rstn => HRESETn,
737 rstn => HRESETn,
734
738
739 run => reg_sp.config_ms_run,
740
735 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
741 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
736 reg0_ready_matrix => reg0_ready_matrix_f2,
742 reg0_ready_matrix => reg0_ready_matrix_f2,
737 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
743 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
@@ -754,6 +760,8 BEGIN -- beh
754 clk => HCLK,
760 clk => HCLK,
755 rstn => HRESETn,
761 rstn => HRESETn,
756
762
763 run => reg_wp.run,
764
757 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
765 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
758 reg0_ready_matrix => reg_ready_buffer_f(2*I),
766 reg0_ready_matrix => reg_ready_buffer_f(2*I),
759 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
767 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
@@ -773,4 +781,4 BEGIN -- beh
773 END GENERATE all_wfp_pointer;
781 END GENERATE all_wfp_pointer;
774 -----------------------------------------------------------------------------
782 -----------------------------------------------------------------------------
775
783
776 END beh; No newline at end of file
784 END beh;
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@@ -29,6 +29,7 ENTITY lpp_apbreg_ms_pointer IS
29 PORT (
29 PORT (
30 clk : IN STD_LOGIC;
30 clk : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
32 run : IN STD_LOGIC;
32
33
33 -- REG 0
34 -- REG 0
34 reg0_status_ready_matrix : IN STD_LOGIC;
35 reg0_status_ready_matrix : IN STD_LOGIC;
@@ -60,22 +61,28 BEGIN -- beh
60 PROCESS (clk, rstn)
61 PROCESS (clk, rstn)
61 BEGIN -- PROCESS
62 BEGIN -- PROCESS
62 IF rstn = '0' THEN -- asynchronous reset (active low)
63 IF rstn = '0' THEN -- asynchronous reset (active low)
63 current_reg <= '0';
64 current_reg <= '0';
64 reg0_matrix_time <= (OTHERS => '0');
65 reg0_matrix_time <= (OTHERS => '0');
65 reg1_matrix_time <= (OTHERS => '0');
66 reg1_matrix_time <= (OTHERS => '0');
66
67
67 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
68 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
68 IF ready_matrix = '1' THEN
69 IF run = '0' THEN
69 current_reg <= NOT current_reg;
70 current_reg <= '0';
70
71 reg0_matrix_time <= (OTHERS => '0');
71 IF current_reg = '0' THEN
72 reg1_matrix_time <= (OTHERS => '0');
72 reg0_matrix_time <= matrix_time;
73 ELSE
74 IF ready_matrix = '1' THEN
75 current_reg <= NOT current_reg;
76
77 IF current_reg = '0' THEN
78 reg0_matrix_time <= matrix_time;
79 END IF;
80
81 IF current_reg = '1' THEN
82 reg1_matrix_time <= matrix_time;
83 END IF;
84
73 END IF;
85 END IF;
74
75 IF current_reg = '1' THEN
76 reg1_matrix_time <= matrix_time;
77 END IF;
78
79 END IF;
86 END IF;
80
87
81 END IF;
88 END IF;
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@@ -347,7 +347,6 PACKAGE lpp_lfr_pkg IS
347 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
347 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
348 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
348 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
349 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
349 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
350
351 );
350 );
352 END COMPONENT;
351 END COMPONENT;
353
352
@@ -355,6 +354,7 PACKAGE lpp_lfr_pkg IS
355 PORT (
354 PORT (
356 clk : IN STD_LOGIC;
355 clk : IN STD_LOGIC;
357 rstn : IN STD_LOGIC;
356 rstn : IN STD_LOGIC;
357 run : IN STD_LOGIC;
358 reg0_status_ready_matrix : IN STD_LOGIC;
358 reg0_status_ready_matrix : IN STD_LOGIC;
359 reg0_ready_matrix : OUT STD_LOGIC;
359 reg0_ready_matrix : OUT STD_LOGIC;
360 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
360 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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@@ -204,12 +204,17 BEGIN
204 sel <= "0000";
204 sel <= "0000";
205 sel_reg <= '0';
205 sel_reg <= '0';
206 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
206 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
207 IF sel_reg = '0' OR sel_ack = '1' THEN
207 IF run = '0' THEN
208 sel <= sel_s;
208 sel <= "0000";
209 IF sel_s = "0000" THEN
209 sel_reg <= '0';
210 sel_reg <= '0';
210 ELSE
211 ELSE
211 IF sel_reg = '0' OR sel_ack = '1' THEN
212 sel_reg <= '1';
212 sel <= sel_s;
213 IF sel_s = "0000" THEN
214 sel_reg <= '0';
215 ELSE
216 sel_reg <= '1';
217 END IF;
213 END IF;
218 END IF;
214 END IF;
219 END IF;
215 END IF;
220 END IF;
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