diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -428,7 +428,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00011E") -- aa.bb.cc version + top_lfr_version => X"00011F") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => reset, diff --git a/lib/lpp/dsp/cic/cic_lfr_control.vhd b/lib/lpp/dsp/cic/cic_lfr_control.vhd --- a/lib/lpp/dsp/cic/cic_lfr_control.vhd +++ b/lib/lpp/dsp/cic/cic_lfr_control.vhd @@ -75,9 +75,14 @@ ARCHITECTURE beh OF cic_lfr_control IS COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2, READ_INT_2_d0, - READ_INT_2_d1 + READ_INT_2_d1, + + Wait_step, + + INT_0, INT_1, INT_2 ); - SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; + SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; + SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE; SIGNAL nb_data_receipt : INTEGER; SIGNAL current_channel : INTEGER; @@ -86,6 +91,10 @@ ARCHITECTURE beh OF cic_lfr_control IS SIGNAL base_addr_INT : ARRAY_OF_ADDR; CONSTANT base_addr_delta : INTEGER := 40; + + CONSTANT SEL_OUT : INTEGER := 6; + + signal nb_cycle_wait : integer; BEGIN all_channel: FOR I IN 5 DOWNTO 0 GENERATE @@ -178,31 +187,39 @@ BEGIN STATE_CIC_LFR <= INT_0_d0; END IF; - ------------------------------------------------------------------- - WHEN INT_0_d0 => - sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); - STATE_CIC_LFR <= INT_0_d1; - r_addr_init <= '1'; - r_addr_base <= base_addr_INT(current_channel); + + WHEN WAIT_step => --------------------------------------------------- + IF nb_cycle_wait > 0 THEN + nb_cycle_wait <= nb_cycle_wait -1; + ELSE + STATE_CIC_LFR <= STATE_CIC_LFR_pre; + END IF; - WHEN INT_0_d1 => - STATE_CIC_LFR <= INT_0_d2; + WHEN INT_0 => ------------------------------------------------------- + sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); + r_addr_init <= '1'; + r_addr_base <= base_addr_INT(current_channel); + nb_cycle_wait <= 1; + op_ADD_SUBn <= '1'; + op_valid <= '1'; + STATE_CIC_LFR <= WAIT_step; + STATE_CIC_LFR_pre <= INT_1; + + WHEN INT_1 => + sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3)); r_addr_add1 <= '1'; - - WHEN INT_0_d2 => - STATE_CIC_LFR <= INT_1_d0; - r_addr_add1 <= '1'; + nb_cycle_wait <= 3; op_ADD_SUBn <= '1'; op_valid <= '1'; - - WHEN INT_1_d0 => STATE_CIC_LFR <= INT_1_d1; - WHEN INT_1_d1 => STATE_CIC_LFR <= INT_1_d2; - WHEN INT_1_d2 => STATE_CIC_LFR <= INT_2_d0; + STATE_CIC_LFR <= INT_2; - WHEN INT_2_d0 => STATE_CIC_LFR <= INT_2_d1; - WHEN INT_2_d1 => STATE_CIC_LFR <= INT_2_d2; - WHEN INT_2_d2 => + WHEN INT_2 => + sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3)); + r_addr_add1 <= '1'; + nb_cycle_wait <= 3; + op_ADD_SUBn <= '1'; + op_valid <= '1'; IF nb_data_receipt = 256 THEN STATE_CIC_LFR <= COMB_0_256_d0; ELSIF (nb_data_receipt mod 16) = 0 THEN @@ -212,7 +229,7 @@ BEGIN STATE_CIC_LFR <= IDLE; ELSE current_channel <= current_channel +1; - STATE_CIC_LFR <= INT_0_d0; + STATE_CIC_LFR <= INT_0; END IF; END IF; @@ -262,4 +279,3 @@ BEGIN END PROCESS; END beh; - diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -692,6 +692,8 @@ BEGIN -- beh clk => HCLK, rstn => HRESETn, + run => reg_sp.config_ms_run, + reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, reg0_ready_matrix => reg0_ready_matrix_f0, reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0, @@ -712,6 +714,8 @@ BEGIN -- beh clk => HCLK, rstn => HRESETn, + run => reg_sp.config_ms_run, + reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, reg0_ready_matrix => reg0_ready_matrix_f1, reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1, @@ -732,6 +736,8 @@ BEGIN -- beh clk => HCLK, rstn => HRESETn, + run => reg_sp.config_ms_run, + reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, reg0_ready_matrix => reg0_ready_matrix_f2, reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2, @@ -754,6 +760,8 @@ BEGIN -- beh clk => HCLK, rstn => HRESETn, + run => reg_wp.run, + reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), reg0_ready_matrix => reg_ready_buffer_f(2*I), reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), @@ -773,4 +781,4 @@ BEGIN -- beh END GENERATE all_wfp_pointer; ----------------------------------------------------------------------------- -END beh; \ No newline at end of file +END beh; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd @@ -29,6 +29,7 @@ ENTITY lpp_apbreg_ms_pointer IS PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; + run : IN STD_LOGIC; -- REG 0 reg0_status_ready_matrix : IN STD_LOGIC; @@ -60,22 +61,28 @@ BEGIN -- beh PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) - current_reg <= '0'; + current_reg <= '0'; reg0_matrix_time <= (OTHERS => '0'); reg1_matrix_time <= (OTHERS => '0'); ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF ready_matrix = '1' THEN - current_reg <= NOT current_reg; - - IF current_reg = '0' THEN - reg0_matrix_time <= matrix_time; + IF run = '0' THEN + current_reg <= '0'; + reg0_matrix_time <= (OTHERS => '0'); + reg1_matrix_time <= (OTHERS => '0'); + ELSE + IF ready_matrix = '1' THEN + current_reg <= NOT current_reg; + + IF current_reg = '0' THEN + reg0_matrix_time <= matrix_time; + END IF; + + IF current_reg = '1' THEN + reg1_matrix_time <= matrix_time; + END IF; + END IF; - - IF current_reg = '1' THEN - reg1_matrix_time <= matrix_time; - END IF; - END IF; END IF; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -347,7 +347,6 @@ PACKAGE lpp_lfr_pkg IS matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) - ); END COMPONENT; @@ -355,6 +354,7 @@ PACKAGE lpp_lfr_pkg IS PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; + run : IN STD_LOGIC; reg0_status_ready_matrix : IN STD_LOGIC; reg0_ready_matrix : OUT STD_LOGIC; reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd @@ -204,12 +204,17 @@ BEGIN sel <= "0000"; sel_reg <= '0'; ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF sel_reg = '0' OR sel_ack = '1' THEN - sel <= sel_s; - IF sel_s = "0000" THEN - sel_reg <= '0'; - ELSE - sel_reg <= '1'; + IF run = '0' THEN + sel <= "0000"; + sel_reg <= '0'; + ELSE + IF sel_reg = '0' OR sel_ack = '1' THEN + sel <= sel_s; + IF sel_s = "0000" THEN + sel_reg <= '0'; + ELSE + sel_reg <= '1'; + END IF; END IF; END IF; END IF;