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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.cic_pkg.ALL;
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USE lpp.data_type_pkg.ALL;
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ENTITY cic_lfr_control IS
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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--
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data_in_valid : IN STD_LOGIC;
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data_out_16_valid : OUT STD_LOGIC;
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data_out_256_valid : OUT STD_LOGIC;
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-- dataflow
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sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
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--
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op_valid : OUT STD_LOGIC;
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op_ADD_SUBn : OUT STD_LOGIC;
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--
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r_addr_init : OUT STD_LOGIC;
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r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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r_addr_add1 : OUT STD_LOGIC;
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--
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w_en : OUT STD_LOGIC;
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w_addr_init : OUT STD_LOGIC;
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w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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w_addr_add1 : OUT STD_LOGIC
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);
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END cic_lfr_control;
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ARCHITECTURE beh OF cic_lfr_control IS
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TYPE STATE_CIC_LFR_TYPE IS (IDLE,
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INT_0_d0, INT_1_d0, INT_2_d0,
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INT_0_d1, INT_1_d1, INT_2_d1,
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INT_0_d2, INT_1_d2, INT_2_d2,
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WAIT_INT_to_COMB_16,
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COMB_0_16_d0, COMB_1_16_d0, COMB_2_16_d0,
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COMB_0_16_d1, COMB_1_16_d1, COMB_2_16_d1,
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COMB_0_256_d0, COMB_1_256_d0, COMB_2_256_d0,
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COMB_0_256_d1, COMB_1_256_d1, COMB_2_256_d1,
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COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2,
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READ_INT_2_d0,
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READ_INT_2_d1,
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Wait_step,
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INT_0, INT_1, INT_2
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);
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SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
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SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE;
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SIGNAL nb_data_receipt : INTEGER;
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SIGNAL current_channel : INTEGER;
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TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL base_addr_INT : ARRAY_OF_ADDR;
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CONSTANT base_addr_delta : INTEGER := 40;
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CONSTANT SEL_OUT : INTEGER := 6;
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signal nb_cycle_wait : integer;
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BEGIN
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all_channel: FOR I IN 5 DOWNTO 0 GENERATE
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all_bit: FOR J IN 7 DOWNTO 0 GENERATE
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base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
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END GENERATE all_bit;
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END GENERATE all_channel;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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STATE_CIC_LFR <= IDLE;
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--
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data_out_16_valid <= '0';
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data_out_256_valid <= '0';
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--
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sel_sample <= (OTHERS => '0');
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--
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op_valid <= '0';
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op_ADD_SUBn <= '0';
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--
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r_addr_init <= '0';
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r_addr_base <= (OTHERS => '0');
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r_addr_add1 <= '0';
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--
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w_en <= '1';
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w_addr_init <= '0';
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w_addr_base <= (OTHERS => '0');
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w_addr_add1 <= '0';
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--
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nb_data_receipt <= 0;
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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data_out_16_valid <= '0';
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data_out_256_valid <= '0';
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op_valid <= '0';
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op_ADD_SUBn <= '0';
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r_addr_init <= '0';
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r_addr_base <= (OTHERS => '0');
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r_addr_add1 <= '0';
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w_en <= '1';
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w_addr_init <= '0';
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w_addr_base <= (OTHERS => '0');
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w_addr_add1 <= '0';
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IF run = '0' THEN
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STATE_CIC_LFR <= IDLE;
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--
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data_out_16_valid <= '0';
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data_out_256_valid <= '0';
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--
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sel_sample <= (OTHERS => '0');
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--
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op_valid <= '0';
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op_ADD_SUBn <= '0';
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--
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r_addr_init <= '0';
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r_addr_base <= (OTHERS => '0');
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r_addr_add1 <= '0';
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--
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w_en <= '1';
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w_addr_init <= '0';
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w_addr_base <= (OTHERS => '0');
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w_addr_add1 <= '0';
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--
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nb_data_receipt <= 0;
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current_channel <= 0;
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ELSE
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CASE STATE_CIC_LFR IS
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WHEN IDLE =>
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data_out_16_valid <= '0';
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data_out_256_valid <= '0';
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--
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sel_sample <= (OTHERS => '0');
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--
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op_valid <= '0';
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op_ADD_SUBn <= '0';
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--
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r_addr_init <= '0';
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r_addr_base <= (OTHERS => '0');
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r_addr_add1 <= '0';
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--
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w_en <= '1';
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w_addr_init <= '0';
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w_addr_base <= (OTHERS => '0');
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w_addr_add1 <= '0';
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--
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IF data_in_valid = '1' THEN
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nb_data_receipt <= nb_data_receipt+1;
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current_channel <= 0;
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STATE_CIC_LFR <= INT_0_d0;
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END IF;
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WHEN WAIT_step => ---------------------------------------------------
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IF nb_cycle_wait > 0 THEN
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nb_cycle_wait <= nb_cycle_wait -1;
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ELSE
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STATE_CIC_LFR <= STATE_CIC_LFR_pre;
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END IF;
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WHEN INT_0 => -------------------------------------------------------
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sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
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r_addr_init <= '1';
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r_addr_base <= base_addr_INT(current_channel);
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nb_cycle_wait <= 1;
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op_ADD_SUBn <= '1';
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op_valid <= '1';
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STATE_CIC_LFR <= WAIT_step;
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STATE_CIC_LFR_pre <= INT_1;
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WHEN INT_1 =>
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sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
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r_addr_add1 <= '1';
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nb_cycle_wait <= 3;
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op_ADD_SUBn <= '1';
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op_valid <= '1';
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STATE_CIC_LFR <= INT_2;
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WHEN INT_2 =>
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sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
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r_addr_add1 <= '1';
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nb_cycle_wait <= 3;
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op_ADD_SUBn <= '1';
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op_valid <= '1';
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IF nb_data_receipt = 256 THEN
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STATE_CIC_LFR <= COMB_0_256_d0;
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ELSIF (nb_data_receipt mod 16) = 0 THEN
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STATE_CIC_LFR <= WAIT_INT_to_COMB_16;
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ELSE
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IF current_channel = 5 THEN
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STATE_CIC_LFR <= IDLE;
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ELSE
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current_channel <= current_channel +1;
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STATE_CIC_LFR <= INT_0;
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END IF;
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END IF;
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-------------------------------------------------------------------
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WHEN WAIT_INT_to_COMB_16 =>
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STATE_CIC_LFR <= COMB_0_16_d0;
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WHEN COMB_0_16_d0 => STATE_CIC_LFR <= COMB_0_16_d1;
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WHEN COMB_0_16_d1 => STATE_CIC_LFR <= COMB_1_16_d0;
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WHEN COMB_1_16_d0 => STATE_CIC_LFR <= COMB_1_16_d1;
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WHEN COMB_1_16_d1 => STATE_CIC_LFR <= COMB_2_16_d0;
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WHEN COMB_2_16_d0 => STATE_CIC_LFR <= COMB_2_16_d1;
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WHEN COMB_2_16_d1 =>
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IF current_channel = 5 THEN
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STATE_CIC_LFR <= IDLE;
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IF nb_data_receipt = 256 THEN
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nb_data_receipt <= 0;
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END IF;
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ELSE
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current_channel <= current_channel +1;
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STATE_CIC_LFR <= INT_0_d0;
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END IF;
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-------------------------------------------------------------------
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WHEN COMB_0_256_d0 => STATE_CIC_LFR <= COMB_0_256_d1;
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WHEN COMB_0_256_d1 => STATE_CIC_LFR <= COMB_0_256_d2;
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WHEN COMB_0_256_d2 => STATE_CIC_LFR <= COMB_1_256_d0;
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WHEN COMB_1_256_d0 => STATE_CIC_LFR <= COMB_1_256_d1;
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WHEN COMB_1_256_d1 => STATE_CIC_LFR <= COMB_1_256_d2;
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WHEN COMB_1_256_d2 => STATE_CIC_LFR <= COMB_2_256_d0;
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WHEN COMB_2_256_d0 => STATE_CIC_LFR <= COMB_2_256_d1;
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WHEN COMB_2_256_d1 => STATE_CIC_LFR <= COMB_2_256_d2;
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WHEN COMB_2_256_d2 => STATE_CIC_LFR <= READ_INT_2_d0;
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-------------------------------------------------------------------
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WHEN READ_INT_2_d0 => STATE_CIC_LFR <= READ_INT_2_d1;
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WHEN READ_INT_2_d1 => STATE_CIC_LFR <= COMB_0_16_d0;
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WHEN OTHERS => NULL;
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END CASE;
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END IF;
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END IF;
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END PROCESS;
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END beh;
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