@@ -428,7 +428,7 BEGIN -- beh | |||
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428 | 428 | pirq_ms => 6, |
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429 | 429 | pirq_wfp => 14, |
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430 | 430 | hindex => 2, |
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431 |
top_lfr_version => X"00011 |
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431 | top_lfr_version => X"00011F") -- aa.bb.cc version | |
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432 | 432 | PORT MAP ( |
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433 | 433 | clk => clk_25, |
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434 | 434 | rstn => reset, |
@@ -75,9 +75,14 ARCHITECTURE beh OF cic_lfr_control IS | |||
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75 | 75 | COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2, |
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76 | 76 | |
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77 | 77 | READ_INT_2_d0, |
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78 | READ_INT_2_d1 | |
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78 | READ_INT_2_d1, | |
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79 | ||
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80 | Wait_step, | |
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81 | ||
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82 | INT_0, INT_1, INT_2 | |
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79 | 83 | ); |
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80 | SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; | |
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84 | SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; | |
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85 | SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE; | |
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81 | 86 | |
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82 | 87 | SIGNAL nb_data_receipt : INTEGER; |
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83 | 88 | SIGNAL current_channel : INTEGER; |
@@ -86,6 +91,10 ARCHITECTURE beh OF cic_lfr_control IS | |||
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86 | 91 | |
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87 | 92 | SIGNAL base_addr_INT : ARRAY_OF_ADDR; |
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88 | 93 | CONSTANT base_addr_delta : INTEGER := 40; |
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94 | ||
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95 | CONSTANT SEL_OUT : INTEGER := 6; | |
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96 | ||
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97 | signal nb_cycle_wait : integer; | |
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89 | 98 | BEGIN |
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90 | 99 | |
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91 | 100 | all_channel: FOR I IN 5 DOWNTO 0 GENERATE |
@@ -178,31 +187,39 BEGIN | |||
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178 | 187 | STATE_CIC_LFR <= INT_0_d0; |
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179 | 188 | END IF; |
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180 | 189 | |
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181 | ------------------------------------------------------------------- | |
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182 | WHEN INT_0_d0 => | |
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183 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); | |
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184 | STATE_CIC_LFR <= INT_0_d1; | |
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185 | r_addr_init <= '1'; | |
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186 | r_addr_base <= base_addr_INT(current_channel); | |
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190 | ||
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191 | WHEN WAIT_step => --------------------------------------------------- | |
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192 | IF nb_cycle_wait > 0 THEN | |
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193 | nb_cycle_wait <= nb_cycle_wait -1; | |
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194 | ELSE | |
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195 | STATE_CIC_LFR <= STATE_CIC_LFR_pre; | |
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196 | END IF; | |
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187 | 197 | |
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188 | 198 | |
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189 | WHEN INT_0_d1 => | |
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190 | STATE_CIC_LFR <= INT_0_d2; | |
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199 | WHEN INT_0 => ------------------------------------------------------- | |
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200 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); | |
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201 | r_addr_init <= '1'; | |
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202 | r_addr_base <= base_addr_INT(current_channel); | |
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203 | nb_cycle_wait <= 1; | |
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204 | op_ADD_SUBn <= '1'; | |
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205 | op_valid <= '1'; | |
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206 | STATE_CIC_LFR <= WAIT_step; | |
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207 | STATE_CIC_LFR_pre <= INT_1; | |
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208 | ||
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209 | WHEN INT_1 => | |
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210 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3)); | |
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191 | 211 |
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192 | ||
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193 | WHEN INT_0_d2 => | |
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194 | STATE_CIC_LFR <= INT_1_d0; | |
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195 | r_addr_add1 <= '1'; | |
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212 | nb_cycle_wait <= 3; | |
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196 | 213 | op_ADD_SUBn <= '1'; |
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197 | 214 | op_valid <= '1'; |
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198 | ||
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199 | WHEN INT_1_d0 => STATE_CIC_LFR <= INT_1_d1; | |
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200 | WHEN INT_1_d1 => STATE_CIC_LFR <= INT_1_d2; | |
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201 | WHEN INT_1_d2 => STATE_CIC_LFR <= INT_2_d0; | |
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215 | STATE_CIC_LFR <= INT_2; | |
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202 | 216 | |
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203 |
WHEN INT_2 |
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204 | WHEN INT_2_d1 => STATE_CIC_LFR <= INT_2_d2; | |
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205 | WHEN INT_2_d2 => | |
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217 | WHEN INT_2 => | |
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218 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3)); | |
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219 | r_addr_add1 <= '1'; | |
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220 | nb_cycle_wait <= 3; | |
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221 | op_ADD_SUBn <= '1'; | |
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222 | op_valid <= '1'; | |
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206 | 223 | IF nb_data_receipt = 256 THEN |
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207 | 224 | STATE_CIC_LFR <= COMB_0_256_d0; |
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208 | 225 | ELSIF (nb_data_receipt mod 16) = 0 THEN |
@@ -212,7 +229,7 BEGIN | |||
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212 | 229 | STATE_CIC_LFR <= IDLE; |
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213 | 230 | ELSE |
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214 | 231 | current_channel <= current_channel +1; |
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215 |
STATE_CIC_LFR <= INT_0 |
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232 | STATE_CIC_LFR <= INT_0; | |
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216 | 233 | END IF; |
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217 | 234 | END IF; |
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218 | 235 | |
@@ -262,4 +279,3 BEGIN | |||
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262 | 279 | END PROCESS; |
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263 | 280 | |
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264 | 281 | END beh; |
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265 |
@@ -692,6 +692,8 BEGIN -- beh | |||
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692 | 692 | clk => HCLK, |
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693 | 693 | rstn => HRESETn, |
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694 | 694 | |
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695 | run => reg_sp.config_ms_run, | |
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696 | ||
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695 | 697 |
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696 | 698 | reg0_ready_matrix => reg0_ready_matrix_f0, |
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697 | 699 | reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0, |
@@ -712,6 +714,8 BEGIN -- beh | |||
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712 | 714 | clk => HCLK, |
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713 | 715 | rstn => HRESETn, |
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714 | 716 | |
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717 | run => reg_sp.config_ms_run, | |
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718 | ||
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715 | 719 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, |
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716 | 720 | reg0_ready_matrix => reg0_ready_matrix_f1, |
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717 | 721 | reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1, |
@@ -732,6 +736,8 BEGIN -- beh | |||
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732 | 736 | clk => HCLK, |
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733 | 737 | rstn => HRESETn, |
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734 | 738 | |
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739 | run => reg_sp.config_ms_run, | |
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740 | ||
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735 | 741 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, |
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736 | 742 | reg0_ready_matrix => reg0_ready_matrix_f2, |
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737 | 743 | reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2, |
@@ -754,6 +760,8 BEGIN -- beh | |||
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754 | 760 | clk => HCLK, |
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755 | 761 | rstn => HRESETn, |
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756 | 762 | |
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763 | run => reg_wp.run, | |
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764 | ||
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757 | 765 | reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), |
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758 | 766 | reg0_ready_matrix => reg_ready_buffer_f(2*I), |
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759 | 767 | reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), |
@@ -773,4 +781,4 BEGIN -- beh | |||
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773 | 781 | END GENERATE all_wfp_pointer; |
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774 | 782 | ----------------------------------------------------------------------------- |
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775 | 783 | |
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776 | END beh; No newline at end of file | |
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784 | END beh; |
@@ -29,6 +29,7 ENTITY lpp_apbreg_ms_pointer IS | |||
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29 | 29 | PORT ( |
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30 | 30 | clk : IN STD_LOGIC; |
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31 | 31 | rstn : IN STD_LOGIC; |
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32 | run : IN STD_LOGIC; | |
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32 | 33 | |
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33 | 34 | -- REG 0 |
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34 | 35 | reg0_status_ready_matrix : IN STD_LOGIC; |
@@ -60,22 +61,28 BEGIN -- beh | |||
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60 | 61 | PROCESS (clk, rstn) |
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61 | 62 | BEGIN -- PROCESS |
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62 | 63 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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63 | current_reg <= '0'; | |
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64 | current_reg <= '0'; | |
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64 | 65 | reg0_matrix_time <= (OTHERS => '0'); |
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65 | 66 | reg1_matrix_time <= (OTHERS => '0'); |
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66 | 67 | |
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67 | 68 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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68 |
IF r |
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69 |
current_reg <= |
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70 | ||
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71 | IF current_reg = '0' THEN | |
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72 | reg0_matrix_time <= matrix_time; | |
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69 | IF run = '0' THEN | |
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70 | current_reg <= '0'; | |
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71 | reg0_matrix_time <= (OTHERS => '0'); | |
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72 | reg1_matrix_time <= (OTHERS => '0'); | |
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73 | ELSE | |
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74 | IF ready_matrix = '1' THEN | |
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75 | current_reg <= NOT current_reg; | |
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76 | ||
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77 | IF current_reg = '0' THEN | |
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78 | reg0_matrix_time <= matrix_time; | |
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79 | END IF; | |
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80 | ||
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81 | IF current_reg = '1' THEN | |
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82 | reg1_matrix_time <= matrix_time; | |
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83 | END IF; | |
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84 | ||
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73 | 85 |
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74 | ||
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75 | IF current_reg = '1' THEN | |
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76 | reg1_matrix_time <= matrix_time; | |
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77 | END IF; | |
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78 | ||
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79 | 86 | END IF; |
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80 | 87 | |
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81 | 88 | END IF; |
@@ -347,7 +347,6 PACKAGE lpp_lfr_pkg IS | |||
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347 | 347 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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348 | 348 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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349 | 349 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
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350 | ||
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351 | 350 | ); |
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352 | 351 | END COMPONENT; |
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353 | 352 | |
@@ -355,6 +354,7 PACKAGE lpp_lfr_pkg IS | |||
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355 | 354 | PORT ( |
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356 | 355 | clk : IN STD_LOGIC; |
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357 | 356 | rstn : IN STD_LOGIC; |
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357 | run : IN STD_LOGIC; | |
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358 | 358 | reg0_status_ready_matrix : IN STD_LOGIC; |
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359 | 359 | reg0_ready_matrix : OUT STD_LOGIC; |
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360 | 360 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
@@ -204,12 +204,17 BEGIN | |||
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204 | 204 | sel <= "0000"; |
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205 | 205 | sel_reg <= '0'; |
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206 | 206 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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207 |
IF |
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208 |
sel <= |
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209 |
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210 | sel_reg <= '0'; | |
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211 | ELSE | |
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212 |
sel |
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207 | IF run = '0' THEN | |
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208 | sel <= "0000"; | |
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209 | sel_reg <= '0'; | |
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210 | ELSE | |
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211 | IF sel_reg = '0' OR sel_ack = '1' THEN | |
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212 | sel <= sel_s; | |
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213 | IF sel_s = "0000" THEN | |
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214 | sel_reg <= '0'; | |
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215 | ELSE | |
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216 | sel_reg <= '1'; | |
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217 | END IF; | |
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213 | 218 | END IF; |
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214 | 219 | END IF; |
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215 | 220 | END IF; |
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