@@ -428,7 +428,7 BEGIN -- beh | |||||
428 | pirq_ms => 6, |
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428 | pirq_ms => 6, | |
429 | pirq_wfp => 14, |
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429 | pirq_wfp => 14, | |
430 | hindex => 2, |
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430 | hindex => 2, | |
431 |
top_lfr_version => X"00011 |
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431 | top_lfr_version => X"00011F") -- aa.bb.cc version | |
432 | PORT MAP ( |
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432 | PORT MAP ( | |
433 | clk => clk_25, |
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433 | clk => clk_25, | |
434 | rstn => reset, |
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434 | rstn => reset, |
@@ -75,9 +75,14 ARCHITECTURE beh OF cic_lfr_control IS | |||||
75 | COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2, |
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75 | COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2, | |
76 |
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76 | |||
77 | READ_INT_2_d0, |
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77 | READ_INT_2_d0, | |
78 | READ_INT_2_d1 |
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78 | READ_INT_2_d1, | |
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79 | ||||
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80 | Wait_step, | |||
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81 | ||||
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82 | INT_0, INT_1, INT_2 | |||
79 | ); |
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83 | ); | |
80 | SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; |
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84 | SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; | |
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85 | SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE; | |||
81 |
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86 | |||
82 | SIGNAL nb_data_receipt : INTEGER; |
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87 | SIGNAL nb_data_receipt : INTEGER; | |
83 | SIGNAL current_channel : INTEGER; |
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88 | SIGNAL current_channel : INTEGER; | |
@@ -86,6 +91,10 ARCHITECTURE beh OF cic_lfr_control IS | |||||
86 |
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91 | |||
87 | SIGNAL base_addr_INT : ARRAY_OF_ADDR; |
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92 | SIGNAL base_addr_INT : ARRAY_OF_ADDR; | |
88 | CONSTANT base_addr_delta : INTEGER := 40; |
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93 | CONSTANT base_addr_delta : INTEGER := 40; | |
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94 | ||||
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95 | CONSTANT SEL_OUT : INTEGER := 6; | |||
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96 | ||||
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97 | signal nb_cycle_wait : integer; | |||
89 | BEGIN |
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98 | BEGIN | |
90 |
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99 | |||
91 | all_channel: FOR I IN 5 DOWNTO 0 GENERATE |
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100 | all_channel: FOR I IN 5 DOWNTO 0 GENERATE | |
@@ -178,31 +187,39 BEGIN | |||||
178 | STATE_CIC_LFR <= INT_0_d0; |
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187 | STATE_CIC_LFR <= INT_0_d0; | |
179 | END IF; |
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188 | END IF; | |
180 |
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189 | |||
181 | ------------------------------------------------------------------- |
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190 | ||
182 | WHEN INT_0_d0 => |
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191 | WHEN WAIT_step => --------------------------------------------------- | |
183 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); |
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192 | IF nb_cycle_wait > 0 THEN | |
184 | STATE_CIC_LFR <= INT_0_d1; |
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193 | nb_cycle_wait <= nb_cycle_wait -1; | |
185 | r_addr_init <= '1'; |
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194 | ELSE | |
186 | r_addr_base <= base_addr_INT(current_channel); |
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195 | STATE_CIC_LFR <= STATE_CIC_LFR_pre; | |
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196 | END IF; | |||
187 |
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197 | |||
188 |
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198 | |||
189 | WHEN INT_0_d1 => |
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199 | WHEN INT_0 => ------------------------------------------------------- | |
190 | STATE_CIC_LFR <= INT_0_d2; |
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200 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); | |
191 |
r_addr_ |
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201 | r_addr_init <= '1'; | |
192 |
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202 | r_addr_base <= base_addr_INT(current_channel); | ||
193 | WHEN INT_0_d2 => |
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203 | nb_cycle_wait <= 1; | |
194 | STATE_CIC_LFR <= INT_1_d0; |
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|||
195 | r_addr_add1 <= '1'; |
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|||
196 | op_ADD_SUBn <= '1'; |
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204 | op_ADD_SUBn <= '1'; | |
197 | op_valid <= '1'; |
|
205 | op_valid <= '1'; | |
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206 | STATE_CIC_LFR <= WAIT_step; | |||
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207 | STATE_CIC_LFR_pre <= INT_1; | |||
198 |
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208 | ||
199 |
WHEN INT_1 |
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209 | WHEN INT_1 => | |
200 | WHEN INT_1_d1 => STATE_CIC_LFR <= INT_1_d2; |
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210 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3)); | |
201 | WHEN INT_1_d2 => STATE_CIC_LFR <= INT_2_d0; |
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211 | r_addr_add1 <= '1'; | |
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212 | nb_cycle_wait <= 3; | |||
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213 | op_ADD_SUBn <= '1'; | |||
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214 | op_valid <= '1'; | |||
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215 | STATE_CIC_LFR <= INT_2; | |||
202 |
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216 | |||
203 |
WHEN INT_2 |
|
217 | WHEN INT_2 => | |
204 | WHEN INT_2_d1 => STATE_CIC_LFR <= INT_2_d2; |
|
218 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3)); | |
205 | WHEN INT_2_d2 => |
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219 | r_addr_add1 <= '1'; | |
|
220 | nb_cycle_wait <= 3; | |||
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221 | op_ADD_SUBn <= '1'; | |||
|
222 | op_valid <= '1'; | |||
206 | IF nb_data_receipt = 256 THEN |
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223 | IF nb_data_receipt = 256 THEN | |
207 | STATE_CIC_LFR <= COMB_0_256_d0; |
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224 | STATE_CIC_LFR <= COMB_0_256_d0; | |
208 | ELSIF (nb_data_receipt mod 16) = 0 THEN |
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225 | ELSIF (nb_data_receipt mod 16) = 0 THEN | |
@@ -212,7 +229,7 BEGIN | |||||
212 | STATE_CIC_LFR <= IDLE; |
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229 | STATE_CIC_LFR <= IDLE; | |
213 | ELSE |
|
230 | ELSE | |
214 | current_channel <= current_channel +1; |
|
231 | current_channel <= current_channel +1; | |
215 |
STATE_CIC_LFR <= INT_0 |
|
232 | STATE_CIC_LFR <= INT_0; | |
216 | END IF; |
|
233 | END IF; | |
217 | END IF; |
|
234 | END IF; | |
218 |
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235 | |||
@@ -262,4 +279,3 BEGIN | |||||
262 | END PROCESS; |
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279 | END PROCESS; | |
263 |
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280 | |||
264 | END beh; |
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281 | END beh; | |
265 |
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@@ -692,6 +692,8 BEGIN -- beh | |||||
692 | clk => HCLK, |
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692 | clk => HCLK, | |
693 | rstn => HRESETn, |
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693 | rstn => HRESETn, | |
694 |
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694 | |||
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695 | run => reg_sp.config_ms_run, | |||
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696 | ||||
695 |
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697 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, | |
696 | reg0_ready_matrix => reg0_ready_matrix_f0, |
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698 | reg0_ready_matrix => reg0_ready_matrix_f0, | |
697 | reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0, |
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699 | reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0, | |
@@ -712,6 +714,8 BEGIN -- beh | |||||
712 | clk => HCLK, |
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714 | clk => HCLK, | |
713 | rstn => HRESETn, |
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715 | rstn => HRESETn, | |
714 |
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716 | |||
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717 | run => reg_sp.config_ms_run, | |||
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718 | ||||
715 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, |
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719 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, | |
716 | reg0_ready_matrix => reg0_ready_matrix_f1, |
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720 | reg0_ready_matrix => reg0_ready_matrix_f1, | |
717 | reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1, |
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721 | reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1, | |
@@ -732,6 +736,8 BEGIN -- beh | |||||
732 | clk => HCLK, |
|
736 | clk => HCLK, | |
733 | rstn => HRESETn, |
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737 | rstn => HRESETn, | |
734 |
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738 | |||
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739 | run => reg_sp.config_ms_run, | |||
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740 | ||||
735 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, |
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741 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, | |
736 | reg0_ready_matrix => reg0_ready_matrix_f2, |
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742 | reg0_ready_matrix => reg0_ready_matrix_f2, | |
737 | reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2, |
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743 | reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2, | |
@@ -754,6 +760,8 BEGIN -- beh | |||||
754 | clk => HCLK, |
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760 | clk => HCLK, | |
755 | rstn => HRESETn, |
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761 | rstn => HRESETn, | |
756 |
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762 | |||
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763 | run => reg_wp.run, | |||
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764 | ||||
757 | reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), |
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765 | reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), | |
758 | reg0_ready_matrix => reg_ready_buffer_f(2*I), |
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766 | reg0_ready_matrix => reg_ready_buffer_f(2*I), | |
759 | reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), |
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767 | reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), | |
@@ -773,4 +781,4 BEGIN -- beh | |||||
773 | END GENERATE all_wfp_pointer; |
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781 | END GENERATE all_wfp_pointer; | |
774 | ----------------------------------------------------------------------------- |
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782 | ----------------------------------------------------------------------------- | |
775 |
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783 | |||
776 | END beh; No newline at end of file |
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784 | END beh; |
@@ -29,6 +29,7 ENTITY lpp_apbreg_ms_pointer IS | |||||
29 | PORT ( |
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29 | PORT ( | |
30 | clk : IN STD_LOGIC; |
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30 | clk : IN STD_LOGIC; | |
31 | rstn : IN STD_LOGIC; |
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31 | rstn : IN STD_LOGIC; | |
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32 | run : IN STD_LOGIC; | |||
32 |
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33 | |||
33 | -- REG 0 |
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34 | -- REG 0 | |
34 | reg0_status_ready_matrix : IN STD_LOGIC; |
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35 | reg0_status_ready_matrix : IN STD_LOGIC; | |
@@ -65,6 +66,11 BEGIN -- beh | |||||
65 | reg1_matrix_time <= (OTHERS => '0'); |
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66 | reg1_matrix_time <= (OTHERS => '0'); | |
66 |
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67 | |||
67 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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68 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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69 | IF run = '0' THEN | |||
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70 | current_reg <= '0'; | |||
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71 | reg0_matrix_time <= (OTHERS => '0'); | |||
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72 | reg1_matrix_time <= (OTHERS => '0'); | |||
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73 | ELSE | |||
68 | IF ready_matrix = '1' THEN |
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74 | IF ready_matrix = '1' THEN | |
69 | current_reg <= NOT current_reg; |
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75 | current_reg <= NOT current_reg; | |
70 |
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76 | |||
@@ -77,6 +83,7 BEGIN -- beh | |||||
77 | END IF; |
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83 | END IF; | |
78 |
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84 | |||
79 | END IF; |
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85 | END IF; | |
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86 | END IF; | |||
80 |
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87 | |||
81 | END IF; |
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88 | END IF; | |
82 | END PROCESS; |
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89 | END PROCESS; |
@@ -347,7 +347,6 PACKAGE lpp_lfr_pkg IS | |||||
347 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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347 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
348 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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348 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
349 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
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349 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |
350 |
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||||
351 | ); |
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350 | ); | |
352 | END COMPONENT; |
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351 | END COMPONENT; | |
353 |
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352 | |||
@@ -355,6 +354,7 PACKAGE lpp_lfr_pkg IS | |||||
355 | PORT ( |
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354 | PORT ( | |
356 | clk : IN STD_LOGIC; |
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355 | clk : IN STD_LOGIC; | |
357 | rstn : IN STD_LOGIC; |
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356 | rstn : IN STD_LOGIC; | |
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357 | run : IN STD_LOGIC; | |||
358 | reg0_status_ready_matrix : IN STD_LOGIC; |
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358 | reg0_status_ready_matrix : IN STD_LOGIC; | |
359 | reg0_ready_matrix : OUT STD_LOGIC; |
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359 | reg0_ready_matrix : OUT STD_LOGIC; | |
360 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
360 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
@@ -204,6 +204,10 BEGIN | |||||
204 | sel <= "0000"; |
|
204 | sel <= "0000"; | |
205 | sel_reg <= '0'; |
|
205 | sel_reg <= '0'; | |
206 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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206 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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207 | IF run = '0' THEN | |||
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208 | sel <= "0000"; | |||
|
209 | sel_reg <= '0'; | |||
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210 | ELSE | |||
207 | IF sel_reg = '0' OR sel_ack = '1' THEN |
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211 | IF sel_reg = '0' OR sel_ack = '1' THEN | |
208 | sel <= sel_s; |
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212 | sel <= sel_s; | |
209 | IF sel_s = "0000" THEN |
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213 | IF sel_s = "0000" THEN | |
@@ -213,6 +217,7 BEGIN | |||||
213 | END IF; |
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217 | END IF; | |
214 | END IF; |
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218 | END IF; | |
215 | END IF; |
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219 | END IF; | |
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220 | END IF; | |||
216 | END PROCESS; |
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221 | END PROCESS; | |
217 |
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222 | |||
218 | no_sel <= '1' WHEN sel = "0000" ELSE '0'; |
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223 | no_sel <= '1' WHEN sel = "0000" ELSE '0'; |
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