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MINI_LFR-WFP_MS-0.1.30.pdb :...
pellion -
r449:af027809897d (MINI-LFR) WFP_MS-0-1-30 JC
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@@ -428,7 +428,7 BEGIN -- beh
428 pirq_ms => 6,
428 pirq_ms => 6,
429 pirq_wfp => 14,
429 pirq_wfp => 14,
430 hindex => 2,
430 hindex => 2,
431 top_lfr_version => X"00011D") -- aa.bb.cc version
431 top_lfr_version => X"00011E") -- aa.bb.cc version
432 PORT MAP (
432 PORT MAP (
433 clk => clk_25,
433 clk => clk_25,
434 rstn => reset,
434 rstn => reset,
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@@ -58,12 +58,13 BEGIN
58 -----------------------------------------------------------------------------
58 -----------------------------------------------------------------------------
59 -- SEL_SAMPLE
59 -- SEL_SAMPLE
60 -----------------------------------------------------------------------------
60 -----------------------------------------------------------------------------
61 sample_temp(0) <= sample_vector(0) WHEN sel_sample(0) = '0' ELSE sample_vector(1);
61 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
62 sample_temp(1) <= sample_vector(3) WHEN sel_sample(0) = '0' ELSE sample_vector(4);
62 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
63 sample_temp(2) <= sample_temp(0) WHEN sel_sample(1) = '0' ELSE sample_vector(2);
63 sample_temp(1,I) <= data_in(3,I) WHEN sel_sample(0) = '0' ELSE data_in(4,I);
64 sample_temp(3) <= sample_temp(1) WHEN sel_sample(1) = '0' ELSE sample_vector(5);
64 sample_temp(2,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE data_in(2,I);
65 sample <= sample_temp(2) WHEN sel_sample(2) = '0' ELSE sample_temp(3);
65 sample_temp(3,I) <= sample_temp(1,I) WHEN sel_sample(1) = '0' ELSE data_in(5,I);
66
66 sample(I) <= sample_temp(2,I) WHEN sel_sample(2) = '0' ELSE sample_temp(3,I);
67 END GENERATE all_bit;
67
68
68 END beh;
69 END beh;
69
70
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@@ -23,6 +23,8
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
27
26
28
27 LIBRARY lpp;
29 LIBRARY lpp;
28 USE lpp.cic_pkg.ALL;
30 USE lpp.cic_pkg.ALL;
@@ -47,6 +49,7 ENTITY cic_lfr_control IS
47 r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
49 r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
48 r_addr_add1 : OUT STD_LOGIC;
50 r_addr_add1 : OUT STD_LOGIC;
49 --
51 --
52 w_en : OUT STD_LOGIC;
50 w_addr_init : OUT STD_LOGIC;
53 w_addr_init : OUT STD_LOGIC;
51 w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
54 w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
52 w_addr_add1 : OUT STD_LOGIC
55 w_addr_add1 : OUT STD_LOGIC
@@ -56,13 +59,41 END cic_lfr_control;
56
59
57 ARCHITECTURE beh OF cic_lfr_control IS
60 ARCHITECTURE beh OF cic_lfr_control IS
58
61
59 TYPE STATE_CIC_LFR_TYPE IS (IDLE,INT_0, INT_1, INT_2);
62 TYPE STATE_CIC_LFR_TYPE IS (IDLE,
63
64 INT_0_d0, INT_1_d0, INT_2_d0,
65 INT_0_d1, INT_1_d1, INT_2_d1,
66 INT_0_d2, INT_1_d2, INT_2_d2,
67
68 WAIT_INT_to_COMB_16,
69
70 COMB_0_16_d0, COMB_1_16_d0, COMB_2_16_d0,
71 COMB_0_16_d1, COMB_1_16_d1, COMB_2_16_d1,
72
73 COMB_0_256_d0, COMB_1_256_d0, COMB_2_256_d0,
74 COMB_0_256_d1, COMB_1_256_d1, COMB_2_256_d1,
75 COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2,
76
77 READ_INT_2_d0,
78 READ_INT_2_d1
79 );
60 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
80 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
61
81
62 SIGNAL nb_data_receipt : INTEGER;
82 SIGNAL nb_data_receipt : INTEGER;
83 SIGNAL current_channel : INTEGER;
84
85 TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
63
86
87 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
88 CONSTANT base_addr_delta : INTEGER := 40;
64 BEGIN
89 BEGIN
65
90
91 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
92 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
93 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
94 END GENERATE all_bit;
95 END GENERATE all_channel;
96
66 PROCESS (clk, rstn)
97 PROCESS (clk, rstn)
67 BEGIN -- PROCESS
98 BEGIN -- PROCESS
68 IF rstn = '0' THEN -- asynchronous reset (active low)
99 IF rstn = '0' THEN -- asynchronous reset (active low)
@@ -80,12 +111,25 BEGIN
80 r_addr_base <= (OTHERS => '0');
111 r_addr_base <= (OTHERS => '0');
81 r_addr_add1 <= '0';
112 r_addr_add1 <= '0';
82 --
113 --
114 w_en <= '1';
83 w_addr_init <= '0';
115 w_addr_init <= '0';
84 w_addr_base <= (OTHERS => '0');
116 w_addr_base <= (OTHERS => '0');
85 w_addr_add1 <= '0';
117 w_addr_add1 <= '0';
86 --
118 --
87 nb_data_receipt <= 0;
119 nb_data_receipt <= 0;
88 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
120 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
121 data_out_16_valid <= '0';
122 data_out_256_valid <= '0';
123 op_valid <= '0';
124 op_ADD_SUBn <= '0';
125 r_addr_init <= '0';
126 r_addr_base <= (OTHERS => '0');
127 r_addr_add1 <= '0';
128 w_en <= '1';
129 w_addr_init <= '0';
130 w_addr_base <= (OTHERS => '0');
131 w_addr_add1 <= '0';
132
89 IF run = '0' THEN
133 IF run = '0' THEN
90 STATE_CIC_LFR <= IDLE;
134 STATE_CIC_LFR <= IDLE;
91 --
135 --
@@ -101,11 +145,13 BEGIN
101 r_addr_base <= (OTHERS => '0');
145 r_addr_base <= (OTHERS => '0');
102 r_addr_add1 <= '0';
146 r_addr_add1 <= '0';
103 --
147 --
148 w_en <= '1';
104 w_addr_init <= '0';
149 w_addr_init <= '0';
105 w_addr_base <= (OTHERS => '0');
150 w_addr_base <= (OTHERS => '0');
106 w_addr_add1 <= '0';
151 w_addr_add1 <= '0';
107 --
152 --
108 nb_data_receipt <= 0;
153 nb_data_receipt <= 0;
154 current_channel <= 0;
109 ELSE
155 ELSE
110 CASE STATE_CIC_LFR IS
156 CASE STATE_CIC_LFR IS
111 WHEN IDLE =>
157 WHEN IDLE =>
@@ -121,14 +167,93 BEGIN
121 r_addr_base <= (OTHERS => '0');
167 r_addr_base <= (OTHERS => '0');
122 r_addr_add1 <= '0';
168 r_addr_add1 <= '0';
123 --
169 --
170 w_en <= '1';
124 w_addr_init <= '0';
171 w_addr_init <= '0';
125 w_addr_base <= (OTHERS => '0');
172 w_addr_base <= (OTHERS => '0');
126 w_addr_add1 <= '0';
173 w_addr_add1 <= '0';
174 --
127 IF data_in_valid = '1' THEN
175 IF data_in_valid = '1' THEN
128 nb_data_receipt <= 0;
176 nb_data_receipt <= nb_data_receipt+1;
129 STATE_CIC_LFR <= INT_0;
177 current_channel <= 0;
178 STATE_CIC_LFR <= INT_0_d0;
130 END IF;
179 END IF;
131 WHEN INT_0 =>
180
181 -------------------------------------------------------------------
182 WHEN INT_0_d0 =>
183 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
184 STATE_CIC_LFR <= INT_0_d1;
185 r_addr_init <= '1';
186 r_addr_base <= base_addr_INT(current_channel);
187
188
189 WHEN INT_0_d1 =>
190 STATE_CIC_LFR <= INT_0_d2;
191 r_addr_add1 <= '1';
192
193 WHEN INT_0_d2 =>
194 STATE_CIC_LFR <= INT_1_d0;
195 r_addr_add1 <= '1';
196 op_ADD_SUBn <= '1';
197 op_valid <= '1';
198
199 WHEN INT_1_d0 => STATE_CIC_LFR <= INT_1_d1;
200 WHEN INT_1_d1 => STATE_CIC_LFR <= INT_1_d2;
201 WHEN INT_1_d2 => STATE_CIC_LFR <= INT_2_d0;
202
203 WHEN INT_2_d0 => STATE_CIC_LFR <= INT_2_d1;
204 WHEN INT_2_d1 => STATE_CIC_LFR <= INT_2_d2;
205 WHEN INT_2_d2 =>
206 IF nb_data_receipt = 256 THEN
207 STATE_CIC_LFR <= COMB_0_256_d0;
208 ELSIF (nb_data_receipt mod 16) = 0 THEN
209 STATE_CIC_LFR <= WAIT_INT_to_COMB_16;
210 ELSE
211 IF current_channel = 5 THEN
212 STATE_CIC_LFR <= IDLE;
213 ELSE
214 current_channel <= current_channel +1;
215 STATE_CIC_LFR <= INT_0_d0;
216 END IF;
217 END IF;
218
219 -------------------------------------------------------------------
220 WHEN WAIT_INT_to_COMB_16 =>
221 STATE_CIC_LFR <= COMB_0_16_d0;
222
223 WHEN COMB_0_16_d0 => STATE_CIC_LFR <= COMB_0_16_d1;
224 WHEN COMB_0_16_d1 => STATE_CIC_LFR <= COMB_1_16_d0;
225
226 WHEN COMB_1_16_d0 => STATE_CIC_LFR <= COMB_1_16_d1;
227 WHEN COMB_1_16_d1 => STATE_CIC_LFR <= COMB_2_16_d0;
228
229 WHEN COMB_2_16_d0 => STATE_CIC_LFR <= COMB_2_16_d1;
230 WHEN COMB_2_16_d1 =>
231 IF current_channel = 5 THEN
232 STATE_CIC_LFR <= IDLE;
233 IF nb_data_receipt = 256 THEN
234 nb_data_receipt <= 0;
235 END IF;
236 ELSE
237 current_channel <= current_channel +1;
238 STATE_CIC_LFR <= INT_0_d0;
239 END IF;
240
241 -------------------------------------------------------------------
242 WHEN COMB_0_256_d0 => STATE_CIC_LFR <= COMB_0_256_d1;
243 WHEN COMB_0_256_d1 => STATE_CIC_LFR <= COMB_0_256_d2;
244 WHEN COMB_0_256_d2 => STATE_CIC_LFR <= COMB_1_256_d0;
245
246 WHEN COMB_1_256_d0 => STATE_CIC_LFR <= COMB_1_256_d1;
247 WHEN COMB_1_256_d1 => STATE_CIC_LFR <= COMB_1_256_d2;
248 WHEN COMB_1_256_d2 => STATE_CIC_LFR <= COMB_2_256_d0;
249
250 WHEN COMB_2_256_d0 => STATE_CIC_LFR <= COMB_2_256_d1;
251 WHEN COMB_2_256_d1 => STATE_CIC_LFR <= COMB_2_256_d2;
252 WHEN COMB_2_256_d2 => STATE_CIC_LFR <= READ_INT_2_d0;
253
254 -------------------------------------------------------------------
255 WHEN READ_INT_2_d0 => STATE_CIC_LFR <= READ_INT_2_d1;
256 WHEN READ_INT_2_d1 => STATE_CIC_LFR <= COMB_0_16_d0;
132
257
133 WHEN OTHERS => NULL;
258 WHEN OTHERS => NULL;
134 END CASE;
259 END CASE;
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@@ -86,4 +86,26 PACKAGE cic_pkg IS
86 END COMPONENT;
86 END COMPONENT;
87 -----------------------------------------------------------------------------
87 -----------------------------------------------------------------------------
88
88
89
90 -----------------------------------------------------------------------------
91 COMPONENT cic_lfr_control
92 PORT (
93 clk : IN STD_LOGIC;
94 rstn : IN STD_LOGIC;
95 run : IN STD_LOGIC;
96 data_in_valid : IN STD_LOGIC;
97 data_out_16_valid : OUT STD_LOGIC;
98 data_out_256_valid : OUT STD_LOGIC;
99 sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
100 op_valid : OUT STD_LOGIC;
101 op_ADD_SUBn : OUT STD_LOGIC;
102 r_addr_init : OUT STD_LOGIC;
103 r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
104 r_addr_add1 : OUT STD_LOGIC;
105 w_en : OUT STD_LOGIC;
106 w_addr_init : OUT STD_LOGIC;
107 w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
108 w_addr_add1 : OUT STD_LOGIC);
109 END COMPONENT;
110 -----------------------------------------------------------------------------
89 END cic_pkg;
111 END cic_pkg;
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@@ -4,3 +4,4 cic_integrator.vhd
4 cic_downsampler.vhd
4 cic_downsampler.vhd
5 cic_comb.vhd
5 cic_comb.vhd
6 cic_lfr.vhd
6 cic_lfr.vhd
7 cic_lfr_control.vhd
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@@ -524,25 +524,25 BEGIN -- beh
524 --34
524 --34
525 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
525 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
526 --35
526 --35
527 WHEN "101000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0);
527 WHEN "101000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); --reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0);
528 WHEN "101001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16);
528 WHEN "101001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); --reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16);
529 WHEN "101010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+15 DOWNTO 48*1);
529 WHEN "101010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
530 WHEN "101011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+47 DOWNTO 48*1+16);
530 WHEN "101011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
531
531
532 WHEN "101100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+15 DOWNTO 48*2);
532 WHEN "101100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
533 WHEN "101101" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+47 DOWNTO 48*2+16);
533 WHEN "101101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
534 WHEN "101110" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+15 DOWNTO 48*3);
534 WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
535 WHEN "101111" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+47 DOWNTO 48*3+16);
535 WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
536
536
537 WHEN "110000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+15 DOWNTO 48*4);
537 WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
538 WHEN "110001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+47 DOWNTO 48*4+16);
538 WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
539 WHEN "110010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+15 DOWNTO 48*5);
539 WHEN "110010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
540 WHEN "110011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+47 DOWNTO 48*5+16);
540 WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
541
541
542 WHEN "110100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6);
542 WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
543 WHEN "110101" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+47 DOWNTO 48*6+16);
543 WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
544 WHEN "110110" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+15 DOWNTO 48*7);
544 WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
545 WHEN "110111" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+47 DOWNTO 48*7+16);
545 WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
546
546
547 WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
547 WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
548
548
@@ -773,4 +773,4 BEGIN -- beh
773 END GENERATE all_wfp_pointer;
773 END GENERATE all_wfp_pointer;
774 -----------------------------------------------------------------------------
774 -----------------------------------------------------------------------------
775
775
776 END beh;
776 END beh; No newline at end of file
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