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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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PACKAGE cic_pkg IS
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-----------------------------------------------------------------------------
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COMPONENT cic
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GENERIC (
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D_delay_number : INTEGER;
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S_stage_number : INTEGER;
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R_downsampling_decimation_factor : INTEGER;
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b_data_size : INTEGER;
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b_grow : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
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data_in_valid : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
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data_out_valid : OUT STD_LOGIC);
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END COMPONENT;
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-----------------------------------------------------------------------------
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COMPONENT cic_integrator
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GENERIC (
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b_data_size : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
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data_in_valid : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
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data_out_valid : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT cic_downsampler
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GENERIC (
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R_downsampling_decimation_factor : INTEGER;
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b_data_size : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
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data_in_valid : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
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data_out_valid : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT cic_comb
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GENERIC (
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b_data_size : INTEGER;
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D_delay_number : INTEGER);
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PORT (
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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run : IN STD_LOGIC;
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data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
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data_in_valid : IN STD_LOGIC;
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data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
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data_out_valid : OUT STD_LOGIC);
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END COMPONENT;
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-----------------------------------------------------------------------------
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END cic_pkg;
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