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MINI_LFR-WFP_MS-0.1.29.pdb :...
pellion -
r447:0383b34f8a01 (MINI-LFR) WFP_MS-0-1-29 JC
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@@ -428,7 +428,7 BEGIN -- beh
428 pirq_ms => 6,
428 pirq_ms => 6,
429 pirq_wfp => 14,
429 pirq_wfp => 14,
430 hindex => 2,
430 hindex => 2,
431 top_lfr_version => X"00011C") -- aa.bb.cc version
431 top_lfr_version => X"00011D") -- aa.bb.cc version
432 PORT MAP (
432 PORT MAP (
433 clk => clk_25,
433 clk => clk_25,
434 rstn => reset,
434 rstn => reset,
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@@ -58,6 +58,8 ARCHITECTURE beh OF cic_lfr_control IS
58
58
59 TYPE STATE_CIC_LFR_TYPE IS (IDLE,INT_0, INT_1, INT_2);
59 TYPE STATE_CIC_LFR_TYPE IS (IDLE,INT_0, INT_1, INT_2);
60 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
60 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
61
62 SIGNAL nb_data_receipt : INTEGER;
61
63
62 BEGIN
64 BEGIN
63
65
@@ -81,6 +83,8 BEGIN
81 w_addr_init <= '0';
83 w_addr_init <= '0';
82 w_addr_base <= (OTHERS => '0');
84 w_addr_base <= (OTHERS => '0');
83 w_addr_add1 <= '0';
85 w_addr_add1 <= '0';
86 --
87 nb_data_receipt <= 0;
84 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
88 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
85 IF run = '0' THEN
89 IF run = '0' THEN
86 STATE_CIC_LFR <= IDLE;
90 STATE_CIC_LFR <= IDLE;
@@ -100,6 +104,8 BEGIN
100 w_addr_init <= '0';
104 w_addr_init <= '0';
101 w_addr_base <= (OTHERS => '0');
105 w_addr_base <= (OTHERS => '0');
102 w_addr_add1 <= '0';
106 w_addr_add1 <= '0';
107 --
108 nb_data_receipt <= 0;
103 ELSE
109 ELSE
104 CASE STATE_CIC_LFR IS
110 CASE STATE_CIC_LFR IS
105 WHEN IDLE =>
111 WHEN IDLE =>
@@ -118,6 +124,12 BEGIN
118 w_addr_init <= '0';
124 w_addr_init <= '0';
119 w_addr_base <= (OTHERS => '0');
125 w_addr_base <= (OTHERS => '0');
120 w_addr_add1 <= '0';
126 w_addr_add1 <= '0';
127 IF data_in_valid = '1' THEN
128 nb_data_receipt <= 0;
129 STATE_CIC_LFR <= INT_0;
130 END IF;
131 WHEN INT_0 =>
132
121 WHEN OTHERS => NULL;
133 WHEN OTHERS => NULL;
122 END CASE;
134 END CASE;
123 END IF;
135 END IF;
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@@ -608,7 +608,7 BEGIN -- beh
608 --26
608 --26
609 WHEN "011111" =>
609 WHEN "011111" =>
610 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
610 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
611 reg_wp.status_ready_buffer_f(I) <= ((NOT apbi.pwdata(I) ) AND reg_wp.status_ready_buffer_f(I) ) OR reg_ready_buffer_f(I);
611 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
612 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
612 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
613 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
613 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
614 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
614 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
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