# HG changeset patch # User pellion # Date 2014-11-03 16:45:26 # Node ID af027809897de976c7ff252b17101160c80cbfc5 # Parent 997e68102175eeabda54e8f48c3dd3042f2bbaee MINI_LFR-WFP_MS-0.1.30.pdb : -> update lpp_lfr_apb_reg (wfp time) diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -428,7 +428,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00011D") -- aa.bb.cc version + top_lfr_version => X"00011E") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => reset, diff --git a/lib/lpp/dsp/cic/cic_lfr.vhd b/lib/lpp/dsp/cic/cic_lfr.vhd --- a/lib/lpp/dsp/cic/cic_lfr.vhd +++ b/lib/lpp/dsp/cic/cic_lfr.vhd @@ -58,12 +58,13 @@ BEGIN ----------------------------------------------------------------------------- -- SEL_SAMPLE ----------------------------------------------------------------------------- - sample_temp(0) <= sample_vector(0) WHEN sel_sample(0) = '0' ELSE sample_vector(1); - sample_temp(1) <= sample_vector(3) WHEN sel_sample(0) = '0' ELSE sample_vector(4); - sample_temp(2) <= sample_temp(0) WHEN sel_sample(1) = '0' ELSE sample_vector(2); - sample_temp(3) <= sample_temp(1) WHEN sel_sample(1) = '0' ELSE sample_vector(5); - sample <= sample_temp(2) WHEN sel_sample(2) = '0' ELSE sample_temp(3); - + all_bit: FOR I IN 15 DOWNTO 0 GENERATE + sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I); + sample_temp(1,I) <= data_in(3,I) WHEN sel_sample(0) = '0' ELSE data_in(4,I); + sample_temp(2,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE data_in(2,I); + sample_temp(3,I) <= sample_temp(1,I) WHEN sel_sample(1) = '0' ELSE data_in(5,I); + sample(I) <= sample_temp(2,I) WHEN sel_sample(2) = '0' ELSE sample_temp(3,I); + END GENERATE all_bit; END beh; diff --git a/lib/lpp/dsp/cic/cic_lfr_control.vhd b/lib/lpp/dsp/cic/cic_lfr_control.vhd --- a/lib/lpp/dsp/cic/cic_lfr_control.vhd +++ b/lib/lpp/dsp/cic/cic_lfr_control.vhd @@ -23,6 +23,8 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + LIBRARY lpp; USE lpp.cic_pkg.ALL; @@ -47,6 +49,7 @@ ENTITY cic_lfr_control IS r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); r_addr_add1 : OUT STD_LOGIC; -- + w_en : OUT STD_LOGIC; w_addr_init : OUT STD_LOGIC; w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); w_addr_add1 : OUT STD_LOGIC @@ -56,13 +59,41 @@ END cic_lfr_control; ARCHITECTURE beh OF cic_lfr_control IS - TYPE STATE_CIC_LFR_TYPE IS (IDLE,INT_0, INT_1, INT_2); + TYPE STATE_CIC_LFR_TYPE IS (IDLE, + + INT_0_d0, INT_1_d0, INT_2_d0, + INT_0_d1, INT_1_d1, INT_2_d1, + INT_0_d2, INT_1_d2, INT_2_d2, + + WAIT_INT_to_COMB_16, + + COMB_0_16_d0, COMB_1_16_d0, COMB_2_16_d0, + COMB_0_16_d1, COMB_1_16_d1, COMB_2_16_d1, + + COMB_0_256_d0, COMB_1_256_d0, COMB_2_256_d0, + COMB_0_256_d1, COMB_1_256_d1, COMB_2_256_d1, + COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2, + + READ_INT_2_d0, + READ_INT_2_d1 + ); SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; SIGNAL nb_data_receipt : INTEGER; + SIGNAL current_channel : INTEGER; + + TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL base_addr_INT : ARRAY_OF_ADDR; + CONSTANT base_addr_delta : INTEGER := 40; BEGIN + all_channel: FOR I IN 5 DOWNTO 0 GENERATE + all_bit: FOR J IN 7 DOWNTO 0 GENERATE + base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0'; + END GENERATE all_bit; + END GENERATE all_channel; + PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) @@ -80,12 +111,25 @@ BEGIN r_addr_base <= (OTHERS => '0'); r_addr_add1 <= '0'; -- + w_en <= '1'; w_addr_init <= '0'; w_addr_base <= (OTHERS => '0'); w_addr_add1 <= '0'; -- nb_data_receipt <= 0; ELSIF clk'event AND clk = '1' THEN -- rising clock edge + data_out_16_valid <= '0'; + data_out_256_valid <= '0'; + op_valid <= '0'; + op_ADD_SUBn <= '0'; + r_addr_init <= '0'; + r_addr_base <= (OTHERS => '0'); + r_addr_add1 <= '0'; + w_en <= '1'; + w_addr_init <= '0'; + w_addr_base <= (OTHERS => '0'); + w_addr_add1 <= '0'; + IF run = '0' THEN STATE_CIC_LFR <= IDLE; -- @@ -101,11 +145,13 @@ BEGIN r_addr_base <= (OTHERS => '0'); r_addr_add1 <= '0'; -- + w_en <= '1'; w_addr_init <= '0'; w_addr_base <= (OTHERS => '0'); w_addr_add1 <= '0'; -- nb_data_receipt <= 0; + current_channel <= 0; ELSE CASE STATE_CIC_LFR IS WHEN IDLE => @@ -121,14 +167,93 @@ BEGIN r_addr_base <= (OTHERS => '0'); r_addr_add1 <= '0'; -- + w_en <= '1'; w_addr_init <= '0'; w_addr_base <= (OTHERS => '0'); w_addr_add1 <= '0'; + -- IF data_in_valid = '1' THEN - nb_data_receipt <= 0; - STATE_CIC_LFR <= INT_0; + nb_data_receipt <= nb_data_receipt+1; + current_channel <= 0; + STATE_CIC_LFR <= INT_0_d0; END IF; - WHEN INT_0 => + + ------------------------------------------------------------------- + WHEN INT_0_d0 => + sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); + STATE_CIC_LFR <= INT_0_d1; + r_addr_init <= '1'; + r_addr_base <= base_addr_INT(current_channel); + + + WHEN INT_0_d1 => + STATE_CIC_LFR <= INT_0_d2; + r_addr_add1 <= '1'; + + WHEN INT_0_d2 => + STATE_CIC_LFR <= INT_1_d0; + r_addr_add1 <= '1'; + op_ADD_SUBn <= '1'; + op_valid <= '1'; + + WHEN INT_1_d0 => STATE_CIC_LFR <= INT_1_d1; + WHEN INT_1_d1 => STATE_CIC_LFR <= INT_1_d2; + WHEN INT_1_d2 => STATE_CIC_LFR <= INT_2_d0; + + WHEN INT_2_d0 => STATE_CIC_LFR <= INT_2_d1; + WHEN INT_2_d1 => STATE_CIC_LFR <= INT_2_d2; + WHEN INT_2_d2 => + IF nb_data_receipt = 256 THEN + STATE_CIC_LFR <= COMB_0_256_d0; + ELSIF (nb_data_receipt mod 16) = 0 THEN + STATE_CIC_LFR <= WAIT_INT_to_COMB_16; + ELSE + IF current_channel = 5 THEN + STATE_CIC_LFR <= IDLE; + ELSE + current_channel <= current_channel +1; + STATE_CIC_LFR <= INT_0_d0; + END IF; + END IF; + + ------------------------------------------------------------------- + WHEN WAIT_INT_to_COMB_16 => + STATE_CIC_LFR <= COMB_0_16_d0; + + WHEN COMB_0_16_d0 => STATE_CIC_LFR <= COMB_0_16_d1; + WHEN COMB_0_16_d1 => STATE_CIC_LFR <= COMB_1_16_d0; + + WHEN COMB_1_16_d0 => STATE_CIC_LFR <= COMB_1_16_d1; + WHEN COMB_1_16_d1 => STATE_CIC_LFR <= COMB_2_16_d0; + + WHEN COMB_2_16_d0 => STATE_CIC_LFR <= COMB_2_16_d1; + WHEN COMB_2_16_d1 => + IF current_channel = 5 THEN + STATE_CIC_LFR <= IDLE; + IF nb_data_receipt = 256 THEN + nb_data_receipt <= 0; + END IF; + ELSE + current_channel <= current_channel +1; + STATE_CIC_LFR <= INT_0_d0; + END IF; + + ------------------------------------------------------------------- + WHEN COMB_0_256_d0 => STATE_CIC_LFR <= COMB_0_256_d1; + WHEN COMB_0_256_d1 => STATE_CIC_LFR <= COMB_0_256_d2; + WHEN COMB_0_256_d2 => STATE_CIC_LFR <= COMB_1_256_d0; + + WHEN COMB_1_256_d0 => STATE_CIC_LFR <= COMB_1_256_d1; + WHEN COMB_1_256_d1 => STATE_CIC_LFR <= COMB_1_256_d2; + WHEN COMB_1_256_d2 => STATE_CIC_LFR <= COMB_2_256_d0; + + WHEN COMB_2_256_d0 => STATE_CIC_LFR <= COMB_2_256_d1; + WHEN COMB_2_256_d1 => STATE_CIC_LFR <= COMB_2_256_d2; + WHEN COMB_2_256_d2 => STATE_CIC_LFR <= READ_INT_2_d0; + + ------------------------------------------------------------------- + WHEN READ_INT_2_d0 => STATE_CIC_LFR <= READ_INT_2_d1; + WHEN READ_INT_2_d1 => STATE_CIC_LFR <= COMB_0_16_d0; WHEN OTHERS => NULL; END CASE; diff --git a/lib/lpp/dsp/cic/cic_pkg.vhd b/lib/lpp/dsp/cic/cic_pkg.vhd --- a/lib/lpp/dsp/cic/cic_pkg.vhd +++ b/lib/lpp/dsp/cic/cic_pkg.vhd @@ -86,4 +86,26 @@ PACKAGE cic_pkg IS END COMPONENT; ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + COMPONENT cic_lfr_control + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + data_in_valid : IN STD_LOGIC; + data_out_16_valid : OUT STD_LOGIC; + data_out_256_valid : OUT STD_LOGIC; + sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + op_valid : OUT STD_LOGIC; + op_ADD_SUBn : OUT STD_LOGIC; + r_addr_init : OUT STD_LOGIC; + r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + r_addr_add1 : OUT STD_LOGIC; + w_en : OUT STD_LOGIC; + w_addr_init : OUT STD_LOGIC; + w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + w_addr_add1 : OUT STD_LOGIC); + END COMPONENT; + ----------------------------------------------------------------------------- END cic_pkg; diff --git a/lib/lpp/dsp/cic/vhdlsyn.txt b/lib/lpp/dsp/cic/vhdlsyn.txt --- a/lib/lpp/dsp/cic/vhdlsyn.txt +++ b/lib/lpp/dsp/cic/vhdlsyn.txt @@ -4,3 +4,4 @@ cic_integrator.vhd cic_downsampler.vhd cic_comb.vhd cic_lfr.vhd +cic_lfr_control.vhd diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -524,25 +524,25 @@ BEGIN -- beh --34 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date; --35 - WHEN "101000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0); - WHEN "101001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16); - WHEN "101010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+15 DOWNTO 48*1); - WHEN "101011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+47 DOWNTO 48*1+16); + WHEN "101000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); --reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0); + WHEN "101001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); --reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16); + WHEN "101010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1); + WHEN "101011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32); - WHEN "101100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+15 DOWNTO 48*2); - WHEN "101101" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+47 DOWNTO 48*2+16); - WHEN "101110" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+15 DOWNTO 48*3); - WHEN "101111" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+47 DOWNTO 48*3+16); + WHEN "101100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2); + WHEN "101101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32); + WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3); + WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32); - WHEN "110000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+15 DOWNTO 48*4); - WHEN "110001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+47 DOWNTO 48*4+16); - WHEN "110010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+15 DOWNTO 48*5); - WHEN "110011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+47 DOWNTO 48*5+16); + WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4); + WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32); + WHEN "110010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5); + WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32); - WHEN "110100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6); - WHEN "110101" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+47 DOWNTO 48*6+16); - WHEN "110110" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+15 DOWNTO 48*7); - WHEN "110111" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+47 DOWNTO 48*7+16); + WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6); + WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32); + WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7); + WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32); WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; @@ -773,4 +773,4 @@ BEGIN -- beh END GENERATE all_wfp_pointer; ----------------------------------------------------------------------------- -END beh; +END beh; \ No newline at end of file