HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r90:a9b0b725b939

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lib/lpp/dsp/lpp_fft/APB_FFT.vhd +1 -3

             signal start   : std_logic;
             signal load    : std_logic;
             signal rdy     : std_logic;
-            signal zero    : std_logic;
             begin
                 APB : ApbDriver
                     generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
-                    port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,zero,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
+                    port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
                 Extremum : Flag_Extremum
                     port map(clk,start,rst,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
             start <= not rst;
-            zero  <= '0';
             DataIn_re <= DataIn(31 downto 16);
             DataIn_im <= DataIn(15 downto 0);

lib/lpp/lpp_cna/lpp_cna.vhd +2 -4

             library lpp;
             use lpp.lpp_amba.all;
             --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
             package lpp_cna is
                 port(
                     clock       : in std_logic;
                     rst         : in std_logic;
-                    flag_nw     : in std_logic;
+                    enable      : in std_logic;
-                    bp          : in std_logic;
                     Data_C      : in std_logic_vector(15 downto 0);
                     SYNC        : out std_logic;
                     SCLK        : out std_logic;
-                    Rz          : out std_logic;
                     flag_sd     : out std_logic;
                     Data        : out std_logic
                     );

lib/lpp/lpp_matrix/APB_Matrix.vhd +2 -2

             --    Read : out std_logic;
             --    Take : out std_logic;
             --    Valid : out std_logic;
-            --    Received : out std_logic;
+            Res       : out std_logic_vector(Result_SZ-1 downto 0);
             --    Conjugate : out std_logic;
             --    OP1 : out std_logic_vector(3 downto 0);
             --    OP2 : out std_logic_vector(3 downto 0);
             Mspec0 : SpectralMatrix
                 generic map (Input_SZ,Result_SZ)
-                port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Result);       --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
+                port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Res,Result);       --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
                 process(rst,clk)
                 begin

lib/lpp/lpp_matrix/SpectralMatrix.vhd +2 -1

             --    Read : out std_logic;
             --    Take : out std_logic;
             --    Valid : out std_logic;
+                  Res       : out std_logic_vector(Result_SZ-1 downto 0);
             --    Received : out std_logic;
             --    Conjugate : out std_logic;
             --    OP1 : out std_logic_vector(3 downto 0);
             --Received <= Received_int;
             --Valid <= Valid_int;
             --Conjugate <= Conjugate_int;
-            --Result <= Resultat;
+            Res <= Resultat;
             end ar_SpectralMatrix;

lib/lpp/lpp_matrix/lpp_matrix.vhd +2 0

                 WriteFIFO : out std_logic;
                 Result       : out std_logic_vector(Result_SZ-1 downto 0);
                 Start : out std_logic;
+                Res       : out std_logic_vector(Result_SZ-1 downto 0);
                 apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
                 apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
             );
                 ReadFIFO : out std_logic_vector(1 downto 0);
                 WriteFIFO : out std_logic;
                 Start : out std_logic;
+                Res       : out std_logic_vector(Result_SZ-1 downto 0);
                 Result       : out std_logic_vector(Result_SZ-1 downto 0)
             );
             end component;

lib/lpp/lpp_memory/APB_FifoRead.vhd +2 0

                 rst         : in std_logic;                             --! Reset general du composant
                 apbi        : in apb_slv_in_type;                       --! Registre de gestion des entr�es du bus
                 WriteEnable : in std_logic;                             --! Demande d'�criture dans la m�moire, g�r� hors de l'IP
+                RE          : out std_logic;
                 Full        : out std_logic;                            --! Flag, Memoire pleine
                 Empty       : out std_logic;                            --! Flag, Memoire vide
                 DATA        : in std_logic_vector(Data_sz-1 downto 0);  --! Donn�es en entr�e de la m�moire
             Empty <= FlagEmpty;
             Full <= FlagFull;
+            RE <= ReadEnable;
             end ar_APB_FifoRead;

lib/lpp/lpp_memory/ApbDriver.vhd +4 -2

                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                            case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
-                                     FlagRE <= '1';
+                                     if(apbi.penable = '1')then
+                                         FlagRE <= '1';
+                                     end if;
                                      Rdata(Data_sz-1 downto 0)  <= Rec.DEVICE_DataR;
                                 when "000001" =>
             --                         Rdata(31 downto 8) <= X"AAAAAA";
             apbo.prdata     <=   Rdata when apbi.penable = '1';
             WriteEnable     <=   FlagWR;
-            ReadEnable      <=   FlagRE;
+            ReadEnable      <=   FlagRE; --when apbi.penable = '1';
             end ar_ApbDriver;

lib/lpp/lpp_memory/Top_FIFO.vhd +5 -5

             signal Raddr     : std_logic_vector(addr_sz-1 downto 0);
             signal Waddr     : std_logic_vector(addr_sz-1 downto 0);
-            --signal Data_int  : std_logic_vector(Data_sz-1 downto 0);
+            signal Data_int  : std_logic_vector(Data_sz-1 downto 0);
             signal s_empty   : std_logic;
             signal s_full    : std_logic;
             --signal s_full2   : std_logic;
                 SRAM : syncram_2p
                    generic map(CFG_MEMTECH,Addr_sz,Data_sz)
-                   port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in);
+                   port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
-            --    Pipe : Pipeline
+                Pipe : Pipeline
-            --       generic map(Data_sz)
+                   generic map(Data_sz)
-            --       port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
+                   port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
                 RE : Fifo_Read

lib/lpp/lpp_memory/lpp_memory.vhd +1 0

                 rst          : in  std_logic;
                 apbi         : in  apb_slv_in_type;
                 WriteEnable  : in std_logic;
+                RE           : out std_logic;
                 Full         : out std_logic;
                 Empty        : out std_logic;
                 DATA         : in std_logic_vector(Data_sz-1 downto 0);

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