# HG changeset patch # User martin # Date 2011-12-05 13:03:53 # Node ID a9b0b725b93968dbb4962a7449dec5a30113e1c4 # Parent 097bccb7dd53e376dae61ded0b9f67875b90bb05 save diff --git a/lib/lpp/dsp/lpp_fft/APB_FFT.vhd b/lib/lpp/dsp/lpp_fft/APB_FFT.vhd --- a/lib/lpp/dsp/lpp_fft/APB_FFT.vhd +++ b/lib/lpp/dsp/lpp_fft/APB_FFT.vhd @@ -71,13 +71,12 @@ signal AddrOut : std_logic_vecto signal start : std_logic; signal load : std_logic; signal rdy : std_logic; -signal zero : std_logic; begin APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,zero,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); + port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); Extremum : Flag_Extremum @@ -100,7 +99,6 @@ begin port map(clk,start,rst,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy); start <= not rst; -zero <= '0'; DataIn_re <= DataIn(31 downto 16); DataIn_im <= DataIn(15 downto 0); diff --git a/lib/lpp/lpp_cna/lpp_cna.vhd b/lib/lpp/lpp_cna/lpp_cna.vhd --- a/lib/lpp/lpp_cna/lpp_cna.vhd +++ b/lib/lpp/lpp_cna/lpp_cna.vhd @@ -27,7 +27,7 @@ use std.textio.all; library lpp; use lpp.lpp_amba.all; ---! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on +--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on package lpp_cna is @@ -54,12 +54,10 @@ component CNA_TabloC is port( clock : in std_logic; rst : in std_logic; - flag_nw : in std_logic; - bp : in std_logic; + enable : in std_logic; Data_C : in std_logic_vector(15 downto 0); SYNC : out std_logic; SCLK : out std_logic; - Rz : out std_logic; flag_sd : out std_logic; Data : out std_logic ); diff --git a/lib/lpp/lpp_matrix/APB_Matrix.vhd b/lib/lpp/lpp_matrix/APB_Matrix.vhd --- a/lib/lpp/lpp_matrix/APB_Matrix.vhd +++ b/lib/lpp/lpp_matrix/APB_Matrix.vhd @@ -55,7 +55,7 @@ entity APB_Matrix is -- Read : out std_logic; -- Take : out std_logic; -- Valid : out std_logic; --- Received : out std_logic; +Res : out std_logic_vector(Result_SZ-1 downto 0); -- Conjugate : out std_logic; -- OP1 : out std_logic_vector(3 downto 0); -- OP2 : out std_logic_vector(3 downto 0); @@ -84,7 +84,7 @@ begin Mspec0 : SpectralMatrix generic map (Input_SZ,Result_SZ) - port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2 + port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Res,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2 process(rst,clk) begin diff --git a/lib/lpp/lpp_matrix/SpectralMatrix.vhd b/lib/lpp/lpp_matrix/SpectralMatrix.vhd --- a/lib/lpp/lpp_matrix/SpectralMatrix.vhd +++ b/lib/lpp/lpp_matrix/SpectralMatrix.vhd @@ -42,6 +42,7 @@ port( -- Read : out std_logic; -- Take : out std_logic; -- Valid : out std_logic; + Res : out std_logic_vector(Result_SZ-1 downto 0); -- Received : out std_logic; -- Conjugate : out std_logic; -- OP1 : out std_logic_vector(3 downto 0); @@ -103,6 +104,6 @@ Start <= Start_int; --Received <= Received_int; --Valid <= Valid_int; --Conjugate <= Conjugate_int; ---Result <= Resultat; +Res <= Resultat; end ar_SpectralMatrix; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -51,6 +51,7 @@ component APB_Matrix is WriteFIFO : out std_logic; Result : out std_logic_vector(Result_SZ-1 downto 0); Start : out std_logic; + Res : out std_logic_vector(Result_SZ-1 downto 0); apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); @@ -72,6 +73,7 @@ port( ReadFIFO : out std_logic_vector(1 downto 0); WriteFIFO : out std_logic; Start : out std_logic; + Res : out std_logic_vector(Result_SZ-1 downto 0); Result : out std_logic_vector(Result_SZ-1 downto 0) ); end component; diff --git a/lib/lpp/lpp_memory/APB_FifoRead.vhd b/lib/lpp/lpp_memory/APB_FifoRead.vhd --- a/lib/lpp/lpp_memory/APB_FifoRead.vhd +++ b/lib/lpp/lpp_memory/APB_FifoRead.vhd @@ -47,6 +47,7 @@ entity APB_FifoRead is rst : in std_logic; --! Reset general du composant apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus WriteEnable : in std_logic; --! Demande d'�criture dans la m�moire, g�r� hors de l'IP + RE : out std_logic; Full : out std_logic; --! Flag, Memoire pleine Empty : out std_logic; --! Flag, Memoire vide DATA : in std_logic_vector(Data_sz-1 downto 0); --! Donn�es en entr�e de la m�moire @@ -83,5 +84,6 @@ begin Empty <= FlagEmpty; Full <= FlagFull; +RE <= ReadEnable; end ar_APB_FifoRead; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/ApbDriver.vhd b/lib/lpp/lpp_memory/ApbDriver.vhd --- a/lib/lpp/lpp_memory/ApbDriver.vhd +++ b/lib/lpp/lpp_memory/ApbDriver.vhd @@ -135,7 +135,9 @@ Rec.DEVICE_AddrR <= AddrOut; if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - FlagRE <= '1'; + if(apbi.penable = '1')then + FlagRE <= '1'; + end if; Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR; when "000001" => -- Rdata(31 downto 8) <= X"AAAAAA"; @@ -166,6 +168,6 @@ Rec.DEVICE_AddrR <= AddrOut; apbo.prdata <= Rdata when apbi.penable = '1'; WriteEnable <= FlagWR; -ReadEnable <= FlagRE; +ReadEnable <= FlagRE; --when apbi.penable = '1'; end ar_ApbDriver; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Top_FIFO.vhd b/lib/lpp/lpp_memory/Top_FIFO.vhd --- a/lib/lpp/lpp_memory/Top_FIFO.vhd +++ b/lib/lpp/lpp_memory/Top_FIFO.vhd @@ -71,7 +71,7 @@ end component; signal Raddr : std_logic_vector(addr_sz-1 downto 0); signal Waddr : std_logic_vector(addr_sz-1 downto 0); ---signal Data_int : std_logic_vector(Data_sz-1 downto 0); +signal Data_int : std_logic_vector(Data_sz-1 downto 0); signal s_empty : std_logic; signal s_full : std_logic; --signal s_full2 : std_logic; @@ -93,12 +93,12 @@ begin SRAM : syncram_2p generic map(CFG_MEMTECH,Addr_sz,Data_sz) - port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in); + port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in); --- Pipe : Pipeline --- generic map(Data_sz) --- port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out); + Pipe : Pipeline + generic map(Data_sz) + port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out); RE : Fifo_Read diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -222,6 +222,7 @@ component APB_FifoRead is rst : in std_logic; apbi : in apb_slv_in_type; WriteEnable : in std_logic; + RE : out std_logic; Full : out std_logic; Empty : out std_logic; DATA : in std_logic_vector(Data_sz-1 downto 0);