HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r90:a9b0b725b939

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lib/lpp/dsp/lpp_fft/APB_FFT.vhd +1 -3

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                        Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
             use lpp.apb_devices_list.all;
             use lpp.lpp_fft.all;
             use lpp.lpp_memory.all;
             use work.fft_components.all;
             --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
             entity APB_FFT is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 Data_sz      : integer := 32;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port (
                 clk     : in  std_logic;           --! Horloge du composant
                 rst     : in  std_logic;           --! Reset general du composant
                 apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
                 apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
                 );
             end APB_FFT;
             architecture ar_APB_FFT of APB_FFT is
             signal ReadEnable      : std_logic;
             signal WriteEnable     : std_logic;
             signal FlagEmpty       : std_logic;
             signal FlagFull        : std_logic;
             signal DataIn_re       : std_logic_vector(gWSIZE-1 downto 0);
             signal DataOut_re      : std_logic_vector(gWSIZE-1 downto 0);
             signal DataIn_im       : std_logic_vector(gWSIZE-1 downto 0);
             signal DataOut_im      : std_logic_vector(gWSIZE-1 downto 0);
             signal DataIn          : std_logic_vector(Data_sz-1 downto 0);
             signal DataOut         : std_logic_vector(Data_sz-1 downto 0);
             signal AddrIn          : std_logic_vector(Addr_sz-1 downto 0);
             signal AddrOut         : std_logic_vector(Addr_sz-1 downto 0);
             signal start   : std_logic;
             signal load    : std_logic;
             signal rdy     : std_logic;
-            signal zero    : std_logic;
             begin
                 APB : ApbDriver
                     generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
-                    port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,zero,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
+                    port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
                 Extremum : Flag_Extremum
                     port map(clk,rst,load,rdy,FlagFull,FlagEmpty);
                 DEVICE : CoreFFT
                     generic map(
                     LOGPTS      => gLOGPTS,
                     LOGLOGPTS   => gLOGLOGPTS,
                     WSIZE       => gWSIZE,
                     TWIDTH      => gTWIDTH,
                     DWIDTH      => gDWIDTH,
                     TDWIDTH     => gTDWIDTH,
                     RND_MODE    => gRND_MODE,
                     SCALE_MODE  => gSCALE_MODE,
                     PTS         => gPTS,
                     HALFPTS     => gHALFPTS,
                     inBuf_RWDLY => gInBuf_RWDLY)
                     port map(clk,start,rst,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
             start <= not rst;
-            zero  <= '0';
             DataIn_re <= DataIn(31 downto 16);
             DataIn_im <= DataIn(15 downto 0);
             DataOut   <= DataOut_re & DataOut_im;
             end ar_APB_FFT;

lib/lpp/lpp_cna/lpp_cna.vhd +2 -4

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use std.textio.all;
             library lpp;
             use lpp.lpp_amba.all;
             --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
             package lpp_cna is
             component APB_CNA is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8);
               port (
                 clk     : in  std_logic;
                 rst     : in  std_logic;
                 apbi    : in  apb_slv_in_type;
                 apbo    : out apb_slv_out_type;
                 SYNC    : out std_logic;
                 SCLK    : out std_logic;
                 DATA    : out std_logic
                 );
             end component;
             component CNA_TabloC is
                 port(
                     clock       : in std_logic;
                     rst         : in std_logic;
-                    flag_nw     : in std_logic;
+                    enable      : in std_logic;
-                    bp          : in std_logic;
                     Data_C      : in std_logic_vector(15 downto 0);
                     SYNC        : out std_logic;
                     SCLK        : out std_logic;
-                    Rz          : out std_logic;
                     flag_sd     : out std_logic;
                     Data        : out std_logic
                     );
             end component;
             component Systeme_Clock is
                 generic(N :integer := 695);
                 port(
                     clk, raz   : in std_logic ;
                     clock      : out std_logic);
             end component;
             component Gene_SYNC is
                 port(
                     clk,raz     : in std_logic;
                     send     : in std_logic;
                     Sysclk      : in std_logic;
                     OKAI_send   : out std_logic;
                     SYNC        : out std_logic);
             end component;
             component Serialize is
             port(
                 clk,raz : in std_logic;
                 sclk    : in std_logic;
                 vectin  : in std_logic_vector(15 downto 0);
                 send    : in std_logic;
                 sended  : out std_logic;
                 Data    : out std_logic);
             end component;
             end;

lib/lpp/lpp_matrix/APB_Matrix.vhd +2 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                        Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
             use lpp.apb_devices_list.all;
             use lpp.lpp_matrix.all;
             --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
             entity APB_Matrix is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8;
                 Input_SZ : integer := 16;
                 Result_SZ : integer := 32);
               port (
                 clk     : in  std_logic;           --! Horloge du composant
                 rst     : in  std_logic;           --! Reset general du composant
                 FIFO1       : in std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2       : in std_logic_vector(Input_SZ-1 downto 0);
                 Full   : in std_logic_vector(1 downto 0);
                 Empty   : in std_logic_vector(1 downto 0);
                 ReadFIFO : out std_logic_vector(1 downto 0);
                 WriteFIFO : out std_logic;
                 Result       : out std_logic_vector(Result_SZ-1 downto 0);
                 Start : out std_logic;
             --    Read : out std_logic;
             --    Take : out std_logic;
             --    Valid : out std_logic;
-            --    Received : out std_logic;
+            Res       : out std_logic_vector(Result_SZ-1 downto 0);
             --    Conjugate : out std_logic;
             --    OP1 : out std_logic_vector(3 downto 0);
             --    OP2 : out std_logic_vector(3 downto 0);
                 apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
                 apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
             );
             end APB_Matrix;
             architecture ar_APB_Matrix of APB_Matrix is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_MATRIX, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             type MATRIX_ctrlr_Reg is record
                  MATRIX_Statu : std_logic_vector(3 downto 0);
             end record;
             signal Rec : MATRIX_ctrlr_Reg;
             signal Rdata : std_logic_vector(31 downto 0);
             begin
             Mspec0 : SpectralMatrix
                 generic map (Input_SZ,Result_SZ)
-                port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Result);       --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
+                port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Res,Result);       --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
                 process(rst,clk)
                 begin
                     if(rst='0')then
                         Rec.MATRIX_Statu <= (others => '0');
                     elsif(clk'event and clk='1')then
                 --APB Write OP
                         if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
                                      Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0);
                                 when others =>
                                     null;
                             end case;
                         end if;
                 --APB READ OP
                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
                                      Rdata(31 downto 4) <= (others => '0');
                                      Rdata(3 downto 0) <= Rec.MATRIX_Statu;
                                 --when "000001" =>
                                 --     Rdata(3 downto 0) <= "000" & Rec.MATRIX_Cfg(0);
                                 --     Rdata(7 downto 4) <= "000" & Rec.MATRIX_Cfg(1);
                                 --     Rdata(11 downto 8) <= "000" & Rec.MATRIX_Cfg(2);
                                 --     Rdata(15 downto 12) <= "000" & Rec.MATRIX_Cfg(3);
                                 --     Rdata(19 downto 16) <= "000" & Rec.MATRIX_Cfg(4);
                                 --     Rdata(23 downto 20) <= "000" & Rec.MATRIX_Cfg(5);
                                 --     Rdata(31 downto 24) <= X"CC";
                                 when others =>
                                     Rdata <= (others => '0');
                             end case;
                         end if;
                     end if;
                     apbo.pconfig <= pconfig;
                 end process;
             apbo.prdata     <=   Rdata when apbi.penable = '1';
             end ar_APB_MATRIX;

lib/lpp/lpp_matrix/SpectralMatrix.vhd +2 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                   Mail : martin.morlot@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             library IEEE;
             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
             use lpp.lpp_matrix.all;
             entity SpectralMatrix is
             generic(
                 Input_SZ  : integer := 16;
                 Result_SZ : integer := 32);
             port(
                 clk      : in std_logic;
                 reset    : in std_logic;
                 FIFO1       : in std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2       : in std_logic_vector(Input_SZ-1 downto 0);
                 Full : in std_logic_vector(1 downto 0);
                 Empty : in std_logic_vector(1 downto 0);
                 Statu : in std_logic_vector(3 downto 0);
                 ReadFIFO : out std_logic_vector(1 downto 0);
                 WriteFIFO : out std_logic;
                 Start : out std_logic;
             --    Read : out std_logic;
             --    Take : out std_logic;
             --    Valid : out std_logic;
+                  Res       : out std_logic_vector(Result_SZ-1 downto 0);
             --    Received : out std_logic;
             --    Conjugate : out std_logic;
             --    OP1 : out std_logic_vector(3 downto 0);
             --    OP2 : out std_logic_vector(3 downto 0);
                 Result       : out std_logic_vector(Result_SZ-1 downto 0)
             );
             end SpectralMatrix;
             architecture ar_SpectralMatrix of SpectralMatrix is
             signal Start_int        :   std_logic;
             signal Read_int         :   std_logic;
             signal Take_int         :   std_logic;
             signal Received_int     :   std_logic;
             signal Valid_int        :   std_logic;
             signal Conjugate_int    :   std_logic;
             --signal OP1          :   std_logic_vector(Input_SZ-1 downto 0);
             --signal OP2          :   std_logic_vector(Input_SZ-1 downto 0);
             signal Resultat     :   std_logic_vector(Result_SZ-1 downto 0);
             --signal Res     :   std_logic_vector(Result_SZ-1 downto 0);
             begin
             ST0 : Starter
                 port map(clk,reset,Full,Empty,Conjugate_int,Received_int,Start_int);
             --IN0 : SelectInputs
             --    generic map(Input_SZ)
             --    port map(clk,Start,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,Statu,OP1,OP2);
             IN1 : DriveInputs
                 port map(clk,Start_int,Read_int,Conjugate_int,Take_int,ReadFIFO);
             CALC0 : Matrix
                 generic map(Input_SZ)
                 port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
             RES0 : GetResult
                 generic map(Result_SZ)
                 port map(clk,Start_int,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);
             With Statu select
                 Conjugate_int <= '1' when "0001",
                                  '1' when "0011",
                                  '1' when "0110",
                                  '1' when "1010",
                                  '1' when "1111",
                                  '0' when others;
             Start <= Start_int;
             --Read <= Read_int;
             --Take <= Take_int;
             --Received <= Received_int;
             --Valid <= Valid_int;
             --Conjugate <= Conjugate_int;
-            --Result <= Resultat;
+            Res <= Resultat;
             end ar_SpectralMatrix;

lib/lpp/lpp_matrix/lpp_matrix.vhd +2 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use std.textio.all;
             library lpp;
             use lpp.lpp_amba.all;
             --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
             package lpp_matrix is
             component APB_Matrix is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8;
                 Input_SZ : integer := 16;
                 Result_SZ : integer := 32);
               port (
                 clk     : in  std_logic;           --! Horloge du composant
                 rst     : in  std_logic;           --! Reset general du composant
                 FIFO1       : in std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2       : in std_logic_vector(Input_SZ-1 downto 0);
                 Full   : in std_logic_vector(1 downto 0);
                 Empty   : in std_logic_vector(1 downto 0);
                 ReadFIFO : out std_logic_vector(1 downto 0);
                 WriteFIFO : out std_logic;
                 Result       : out std_logic_vector(Result_SZ-1 downto 0);
                 Start : out std_logic;
+                Res       : out std_logic_vector(Result_SZ-1 downto 0);
                 apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
                 apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
             );
             end component;
             component SpectralMatrix is
             generic(
                 Input_SZ  : integer := 16;
                 Result_SZ : integer := 32);
             port(
                 clk      : in std_logic;
                 reset    : in std_logic;
                 FIFO1       : in std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2       : in std_logic_vector(Input_SZ-1 downto 0);
                 Full : in std_logic_vector(1 downto 0);
                 Empty : in std_logic_vector(1 downto 0);
                 Statu : in std_logic_vector(3 downto 0);
                 ReadFIFO : out std_logic_vector(1 downto 0);
                 WriteFIFO : out std_logic;
                 Start : out std_logic;
+                Res       : out std_logic_vector(Result_SZ-1 downto 0);
                 Result       : out std_logic_vector(Result_SZ-1 downto 0)
             );
             end component;
             component Matrix is
               generic(
                   Input_SZ : integer := 16);
               port(
                   clk        : in std_logic;
                   raz        : in std_logic;
                   IN1        : in std_logic_vector(Input_SZ-1 downto 0);
                   IN2        : in std_logic_vector(Input_SZ-1 downto 0);
                   Take       : in std_logic;
                   Received   : in std_logic;
                   Conjugate  : in std_logic;
                   Valid      : out std_logic;
                   Read       : out std_logic;
                   Result     : out std_logic_vector(2*Input_SZ-1 downto 0)
             );
             end component;
             component ALU_Driver is
               generic(
                   Input_SZ_1      :   integer := 16;
                   Input_SZ_2      :   integer := 16);
               port(
                   clk       :   in std_logic;
                   reset     :   in std_logic;
                   IN1       :   in std_logic_vector(Input_SZ_1-1 downto 0);
                   IN2       :   in std_logic_vector(Input_SZ_2-1 downto 0);
                   Take      :   in std_logic;
                   Received  :   in std_logic;
                   Conjugate :   in std_logic;
                   Valid     :   out std_logic;
                   Read      :   out std_logic;
                   CTRL      :   out std_logic_vector(4 downto 0);
                   OP1       :   out std_logic_vector(Input_SZ_1-1 downto 0);
                   OP2       :   out std_logic_vector(Input_SZ_2-1 downto 0)
             );
             end component;
             component ALU_v2 is
             generic(
                 Arith_en        :   integer := 1;
                 Logic_en        :   integer := 1;
                 Input_SZ_1      :   integer := 16;
                 Input_SZ_2      :   integer := 9);
             port(
                 clk     :   in  std_logic;
                 reset   :   in  std_logic;
                 ctrl    :   in  std_logic_vector(4 downto 0);
                 OP1     :   in  std_logic_vector(Input_SZ_1-1 downto 0);
                 OP2     :   in  std_logic_vector(Input_SZ_2-1 downto 0);
                 RES     :   out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
             );
             end component;
             component MAC_v2 is
             generic(
                 Input_SZ_A     :   integer := 8;
                 Input_SZ_B     :   integer := 8);
             port(
                 clk             :   in  std_logic;
                 reset           :   in  std_logic;
                 clr_MAC         :   in  std_logic;
                 MAC_MUL_ADD_2C  :   in  std_logic_vector(3 downto 0);
                 OP1             :   in  std_logic_vector(Input_SZ_A-1 downto 0);
                 OP2             :   in  std_logic_vector(Input_SZ_B-1 downto 0);
                 RES             :   out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
             );
             end component;
             component TwoComplementer is
             generic(
                 Input_SZ : integer := 16);
             port(
                 clk     : in  std_logic;
                 reset   : in  std_logic;
                 clr     : in  std_logic;
                 TwoComp : in  std_logic;
                 OP      : in  std_logic_vector(Input_SZ-1 downto 0);
                 RES     : out std_logic_vector(Input_SZ-1 downto 0)
             );
             end component;
             component GetResult is
             generic(
                 Result_SZ : integer := 32);
             port(
                 clk       : in  std_logic;
                 raz       : in  std_logic;
                 Valid     : in  std_logic;
                 Conjugate : in  std_logic;
                 Res       : in  std_logic_vector(Result_SZ-1 downto 0);
                 WriteFIFO : out std_logic;
                 Received  : out std_logic;
                 Result    : out std_logic_vector(Result_SZ-1 downto 0)
             );
             end component;
             component SelectInputs is
             generic(
                 Input_SZ : integer := 16);
             port(
                 clk       : in  std_logic;
                 raz       : in  std_logic;
                 Read      : in  std_logic;
                 B1        : in  std_logic_vector(Input_SZ-1 downto 0);
                 B2        : in  std_logic_vector(Input_SZ-1 downto 0);
                 B3        : in  std_logic_vector(Input_SZ-1 downto 0);
                 E1        : in  std_logic_vector(Input_SZ-1 downto 0);
                 E2        : in  std_logic_vector(Input_SZ-1 downto 0);
                 Conjugate : out std_logic;
                 Take      : out std_logic;
                 ReadFIFO  : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
                 Statu : out std_logic_vector(3 downto 0);
                 OP1       : out std_logic_vector(Input_SZ-1 downto 0);
                 OP2       : out std_logic_vector(Input_SZ-1 downto 0)
             );
             end component;
             ---------------------------------------------------------------------------
             component DriveInputs is
             port(
                 clk     : in  std_logic;
                 raz     : in  std_logic;
                 Read    : in  std_logic;
             --    FIFO1      : in std_logic_vector(Input_SZ-1 downto 0);
             --    FIFO2      : in std_logic_vector(Input_SZ-1 downto 0);
             --    Statu : in std_logic_vector(3 downto 0);
                 Conjugate : in std_logic;
                 Take    : out std_logic;
                 ReadFIFO : out std_logic_vector(1 downto 0)
             --    OP1     : out std_logic_vector(Input_SZ-1 downto 0);
             --    OP2     : out std_logic_vector(Input_SZ-1 downto 0)
             );
             end component;
             component Starter is
             port(
                 clk     : in  std_logic;
                 raz     : in  std_logic;
                 Full    : in  std_logic_vector(1 downto 0);
                 Empty    : in  std_logic_vector(1 downto 0);
                 Conjugate : in std_logic;
                 received : in std_logic;
                 Start    : out std_logic
             );
             end component;
             end;

lib/lpp/lpp_memory/APB_FifoRead.vhd +2 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                        Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
             use lpp.apb_devices_list.all;
             use lpp.lpp_memory.all;
             --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
             entity APB_FifoRead is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port (
                 clk         : in std_logic;                             --! Horloge du composant
                 rst         : in std_logic;                             --! Reset general du composant
                 apbi        : in apb_slv_in_type;                       --! Registre de gestion des entr�es du bus
                 WriteEnable : in std_logic;                             --! Demande d'�criture dans la m�moire, g�r� hors de l'IP
+                RE          : out std_logic;
                 Full        : out std_logic;                            --! Flag, Memoire pleine
                 Empty       : out std_logic;                            --! Flag, Memoire vide
                 DATA        : in std_logic_vector(Data_sz-1 downto 0);  --! Donn�es en entr�e de la m�moire
                 apbo        : out apb_slv_out_type                      --! Registre de gestion des sorties du bus
                 );
             end APB_FifoRead;
             --! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA
             architecture ar_APB_FifoRead of APB_FifoRead is
             signal Low          : std_logic:='0';
             signal ReadEnable   : std_logic;
             signal FlagEmpty    : std_logic;
             signal FlagFull     : std_logic;
             --signal ReUse        : std_logic;
             --signal Lock         : std_logic;
             --signal RstMem       : std_logic;
             signal DataIn       : std_logic_vector(Data_sz-1 downto 0);
             signal DataOut      : std_logic_vector(Data_sz-1 downto 0);
             signal AddrIn       : std_logic_vector(Addr_sz-1 downto 0);
             signal AddrOut      : std_logic_vector(Addr_sz-1 downto 0);
             begin
                 APB : ApbDriver
                     generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
                     port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
                 FIFO : Top_FIFO
                     generic map(Data_sz,Addr_sz,addr_max_int)
                     port map(clk,rst,ReadEnable,WriteEnable,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
             Empty <= FlagEmpty;
             Full <= FlagFull;
+            RE <= ReadEnable;
             end ar_APB_FifoRead;

lib/lpp/lpp_memory/ApbDriver.vhd +4 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                        Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
             use lpp.apb_devices_list.all;
             --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO
             entity ApbDriver is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 LPP_DEVICE   : integer;
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port (
                 clk          : in  std_logic;                              --! Horloge du composant
                 rst          : in  std_logic;                              --! Reset general du composant
                 ReadEnable   : out std_logic;                              --! Instruction de lecture en m�moire
                 WriteEnable  : out std_logic;                              --! Instruction d'�criture en m�moire
                 FlagEmpty    : in std_logic;                               --! Flag, M�moire vide
                 FlagFull     : in std_logic;                               --! Flag, M�moire pleine
             --    ReUse        : out std_logic;                              --! Flag, Permet de relire la m�moire en boucle sans nouvelle donn�es
             --    Lock         : out std_logic;                              --! Flag, Permet de bloquer l'�criture dans la m�moire
             --    RstMem       : out std_logic;                              --! Flag, Reset "manuel" sp�cifique au composant
                 DataIn       : out std_logic_vector(Data_sz-1 downto 0);   --! Registre de donn�es en entr�e
                 DataOut      : in std_logic_vector(Data_sz-1 downto 0);    --! Registre de donn�es en sortie
                 AddrIn       : in std_logic_vector(Addr_sz-1 downto 0);    --! Registre d'addresse (�criture)
                 AddrOut      : in std_logic_vector(Addr_sz-1 downto 0);    --! Registre d'addresse (lecture)
                 apbi         : in  apb_slv_in_type;                        --! Registre de gestion des entr�es du bus
                 apbo         : out apb_slv_out_type                        --! Registre de gestion des sorties du bus
                 );
             end ApbDriver;
             --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
             architecture ar_ApbDriver of ApbDriver is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             type DEVICE_ctrlr_Reg is record
                  DEVICE_Cfg   : std_logic_vector(3 downto 0);
                  DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
                  DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
                  DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
                  DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
             end record;
             signal Rec    : DEVICE_ctrlr_Reg;
             signal Rdata  : std_logic_vector(31 downto 0);
             signal FlagRE : std_logic;
             signal FlagWR : std_logic;
             begin
             Rec.DEVICE_Cfg(0) <= FlagRE;
             Rec.DEVICE_Cfg(1) <= FlagWR;
             Rec.DEVICE_Cfg(2) <= FlagEmpty;
             Rec.DEVICE_Cfg(3) <= FlagFull;
             --ReUse    <= Rec.DEVICE_Cfg(4);
             --Lock     <= Rec.DEVICE_Cfg(5);
             --RstMem   <= Rec.DEVICE_Cfg(7);
             DataIn <= Rec.DEVICE_DataW;
             Rec.DEVICE_DataR <= DataOut;
             Rec.DEVICE_AddrW <= AddrIn;
             Rec.DEVICE_AddrR <= AddrOut;
                 process(rst,clk)
                 begin
                     if(rst='0')then
                         Rec.DEVICE_DataW <= (others => '0');
                         FlagWR <= '0';
                         FlagRE <= '0';
             --            Rec.DEVICE_Cfg(4)  <= '0';
             --            Rec.DEVICE_Cfg(5)  <= '0';
             --            Rec.DEVICE_Cfg(7)  <= '0';
                     elsif(clk'event and clk='1')then
                 --APB Write OP
                         if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                            case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
                                      FlagWR <= '1';
                                      Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
             --                    when "000010" =>
             --                         Rec.DEVICE_Cfg(7) <= apbi.pwdata(28);
             --                         Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
             --                         Rec.DEVICE_Cfg(6) <= apbi.pwdata(24);
                                 when others =>
                                      null;
                            end case;
                         else
                             FlagWR <= '0';
                         end if;
                 --APB Read OP
                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                            case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
-                                     FlagRE <= '1';
+                                     if(apbi.penable = '1')then
+                                         FlagRE <= '1';
+                                     end if;
                                      Rdata(Data_sz-1 downto 0)  <= Rec.DEVICE_DataR;
                                 when "000001" =>
             --                         Rdata(31 downto 8) <= X"AAAAAA";
                                      Rdata(Addr_sz-1 downto 0)  <= Rec.DEVICE_AddrR;
                                 when "000101" =>
             --                         Rdata(31 downto 8) <= X"AAAAAA";
                                      Rdata(Addr_sz-1 downto 0)  <= Rec.DEVICE_AddrW;
                                 when "000010" =>
                                      Rdata(3 downto 0)   <= "000" & Rec.DEVICE_Cfg(0);
                                      Rdata(7 downto 4)   <= "000" & Rec.DEVICE_Cfg(1);
                                      Rdata(11 downto 8)  <= "000" & Rec.DEVICE_Cfg(2);
                                      Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
             --                         Rdata(27 downto 16) <= X"000";
             --                         Rdata(31 downto 28) <= "000" & Rec.DEVICE_Cfg(7);
             --                         Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
             --                         Rdata(27 downto 24) <= "000" & Rec.DEVICE_Cfg(6);
                                      Rdata(31 downto 16) <= X"CCCC";
                                 when others =>
                                      Rdata <= (others => '0');
                            end case;
                         else
                             FlagRE <= '0';
                         end if;
                     end if;
                     apbo.pconfig <= pconfig;
                 end process;
             apbo.prdata     <=   Rdata when apbi.penable = '1';
             WriteEnable     <=   FlagWR;
-            ReadEnable      <=   FlagRE;
+            ReadEnable      <=   FlagRE; --when apbi.penable = '1';
             end ar_ApbDriver;

lib/lpp/lpp_memory/Top_FIFO.vhd +5 -5

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
             library techmap;
             use techmap.gencomp.all;
             use work.config.all;
             use lpp.lpp_memory.all;
             --! Programme de la FIFO
             entity Top_FIFO is
               generic(
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256
                 );
               port(
                 clk,raz  : in std_logic;                             --! Horloge et reset general du composant
                 flag_RE  : in std_logic;                             --! Flag, Demande la lecture de la m�moire
                 flag_WR  : in std_logic;                             --! Flag, Demande l'�criture dans la m�moire
             --    ReUse    : in std_logic;                             --! Flag, Permet de relire la m�moire en boucle sans nouvelle donn�es
             --    Lock     : in std_logic;                             --! Permet de bloquer l'�criture dans la m�moire
             --    RstMem   : in std_logic;                             --! Flag, Reset "manuel" sp�cifique au composant
                 Data_in  : in std_logic_vector(Data_sz-1 downto 0);  --! Data en entr�e du composant
                 Addr_RE  : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
                 Addr_WR  : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
                 full     : out std_logic;                            --! Flag, M�moire pleine
                 empty    : out std_logic;                            --! Flag, M�moire vide
                 Data_out : out std_logic_vector(Data_sz-1 downto 0)  --! Data en sortie du composant
                 );
             end Top_FIFO;
             --! @details Une m�moire SRAM de chez Gaisler est utilis�e,
             --! associ�e a deux Drivers, un pour �crire l'autre pour lire cette m�moire
             architecture ar_Top_FIFO of Top_FIFO is
             component syncram_2p
                 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
                 port (
                     rclk      : in std_ulogic;
                     renable   : in std_ulogic;
                     raddress  : in std_logic_vector((abits -1) downto 0);
                     dataout   : out std_logic_vector((dbits -1) downto 0);
                     wclk      : in std_ulogic;
                     write     : in std_ulogic;
                     waddress  : in std_logic_vector((abits -1) downto 0);
                     datain    : in std_logic_vector((dbits -1) downto 0));
             end component;
             signal Raddr     : std_logic_vector(addr_sz-1 downto 0);
             signal Waddr     : std_logic_vector(addr_sz-1 downto 0);
-            --signal Data_int  : std_logic_vector(Data_sz-1 downto 0);
+            signal Data_int  : std_logic_vector(Data_sz-1 downto 0);
             signal s_empty   : std_logic;
             signal s_full    : std_logic;
             --signal s_full2   : std_logic;
             signal s_flag_RE : std_logic;
             signal s_flag_WR : std_logic;
             signal Flag_WR_reg : std_logic;
             --signal rst       : std_logic;
             --signal RstMem_inv  : std_logic;
             begin
             --RstMem_inv <= not RstMem;
             --rst <= raz and RstMem_inv;
                 WR : Fifo_Write
                    generic map(Addr_sz,addr_max_int)
                    port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
                 SRAM : syncram_2p
                    generic map(CFG_MEMTECH,Addr_sz,Data_sz)
-                   port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in);
+                   port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
-            --    Pipe : Pipeline
+                Pipe : Pipeline
-            --       generic map(Data_sz)
+                   generic map(Data_sz)
-            --       port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
+                   port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
                 RE : Fifo_Read
                    generic map(Addr_sz,addr_max_int)
                    port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr);
                 process(clk,raz)
                 begin
                     if(raz='0')then
                         s_flag_RE <= '0';
                         s_flag_WR <= '0';
             --            s_full2   <= s_full;
                         Flag_WR_reg <= '0';
                     elsif(clk'event and clk='1')then
                         Flag_WR_reg <= Flag_WR;
                         if(s_full='0')then         --2
                             if(s_empty='1')then
                                 s_flag_WR <= Flag_WR_reg;
                             else
                                 s_flag_WR <= Flag_WR;
                             end if;
                         else
                             s_flag_WR <= '0';
                         end if;
                         if(s_empty='0')then
                             s_flag_RE <= Flag_RE;
                         else
                             s_flag_RE <= '0';
                         end if;
             --            if(Lock='1')then
             --                s_full2 <= '1';
             --            else
             --                s_full2 <= s_full;
             --            end if;
                     end if;
                 end process;
             full    <= s_full;     --2
             empty   <= s_empty;
             Addr_RE <= Raddr;
             Addr_WR <= Waddr;
             end ar_Top_FIFO;

lib/lpp/lpp_memory/lpp_memory.vhd +1 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use std.textio.all;
             library lpp;
             use lpp.lpp_amba.all;
             --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
             package lpp_memory is
             --===========================================================|
             --=================== FIFO Compl�te =========================|
             --===========================================================|
             component APB_FIFO is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port (
                 clk          : in  std_logic;
                 rst          : in  std_logic;
                 apbi         : in  apb_slv_in_type;
                 Full    : out std_logic;
                 Empty   : out std_logic;
                 WR : out std_logic;
                 RE : out std_logic;
                 apbo         : out apb_slv_out_type
                 );
             end component;
             component ApbDriver is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 LPP_DEVICE   : integer;
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port (
                 clk          : in  std_logic;
                 rst          : in  std_logic;
                 ReadEnable   : out std_logic;
                 WriteEnable  : out std_logic;
                 FlagEmpty    : in std_logic;
                 FlagFull     : in std_logic;
             --    ReUse        : out std_logic;
             --    Lock         : out std_logic;
             --    RstMem       : out std_logic;
                 DataIn       : out std_logic_vector(Data_sz-1 downto 0);
                 DataOut      : in std_logic_vector(Data_sz-1 downto 0);
                 AddrIn       : in std_logic_vector(Addr_sz-1 downto 0);
                 AddrOut      : in std_logic_vector(Addr_sz-1 downto 0);
                 apbi         : in  apb_slv_in_type;
                 apbo         : out apb_slv_out_type
                 );
             end component;
             component Top_FIFO is
               generic(
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256
                 );
               port(
                 clk,raz  : in std_logic;
                 flag_RE  : in std_logic;
                 flag_WR  : in std_logic;
             --    ReUse    : in std_logic;
             --    Lock     : in std_logic;
             --    RstMem   : in std_logic;
                 Data_in  : in std_logic_vector(Data_sz-1 downto 0);
                 Addr_RE  : out std_logic_vector(addr_sz-1 downto 0);
                 Addr_WR  : out std_logic_vector(addr_sz-1 downto 0);
                 full     : out std_logic;
                 empty    : out std_logic;
                 Data_out : out std_logic_vector(Data_sz-1 downto 0)
                 );
             end component;
             component Fifo_Read is
               generic(
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port(
                 clk          : in std_logic;
                 raz          : in std_logic;
                 flag_RE      : in std_logic;
             --    ReUse        : in std_logic;
                 Waddr        : in std_logic_vector(addr_sz-1 downto 0);
                 empty        : out std_logic;
                 Raddr        : out std_logic_vector(addr_sz-1 downto 0)
                 );
             end component;
             component Fifo_Write is
               generic(
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port(
                 clk          : in std_logic;
                 raz          : in std_logic;
                 flag_WR      : in std_logic;
                 Raddr        : in std_logic_vector(addr_sz-1 downto 0);
                 full         : out std_logic;
                 Waddr        : out std_logic_vector(addr_sz-1 downto 0)
                 );
             end component;
             component Pipeline is
               generic(Data_sz : integer := 16);
               port(
                 clk,raz       : in std_logic;
                 Data_one      : in std_logic_vector(Data_sz-1 downto 0);
                 Data_two      : in std_logic_vector(Data_sz-1 downto 0);
             --    ReUse         : in std_logic;
                 flag_RE       : in std_logic;
                 flag_WR       : in std_logic;
                 empty         : in std_logic;
                 Data_out      : out std_logic_vector(Data_sz-1 downto 0)
                 );
             end component;
             --===========================================================|
             --================= Demi FIFO Ecriture ======================|
             --===========================================================|
             component APB_FifoWrite is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port (
                 clk          : in  std_logic;
                 rst          : in  std_logic;
                 apbi         : in  apb_slv_in_type;
                 ReadEnable   : in  std_logic;
                 Empty        : out std_logic;
                 Full         : out std_logic;
                 DATA         : out std_logic_vector(Data_sz-1 downto 0);
                 apbo         : out apb_slv_out_type
                 );
             end component;
             --component Top_FifoWrite is
             --  generic(
             --    Data_sz      : integer := 16;
             --    Addr_sz      : integer := 8;
             --    addr_max_int : integer := 256);
             --  port(
             --    clk          : in std_logic;
             --    raz          : in std_logic;
             --    flag_RE      : in std_logic;
             --    flag_WR      : in std_logic;
             --    Data_in      : in std_logic_vector(Data_sz-1 downto 0);
             --    Raddr        : in std_logic_vector(addr_sz-1 downto 0);
             --    full         : out std_logic;
             --    empty        : out std_logic;
             --    Waddr        : out std_logic_vector(addr_sz-1 downto 0);
             --    Data_out     : out std_logic_vector(Data_sz-1 downto 0)
             --    );
             --end component;
             --===========================================================|
             --================== Demi FIFO Lecture ======================|
             --===========================================================|
             component APB_FifoRead is
               generic (
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 Data_sz      : integer := 16;
                 Addr_sz      : integer := 8;
                 addr_max_int : integer := 256);
               port (
                 clk          : in  std_logic;
                 rst          : in  std_logic;
                 apbi         : in  apb_slv_in_type;
                 WriteEnable  : in std_logic;
+                RE           : out std_logic;
                 Full         : out std_logic;
                 Empty        : out std_logic;
                 DATA         : in std_logic_vector(Data_sz-1 downto 0);
                 apbo         : out apb_slv_out_type
                 );
             end component;
             --component Top_FifoRead is
             --  generic(
             --    Data_sz      : integer := 16;
             --    Addr_sz      : integer := 8;
             --    addr_max_int : integer := 256);
             --  port(
             --    clk          : in std_logic;
             --    raz          : in std_logic;
             --    flag_RE      : in std_logic;
             --    flag_WR      : in std_logic;
             --    Data_in      : in std_logic_vector(Data_sz-1 downto 0);
             --    Waddr        : in std_logic_vector(addr_sz-1 downto 0);
             --    full         : out std_logic;
             --    empty        : out std_logic;
             --    Raddr        : out std_logic_vector(addr_sz-1 downto 0);
             --    Data_out     : out std_logic_vector(Data_sz-1 downto 0)
             --    );
             --end component;
             end;

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