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r90:a9b0b725b939 martin
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@@ -71,13 +71,12 signal AddrOut : std_logic_vecto
71 71 signal start : std_logic;
72 72 signal load : std_logic;
73 73 signal rdy : std_logic;
74 signal zero : std_logic;
75 74
76 75 begin
77 76
78 77 APB : ApbDriver
79 78 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
80 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,zero,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
79 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
81 80
82 81
83 82 Extremum : Flag_Extremum
@@ -100,7 +99,6 begin
100 99 port map(clk,start,rst,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
101 100
102 101 start <= not rst;
103 zero <= '0';
104 102
105 103 DataIn_re <= DataIn(31 downto 16);
106 104 DataIn_im <= DataIn(15 downto 0);
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@@ -27,7 +27,7 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31 31
32 32 package lpp_cna is
33 33
@@ -54,12 +54,10 component CNA_TabloC is
54 54 port(
55 55 clock : in std_logic;
56 56 rst : in std_logic;
57 flag_nw : in std_logic;
58 bp : in std_logic;
57 enable : in std_logic;
59 58 Data_C : in std_logic_vector(15 downto 0);
60 59 SYNC : out std_logic;
61 60 SCLK : out std_logic;
62 Rz : out std_logic;
63 61 flag_sd : out std_logic;
64 62 Data : out std_logic
65 63 );
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@@ -55,7 +55,7 entity APB_Matrix is
55 55 -- Read : out std_logic;
56 56 -- Take : out std_logic;
57 57 -- Valid : out std_logic;
58 -- Received : out std_logic;
58 Res : out std_logic_vector(Result_SZ-1 downto 0);
59 59 -- Conjugate : out std_logic;
60 60 -- OP1 : out std_logic_vector(3 downto 0);
61 61 -- OP2 : out std_logic_vector(3 downto 0);
@@ -84,7 +84,7 begin
84 84
85 85 Mspec0 : SpectralMatrix
86 86 generic map (Input_SZ,Result_SZ)
87 port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
87 port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Res,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
88 88
89 89 process(rst,clk)
90 90 begin
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@@ -42,6 +42,7 port(
42 42 -- Read : out std_logic;
43 43 -- Take : out std_logic;
44 44 -- Valid : out std_logic;
45 Res : out std_logic_vector(Result_SZ-1 downto 0);
45 46 -- Received : out std_logic;
46 47 -- Conjugate : out std_logic;
47 48 -- OP1 : out std_logic_vector(3 downto 0);
@@ -103,6 +104,6 Start <= Start_int;
103 104 --Received <= Received_int;
104 105 --Valid <= Valid_int;
105 106 --Conjugate <= Conjugate_int;
106 --Result <= Resultat;
107 Res <= Resultat;
107 108
108 109 end ar_SpectralMatrix; No newline at end of file
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@@ -51,6 +51,7 component APB_Matrix is
51 51 WriteFIFO : out std_logic;
52 52 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 53 Start : out std_logic;
54 Res : out std_logic_vector(Result_SZ-1 downto 0);
54 55 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 56 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 57 );
@@ -72,6 +73,7 port(
72 73 ReadFIFO : out std_logic_vector(1 downto 0);
73 74 WriteFIFO : out std_logic;
74 75 Start : out std_logic;
76 Res : out std_logic_vector(Result_SZ-1 downto 0);
75 77 Result : out std_logic_vector(Result_SZ-1 downto 0)
76 78 );
77 79 end component;
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@@ -47,6 +47,7 entity APB_FifoRead is
47 47 rst : in std_logic; --! Reset general du composant
48 48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 49 WriteEnable : in std_logic; --! Demande d'�criture dans la m�moire, g�r� hors de l'IP
50 RE : out std_logic;
50 51 Full : out std_logic; --! Flag, Memoire pleine
51 52 Empty : out std_logic; --! Flag, Memoire vide
52 53 DATA : in std_logic_vector(Data_sz-1 downto 0); --! Donn�es en entr�e de la m�moire
@@ -83,5 +84,6 begin
83 84
84 85 Empty <= FlagEmpty;
85 86 Full <= FlagFull;
87 RE <= ReadEnable;
86 88
87 89 end ar_APB_FifoRead; No newline at end of file
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@@ -135,7 +135,9 Rec.DEVICE_AddrR <= AddrOut;
135 135 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
136 136 case apbi.paddr(abits-1 downto 2) is
137 137 when "000000" =>
138 FlagRE <= '1';
138 if(apbi.penable = '1')then
139 FlagRE <= '1';
140 end if;
139 141 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
140 142 when "000001" =>
141 143 -- Rdata(31 downto 8) <= X"AAAAAA";
@@ -166,6 +168,6 Rec.DEVICE_AddrR <= AddrOut;
166 168
167 169 apbo.prdata <= Rdata when apbi.penable = '1';
168 170 WriteEnable <= FlagWR;
169 ReadEnable <= FlagRE;
171 ReadEnable <= FlagRE; --when apbi.penable = '1';
170 172
171 173 end ar_ApbDriver; No newline at end of file
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@@ -71,7 +71,7 end component;
71 71
72 72 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
73 73 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
74 --signal Data_int : std_logic_vector(Data_sz-1 downto 0);
74 signal Data_int : std_logic_vector(Data_sz-1 downto 0);
75 75 signal s_empty : std_logic;
76 76 signal s_full : std_logic;
77 77 --signal s_full2 : std_logic;
@@ -93,12 +93,12 begin
93 93
94 94 SRAM : syncram_2p
95 95 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
96 port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in);
96 port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
97 97
98 98
99 -- Pipe : Pipeline
100 -- generic map(Data_sz)
101 -- port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
99 Pipe : Pipeline
100 generic map(Data_sz)
101 port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
102 102
103 103
104 104 RE : Fifo_Read
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@@ -222,6 +222,7 component APB_FifoRead is
222 222 rst : in std_logic;
223 223 apbi : in apb_slv_in_type;
224 224 WriteEnable : in std_logic;
225 RE : out std_logic;
225 226 Full : out std_logic;
226 227 Empty : out std_logic;
227 228 DATA : in std_logic_vector(Data_sz-1 downto 0);
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