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1 | LIBRARY IEEE; | |||
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2 | USE IEEE.std_logic_1164.ALL; | |||
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3 | ||||
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4 | LIBRARY lpp; | |||
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5 | USE lpp.general_purpose.ALL; | |||
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6 | ||||
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7 | ENTITY MS_calculation IS | |||
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8 | PORT ( | |||
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9 | clk : IN STD_LOGIC; | |||
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10 | rstn : IN STD_LOGIC; | |||
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11 | -- IN | |||
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12 | fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |||
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13 | fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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14 | fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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15 | -- OUT | |||
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16 | fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0); | |||
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17 | fifo_out_wen : OUT STD_LOGIC; | |||
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18 | fifo_out_full : IN STD_LOGIC; | |||
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19 | -- | |||
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20 | correlation_start : IN STD_LOGIC; | |||
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21 | correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation | |||
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22 | ||||
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23 | correlation_begin : OUT STD_LOGIC; | |||
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24 | correlation_done : OUT STD_LOGIC | |||
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25 | ); | |||
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26 | END MS_calculation; | |||
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27 | ||||
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28 | ARCHITECTURE beh OF MS_calculation IS | |||
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29 | ||||
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30 | TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a); | |||
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31 | SIGNAL state : fsm_calculation_MS; | |||
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32 | ||||
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33 | SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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34 | SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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35 | SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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36 | ||||
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37 | SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
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38 | ||||
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39 | ||||
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40 | CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000"; | |||
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41 | CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010"; | |||
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42 | CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001"; | |||
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43 | CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001"; | |||
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44 | ||||
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45 | ||||
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46 | ||||
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47 | SIGNAL select_op1 : STD_LOGIC; | |||
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48 | SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ; | |||
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49 | ||||
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50 | CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; | |||
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51 | CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; | |||
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52 | CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; | |||
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53 | CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; | |||
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54 | ||||
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55 | SIGNAL res_wen : STD_LOGIC; | |||
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56 | SIGNAL res_wen_reg1 : STD_LOGIC; | |||
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57 | -- SIGNAL res_wen_reg2 : STD_LOGIC; | |||
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58 | --SIGNAL res_wen_reg3 : STD_LOGIC; | |||
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59 | ||||
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60 | BEGIN | |||
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61 | ||||
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62 | ||||
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63 | ||||
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64 | PROCESS (clk, rstn) | |||
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65 | BEGIN | |||
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66 | IF rstn = '0' THEN | |||
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67 | ||||
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68 | correlation_begin <= '0'; | |||
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69 | correlation_done <= '0'; | |||
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70 | state <= IDLE; | |||
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71 | fifo_in_ren <= "11"; | |||
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72 | ALU_CTRL <= ALU_CTRL_NOP; | |||
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73 | select_op1 <= select_R0(0); | |||
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74 | select_op2 <= select_R0; | |||
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75 | res_wen <= '1'; | |||
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76 | ||||
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77 | ELSIF clk'EVENT AND clk = '1' THEN | |||
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78 | correlation_begin <= '0'; | |||
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79 | fifo_in_ren <= "11"; | |||
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80 | res_wen <= '1'; | |||
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81 | correlation_done <= '0'; | |||
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82 | CASE state IS | |||
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83 | WHEN IDLE => | |||
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84 | IF correlation_start = '1' THEN | |||
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85 | IF correlation_auto = '1' THEN | |||
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86 | IF fifo_out_full = '1' THEN | |||
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87 | state <= WFa; | |||
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88 | ELSE | |||
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89 | correlation_begin <= '1'; | |||
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90 | state <= S1a; | |||
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91 | fifo_in_ren <= "10"; | |||
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92 | END IF; | |||
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93 | ELSE | |||
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94 | IF fifo_out_full = '1' THEN | |||
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95 | state <= WF; | |||
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96 | ELSE | |||
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97 | correlation_begin <= '1'; | |||
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98 | state <= S1; | |||
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99 | fifo_in_ren <= "00"; | |||
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100 | END IF; | |||
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101 | END IF; | |||
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102 | END IF; | |||
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103 | ||||
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104 | --------------------------------------------------------------------- | |||
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105 | -- INTER CORRELATION | |||
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106 | --------------------------------------------------------------------- | |||
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107 | WHEN WF => | |||
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108 | IF fifo_out_full = '0' THEN | |||
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109 | correlation_begin <= '1'; | |||
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110 | state <= S1; | |||
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111 | fifo_in_ren <= "00"; | |||
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112 | END IF; | |||
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113 | WHEN S1 => | |||
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114 | ALU_CTRL <= ALU_CTRL_MULT; | |||
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115 | select_op1 <= select_R0(0); | |||
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116 | select_op2 <= select_R1; | |||
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117 | state <= S2; | |||
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118 | WHEN S2 => | |||
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119 | ALU_CTRL <= ALU_CTRL_MAC; | |||
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120 | select_op1 <= select_I0(0); | |||
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121 | select_op2 <= select_I1; | |||
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122 | res_wen <= '0'; | |||
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123 | state <= S3; | |||
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124 | WHEN S3 => | |||
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125 | ALU_CTRL <= ALU_CTRL_MULT; | |||
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126 | select_op1 <= select_I0(0); | |||
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127 | select_op2 <= select_R1; | |||
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128 | state <= S4; | |||
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129 | WHEN S4 => | |||
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130 | ALU_CTRL <= ALU_CTRL_MACn; | |||
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131 | select_op1 <= select_R0(0); | |||
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132 | select_op2 <= select_I1; | |||
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133 | res_wen <= '0'; | |||
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134 | IF fifo_in_empty = "00" THEN | |||
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135 | state <= S1; | |||
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136 | fifo_in_ren <= "00"; | |||
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137 | ELSE | |||
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138 | correlation_done <= '1'; | |||
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139 | state <= IDLE; | |||
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140 | END IF; | |||
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141 | ||||
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142 | ||||
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143 | ||||
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144 | --------------------------------------------------------------------- | |||
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145 | -- AUTO CORRELATION | |||
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146 | --------------------------------------------------------------------- | |||
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147 | WHEN WFa => | |||
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148 | IF fifo_out_full = '0' THEN | |||
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149 | correlation_begin <= '1'; | |||
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150 | state <= S1a; | |||
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151 | fifo_in_ren <= "10"; | |||
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152 | END IF; | |||
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153 | WHEN S1a => | |||
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154 | ALU_CTRL <= ALU_CTRL_MULT; | |||
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155 | select_op1 <= select_R0(0); | |||
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156 | select_op2 <= select_R0; | |||
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157 | state <= S2a; | |||
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158 | WHEN S2a => | |||
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159 | ALU_CTRL <= ALU_CTRL_MAC; | |||
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160 | select_op1 <= select_I0(0); | |||
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161 | select_op2 <= select_I0; | |||
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162 | res_wen <= '0'; | |||
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163 | IF fifo_in_empty(0) = '0' THEN | |||
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164 | state <= S1a; | |||
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165 | fifo_in_ren <= "10"; | |||
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166 | ELSE | |||
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167 | correlation_done <= '1'; | |||
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168 | state <= IDLE; | |||
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169 | END IF; | |||
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170 | ||||
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171 | ||||
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172 | WHEN OTHERS => NULL; | |||
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173 | END CASE; | |||
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174 | ||||
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175 | END IF; | |||
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176 | END PROCESS; | |||
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177 | ||||
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178 | OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE | |||
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179 | fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE | |||
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180 | ||||
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181 | OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE | |||
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182 | fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE | |||
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183 | fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE | |||
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184 | fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE | |||
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185 | ||||
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186 | ALU_MS : ALU | |||
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187 | GENERIC MAP ( | |||
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188 | Arith_en => 1, | |||
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189 | Logic_en => 0, | |||
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190 | Input_SZ_1 => 16, | |||
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191 | Input_SZ_2 => 16, | |||
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192 | COMP_EN => 1) | |||
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193 | PORT MAP ( | |||
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194 | clk => clk, | |||
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195 | reset => rstn, | |||
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196 | ||||
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197 | ctrl => ALU_CTRL(2 DOWNTO 0), | |||
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198 | comp => ALU_CTRL(4 DOWNTO 3), | |||
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199 | ||||
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200 | OP1 => OP1, | |||
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201 | OP2 => OP2, | |||
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202 | ||||
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203 | RES => RES); | |||
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204 | ||||
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205 | fifo_out_data <= RES; | |||
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206 | ||||
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207 | ||||
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208 | PROCESS (clk, rstn) | |||
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209 | BEGIN | |||
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210 | IF rstn = '0' THEN | |||
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211 | res_wen_reg1 <= '1'; | |||
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212 | --res_wen_reg2 <= '1'; | |||
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213 | --res_wen_reg3 <= '1'; | |||
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214 | fifo_out_wen <= '1'; | |||
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215 | ELSIF clk'event AND clk = '1' THEN | |||
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216 | res_wen_reg1 <= res_wen; | |||
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217 | --res_wen_reg2 <= res_wen_reg1; | |||
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218 | --res_wen_reg3 <= res_wen_reg2; | |||
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219 | fifo_out_wen <= res_wen_reg1; | |||
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220 | END IF; | |||
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221 | END PROCESS; | |||
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222 | ||||
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223 | ||||
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224 | END beh; |
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1 | ||||
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2 | ------------------------------------------------------------------------------ | |||
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3 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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5 | -- | |||
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6 | -- This program is free software; you can redistribute it and/or modify | |||
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7 | -- it under the terms of the GNU General Public License as published by | |||
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8 | -- the Free Software Foundation; either version 3 of the License, or | |||
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9 | -- (at your option) any later version. | |||
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10 | -- | |||
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11 | -- This program is distributed in the hope that it will be useful, | |||
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12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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14 | -- GNU General Public License for more details. | |||
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15 | -- | |||
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16 | -- You should have received a copy of the GNU General Public License | |||
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17 | -- along with this program; if not, write to the Free Software | |||
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18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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19 | ------------------------------------------------------------------------------- | |||
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20 | -- Author : Jean-christophe Pellion | |||
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21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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22 | -- jean-christophe.pellion@easii-ic.com | |||
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23 | ------------------------------------------------------------------------------- | |||
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24 | LIBRARY ieee; | |||
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25 | USE ieee.std_logic_1164.ALL; | |||
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26 | USE ieee.numeric_std.ALL; | |||
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27 | LIBRARY grlib; | |||
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28 | USE grlib.amba.ALL; | |||
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29 | USE grlib.stdlib.ALL; | |||
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30 | USE grlib.devices.ALL; | |||
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31 | USE GRLIB.DMA2AHB_Package.ALL; | |||
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32 | LIBRARY lpp; | |||
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33 | USE lpp.lpp_amba.ALL; | |||
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34 | USE lpp.apb_devices_list.ALL; | |||
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35 | USE lpp.lpp_memory.ALL; | |||
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36 | USE lpp.lpp_dma_pkg.ALL; | |||
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37 | LIBRARY techmap; | |||
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38 | USE techmap.gencomp.ALL; | |||
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39 | ||||
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40 | ||||
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41 | ENTITY lpp_lfr_ms_fsmdma IS | |||
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42 | PORT ( | |||
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43 | -- AMBA AHB system signals | |||
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44 | HCLK : IN STD_ULOGIC; | |||
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45 | HRESETn : IN STD_ULOGIC; | |||
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46 | ||||
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47 | --------------------------------------------------------------------------- | |||
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48 | -- FIFO - IN | |||
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49 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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50 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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51 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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52 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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53 | fifo_empty : IN STD_LOGIC; | |||
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54 | fifo_ren : OUT STD_LOGIC; | |||
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55 | ||||
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56 | --------------------------------------------------------------------------- | |||
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57 | -- DMA - OUT | |||
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58 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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59 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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60 | dma_valid : OUT STD_LOGIC; | |||
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61 | dma_valid_burst : OUT STD_LOGIC; | |||
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62 | dma_ren : IN STD_LOGIC; | |||
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63 | dma_done : IN STD_LOGIC; | |||
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64 | ||||
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65 | --------------------------------------------------------------------------- | |||
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66 | -- Reg out | |||
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67 | ready_matrix_f0 : OUT STD_LOGIC; | |||
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68 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |||
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69 | ready_matrix_f1 : OUT STD_LOGIC; | |||
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70 | ready_matrix_f2 : OUT STD_LOGIC; | |||
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71 | --error_anticipating_empty_fifo : OUT STD_LOGIC; | |||
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72 | error_bad_component_error : OUT STD_LOGIC; | |||
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73 | error_buffer_full : OUT STD_LOGIC; | |||
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74 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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75 | ||||
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76 | -- Reg In | |||
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77 | status_ready_matrix_f0 : IN STD_LOGIC; | |||
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78 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |||
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79 | status_ready_matrix_f1 : IN STD_LOGIC; | |||
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80 | status_ready_matrix_f2 : IN STD_LOGIC; | |||
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81 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |||
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82 | -- status_error_bad_component_error : IN STD_LOGIC; | |||
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83 | -- status_error_buffer_full : IN STD_LOGIC; | |||
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84 | ||||
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85 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |||
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86 | config_active_interruption_onError : IN STD_LOGIC; | |||
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87 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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88 | --s addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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89 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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90 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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91 | ||||
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92 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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93 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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94 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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95 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |||
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96 | ||||
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97 | ); | |||
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98 | END; | |||
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99 | ||||
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100 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS | |||
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101 | ----------------------------------------------------------------------------- | |||
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102 | TYPE state_DMAWriteBurst IS (IDLE, | |||
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103 | CHECK_COMPONENT_TYPE, | |||
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104 | WRITE_COARSE_TIME, | |||
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105 | WRITE_FINE_TIME, | |||
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106 | TRASH_FIFO, | |||
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107 | SEND_DATA, | |||
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108 | WAIT_DATA_ACK | |||
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109 | ); | |||
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110 | SIGNAL state : state_DMAWriteBurst; | |||
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111 | ||||
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112 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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113 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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114 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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115 | SIGNAL header_check_ok : STD_LOGIC; | |||
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116 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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117 | SIGNAL send_matrix : STD_LOGIC; | |||
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118 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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119 | ----------------------------------------------------------------------------- | |||
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120 | ----------------------------------------------------------------------------- | |||
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121 | ||||
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122 | SIGNAL component_send : STD_LOGIC; | |||
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123 | SIGNAL component_send_ok : STD_LOGIC; | |||
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124 | -- SIGNAL component_send_ko : STD_LOGIC; | |||
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125 | ----------------------------------------------------------------------------- | |||
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126 | SIGNAL fifo_ren_trash : STD_LOGIC; | |||
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127 | SIGNAL component_fifo_ren : STD_LOGIC; | |||
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128 | ||||
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129 | ----------------------------------------------------------------------------- | |||
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130 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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131 | ----------------------------------------------------------------------------- | |||
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132 | SIGNAL log_empty_fifo : STD_LOGIC; | |||
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133 | ----------------------------------------------------------------------------- | |||
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134 | SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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135 | SIGNAL header_reg_val : STD_LOGIC; | |||
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136 | SIGNAL header_reg_ack : STD_LOGIC; | |||
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137 | SIGNAL header_error : STD_LOGIC; | |||
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138 | ||||
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139 | SIGNAL matrix_buffer_ready : STD_LOGIC; | |||
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140 | BEGIN | |||
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141 | ||||
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142 | debug_reg <= debug_reg_s; | |||
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143 | ||||
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144 | ||||
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145 | matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE | |||
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146 | --'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |||
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147 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE | |||
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148 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE | |||
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149 | '0'; | |||
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150 | ||||
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151 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" | |||
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152 | '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE | |||
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153 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |||
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154 | '0'; | |||
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155 | ||||
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156 | address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE | |||
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157 | --addr_matrix_f0_1 WHEN matrix_type = "01" ELSE | |||
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158 | addr_matrix_f1 WHEN matrix_type = "01" ELSE | |||
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159 | addr_matrix_f2 WHEN matrix_type = "10" ELSE | |||
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160 | (OTHERS => '0'); | |||
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161 | ||||
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162 | ----------------------------------------------------------------------------- | |||
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163 | -- DMA control | |||
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164 | ----------------------------------------------------------------------------- | |||
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165 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |||
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166 | BEGIN | |||
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167 | IF HRESETn = '0' THEN | |||
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168 | matrix_type <= (OTHERS => '0'); | |||
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169 | component_type <= (OTHERS => '0'); | |||
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170 | state <= IDLE; | |||
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171 | ready_matrix_f0 <= '0'; | |||
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172 | -- ready_matrix_f0_1 <= '0'; | |||
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173 | ready_matrix_f1 <= '0'; | |||
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174 | ready_matrix_f2 <= '0'; | |||
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175 | -- error_anticipating_empty_fifo <= '0'; | |||
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176 | error_bad_component_error <= '0'; | |||
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177 | error_buffer_full <= '0'; -- TODO | |||
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178 | component_type_pre <= "0000"; | |||
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179 | fifo_ren_trash <= '1'; | |||
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180 | component_send <= '0'; | |||
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181 | address <= (OTHERS => '0'); | |||
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182 | ||||
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183 | debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); | |||
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184 | debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0'); | |||
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185 | ||||
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186 | log_empty_fifo <= '0'; | |||
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187 | ||||
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188 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |||
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189 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); | |||
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190 | ||||
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191 | ready_matrix_f0 <= '0'; | |||
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192 | -- ready_matrix_f0_1 <= '0'; | |||
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193 | ready_matrix_f1 <= '0'; | |||
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194 | ready_matrix_f2 <= '0'; | |||
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195 | error_bad_component_error <= '0'; | |||
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196 | error_buffer_full <= '0'; | |||
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197 | ||||
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198 | CASE state IS | |||
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199 | WHEN IDLE => | |||
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200 | debug_reg_s(2 DOWNTO 0) <= "000"; | |||
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201 | IF fifo_empty = '0' THEN | |||
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202 | state <= CHECK_COMPONENT_TYPE; | |||
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203 | matrix_type <= fifo_matrix_type; | |||
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204 | component_type <= fifo_matrix_component; | |||
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205 | component_type_pre <= component_type; | |||
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206 | END IF; | |||
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207 | ||||
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208 | log_empty_fifo <= '0'; | |||
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209 | ||||
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210 | WHEN CHECK_COMPONENT_TYPE => | |||
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211 | debug_reg_s(2 DOWNTO 0) <= "001"; | |||
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212 | ||||
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213 | IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN | |||
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214 | IF component_type = "0000" THEN | |||
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215 | address <= address_matrix; | |||
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216 | CASE matrix_type IS | |||
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217 | WHEN "00" => matrix_time_f0 <= fifo_matrix_time; | |||
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218 | WHEN "01" => matrix_time_f1 <= fifo_matrix_time; | |||
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219 | WHEN "10" => matrix_time_f2 <= fifo_matrix_time; | |||
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220 | WHEN OTHERS => NULL; | |||
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221 | END CASE; | |||
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222 | component_send <= '1'; | |||
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223 | END IF; | |||
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224 | state <= SEND_DATA; | |||
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225 | -- | |||
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226 | ELSE | |||
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227 | error_bad_component_error <= NOT header_check_ok; | |||
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228 | error_buffer_full <= NOT matrix_buffer_ready; -- TODO | |||
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229 | component_type_pre <= "0000"; | |||
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230 | state <= TRASH_FIFO; | |||
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231 | END IF; | |||
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232 | ||||
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233 | WHEN TRASH_FIFO => | |||
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234 | debug_reg_s(2 DOWNTO 0) <= "100"; | |||
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235 | ||||
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236 | error_bad_component_error <= '0'; | |||
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237 | -- error_anticipating_empty_fifo <= '0'; | |||
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238 | IF fifo_empty = '1' THEN | |||
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239 | state <= IDLE; | |||
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240 | fifo_ren_trash <= '1'; | |||
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241 | ELSE | |||
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242 | fifo_ren_trash <= '0'; | |||
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243 | END IF; | |||
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244 | ||||
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245 | WHEN SEND_DATA => | |||
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246 | debug_reg_s(2 DOWNTO 0) <= "101"; | |||
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247 | ||||
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248 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN | |||
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249 | state <= IDLE; | |||
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250 | IF component_type = "1110" THEN | |||
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251 | CASE matrix_type IS | |||
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252 | WHEN "00" => ready_matrix_f0 <= '1'; | |||
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253 | WHEN "01" => ready_matrix_f1 <= '1'; | |||
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254 | WHEN "10" => ready_matrix_f2 <= '1'; | |||
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255 | WHEN OTHERS => NULL; | |||
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256 | END CASE; | |||
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257 | END IF; | |||
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258 | ELSE | |||
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259 | component_send <= '1'; | |||
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260 | address <= address; | |||
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261 | state <= WAIT_DATA_ACK; | |||
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262 | END IF; | |||
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263 | ||||
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264 | WHEN WAIT_DATA_ACK => | |||
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265 | log_empty_fifo <= fifo_empty OR log_empty_fifo; | |||
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266 | ||||
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267 | debug_reg_s(2 DOWNTO 0) <= "110"; | |||
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268 | ||||
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269 | component_send <= '0'; | |||
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270 | IF component_send_ok = '1' THEN | |||
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271 | address <= address + 64; | |||
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272 | state <= SEND_DATA; | |||
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273 | -- ELSIF component_send_ko = '1' THEN | |||
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274 | -- error_anticipating_empty_fifo <= '0'; | |||
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275 | -- state <= TRASH_FIFO; | |||
|
276 | END IF; | |||
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277 | ||||
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278 | WHEN OTHERS => NULL; | |||
|
279 | END CASE; | |||
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280 | ||||
|
281 | END IF; | |||
|
282 | END PROCESS DMAWriteFSM_p; | |||
|
283 | ||||
|
284 | dma_valid_burst <= component_send; | |||
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285 | dma_valid <= '0'; | |||
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286 | dma_data <= fifo_data; | |||
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287 | dma_addr <= address; | |||
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288 | fifo_ren <= dma_ren AND fifo_ren_trash; | |||
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289 | ||||
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290 | component_send_ok <= dma_done; | |||
|
291 | -- component_send_ko <= '0'; | |||
|
292 | ||||
|
293 | END Behavioral; |
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