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MS (first version, ok in simulation but whitout data integrity)
pellion -
r361:9b9e33dfcc96 JC
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1 LIBRARY IEEE;
2 USE IEEE.std_logic_1164.ALL;
3
4 LIBRARY lpp;
5 USE lpp.general_purpose.ALL;
6
7 ENTITY MS_calculation IS
8 PORT (
9 clk : IN STD_LOGIC;
10 rstn : IN STD_LOGIC;
11 -- IN
12 fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
13 fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
14 fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
15 -- OUT
16 fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
17 fifo_out_wen : OUT STD_LOGIC;
18 fifo_out_full : IN STD_LOGIC;
19 --
20 correlation_start : IN STD_LOGIC;
21 correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
22
23 correlation_begin : OUT STD_LOGIC;
24 correlation_done : OUT STD_LOGIC
25 );
26 END MS_calculation;
27
28 ARCHITECTURE beh OF MS_calculation IS
29
30 TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a);
31 SIGNAL state : fsm_calculation_MS;
32
33 SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
34 SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
35 SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0);
36
37 SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0);
38
39
40 CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
41 CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010";
42 CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001";
43 CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001";
44
45
46
47 SIGNAL select_op1 : STD_LOGIC;
48 SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
49
50 CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
51 CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
52 CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
53 CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
54
55 SIGNAL res_wen : STD_LOGIC;
56 SIGNAL res_wen_reg1 : STD_LOGIC;
57 -- SIGNAL res_wen_reg2 : STD_LOGIC;
58 --SIGNAL res_wen_reg3 : STD_LOGIC;
59
60 BEGIN
61
62
63
64 PROCESS (clk, rstn)
65 BEGIN
66 IF rstn = '0' THEN
67
68 correlation_begin <= '0';
69 correlation_done <= '0';
70 state <= IDLE;
71 fifo_in_ren <= "11";
72 ALU_CTRL <= ALU_CTRL_NOP;
73 select_op1 <= select_R0(0);
74 select_op2 <= select_R0;
75 res_wen <= '1';
76
77 ELSIF clk'EVENT AND clk = '1' THEN
78 correlation_begin <= '0';
79 fifo_in_ren <= "11";
80 res_wen <= '1';
81 correlation_done <= '0';
82 CASE state IS
83 WHEN IDLE =>
84 IF correlation_start = '1' THEN
85 IF correlation_auto = '1' THEN
86 IF fifo_out_full = '1' THEN
87 state <= WFa;
88 ELSE
89 correlation_begin <= '1';
90 state <= S1a;
91 fifo_in_ren <= "10";
92 END IF;
93 ELSE
94 IF fifo_out_full = '1' THEN
95 state <= WF;
96 ELSE
97 correlation_begin <= '1';
98 state <= S1;
99 fifo_in_ren <= "00";
100 END IF;
101 END IF;
102 END IF;
103
104 ---------------------------------------------------------------------
105 -- INTER CORRELATION
106 ---------------------------------------------------------------------
107 WHEN WF =>
108 IF fifo_out_full = '0' THEN
109 correlation_begin <= '1';
110 state <= S1;
111 fifo_in_ren <= "00";
112 END IF;
113 WHEN S1 =>
114 ALU_CTRL <= ALU_CTRL_MULT;
115 select_op1 <= select_R0(0);
116 select_op2 <= select_R1;
117 state <= S2;
118 WHEN S2 =>
119 ALU_CTRL <= ALU_CTRL_MAC;
120 select_op1 <= select_I0(0);
121 select_op2 <= select_I1;
122 res_wen <= '0';
123 state <= S3;
124 WHEN S3 =>
125 ALU_CTRL <= ALU_CTRL_MULT;
126 select_op1 <= select_I0(0);
127 select_op2 <= select_R1;
128 state <= S4;
129 WHEN S4 =>
130 ALU_CTRL <= ALU_CTRL_MACn;
131 select_op1 <= select_R0(0);
132 select_op2 <= select_I1;
133 res_wen <= '0';
134 IF fifo_in_empty = "00" THEN
135 state <= S1;
136 fifo_in_ren <= "00";
137 ELSE
138 correlation_done <= '1';
139 state <= IDLE;
140 END IF;
141
142
143
144 ---------------------------------------------------------------------
145 -- AUTO CORRELATION
146 ---------------------------------------------------------------------
147 WHEN WFa =>
148 IF fifo_out_full = '0' THEN
149 correlation_begin <= '1';
150 state <= S1a;
151 fifo_in_ren <= "10";
152 END IF;
153 WHEN S1a =>
154 ALU_CTRL <= ALU_CTRL_MULT;
155 select_op1 <= select_R0(0);
156 select_op2 <= select_R0;
157 state <= S2a;
158 WHEN S2a =>
159 ALU_CTRL <= ALU_CTRL_MAC;
160 select_op1 <= select_I0(0);
161 select_op2 <= select_I0;
162 res_wen <= '0';
163 IF fifo_in_empty(0) = '0' THEN
164 state <= S1a;
165 fifo_in_ren <= "10";
166 ELSE
167 correlation_done <= '1';
168 state <= IDLE;
169 END IF;
170
171
172 WHEN OTHERS => NULL;
173 END CASE;
174
175 END IF;
176 END PROCESS;
177
178 OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE
179 fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE
180
181 OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE
182 fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE
183 fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE
184 fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE
185
186 ALU_MS : ALU
187 GENERIC MAP (
188 Arith_en => 1,
189 Logic_en => 0,
190 Input_SZ_1 => 16,
191 Input_SZ_2 => 16,
192 COMP_EN => 1)
193 PORT MAP (
194 clk => clk,
195 reset => rstn,
196
197 ctrl => ALU_CTRL(2 DOWNTO 0),
198 comp => ALU_CTRL(4 DOWNTO 3),
199
200 OP1 => OP1,
201 OP2 => OP2,
202
203 RES => RES);
204
205 fifo_out_data <= RES;
206
207
208 PROCESS (clk, rstn)
209 BEGIN
210 IF rstn = '0' THEN
211 res_wen_reg1 <= '1';
212 --res_wen_reg2 <= '1';
213 --res_wen_reg3 <= '1';
214 fifo_out_wen <= '1';
215 ELSIF clk'event AND clk = '1' THEN
216 res_wen_reg1 <= res_wen;
217 --res_wen_reg2 <= res_wen_reg1;
218 --res_wen_reg3 <= res_wen_reg2;
219 fifo_out_wen <= res_wen_reg1;
220 END IF;
221 END PROCESS;
222
223
224 END beh;
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1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY lpp;
33 USE lpp.lpp_amba.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_dma_pkg.ALL;
37 LIBRARY techmap;
38 USE techmap.gencomp.ALL;
39
40
41 ENTITY lpp_lfr_ms_fsmdma IS
42 PORT (
43 -- AMBA AHB system signals
44 HCLK : IN STD_ULOGIC;
45 HRESETn : IN STD_ULOGIC;
46
47 ---------------------------------------------------------------------------
48 -- FIFO - IN
49 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_empty : IN STD_LOGIC;
54 fifo_ren : OUT STD_LOGIC;
55
56 ---------------------------------------------------------------------------
57 -- DMA - OUT
58 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 dma_valid : OUT STD_LOGIC;
61 dma_valid_burst : OUT STD_LOGIC;
62 dma_ren : IN STD_LOGIC;
63 dma_done : IN STD_LOGIC;
64
65 ---------------------------------------------------------------------------
66 -- Reg out
67 ready_matrix_f0 : OUT STD_LOGIC;
68 -- ready_matrix_f0_1 : OUT STD_LOGIC;
69 ready_matrix_f1 : OUT STD_LOGIC;
70 ready_matrix_f2 : OUT STD_LOGIC;
71 --error_anticipating_empty_fifo : OUT STD_LOGIC;
72 error_bad_component_error : OUT STD_LOGIC;
73 error_buffer_full : OUT STD_LOGIC;
74 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
75
76 -- Reg In
77 status_ready_matrix_f0 : IN STD_LOGIC;
78 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
79 status_ready_matrix_f1 : IN STD_LOGIC;
80 status_ready_matrix_f2 : IN STD_LOGIC;
81 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
82 -- status_error_bad_component_error : IN STD_LOGIC;
83 -- status_error_buffer_full : IN STD_LOGIC;
84
85 config_active_interruption_onNewMatrix : IN STD_LOGIC;
86 config_active_interruption_onError : IN STD_LOGIC;
87 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --s addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91
92 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
93 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
96
97 );
98 END;
99
100 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
101 -----------------------------------------------------------------------------
102 TYPE state_DMAWriteBurst IS (IDLE,
103 CHECK_COMPONENT_TYPE,
104 WRITE_COARSE_TIME,
105 WRITE_FINE_TIME,
106 TRASH_FIFO,
107 SEND_DATA,
108 WAIT_DATA_ACK
109 );
110 SIGNAL state : state_DMAWriteBurst;
111
112 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
113 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
114 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
115 SIGNAL header_check_ok : STD_LOGIC;
116 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
117 SIGNAL send_matrix : STD_LOGIC;
118 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
121
122 SIGNAL component_send : STD_LOGIC;
123 SIGNAL component_send_ok : STD_LOGIC;
124 -- SIGNAL component_send_ko : STD_LOGIC;
125 -----------------------------------------------------------------------------
126 SIGNAL fifo_ren_trash : STD_LOGIC;
127 SIGNAL component_fifo_ren : STD_LOGIC;
128
129 -----------------------------------------------------------------------------
130 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 -----------------------------------------------------------------------------
132 SIGNAL log_empty_fifo : STD_LOGIC;
133 -----------------------------------------------------------------------------
134 SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 SIGNAL header_reg_val : STD_LOGIC;
136 SIGNAL header_reg_ack : STD_LOGIC;
137 SIGNAL header_error : STD_LOGIC;
138
139 SIGNAL matrix_buffer_ready : STD_LOGIC;
140 BEGIN
141
142 debug_reg <= debug_reg_s;
143
144
145 matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
146 --'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
147 '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE
148 '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE
149 '0';
150
151 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
152 '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE
153 '1' WHEN component_type = component_type_pre + "0001" ELSE
154 '0';
155
156 address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
157 --addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
158 addr_matrix_f1 WHEN matrix_type = "01" ELSE
159 addr_matrix_f2 WHEN matrix_type = "10" ELSE
160 (OTHERS => '0');
161
162 -----------------------------------------------------------------------------
163 -- DMA control
164 -----------------------------------------------------------------------------
165 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
166 BEGIN
167 IF HRESETn = '0' THEN
168 matrix_type <= (OTHERS => '0');
169 component_type <= (OTHERS => '0');
170 state <= IDLE;
171 ready_matrix_f0 <= '0';
172 -- ready_matrix_f0_1 <= '0';
173 ready_matrix_f1 <= '0';
174 ready_matrix_f2 <= '0';
175 -- error_anticipating_empty_fifo <= '0';
176 error_bad_component_error <= '0';
177 error_buffer_full <= '0'; -- TODO
178 component_type_pre <= "0000";
179 fifo_ren_trash <= '1';
180 component_send <= '0';
181 address <= (OTHERS => '0');
182
183 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
184 debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0');
185
186 log_empty_fifo <= '0';
187
188 ELSIF HCLK'EVENT AND HCLK = '1' THEN
189 debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
190
191 ready_matrix_f0 <= '0';
192 -- ready_matrix_f0_1 <= '0';
193 ready_matrix_f1 <= '0';
194 ready_matrix_f2 <= '0';
195 error_bad_component_error <= '0';
196 error_buffer_full <= '0';
197
198 CASE state IS
199 WHEN IDLE =>
200 debug_reg_s(2 DOWNTO 0) <= "000";
201 IF fifo_empty = '0' THEN
202 state <= CHECK_COMPONENT_TYPE;
203 matrix_type <= fifo_matrix_type;
204 component_type <= fifo_matrix_component;
205 component_type_pre <= component_type;
206 END IF;
207
208 log_empty_fifo <= '0';
209
210 WHEN CHECK_COMPONENT_TYPE =>
211 debug_reg_s(2 DOWNTO 0) <= "001";
212
213 IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN
214 IF component_type = "0000" THEN
215 address <= address_matrix;
216 CASE matrix_type IS
217 WHEN "00" => matrix_time_f0 <= fifo_matrix_time;
218 WHEN "01" => matrix_time_f1 <= fifo_matrix_time;
219 WHEN "10" => matrix_time_f2 <= fifo_matrix_time;
220 WHEN OTHERS => NULL;
221 END CASE;
222 component_send <= '1';
223 END IF;
224 state <= SEND_DATA;
225 --
226 ELSE
227 error_bad_component_error <= NOT header_check_ok;
228 error_buffer_full <= NOT matrix_buffer_ready; -- TODO
229 component_type_pre <= "0000";
230 state <= TRASH_FIFO;
231 END IF;
232
233 WHEN TRASH_FIFO =>
234 debug_reg_s(2 DOWNTO 0) <= "100";
235
236 error_bad_component_error <= '0';
237 -- error_anticipating_empty_fifo <= '0';
238 IF fifo_empty = '1' THEN
239 state <= IDLE;
240 fifo_ren_trash <= '1';
241 ELSE
242 fifo_ren_trash <= '0';
243 END IF;
244
245 WHEN SEND_DATA =>
246 debug_reg_s(2 DOWNTO 0) <= "101";
247
248 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
249 state <= IDLE;
250 IF component_type = "1110" THEN
251 CASE matrix_type IS
252 WHEN "00" => ready_matrix_f0 <= '1';
253 WHEN "01" => ready_matrix_f1 <= '1';
254 WHEN "10" => ready_matrix_f2 <= '1';
255 WHEN OTHERS => NULL;
256 END CASE;
257 END IF;
258 ELSE
259 component_send <= '1';
260 address <= address;
261 state <= WAIT_DATA_ACK;
262 END IF;
263
264 WHEN WAIT_DATA_ACK =>
265 log_empty_fifo <= fifo_empty OR log_empty_fifo;
266
267 debug_reg_s(2 DOWNTO 0) <= "110";
268
269 component_send <= '0';
270 IF component_send_ok = '1' THEN
271 address <= address + 64;
272 state <= SEND_DATA;
273 -- ELSIF component_send_ko = '1' THEN
274 -- error_anticipating_empty_fifo <= '0';
275 -- state <= TRASH_FIFO;
276 END IF;
277
278 WHEN OTHERS => NULL;
279 END CASE;
280
281 END IF;
282 END PROCESS DMAWriteFSM_p;
283
284 dma_valid_burst <= component_send;
285 dma_valid <= '0';
286 dma_data <= fifo_data;
287 dma_addr <= address;
288 fifo_ren <= dma_ren AND fifo_ren_trash;
289
290 component_send_ok <= dma_done;
291 -- component_send_ko <= '0';
292
293 END Behavioral;
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