diff --git a/designs/Validation_LFR_SpectralMatrix/MS_calculation.vhd b/designs/Validation_LFR_SpectralMatrix/MS_calculation.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/MS_calculation.vhd @@ -0,0 +1,224 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +LIBRARY lpp; +USE lpp.general_purpose.ALL; + +ENTITY MS_calculation IS + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + -- IN + fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); + fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + -- OUT + fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0); + fifo_out_wen : OUT STD_LOGIC; + fifo_out_full : IN STD_LOGIC; + -- + correlation_start : IN STD_LOGIC; + correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation + + correlation_begin : OUT STD_LOGIC; + correlation_done : OUT STD_LOGIC + ); +END MS_calculation; + +ARCHITECTURE beh OF MS_calculation IS + + TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a); + SIGNAL state : fsm_calculation_MS; + + SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0); + + + CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000"; + CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010"; + CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001"; + CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001"; + + + + SIGNAL select_op1 : STD_LOGIC; + SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ; + + CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; + CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; + CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; + CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; + + SIGNAL res_wen : STD_LOGIC; + SIGNAL res_wen_reg1 : STD_LOGIC; +-- SIGNAL res_wen_reg2 : STD_LOGIC; + --SIGNAL res_wen_reg3 : STD_LOGIC; + +BEGIN + + + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + + correlation_begin <= '0'; + correlation_done <= '0'; + state <= IDLE; + fifo_in_ren <= "11"; + ALU_CTRL <= ALU_CTRL_NOP; + select_op1 <= select_R0(0); + select_op2 <= select_R0; + res_wen <= '1'; + + ELSIF clk'EVENT AND clk = '1' THEN + correlation_begin <= '0'; + fifo_in_ren <= "11"; + res_wen <= '1'; + correlation_done <= '0'; + CASE state IS + WHEN IDLE => + IF correlation_start = '1' THEN + IF correlation_auto = '1' THEN + IF fifo_out_full = '1' THEN + state <= WFa; + ELSE + correlation_begin <= '1'; + state <= S1a; + fifo_in_ren <= "10"; + END IF; + ELSE + IF fifo_out_full = '1' THEN + state <= WF; + ELSE + correlation_begin <= '1'; + state <= S1; + fifo_in_ren <= "00"; + END IF; + END IF; + END IF; + + --------------------------------------------------------------------- + -- INTER CORRELATION + --------------------------------------------------------------------- + WHEN WF => + IF fifo_out_full = '0' THEN + correlation_begin <= '1'; + state <= S1; + fifo_in_ren <= "00"; + END IF; + WHEN S1 => + ALU_CTRL <= ALU_CTRL_MULT; + select_op1 <= select_R0(0); + select_op2 <= select_R1; + state <= S2; + WHEN S2 => + ALU_CTRL <= ALU_CTRL_MAC; + select_op1 <= select_I0(0); + select_op2 <= select_I1; + res_wen <= '0'; + state <= S3; + WHEN S3 => + ALU_CTRL <= ALU_CTRL_MULT; + select_op1 <= select_I0(0); + select_op2 <= select_R1; + state <= S4; + WHEN S4 => + ALU_CTRL <= ALU_CTRL_MACn; + select_op1 <= select_R0(0); + select_op2 <= select_I1; + res_wen <= '0'; + IF fifo_in_empty = "00" THEN + state <= S1; + fifo_in_ren <= "00"; + ELSE + correlation_done <= '1'; + state <= IDLE; + END IF; + + + + --------------------------------------------------------------------- + -- AUTO CORRELATION + --------------------------------------------------------------------- + WHEN WFa => + IF fifo_out_full = '0' THEN + correlation_begin <= '1'; + state <= S1a; + fifo_in_ren <= "10"; + END IF; + WHEN S1a => + ALU_CTRL <= ALU_CTRL_MULT; + select_op1 <= select_R0(0); + select_op2 <= select_R0; + state <= S2a; + WHEN S2a => + ALU_CTRL <= ALU_CTRL_MAC; + select_op1 <= select_I0(0); + select_op2 <= select_I0; + res_wen <= '0'; + IF fifo_in_empty(0) = '0' THEN + state <= S1a; + fifo_in_ren <= "10"; + ELSE + correlation_done <= '1'; + state <= IDLE; + END IF; + + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + + OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE + fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE + + OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE + fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE + fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE + fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE + + ALU_MS : ALU + GENERIC MAP ( + Arith_en => 1, + Logic_en => 0, + Input_SZ_1 => 16, + Input_SZ_2 => 16, + COMP_EN => 1) + PORT MAP ( + clk => clk, + reset => rstn, + + ctrl => ALU_CTRL(2 DOWNTO 0), + comp => ALU_CTRL(4 DOWNTO 3), + + OP1 => OP1, + OP2 => OP2, + + RES => RES); + + fifo_out_data <= RES; + + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + res_wen_reg1 <= '1'; + --res_wen_reg2 <= '1'; + --res_wen_reg3 <= '1'; + fifo_out_wen <= '1'; + ELSIF clk'event AND clk = '1' THEN + res_wen_reg1 <= res_wen; + --res_wen_reg2 <= res_wen_reg1; + --res_wen_reg3 <= res_wen_reg2; + fifo_out_wen <= res_wen_reg1; + END IF; + END PROCESS; + + +END beh; diff --git a/designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms_fsmdma.vhd b/designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms_fsmdma.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms_fsmdma.vhd @@ -0,0 +1,293 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_dma_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + + +ENTITY lpp_lfr_ms_fsmdma IS + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + --------------------------------------------------------------------------- + -- FIFO - IN + fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fifo_empty : IN STD_LOGIC; + fifo_ren : OUT STD_LOGIC; + + --------------------------------------------------------------------------- + -- DMA - OUT + dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_valid : OUT STD_LOGIC; + dma_valid_burst : OUT STD_LOGIC; + dma_ren : IN STD_LOGIC; + dma_done : IN STD_LOGIC; + + --------------------------------------------------------------------------- + -- Reg out + ready_matrix_f0 : OUT STD_LOGIC; +-- ready_matrix_f0_1 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + --error_anticipating_empty_fifo : OUT STD_LOGIC; + error_bad_component_error : OUT STD_LOGIC; + error_buffer_full : OUT STD_LOGIC; + debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- Reg In + status_ready_matrix_f0 : IN STD_LOGIC; +-- status_ready_matrix_f0_1 : IN STD_LOGIC; + status_ready_matrix_f1 : IN STD_LOGIC; + status_ready_matrix_f2 : IN STD_LOGIC; +-- status_error_anticipating_empty_fifo : IN STD_LOGIC; +-- status_error_bad_component_error : IN STD_LOGIC; +-- status_error_buffer_full : IN STD_LOGIC; + + config_active_interruption_onNewMatrix : IN STD_LOGIC; + config_active_interruption_onError : IN STD_LOGIC; + addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); +--s addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); +-- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + + ); +END; + +ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS + ----------------------------------------------------------------------------- + TYPE state_DMAWriteBurst IS (IDLE, + CHECK_COMPONENT_TYPE, + WRITE_COARSE_TIME, + WRITE_FINE_TIME, + TRASH_FIFO, + SEND_DATA, + WAIT_DATA_ACK + ); + SIGNAL state : state_DMAWriteBurst; + + SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL header_check_ok : STD_LOGIC; + SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL send_matrix : STD_LOGIC; + SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + + SIGNAL component_send : STD_LOGIC; + SIGNAL component_send_ok : STD_LOGIC; +-- SIGNAL component_send_ko : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL fifo_ren_trash : STD_LOGIC; + SIGNAL component_fifo_ren : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL log_empty_fifo : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL header_reg_val : STD_LOGIC; + SIGNAL header_reg_ack : STD_LOGIC; + SIGNAL header_error : STD_LOGIC; + + SIGNAL matrix_buffer_ready : STD_LOGIC; +BEGIN + + debug_reg <= debug_reg_s; + + + matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE + --'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE + '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE + '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE + '0'; + + header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" + '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE + '1' WHEN component_type = component_type_pre + "0001" ELSE + '0'; + + address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE + --addr_matrix_f0_1 WHEN matrix_type = "01" ELSE + addr_matrix_f1 WHEN matrix_type = "01" ELSE + addr_matrix_f2 WHEN matrix_type = "10" ELSE + (OTHERS => '0'); + + ----------------------------------------------------------------------------- + -- DMA control + ----------------------------------------------------------------------------- + DMAWriteFSM_p : PROCESS (HCLK, HRESETn) + BEGIN + IF HRESETn = '0' THEN + matrix_type <= (OTHERS => '0'); + component_type <= (OTHERS => '0'); + state <= IDLE; + ready_matrix_f0 <= '0'; +-- ready_matrix_f0_1 <= '0'; + ready_matrix_f1 <= '0'; + ready_matrix_f2 <= '0'; +-- error_anticipating_empty_fifo <= '0'; + error_bad_component_error <= '0'; + error_buffer_full <= '0'; -- TODO + component_type_pre <= "0000"; + fifo_ren_trash <= '1'; + component_send <= '0'; + address <= (OTHERS => '0'); + + debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); + debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0'); + + log_empty_fifo <= '0'; + + ELSIF HCLK'EVENT AND HCLK = '1' THEN + debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); + + ready_matrix_f0 <= '0'; +-- ready_matrix_f0_1 <= '0'; + ready_matrix_f1 <= '0'; + ready_matrix_f2 <= '0'; + error_bad_component_error <= '0'; + error_buffer_full <= '0'; + + CASE state IS + WHEN IDLE => + debug_reg_s(2 DOWNTO 0) <= "000"; + IF fifo_empty = '0' THEN + state <= CHECK_COMPONENT_TYPE; + matrix_type <= fifo_matrix_type; + component_type <= fifo_matrix_component; + component_type_pre <= component_type; + END IF; + + log_empty_fifo <= '0'; + + WHEN CHECK_COMPONENT_TYPE => + debug_reg_s(2 DOWNTO 0) <= "001"; + + IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN + IF component_type = "0000" THEN + address <= address_matrix; + CASE matrix_type IS + WHEN "00" => matrix_time_f0 <= fifo_matrix_time; + WHEN "01" => matrix_time_f1 <= fifo_matrix_time; + WHEN "10" => matrix_time_f2 <= fifo_matrix_time; + WHEN OTHERS => NULL; + END CASE; + component_send <= '1'; + END IF; + state <= SEND_DATA; + -- + ELSE + error_bad_component_error <= NOT header_check_ok; + error_buffer_full <= NOT matrix_buffer_ready; -- TODO + component_type_pre <= "0000"; + state <= TRASH_FIFO; + END IF; + + WHEN TRASH_FIFO => + debug_reg_s(2 DOWNTO 0) <= "100"; + + error_bad_component_error <= '0'; +-- error_anticipating_empty_fifo <= '0'; + IF fifo_empty = '1' THEN + state <= IDLE; + fifo_ren_trash <= '1'; + ELSE + fifo_ren_trash <= '0'; + END IF; + + WHEN SEND_DATA => + debug_reg_s(2 DOWNTO 0) <= "101"; + + IF fifo_empty = '1' OR log_empty_fifo = '1' THEN + state <= IDLE; + IF component_type = "1110" THEN + CASE matrix_type IS + WHEN "00" => ready_matrix_f0 <= '1'; + WHEN "01" => ready_matrix_f1 <= '1'; + WHEN "10" => ready_matrix_f2 <= '1'; + WHEN OTHERS => NULL; + END CASE; + END IF; + ELSE + component_send <= '1'; + address <= address; + state <= WAIT_DATA_ACK; + END IF; + + WHEN WAIT_DATA_ACK => + log_empty_fifo <= fifo_empty OR log_empty_fifo; + + debug_reg_s(2 DOWNTO 0) <= "110"; + + component_send <= '0'; + IF component_send_ok = '1' THEN + address <= address + 64; + state <= SEND_DATA; +-- ELSIF component_send_ko = '1' THEN +-- error_anticipating_empty_fifo <= '0'; +-- state <= TRASH_FIFO; + END IF; + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS DMAWriteFSM_p; + + dma_valid_burst <= component_send; + dma_valid <= '0'; + dma_data <= fifo_data; + dma_addr <= address; + fifo_ren <= dma_ren AND fifo_ren_trash; + + component_send_ok <= dma_done; +-- component_send_ko <= '0'; + +END Behavioral;