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1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 09:21:03 10/19/2010 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: FRAME_CLK_GEN - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
|
21 | use IEEE.STD_LOGIC_1164.ALL; | |
|
22 | use IEEE.NUMERIC_STD.ALL; | |
|
23 | ||
|
24 | ||
|
25 | entity FRAME_CLK_GEN is | |
|
26 | generic(OSC_freqKHz : integer := 50000); | |
|
27 | Port ( clk : in STD_LOGIC; | |
|
28 | reset : in STD_LOGIC; | |
|
29 | FRAME_CLK : out STD_LOGIC); | |
|
30 | end FRAME_CLK_GEN; | |
|
31 | ||
|
32 | architecture Behavioral of FRAME_CLK_GEN is | |
|
33 | ||
|
34 | Constant Goal_FRAME_CLK_FREQ : integer := 20; | |
|
35 | ||
|
36 | Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1; | |
|
37 | ||
|
38 | signal CPT : integer := 0; | |
|
39 | signal FRAME_CLK_reg : std_logic :='0'; | |
|
40 | ||
|
41 | begin | |
|
42 | ||
|
43 | FRAME_CLK <= FRAME_CLK_reg; | |
|
44 | ||
|
45 | process(reset,clk) | |
|
46 | begin | |
|
47 | if reset = '0' then | |
|
48 | CPT <= 0; | |
|
49 | FRAME_CLK_reg <= '0'; | |
|
50 | elsif clk'event and clk = '1' then | |
|
51 | if CPT = FRAME_CLK_TRIG then | |
|
52 | CPT <= 0; | |
|
53 | FRAME_CLK_reg <= not FRAME_CLK_reg; | |
|
54 | else | |
|
55 | CPT <= CPT + 1; | |
|
56 | end if; | |
|
57 | end if; | |
|
58 | end process; | |
|
59 | end Behavioral; | |
|
60 | ||
|
61 | ||
|
62 | ||
|
63 | ||
|
64 | ||
|
65 | ||
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66 | ||
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67 | ||
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68 |
@@ -0,0 +1,57 | |||
|
1 | -- Package File Template | |
|
2 | -- | |
|
3 | -- Purpose: This package defines supplemental types, subtypes, | |
|
4 | -- constants, and functions | |
|
5 | ||
|
6 | ||
|
7 | library IEEE; | |
|
8 | use IEEE.STD_LOGIC_1164.all; | |
|
9 | ||
|
10 | package LCD_16x2_CFG is | |
|
11 | ||
|
12 | type LCD_DRVR_CTRL_BUSS is | |
|
13 | record | |
|
14 | LCD_RW : std_logic; | |
|
15 | LCD_RS : std_logic; | |
|
16 | LCD_E : std_logic; | |
|
17 | LCD_DATA : std_logic_vector(7 downto 0); | |
|
18 | end record; | |
|
19 | ||
|
20 | type LCD_DRVR_SYNCH_BUSS is | |
|
21 | record | |
|
22 | DRVR_READY : std_logic; | |
|
23 | LCD_INITIALISED : std_logic; | |
|
24 | end record; | |
|
25 | ||
|
26 | ||
|
27 | type LCD_DRVR_CMD_BUSS is | |
|
28 | record | |
|
29 | Word : std_logic_vector(7 downto 0); | |
|
30 | CMD_Data : std_logic; --CMD = '0' and data = '1' | |
|
31 | Exec : std_logic; | |
|
32 | Duration : std_logic_vector(1 downto 0); | |
|
33 | end record; | |
|
34 | type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0); | |
|
35 | ||
|
36 | ||
|
37 | constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01"; | |
|
38 | constant FunctionSet : std_logic_vector(7 downto 0):= X"38"; | |
|
39 | constant RetHome : std_logic_vector(7 downto 0):= X"02"; | |
|
40 | constant SetEntryMode : std_logic_vector(7 downto 0):= X"06"; | |
|
41 | constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0C"; | |
|
42 | ||
|
43 | constant CursorON : std_logic_vector(7 downto 0):= X"0E"; | |
|
44 | constant CursorOFF : std_logic_vector(7 downto 0):= X"0C"; | |
|
45 | ||
|
46 | --===========================================================| | |
|
47 | --======L C D D R I V E R T I M I N G C O D E=====| | |
|
48 | --===========================================================| | |
|
49 | ||
|
50 | constant Duration_4us : std_logic_vector(1 downto 0) := "00"; | |
|
51 | constant Duration_100us : std_logic_vector(1 downto 0) := "01"; | |
|
52 | constant Duration_4ms : std_logic_vector(1 downto 0) := "10"; | |
|
53 | constant Duration_20ms : std_logic_vector(1 downto 0) := "11"; | |
|
54 | ||
|
55 | ||
|
56 | end LCD_16x2_CFG; | |
|
57 |
@@ -0,0 +1,206 | |||
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1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 08:32:21 10/19/2010 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: LCD_16x2_ENGINE - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
|
21 | use IEEE.STD_LOGIC_1164.ALL; | |
|
22 | use IEEE.NUMERIC_STD.ALL; | |
|
23 | use work.LCD_16x2_CFG.all; | |
|
24 | ||
|
25 | entity LCD_16x2_ENGINE is | |
|
26 | generic(OSC_freqKHz : integer := 50000); | |
|
27 | Port ( clk : in STD_LOGIC; | |
|
28 | reset : in STD_LOGIC; | |
|
29 | DATA : in std_logic_vector(16*2*8-1 downto 0); | |
|
30 | CMD : in std_logic_vector(10 downto 0); | |
|
31 | Exec : in std_logic; | |
|
32 | Ready : out std_logic; | |
|
33 | LCD_CTRL : out LCD_DRVR_CTRL_BUSS | |
|
34 | ); | |
|
35 | end LCD_16x2_ENGINE; | |
|
36 | ||
|
37 | architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is | |
|
38 | ||
|
39 | constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome); | |
|
40 | ||
|
41 | ||
|
42 | ||
|
43 | signal SYNCH : LCD_DRVR_SYNCH_BUSS; | |
|
44 | signal DRIVER_CMD : LCD_DRVR_CMD_BUSS; | |
|
45 | signal FRAME_CLK : std_logic; | |
|
46 | ||
|
47 | signal FRAME_CLK_reg : std_logic; | |
|
48 | signal RefreshFlag : std_logic; | |
|
49 | signal CMD_Flag : std_logic; | |
|
50 | signal Exec_Reg : std_logic; | |
|
51 | ||
|
52 | type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1); | |
|
53 | signal state : state_t; | |
|
54 | signal i : integer range 0 to 32 := 0; | |
|
55 | ||
|
56 | ||
|
57 | ||
|
58 | begin | |
|
59 | ||
|
60 | Driver0 : entity work.LCD_16x2_DRIVER | |
|
61 | generic map(OSC_freqKHz) | |
|
62 | Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD); | |
|
63 | ||
|
64 | FRAME_CLK_GEN0 : entity work.FRAME_CLK_GEN | |
|
65 | generic map(OSC_freqKHz) | |
|
66 | Port map( clk,reset,FRAME_CLK); | |
|
67 | ||
|
68 | ||
|
69 | ||
|
70 | process(reset,clk) | |
|
71 | begin | |
|
72 | if reset = '0' then | |
|
73 | state <= INIT0; | |
|
74 | Ready <= '0'; | |
|
75 | RefreshFlag <= '0'; | |
|
76 | i <= 0; | |
|
77 | elsif clk'event and clk ='1' then | |
|
78 | FRAME_CLK_reg <= FRAME_CLK; | |
|
79 | Exec_Reg <= Exec; | |
|
80 | ||
|
81 | if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then | |
|
82 | RefreshFlag <= '1'; | |
|
83 | elsif state = Refresh or state = Refresh0 or state = Refresh1 then | |
|
84 | RefreshFlag <= '0'; | |
|
85 | end if; | |
|
86 | ||
|
87 | if Exec_Reg = '0' and Exec = '1' then | |
|
88 | CMD_Flag <= '1'; | |
|
89 | elsif state = ExecCMD0 or state = ExecCMD1 then | |
|
90 | CMD_Flag <= '0'; | |
|
91 | end if; | |
|
92 | ||
|
93 | case state is | |
|
94 | when INIT0 => | |
|
95 | if SYNCH.DRVR_READY = '1' then | |
|
96 | DRIVER_CMD.Exec <= '1'; | |
|
97 | DRIVER_CMD.Duration <= Duration_20ms; | |
|
98 | DRIVER_CMD.CMD_Data <= '0'; | |
|
99 | DRIVER_CMD.Word <= ConfigTbl(i); | |
|
100 | i <= i + 1; | |
|
101 | state <= INIT1; | |
|
102 | else | |
|
103 | DRIVER_CMD.Exec <= '0'; | |
|
104 | end if; | |
|
105 | when INIT1 => | |
|
106 | state <= INIT2; | |
|
107 | DRIVER_CMD.Exec <= '0'; | |
|
108 | when INIT2 => | |
|
109 | if SYNCH.DRVR_READY = '1' then | |
|
110 | if i = 5 then | |
|
111 | state <= Idle; | |
|
112 | else | |
|
113 | state <= INIT0; | |
|
114 | end if; | |
|
115 | end if; | |
|
116 | when Idle=> | |
|
117 | DRIVER_CMD.Exec <= '0'; | |
|
118 | if RefreshFlag = '1' then | |
|
119 | Ready <= '0'; | |
|
120 | state <= Refresh; | |
|
121 | elsif CMD_Flag = '1' then | |
|
122 | Ready <= '0'; | |
|
123 | state <= ExecCMD0; | |
|
124 | else | |
|
125 | Ready <= '1'; | |
|
126 | end if; | |
|
127 | i <= 0; | |
|
128 | when Refresh=> | |
|
129 | if SYNCH.DRVR_READY = '1' then | |
|
130 | DRIVER_CMD.Exec <= '1'; | |
|
131 | DRIVER_CMD.Duration <= Duration_100us; | |
|
132 | DRIVER_CMD.CMD_Data <= '1'; | |
|
133 | DRIVER_CMD.Word <= DATA(i*8+7 downto i*8); | |
|
134 | i <= i + 1; | |
|
135 | state <= Refresh0; | |
|
136 | else | |
|
137 | DRIVER_CMD.Exec <= '0'; | |
|
138 | end if; | |
|
139 | when Refresh0=> | |
|
140 | state <= Refresh1; | |
|
141 | DRIVER_CMD.Exec <= '0'; | |
|
142 | when Refresh1=> | |
|
143 | if SYNCH.DRVR_READY = '1' then | |
|
144 | if i = 32 then | |
|
145 | state <= ReturnHome; | |
|
146 | elsif i = 16 then | |
|
147 | state <= GoLine2; | |
|
148 | else | |
|
149 | state <= Refresh; | |
|
150 | end if; | |
|
151 | end if; | |
|
152 | ||
|
153 | when ExecCMD0=> | |
|
154 | if SYNCH.DRVR_READY = '1' then | |
|
155 | DRIVER_CMD.Exec <= '1'; | |
|
156 | DRIVER_CMD.Duration <= CMD(9 downto 8); | |
|
157 | DRIVER_CMD.CMD_Data <= '0'; | |
|
158 | DRIVER_CMD.Word <= CMD(7 downto 0); | |
|
159 | state <= ExecCMD1; | |
|
160 | else | |
|
161 | DRIVER_CMD.Exec <= '0'; | |
|
162 | end if; | |
|
163 | ||
|
164 | when ExecCMD1=> | |
|
165 | state <= Idle; | |
|
166 | DRIVER_CMD.Exec <= '0'; | |
|
167 | ||
|
168 | when GoLine2=> | |
|
169 | if SYNCH.DRVR_READY = '1' then | |
|
170 | DRIVER_CMD.Exec <= '1'; | |
|
171 | DRIVER_CMD.Duration <= Duration_100us; | |
|
172 | DRIVER_CMD.CMD_Data <= '0'; | |
|
173 | DRIVER_CMD.Word <= X"C0"; | |
|
174 | state <= GoLine2_0; | |
|
175 | else | |
|
176 | DRIVER_CMD.Exec <= '0'; | |
|
177 | end if; | |
|
178 | when GoLine2_0=> | |
|
179 | state <= Refresh; | |
|
180 | DRIVER_CMD.Exec <= '0'; | |
|
181 | when ReturnHome=> | |
|
182 | if SYNCH.DRVR_READY = '1' then | |
|
183 | DRIVER_CMD.Exec <= '1'; | |
|
184 | DRIVER_CMD.Duration <= Duration_4ms; | |
|
185 | DRIVER_CMD.CMD_Data <= '0'; | |
|
186 | DRIVER_CMD.Word <= X"02"; | |
|
187 | state <= Idle; | |
|
188 | else | |
|
189 | DRIVER_CMD.Exec <= '0'; | |
|
190 | end if; | |
|
191 | end case; | |
|
192 | end if; | |
|
193 | end process; | |
|
194 | ||
|
195 | ||
|
196 | end ar_LCD_16x2_ENGINE; | |
|
197 | ||
|
198 | ||
|
199 | ||
|
200 | ||
|
201 | ||
|
202 | ||
|
203 | ||
|
204 | ||
|
205 | ||
|
206 |
@@ -0,0 +1,156 | |||
|
1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 10:09:57 10/13/2010 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: LCD_2x16_DRIVER - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
|
21 | use IEEE.STD_LOGIC_1164.ALL; | |
|
22 | use IEEE.NUMERIC_STD.all; | |
|
23 | ||
|
24 | ||
|
25 | entity LCD_2x16_DRIVER is | |
|
26 | generic( | |
|
27 | OSC_Freq_MHz : integer:=60; | |
|
28 | Refresh_RateHz : integer:=5 | |
|
29 | ); | |
|
30 | Port ( clk : in STD_LOGIC; | |
|
31 | reset : in STD_LOGIC; | |
|
32 | FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0); | |
|
33 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); | |
|
34 | LCD_RS : out STD_LOGIC; | |
|
35 | LCD_RW : out STD_LOGIC; | |
|
36 | LCD_E : out STD_LOGIC; | |
|
37 | LCD_RET : out STD_LOGIC; | |
|
38 | LCD_CS1 : out STD_LOGIC; | |
|
39 | LCD_CS2 : out STD_LOGIC; | |
|
40 | STATEOUT: out std_logic_vector(3 downto 0); | |
|
41 | refreshPulse : out std_logic | |
|
42 | ); | |
|
43 | end LCD_2x16_DRIVER; | |
|
44 | ||
|
45 | architecture Behavioral of LCD_2x16_DRIVER is | |
|
46 | ||
|
47 | type stateT is(Rst,Configure,IDLE,RefreshScreen); | |
|
48 | signal state : stateT; | |
|
49 | ||
|
50 | signal ShortTimePulse : std_logic; | |
|
51 | signal MidleTimePulse : std_logic; | |
|
52 | signal Refresh_RatePulse : std_logic; | |
|
53 | signal Start : STD_LOGIC; | |
|
54 | ||
|
55 | signal CFGM_LCD_RS : std_logic; | |
|
56 | signal CFGM_LCD_RW : std_logic; | |
|
57 | signal CFGM_LCD_E : std_logic; | |
|
58 | signal CFGM_LCD_DATA : std_logic_vector(7 downto 0); | |
|
59 | signal CFGM_Enable : std_logic; | |
|
60 | signal CFGM_completed : std_logic; | |
|
61 | ||
|
62 | ||
|
63 | signal FRMW_LCD_RS : std_logic; | |
|
64 | signal FRMW_LCD_RW : std_logic; | |
|
65 | signal FRMW_LCD_E : std_logic; | |
|
66 | signal FRMW_LCD_DATA : std_logic_vector(7 downto 0); | |
|
67 | signal FRMW_Enable : std_logic; | |
|
68 | signal FRMW_completed : std_logic; | |
|
69 | ||
|
70 | begin | |
|
71 | ||
|
72 | ||
|
73 | Counter : entity work.LCD_Counter | |
|
74 | generic map(OSC_Freq_MHz,Refresh_RateHz) | |
|
75 | port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start); | |
|
76 | ||
|
77 | ConfigModule : entity work.Config_Module | |
|
78 | port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse); | |
|
79 | ||
|
80 | ||
|
81 | FrameWriter : entity work.FRAME_WRITER | |
|
82 | port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse); | |
|
83 | ||
|
84 | ||
|
85 | STATEOUT(0) <= '1' when state = Rst else '0'; | |
|
86 | STATEOUT(1) <= '1' when state = Configure else '0'; | |
|
87 | STATEOUT(2) <= '1' when state = IDLE else '0'; | |
|
88 | STATEOUT(3) <= '1' when state = RefreshScreen else '0'; | |
|
89 | ||
|
90 | ||
|
91 | ||
|
92 | refreshPulse <= Refresh_RatePulse; | |
|
93 | ||
|
94 | Start <= '1'; | |
|
95 | ||
|
96 | process(reset,clk) | |
|
97 | begin | |
|
98 | if reset = '0' then | |
|
99 | LCD_data <= (others=>'0'); | |
|
100 | LCD_RS <= '0'; | |
|
101 | LCD_RW <= '0'; | |
|
102 | LCD_RET <= '0'; | |
|
103 | LCD_CS1 <= '0'; | |
|
104 | LCD_CS2 <= '0'; | |
|
105 | LCD_E <= '0'; | |
|
106 | state <= Rst; | |
|
107 | CFGM_Enable <= '0'; | |
|
108 | FRMW_Enable <= '0'; | |
|
109 | elsif clk'event and clk ='1' then | |
|
110 | case state is | |
|
111 | when Rst => | |
|
112 | LCD_data <= (others=>'0'); | |
|
113 | LCD_RS <= '0'; | |
|
114 | LCD_RW <= '0'; | |
|
115 | LCD_E <= '0'; | |
|
116 | CFGM_Enable <= '1'; | |
|
117 | FRMW_Enable <= '0'; | |
|
118 | if Refresh_RatePulse = '1' then | |
|
119 | state <= Configure; | |
|
120 | end if; | |
|
121 | when Configure => | |
|
122 | LCD_data <= CFGM_LCD_data; | |
|
123 | LCD_RS <= CFGM_LCD_RS; | |
|
124 | LCD_RW <= CFGM_LCD_RW; | |
|
125 | LCD_E <= CFGM_LCD_E; | |
|
126 | CFGM_Enable <= '0'; | |
|
127 | if CFGM_completed = '1' then | |
|
128 | state <= IDLE; | |
|
129 | end if; | |
|
130 | when IDLE => | |
|
131 | if Refresh_RatePulse = '1' then | |
|
132 | state <= RefreshScreen; | |
|
133 | FRMW_Enable <= '1'; | |
|
134 | end if; | |
|
135 | LCD_RS <= '0'; | |
|
136 | LCD_RW <= '0'; | |
|
137 | LCD_E <= '0'; | |
|
138 | LCD_data <= (others=>'0'); | |
|
139 | when RefreshScreen => | |
|
140 | LCD_data <= FRMW_LCD_data; | |
|
141 | LCD_RS <= FRMW_LCD_RS; | |
|
142 | LCD_RW <= FRMW_LCD_RW; | |
|
143 | LCD_E <= FRMW_LCD_E; | |
|
144 | FRMW_Enable <= '0'; | |
|
145 | if FRMW_completed = '1' then | |
|
146 | state <= IDLE; | |
|
147 | end if; | |
|
148 | end case; | |
|
149 | end if; | |
|
150 | end process; | |
|
151 | end Behavioral; | |
|
152 | ||
|
153 | ||
|
154 | ||
|
155 | ||
|
156 |
@@ -0,0 +1,72 | |||
|
1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 08:52:25 10/18/2010 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: LCD_CLK_GENERATOR - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
|
21 | use IEEE.STD_LOGIC_1164.ALL; | |
|
22 | use IEEE.NUMERIC_STD.ALL; | |
|
23 | ||
|
24 | ||
|
25 | entity LCD_CLK_GENERATOR is | |
|
26 | generic(OSC_freqKHz : integer := 50000); | |
|
27 | Port ( clk : in STD_LOGIC; | |
|
28 | reset : in STD_LOGIC; | |
|
29 | clk_1us : out STD_LOGIC); | |
|
30 | end LCD_CLK_GENERATOR; | |
|
31 | ||
|
32 | architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is | |
|
33 | ||
|
34 | Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1; | |
|
35 | ||
|
36 | ||
|
37 | signal cpt1 : integer; | |
|
38 | ||
|
39 | signal clk_1us_int : std_logic := '0'; | |
|
40 | ||
|
41 | ||
|
42 | begin | |
|
43 | ||
|
44 | clk_1us <= clk_1us_int; | |
|
45 | ||
|
46 | ||
|
47 | process(reset,clk) | |
|
48 | begin | |
|
49 | if reset = '0' then | |
|
50 | cpt1 <= 0; | |
|
51 | clk_1us_int <= '0'; | |
|
52 | elsif clk'event and clk = '1' then | |
|
53 | if cpt1 = clk_1usTRIGER then | |
|
54 | clk_1us_int <= not clk_1us_int; | |
|
55 | cpt1 <= 0; | |
|
56 | else | |
|
57 | cpt1 <= cpt1 + 1; | |
|
58 | end if; | |
|
59 | end if; | |
|
60 | end process; | |
|
61 | ||
|
62 | ||
|
63 | end ar_LCD_CLK_GENERATOR; | |
|
64 | ||
|
65 | ||
|
66 | ||
|
67 | ||
|
68 | ||
|
69 | ||
|
70 | ||
|
71 | ||
|
72 |
@@ -0,0 +1,102 | |||
|
1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 08:44:41 10/14/2010 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: Top_LCD - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
|
21 | use IEEE.STD_LOGIC_1164.ALL; | |
|
22 | use work.LCD_16x2_CFG.all; | |
|
23 | ||
|
24 | entity Top_LCD is | |
|
25 | Port ( reset : in STD_LOGIC; | |
|
26 | clk : in STD_LOGIC; | |
|
27 | Bp0 : in STD_LOGIC; | |
|
28 | Bp1 : in STD_LOGIC; | |
|
29 | Bp2 : in STD_LOGIC; | |
|
30 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); | |
|
31 | LCD_RS : out STD_LOGIC; | |
|
32 | LCD_RW : out STD_LOGIC; | |
|
33 | LCD_E : out STD_LOGIC; | |
|
34 | LCD_RET : out STD_LOGIC; | |
|
35 | LCD_CS1 : out STD_LOGIC; | |
|
36 | LCD_CS2 : out STD_LOGIC; | |
|
37 | SF_CE0 : out std_logic | |
|
38 | ); | |
|
39 | end Top_LCD; | |
|
40 | ||
|
41 | architecture Behavioral of Top_LCD is | |
|
42 | ||
|
43 | signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0); | |
|
44 | signal CMD : std_logic_vector(10 downto 0); | |
|
45 | signal Exec : std_logic; | |
|
46 | signal Ready : std_logic; | |
|
47 | signal rst : std_logic; | |
|
48 | signal LCD_CTRL : LCD_DRVR_CTRL_BUSS; | |
|
49 | ||
|
50 | begin | |
|
51 | ||
|
52 | LCD_data <= LCD_CTRL.LCD_DATA; | |
|
53 | LCD_RS <= LCD_CTRL.LCD_RS; | |
|
54 | LCD_RW <= LCD_CTRL.LCD_RW; | |
|
55 | LCD_E <= LCD_CTRL.LCD_E; | |
|
56 | ||
|
57 | ||
|
58 | LCD_RET <= '0'; | |
|
59 | LCD_CS1 <= '0'; | |
|
60 | LCD_CS2 <= '0'; | |
|
61 | ||
|
62 | SF_CE0 <= '1'; | |
|
63 | ||
|
64 | rst <= not reset; | |
|
65 | ||
|
66 | ||
|
67 | ||
|
68 | Driver0 : entity work.LCD_16x2_ENGINE | |
|
69 | generic map(50000) | |
|
70 | Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL); | |
|
71 | ||
|
72 | FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else | |
|
73 | X"42" when Bp1 = '1' else | |
|
74 | X"43" when Bp2 = '1' else | |
|
75 | X"44"; | |
|
76 | ||
|
77 | FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else | |
|
78 | X"47" when Bp1 = '1' else | |
|
79 | X"48" when Bp2 = '1' else | |
|
80 | X"49"; | |
|
81 | ||
|
82 | ||
|
83 | CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else | |
|
84 | Duration_100us & CursorOFF; | |
|
85 | ||
|
86 | ||
|
87 | Exec <= Bp1; | |
|
88 | ||
|
89 | FramBUFF(2*8+7 downto 2*8) <= X"23"; | |
|
90 | FramBUFF(3*8+7 downto 3*8) <= X"66"; | |
|
91 | FramBUFF(4*8+7 downto 4*8) <= X"67"; | |
|
92 | FramBUFF(5*8+7 downto 5*8) <= X"68"; | |
|
93 | FramBUFF(17*8+7 downto 17*8) <= X"69"; | |
|
94 | --FramBUFF(16*2*8-1 downto 16) <= (others => '0'); | |
|
95 | ||
|
96 | end Behavioral; | |
|
97 | ||
|
98 | ||
|
99 | ||
|
100 | ||
|
101 | ||
|
102 |
@@ -0,0 +1,37 | |||
|
1 | ||
|
2 | NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
3 | ||
|
4 | NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
5 | ||
|
6 | NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
7 | ||
|
8 | NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
9 | ||
|
10 | NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I; | |
|
11 | NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I; | |
|
12 | NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I; | |
|
13 | ||
|
14 | NET "LCD_data<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
15 | NET "LCD_data<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
16 | NET "LCD_data<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
17 | NET "LCD_data<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
18 | NET "LCD_data<4>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
19 | NET "LCD_data<5>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
20 | NET "LCD_data<6>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
21 | NET "LCD_data<7>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
22 | ||
|
23 | NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN; | |
|
24 | NET "Bp0" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN; | |
|
25 | NET "Bp1" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN; | |
|
26 | NET "Bp2" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN; | |
|
27 | ||
|
28 | net "clk" LOC = "C9" | IOSTANDARD = LVCMOS33; | |
|
29 | net "clk" PERIOD = 20.0ns HIGH 40%; | |
|
30 | #net "clkOUT" LOC = "N14" | IOSTANDARD = LVCMOS33; | |
|
31 | ||
|
32 | #net "STATEOUT<0>" LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; | |
|
33 | #net "STATEOUT<1>" LOC = "V6" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; | |
|
34 | #net "STATEOUT<2>" LOC = "N12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; | |
|
35 | #net "STATEOUT<3>" LOC = "P12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; | |
|
36 | ||
|
37 | #net "refreshPulse" LOC = "N15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; No newline at end of file |
@@ -0,0 +1,68 | |||
|
1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 09:21:03 10/19/2010 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: FRAME_CLK_GEN - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
|
21 | use IEEE.STD_LOGIC_1164.ALL; | |
|
22 | use IEEE.NUMERIC_STD.ALL; | |
|
23 | ||
|
24 | ||
|
25 | entity FRAME_CLK_GEN is | |
|
26 | generic(OSC_freqKHz : integer := 50000); | |
|
27 | Port ( clk : in STD_LOGIC; | |
|
28 | reset : in STD_LOGIC; | |
|
29 | FRAME_CLK : out STD_LOGIC); | |
|
30 | end FRAME_CLK_GEN; | |
|
31 | ||
|
32 | architecture Behavioral of FRAME_CLK_GEN is | |
|
33 | ||
|
34 | Constant Goal_FRAME_CLK_FREQ : integer := 20; | |
|
35 | ||
|
36 | Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1; | |
|
37 | ||
|
38 | signal CPT : integer := 0; | |
|
39 | signal FRAME_CLK_reg : std_logic :='0'; | |
|
40 | ||
|
41 | begin | |
|
42 | ||
|
43 | FRAME_CLK <= FRAME_CLK_reg; | |
|
44 | ||
|
45 | process(reset,clk) | |
|
46 | begin | |
|
47 | if reset = '0' then | |
|
48 | CPT <= 0; | |
|
49 | FRAME_CLK_reg <= '0'; | |
|
50 | elsif clk'event and clk = '1' then | |
|
51 | if CPT = FRAME_CLK_TRIG then | |
|
52 | CPT <= 0; | |
|
53 | FRAME_CLK_reg <= not FRAME_CLK_reg; | |
|
54 | else | |
|
55 | CPT <= CPT + 1; | |
|
56 | end if; | |
|
57 | end if; | |
|
58 | end process; | |
|
59 | end Behavioral; | |
|
60 | ||
|
61 | ||
|
62 | ||
|
63 | ||
|
64 | ||
|
65 | ||
|
66 | ||
|
67 | ||
|
68 |
@@ -0,0 +1,57 | |||
|
1 | -- Package File Template | |
|
2 | -- | |
|
3 | -- Purpose: This package defines supplemental types, subtypes, | |
|
4 | -- constants, and functions | |
|
5 | ||
|
6 | ||
|
7 | library IEEE; | |
|
8 | use IEEE.STD_LOGIC_1164.all; | |
|
9 | ||
|
10 | package LCD_16x2_CFG is | |
|
11 | ||
|
12 | type LCD_DRVR_CTRL_BUSS is | |
|
13 | record | |
|
14 | LCD_RW : std_logic; | |
|
15 | LCD_RS : std_logic; | |
|
16 | LCD_E : std_logic; | |
|
17 | LCD_DATA : std_logic_vector(7 downto 0); | |
|
18 | end record; | |
|
19 | ||
|
20 | type LCD_DRVR_SYNCH_BUSS is | |
|
21 | record | |
|
22 | DRVR_READY : std_logic; | |
|
23 | LCD_INITIALISED : std_logic; | |
|
24 | end record; | |
|
25 | ||
|
26 | ||
|
27 | type LCD_DRVR_CMD_BUSS is | |
|
28 | record | |
|
29 | Word : std_logic_vector(7 downto 0); | |
|
30 | CMD_Data : std_logic; --CMD = '0' and data = '1' | |
|
31 | Exec : std_logic; | |
|
32 | Duration : std_logic_vector(1 downto 0); | |
|
33 | end record; | |
|
34 | type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0); | |
|
35 | ||
|
36 | ||
|
37 | constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01"; | |
|
38 | constant FunctionSet : std_logic_vector(7 downto 0):= X"38"; | |
|
39 | constant RetHome : std_logic_vector(7 downto 0):= X"02"; | |
|
40 | constant SetEntryMode : std_logic_vector(7 downto 0):= X"06"; | |
|
41 | constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0C"; | |
|
42 | ||
|
43 | constant CursorON : std_logic_vector(7 downto 0):= X"0E"; | |
|
44 | constant CursorOFF : std_logic_vector(7 downto 0):= X"0C"; | |
|
45 | ||
|
46 | --===========================================================| | |
|
47 | --======L C D D R I V E R T I M I N G C O D E=====| | |
|
48 | --===========================================================| | |
|
49 | ||
|
50 | constant Duration_4us : std_logic_vector(1 downto 0) := "00"; | |
|
51 | constant Duration_100us : std_logic_vector(1 downto 0) := "01"; | |
|
52 | constant Duration_4ms : std_logic_vector(1 downto 0) := "10"; | |
|
53 | constant Duration_20ms : std_logic_vector(1 downto 0) := "11"; | |
|
54 | ||
|
55 | ||
|
56 | end LCD_16x2_CFG; | |
|
57 |
@@ -0,0 +1,206 | |||
|
1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 08:32:21 10/19/2010 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: LCD_16x2_ENGINE - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
|
21 | use IEEE.STD_LOGIC_1164.ALL; | |
|
22 | use IEEE.NUMERIC_STD.ALL; | |
|
23 | use work.LCD_16x2_CFG.all; | |
|
24 | ||
|
25 | entity LCD_16x2_ENGINE is | |
|
26 | generic(OSC_freqKHz : integer := 50000); | |
|
27 | Port ( clk : in STD_LOGIC; | |
|
28 | reset : in STD_LOGIC; | |
|
29 | DATA : in std_logic_vector(16*2*8-1 downto 0); | |
|
30 | CMD : in std_logic_vector(10 downto 0); | |
|
31 | Exec : in std_logic; | |
|
32 | Ready : out std_logic; | |
|
33 | LCD_CTRL : out LCD_DRVR_CTRL_BUSS | |
|
34 | ); | |
|
35 | end LCD_16x2_ENGINE; | |
|
36 | ||
|
37 | architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is | |
|
38 | ||
|
39 | constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome); | |
|
40 | ||
|
41 | ||
|
42 | ||
|
43 | signal SYNCH : LCD_DRVR_SYNCH_BUSS; | |
|
44 | signal DRIVER_CMD : LCD_DRVR_CMD_BUSS; | |
|
45 | signal FRAME_CLK : std_logic; | |
|
46 | ||
|
47 | signal FRAME_CLK_reg : std_logic; | |
|
48 | signal RefreshFlag : std_logic; | |
|
49 | signal CMD_Flag : std_logic; | |
|
50 | signal Exec_Reg : std_logic; | |
|
51 | ||
|
52 | type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1); | |
|
53 | signal state : state_t; | |
|
54 | signal i : integer range 0 to 32 := 0; | |
|
55 | ||
|
56 | ||
|
57 | ||
|
58 | begin | |
|
59 | ||
|
60 | Driver0 : entity work.LCD_16x2_DRIVER | |
|
61 | generic map(OSC_freqKHz) | |
|
62 | Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD); | |
|
63 | ||
|
64 | FRAME_CLK_GEN0 : entity work.FRAME_CLK_GEN | |
|
65 | generic map(OSC_freqKHz) | |
|
66 | Port map( clk,reset,FRAME_CLK); | |
|
67 | ||
|
68 | ||
|
69 | ||
|
70 | process(reset,clk) | |
|
71 | begin | |
|
72 | if reset = '0' then | |
|
73 | state <= INIT0; | |
|
74 | Ready <= '0'; | |
|
75 | RefreshFlag <= '0'; | |
|
76 | i <= 0; | |
|
77 | elsif clk'event and clk ='1' then | |
|
78 | FRAME_CLK_reg <= FRAME_CLK; | |
|
79 | Exec_Reg <= Exec; | |
|
80 | ||
|
81 | if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then | |
|
82 | RefreshFlag <= '1'; | |
|
83 | elsif state = Refresh or state = Refresh0 or state = Refresh1 then | |
|
84 | RefreshFlag <= '0'; | |
|
85 | end if; | |
|
86 | ||
|
87 | if Exec_Reg = '0' and Exec = '1' then | |
|
88 | CMD_Flag <= '1'; | |
|
89 | elsif state = ExecCMD0 or state = ExecCMD1 then | |
|
90 | CMD_Flag <= '0'; | |
|
91 | end if; | |
|
92 | ||
|
93 | case state is | |
|
94 | when INIT0 => | |
|
95 | if SYNCH.DRVR_READY = '1' then | |
|
96 | DRIVER_CMD.Exec <= '1'; | |
|
97 | DRIVER_CMD.Duration <= Duration_20ms; | |
|
98 | DRIVER_CMD.CMD_Data <= '0'; | |
|
99 | DRIVER_CMD.Word <= ConfigTbl(i); | |
|
100 | i <= i + 1; | |
|
101 | state <= INIT1; | |
|
102 | else | |
|
103 | DRIVER_CMD.Exec <= '0'; | |
|
104 | end if; | |
|
105 | when INIT1 => | |
|
106 | state <= INIT2; | |
|
107 | DRIVER_CMD.Exec <= '0'; | |
|
108 | when INIT2 => | |
|
109 | if SYNCH.DRVR_READY = '1' then | |
|
110 | if i = 5 then | |
|
111 | state <= Idle; | |
|
112 | else | |
|
113 | state <= INIT0; | |
|
114 | end if; | |
|
115 | end if; | |
|
116 | when Idle=> | |
|
117 | DRIVER_CMD.Exec <= '0'; | |
|
118 | if RefreshFlag = '1' then | |
|
119 | Ready <= '0'; | |
|
120 | state <= Refresh; | |
|
121 | elsif CMD_Flag = '1' then | |
|
122 | Ready <= '0'; | |
|
123 | state <= ExecCMD0; | |
|
124 | else | |
|
125 | Ready <= '1'; | |
|
126 | end if; | |
|
127 | i <= 0; | |
|
128 | when Refresh=> | |
|
129 | if SYNCH.DRVR_READY = '1' then | |
|
130 | DRIVER_CMD.Exec <= '1'; | |
|
131 | DRIVER_CMD.Duration <= Duration_100us; | |
|
132 | DRIVER_CMD.CMD_Data <= '1'; | |
|
133 | DRIVER_CMD.Word <= DATA(i*8+7 downto i*8); | |
|
134 | i <= i + 1; | |
|
135 | state <= Refresh0; | |
|
136 | else | |
|
137 | DRIVER_CMD.Exec <= '0'; | |
|
138 | end if; | |
|
139 | when Refresh0=> | |
|
140 | state <= Refresh1; | |
|
141 | DRIVER_CMD.Exec <= '0'; | |
|
142 | when Refresh1=> | |
|
143 | if SYNCH.DRVR_READY = '1' then | |
|
144 | if i = 32 then | |
|
145 | state <= ReturnHome; | |
|
146 | elsif i = 16 then | |
|
147 | state <= GoLine2; | |
|
148 | else | |
|
149 | state <= Refresh; | |
|
150 | end if; | |
|
151 | end if; | |
|
152 | ||
|
153 | when ExecCMD0=> | |
|
154 | if SYNCH.DRVR_READY = '1' then | |
|
155 | DRIVER_CMD.Exec <= '1'; | |
|
156 | DRIVER_CMD.Duration <= CMD(9 downto 8); | |
|
157 | DRIVER_CMD.CMD_Data <= '0'; | |
|
158 | DRIVER_CMD.Word <= CMD(7 downto 0); | |
|
159 | state <= ExecCMD1; | |
|
160 | else | |
|
161 | DRIVER_CMD.Exec <= '0'; | |
|
162 | end if; | |
|
163 | ||
|
164 | when ExecCMD1=> | |
|
165 | state <= Idle; | |
|
166 | DRIVER_CMD.Exec <= '0'; | |
|
167 | ||
|
168 | when GoLine2=> | |
|
169 | if SYNCH.DRVR_READY = '1' then | |
|
170 | DRIVER_CMD.Exec <= '1'; | |
|
171 | DRIVER_CMD.Duration <= Duration_100us; | |
|
172 | DRIVER_CMD.CMD_Data <= '0'; | |
|
173 | DRIVER_CMD.Word <= X"C0"; | |
|
174 | state <= GoLine2_0; | |
|
175 | else | |
|
176 | DRIVER_CMD.Exec <= '0'; | |
|
177 | end if; | |
|
178 | when GoLine2_0=> | |
|
179 | state <= Refresh; | |
|
180 | DRIVER_CMD.Exec <= '0'; | |
|
181 | when ReturnHome=> | |
|
182 | if SYNCH.DRVR_READY = '1' then | |
|
183 | DRIVER_CMD.Exec <= '1'; | |
|
184 | DRIVER_CMD.Duration <= Duration_4ms; | |
|
185 | DRIVER_CMD.CMD_Data <= '0'; | |
|
186 | DRIVER_CMD.Word <= X"02"; | |
|
187 | state <= Idle; | |
|
188 | else | |
|
189 | DRIVER_CMD.Exec <= '0'; | |
|
190 | end if; | |
|
191 | end case; | |
|
192 | end if; | |
|
193 | end process; | |
|
194 | ||
|
195 | ||
|
196 | end ar_LCD_16x2_ENGINE; | |
|
197 | ||
|
198 | ||
|
199 | ||
|
200 | ||
|
201 | ||
|
202 | ||
|
203 | ||
|
204 | ||
|
205 | ||
|
206 |
@@ -0,0 +1,156 | |||
|
1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 10:09:57 10/13/2010 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: LCD_2x16_DRIVER - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
|
21 | use IEEE.STD_LOGIC_1164.ALL; | |
|
22 | use IEEE.NUMERIC_STD.all; | |
|
23 | ||
|
24 | ||
|
25 | entity LCD_2x16_DRIVER is | |
|
26 | generic( | |
|
27 | OSC_Freq_MHz : integer:=60; | |
|
28 | Refresh_RateHz : integer:=5 | |
|
29 | ); | |
|
30 | Port ( clk : in STD_LOGIC; | |
|
31 | reset : in STD_LOGIC; | |
|
32 | FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0); | |
|
33 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); | |
|
34 | LCD_RS : out STD_LOGIC; | |
|
35 | LCD_RW : out STD_LOGIC; | |
|
36 | LCD_E : out STD_LOGIC; | |
|
37 | LCD_RET : out STD_LOGIC; | |
|
38 | LCD_CS1 : out STD_LOGIC; | |
|
39 | LCD_CS2 : out STD_LOGIC; | |
|
40 | STATEOUT: out std_logic_vector(3 downto 0); | |
|
41 | refreshPulse : out std_logic | |
|
42 | ); | |
|
43 | end LCD_2x16_DRIVER; | |
|
44 | ||
|
45 | architecture Behavioral of LCD_2x16_DRIVER is | |
|
46 | ||
|
47 | type stateT is(Rst,Configure,IDLE,RefreshScreen); | |
|
48 | signal state : stateT; | |
|
49 | ||
|
50 | signal ShortTimePulse : std_logic; | |
|
51 | signal MidleTimePulse : std_logic; | |
|
52 | signal Refresh_RatePulse : std_logic; | |
|
53 | signal Start : STD_LOGIC; | |
|
54 | ||
|
55 | signal CFGM_LCD_RS : std_logic; | |
|
56 | signal CFGM_LCD_RW : std_logic; | |
|
57 | signal CFGM_LCD_E : std_logic; | |
|
58 | signal CFGM_LCD_DATA : std_logic_vector(7 downto 0); | |
|
59 | signal CFGM_Enable : std_logic; | |
|
60 | signal CFGM_completed : std_logic; | |
|
61 | ||
|
62 | ||
|
63 | signal FRMW_LCD_RS : std_logic; | |
|
64 | signal FRMW_LCD_RW : std_logic; | |
|
65 | signal FRMW_LCD_E : std_logic; | |
|
66 | signal FRMW_LCD_DATA : std_logic_vector(7 downto 0); | |
|
67 | signal FRMW_Enable : std_logic; | |
|
68 | signal FRMW_completed : std_logic; | |
|
69 | ||
|
70 | begin | |
|
71 | ||
|
72 | ||
|
73 | Counter : entity work.LCD_Counter | |
|
74 | generic map(OSC_Freq_MHz,Refresh_RateHz) | |
|
75 | port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start); | |
|
76 | ||
|
77 | ConfigModule : entity work.Config_Module | |
|
78 | port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse); | |
|
79 | ||
|
80 | ||
|
81 | FrameWriter : entity work.FRAME_WRITER | |
|
82 | port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse); | |
|
83 | ||
|
84 | ||
|
85 | STATEOUT(0) <= '1' when state = Rst else '0'; | |
|
86 | STATEOUT(1) <= '1' when state = Configure else '0'; | |
|
87 | STATEOUT(2) <= '1' when state = IDLE else '0'; | |
|
88 | STATEOUT(3) <= '1' when state = RefreshScreen else '0'; | |
|
89 | ||
|
90 | ||
|
91 | ||
|
92 | refreshPulse <= Refresh_RatePulse; | |
|
93 | ||
|
94 | Start <= '1'; | |
|
95 | ||
|
96 | process(reset,clk) | |
|
97 | begin | |
|
98 | if reset = '0' then | |
|
99 | LCD_data <= (others=>'0'); | |
|
100 | LCD_RS <= '0'; | |
|
101 | LCD_RW <= '0'; | |
|
102 | LCD_RET <= '0'; | |
|
103 | LCD_CS1 <= '0'; | |
|
104 | LCD_CS2 <= '0'; | |
|
105 | LCD_E <= '0'; | |
|
106 | state <= Rst; | |
|
107 | CFGM_Enable <= '0'; | |
|
108 | FRMW_Enable <= '0'; | |
|
109 | elsif clk'event and clk ='1' then | |
|
110 | case state is | |
|
111 | when Rst => | |
|
112 | LCD_data <= (others=>'0'); | |
|
113 | LCD_RS <= '0'; | |
|
114 | LCD_RW <= '0'; | |
|
115 | LCD_E <= '0'; | |
|
116 | CFGM_Enable <= '1'; | |
|
117 | FRMW_Enable <= '0'; | |
|
118 | if Refresh_RatePulse = '1' then | |
|
119 | state <= Configure; | |
|
120 | end if; | |
|
121 | when Configure => | |
|
122 | LCD_data <= CFGM_LCD_data; | |
|
123 | LCD_RS <= CFGM_LCD_RS; | |
|
124 | LCD_RW <= CFGM_LCD_RW; | |
|
125 | LCD_E <= CFGM_LCD_E; | |
|
126 | CFGM_Enable <= '0'; | |
|
127 | if CFGM_completed = '1' then | |
|
128 | state <= IDLE; | |
|
129 | end if; | |
|
130 | when IDLE => | |
|
131 | if Refresh_RatePulse = '1' then | |
|
132 | state <= RefreshScreen; | |
|
133 | FRMW_Enable <= '1'; | |
|
134 | end if; | |
|
135 | LCD_RS <= '0'; | |
|
136 | LCD_RW <= '0'; | |
|
137 | LCD_E <= '0'; | |
|
138 | LCD_data <= (others=>'0'); | |
|
139 | when RefreshScreen => | |
|
140 | LCD_data <= FRMW_LCD_data; | |
|
141 | LCD_RS <= FRMW_LCD_RS; | |
|
142 | LCD_RW <= FRMW_LCD_RW; | |
|
143 | LCD_E <= FRMW_LCD_E; | |
|
144 | FRMW_Enable <= '0'; | |
|
145 | if FRMW_completed = '1' then | |
|
146 | state <= IDLE; | |
|
147 | end if; | |
|
148 | end case; | |
|
149 | end if; | |
|
150 | end process; | |
|
151 | end Behavioral; | |
|
152 | ||
|
153 | ||
|
154 | ||
|
155 | ||
|
156 |
@@ -0,0 +1,72 | |||
|
1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 08:52:25 10/18/2010 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: LCD_CLK_GENERATOR - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
|
21 | use IEEE.STD_LOGIC_1164.ALL; | |
|
22 | use IEEE.NUMERIC_STD.ALL; | |
|
23 | ||
|
24 | ||
|
25 | entity LCD_CLK_GENERATOR is | |
|
26 | generic(OSC_freqKHz : integer := 50000); | |
|
27 | Port ( clk : in STD_LOGIC; | |
|
28 | reset : in STD_LOGIC; | |
|
29 | clk_1us : out STD_LOGIC); | |
|
30 | end LCD_CLK_GENERATOR; | |
|
31 | ||
|
32 | architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is | |
|
33 | ||
|
34 | Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1; | |
|
35 | ||
|
36 | ||
|
37 | signal cpt1 : integer; | |
|
38 | ||
|
39 | signal clk_1us_int : std_logic := '0'; | |
|
40 | ||
|
41 | ||
|
42 | begin | |
|
43 | ||
|
44 | clk_1us <= clk_1us_int; | |
|
45 | ||
|
46 | ||
|
47 | process(reset,clk) | |
|
48 | begin | |
|
49 | if reset = '0' then | |
|
50 | cpt1 <= 0; | |
|
51 | clk_1us_int <= '0'; | |
|
52 | elsif clk'event and clk = '1' then | |
|
53 | if cpt1 = clk_1usTRIGER then | |
|
54 | clk_1us_int <= not clk_1us_int; | |
|
55 | cpt1 <= 0; | |
|
56 | else | |
|
57 | cpt1 <= cpt1 + 1; | |
|
58 | end if; | |
|
59 | end if; | |
|
60 | end process; | |
|
61 | ||
|
62 | ||
|
63 | end ar_LCD_CLK_GENERATOR; | |
|
64 | ||
|
65 | ||
|
66 | ||
|
67 | ||
|
68 | ||
|
69 | ||
|
70 | ||
|
71 | ||
|
72 |
@@ -0,0 +1,102 | |||
|
1 | ---------------------------------------------------------------------------------- | |
|
2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 08:44:41 10/14/2010 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: Top_LCD - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
|
21 | use IEEE.STD_LOGIC_1164.ALL; | |
|
22 | use work.LCD_16x2_CFG.all; | |
|
23 | ||
|
24 | entity Top_LCD is | |
|
25 | Port ( reset : in STD_LOGIC; | |
|
26 | clk : in STD_LOGIC; | |
|
27 | Bp0 : in STD_LOGIC; | |
|
28 | Bp1 : in STD_LOGIC; | |
|
29 | Bp2 : in STD_LOGIC; | |
|
30 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); | |
|
31 | LCD_RS : out STD_LOGIC; | |
|
32 | LCD_RW : out STD_LOGIC; | |
|
33 | LCD_E : out STD_LOGIC; | |
|
34 | LCD_RET : out STD_LOGIC; | |
|
35 | LCD_CS1 : out STD_LOGIC; | |
|
36 | LCD_CS2 : out STD_LOGIC; | |
|
37 | SF_CE0 : out std_logic | |
|
38 | ); | |
|
39 | end Top_LCD; | |
|
40 | ||
|
41 | architecture Behavioral of Top_LCD is | |
|
42 | ||
|
43 | signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0); | |
|
44 | signal CMD : std_logic_vector(10 downto 0); | |
|
45 | signal Exec : std_logic; | |
|
46 | signal Ready : std_logic; | |
|
47 | signal rst : std_logic; | |
|
48 | signal LCD_CTRL : LCD_DRVR_CTRL_BUSS; | |
|
49 | ||
|
50 | begin | |
|
51 | ||
|
52 | LCD_data <= LCD_CTRL.LCD_DATA; | |
|
53 | LCD_RS <= LCD_CTRL.LCD_RS; | |
|
54 | LCD_RW <= LCD_CTRL.LCD_RW; | |
|
55 | LCD_E <= LCD_CTRL.LCD_E; | |
|
56 | ||
|
57 | ||
|
58 | LCD_RET <= '0'; | |
|
59 | LCD_CS1 <= '0'; | |
|
60 | LCD_CS2 <= '0'; | |
|
61 | ||
|
62 | SF_CE0 <= '1'; | |
|
63 | ||
|
64 | rst <= not reset; | |
|
65 | ||
|
66 | ||
|
67 | ||
|
68 | Driver0 : entity work.LCD_16x2_ENGINE | |
|
69 | generic map(50000) | |
|
70 | Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL); | |
|
71 | ||
|
72 | FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else | |
|
73 | X"42" when Bp1 = '1' else | |
|
74 | X"43" when Bp2 = '1' else | |
|
75 | X"44"; | |
|
76 | ||
|
77 | FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else | |
|
78 | X"47" when Bp1 = '1' else | |
|
79 | X"48" when Bp2 = '1' else | |
|
80 | X"49"; | |
|
81 | ||
|
82 | ||
|
83 | CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else | |
|
84 | Duration_100us & CursorOFF; | |
|
85 | ||
|
86 | ||
|
87 | Exec <= Bp1; | |
|
88 | ||
|
89 | FramBUFF(2*8+7 downto 2*8) <= X"23"; | |
|
90 | FramBUFF(3*8+7 downto 3*8) <= X"66"; | |
|
91 | FramBUFF(4*8+7 downto 4*8) <= X"67"; | |
|
92 | FramBUFF(5*8+7 downto 5*8) <= X"68"; | |
|
93 | FramBUFF(17*8+7 downto 17*8) <= X"69"; | |
|
94 | --FramBUFF(16*2*8-1 downto 16) <= (others => '0'); | |
|
95 | ||
|
96 | end Behavioral; | |
|
97 | ||
|
98 | ||
|
99 | ||
|
100 | ||
|
101 | ||
|
102 |
@@ -0,0 +1,37 | |||
|
1 | ||
|
2 | NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
3 | ||
|
4 | NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
5 | ||
|
6 | NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
7 | ||
|
8 | NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
9 | ||
|
10 | NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I; | |
|
11 | NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I; | |
|
12 | NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I; | |
|
13 | ||
|
14 | NET "LCD_data<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
15 | NET "LCD_data<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
16 | NET "LCD_data<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
17 | NET "LCD_data<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
18 | NET "LCD_data<4>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
19 | NET "LCD_data<5>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
20 | NET "LCD_data<6>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
21 | NET "LCD_data<7>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | |
|
22 | ||
|
23 | NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN; | |
|
24 | NET "Bp0" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN; | |
|
25 | NET "Bp1" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN; | |
|
26 | NET "Bp2" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN; | |
|
27 | ||
|
28 | net "clk" LOC = "C9" | IOSTANDARD = LVCMOS33; | |
|
29 | net "clk" PERIOD = 20.0ns HIGH 40%; | |
|
30 | #net "clkOUT" LOC = "N14" | IOSTANDARD = LVCMOS33; | |
|
31 | ||
|
32 | #net "STATEOUT<0>" LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; | |
|
33 | #net "STATEOUT<1>" LOC = "V6" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; | |
|
34 | #net "STATEOUT<2>" LOC = "N12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; | |
|
35 | #net "STATEOUT<3>" LOC = "P12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; | |
|
36 | ||
|
37 | #net "refreshPulse" LOC = "N15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; No newline at end of file |
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