# HG changeset patch # User alexis # Date 2010-10-20 07:35:01 # Node ID 98955b8fb9a7768df9705a206f99e8311dc06662 # Parent 0000000000000000000000000000000000000000 First Init diff --git a/LCD_16x2_DRIVER/With_AMBA/FRAME_CLK.vhd b/LCD_16x2_DRIVER/With_AMBA/FRAME_CLK.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/With_AMBA/FRAME_CLK.vhd @@ -0,0 +1,68 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:21:03 10/19/2010 +-- Design Name: +-- Module Name: FRAME_CLK_GEN - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + + +entity FRAME_CLK_GEN is + generic(OSC_freqKHz : integer := 50000); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + FRAME_CLK : out STD_LOGIC); +end FRAME_CLK_GEN; + +architecture Behavioral of FRAME_CLK_GEN is + +Constant Goal_FRAME_CLK_FREQ : integer := 20; + +Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1; + +signal CPT : integer := 0; +signal FRAME_CLK_reg : std_logic :='0'; + +begin + +FRAME_CLK <= FRAME_CLK_reg; + +process(reset,clk) +begin + if reset = '0' then + CPT <= 0; + FRAME_CLK_reg <= '0'; + elsif clk'event and clk = '1' then + if CPT = FRAME_CLK_TRIG then + CPT <= 0; + FRAME_CLK_reg <= not FRAME_CLK_reg; + else + CPT <= CPT + 1; + end if; + end if; +end process; +end Behavioral; + + + + + + + + + diff --git a/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_CFG.vhd b/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_CFG.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_CFG.vhd @@ -0,0 +1,57 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package LCD_16x2_CFG is + + type LCD_DRVR_CTRL_BUSS is + record + LCD_RW : std_logic; + LCD_RS : std_logic; + LCD_E : std_logic; + LCD_DATA : std_logic_vector(7 downto 0); + end record; + + type LCD_DRVR_SYNCH_BUSS is + record + DRVR_READY : std_logic; + LCD_INITIALISED : std_logic; + end record; + + + type LCD_DRVR_CMD_BUSS is + record + Word : std_logic_vector(7 downto 0); + CMD_Data : std_logic; --CMD = '0' and data = '1' + Exec : std_logic; + Duration : std_logic_vector(1 downto 0); + end record; + type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0); + + +constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01"; +constant FunctionSet : std_logic_vector(7 downto 0):= X"38"; +constant RetHome : std_logic_vector(7 downto 0):= X"02"; +constant SetEntryMode : std_logic_vector(7 downto 0):= X"06"; +constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0C"; + +constant CursorON : std_logic_vector(7 downto 0):= X"0E"; +constant CursorOFF : std_logic_vector(7 downto 0):= X"0C"; + +--===========================================================| +--======L C D D R I V E R T I M I N G C O D E=====| +--===========================================================| + +constant Duration_4us : std_logic_vector(1 downto 0) := "00"; +constant Duration_100us : std_logic_vector(1 downto 0) := "01"; +constant Duration_4ms : std_logic_vector(1 downto 0) := "10"; +constant Duration_20ms : std_logic_vector(1 downto 0) := "11"; + + +end LCD_16x2_CFG; + diff --git a/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_ENGINE.vhd b/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_ENGINE.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_ENGINE.vhd @@ -0,0 +1,206 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 08:32:21 10/19/2010 +-- Design Name: +-- Module Name: LCD_16x2_ENGINE - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.LCD_16x2_CFG.all; + +entity LCD_16x2_ENGINE is + generic(OSC_freqKHz : integer := 50000); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + DATA : in std_logic_vector(16*2*8-1 downto 0); + CMD : in std_logic_vector(10 downto 0); + Exec : in std_logic; + Ready : out std_logic; + LCD_CTRL : out LCD_DRVR_CTRL_BUSS + ); +end LCD_16x2_ENGINE; + +architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is + +constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome); + + + +signal SYNCH : LCD_DRVR_SYNCH_BUSS; +signal DRIVER_CMD : LCD_DRVR_CMD_BUSS; +signal FRAME_CLK : std_logic; + +signal FRAME_CLK_reg : std_logic; +signal RefreshFlag : std_logic; +signal CMD_Flag : std_logic; +signal Exec_Reg : std_logic; + +type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1); +signal state : state_t; +signal i : integer range 0 to 32 := 0; + + + +begin + +Driver0 : entity work.LCD_16x2_DRIVER + generic map(OSC_freqKHz) + Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD); + +FRAME_CLK_GEN0 : entity work.FRAME_CLK_GEN + generic map(OSC_freqKHz) + Port map( clk,reset,FRAME_CLK); + + + +process(reset,clk) +begin + if reset = '0' then + state <= INIT0; + Ready <= '0'; + RefreshFlag <= '0'; + i <= 0; + elsif clk'event and clk ='1' then + FRAME_CLK_reg <= FRAME_CLK; + Exec_Reg <= Exec; + + if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then + RefreshFlag <= '1'; + elsif state = Refresh or state = Refresh0 or state = Refresh1 then + RefreshFlag <= '0'; + end if; + + if Exec_Reg = '0' and Exec = '1' then + CMD_Flag <= '1'; + elsif state = ExecCMD0 or state = ExecCMD1 then + CMD_Flag <= '0'; + end if; + + case state is + when INIT0 => + if SYNCH.DRVR_READY = '1' then + DRIVER_CMD.Exec <= '1'; + DRIVER_CMD.Duration <= Duration_20ms; + DRIVER_CMD.CMD_Data <= '0'; + DRIVER_CMD.Word <= ConfigTbl(i); + i <= i + 1; + state <= INIT1; + else + DRIVER_CMD.Exec <= '0'; + end if; + when INIT1 => + state <= INIT2; + DRIVER_CMD.Exec <= '0'; + when INIT2 => + if SYNCH.DRVR_READY = '1' then + if i = 5 then + state <= Idle; + else + state <= INIT0; + end if; + end if; + when Idle=> + DRIVER_CMD.Exec <= '0'; + if RefreshFlag = '1' then + Ready <= '0'; + state <= Refresh; + elsif CMD_Flag = '1' then + Ready <= '0'; + state <= ExecCMD0; + else + Ready <= '1'; + end if; + i <= 0; + when Refresh=> + if SYNCH.DRVR_READY = '1' then + DRIVER_CMD.Exec <= '1'; + DRIVER_CMD.Duration <= Duration_100us; + DRIVER_CMD.CMD_Data <= '1'; + DRIVER_CMD.Word <= DATA(i*8+7 downto i*8); + i <= i + 1; + state <= Refresh0; + else + DRIVER_CMD.Exec <= '0'; + end if; + when Refresh0=> + state <= Refresh1; + DRIVER_CMD.Exec <= '0'; + when Refresh1=> + if SYNCH.DRVR_READY = '1' then + if i = 32 then + state <= ReturnHome; + elsif i = 16 then + state <= GoLine2; + else + state <= Refresh; + end if; + end if; + + when ExecCMD0=> + if SYNCH.DRVR_READY = '1' then + DRIVER_CMD.Exec <= '1'; + DRIVER_CMD.Duration <= CMD(9 downto 8); + DRIVER_CMD.CMD_Data <= '0'; + DRIVER_CMD.Word <= CMD(7 downto 0); + state <= ExecCMD1; + else + DRIVER_CMD.Exec <= '0'; + end if; + + when ExecCMD1=> + state <= Idle; + DRIVER_CMD.Exec <= '0'; + + when GoLine2=> + if SYNCH.DRVR_READY = '1' then + DRIVER_CMD.Exec <= '1'; + DRIVER_CMD.Duration <= Duration_100us; + DRIVER_CMD.CMD_Data <= '0'; + DRIVER_CMD.Word <= X"C0"; + state <= GoLine2_0; + else + DRIVER_CMD.Exec <= '0'; + end if; + when GoLine2_0=> + state <= Refresh; + DRIVER_CMD.Exec <= '0'; + when ReturnHome=> + if SYNCH.DRVR_READY = '1' then + DRIVER_CMD.Exec <= '1'; + DRIVER_CMD.Duration <= Duration_4ms; + DRIVER_CMD.CMD_Data <= '0'; + DRIVER_CMD.Word <= X"02"; + state <= Idle; + else + DRIVER_CMD.Exec <= '0'; + end if; + end case; + end if; +end process; + + +end ar_LCD_16x2_ENGINE; + + + + + + + + + + diff --git a/LCD_16x2_DRIVER/With_AMBA/LCD_2x16_DRIVER.vhd b/LCD_16x2_DRIVER/With_AMBA/LCD_2x16_DRIVER.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/With_AMBA/LCD_2x16_DRIVER.vhd @@ -0,0 +1,156 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:09:57 10/13/2010 +-- Design Name: +-- Module Name: LCD_2x16_DRIVER - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; + + +entity LCD_2x16_DRIVER is + generic( + OSC_Freq_MHz : integer:=60; + Refresh_RateHz : integer:=5 + ); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0); + LCD_data : out STD_LOGIC_VECTOR (7 downto 0); + LCD_RS : out STD_LOGIC; + LCD_RW : out STD_LOGIC; + LCD_E : out STD_LOGIC; + LCD_RET : out STD_LOGIC; + LCD_CS1 : out STD_LOGIC; + LCD_CS2 : out STD_LOGIC; + STATEOUT: out std_logic_vector(3 downto 0); + refreshPulse : out std_logic + ); +end LCD_2x16_DRIVER; + +architecture Behavioral of LCD_2x16_DRIVER is + +type stateT is(Rst,Configure,IDLE,RefreshScreen); +signal state : stateT; + +signal ShortTimePulse : std_logic; +signal MidleTimePulse : std_logic; +signal Refresh_RatePulse : std_logic; +signal Start : STD_LOGIC; + +signal CFGM_LCD_RS : std_logic; +signal CFGM_LCD_RW : std_logic; +signal CFGM_LCD_E : std_logic; +signal CFGM_LCD_DATA : std_logic_vector(7 downto 0); +signal CFGM_Enable : std_logic; +signal CFGM_completed : std_logic; + + +signal FRMW_LCD_RS : std_logic; +signal FRMW_LCD_RW : std_logic; +signal FRMW_LCD_E : std_logic; +signal FRMW_LCD_DATA : std_logic_vector(7 downto 0); +signal FRMW_Enable : std_logic; +signal FRMW_completed : std_logic; + +begin + + +Counter : entity work.LCD_Counter +generic map(OSC_Freq_MHz,Refresh_RateHz) +port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start); + +ConfigModule : entity work.Config_Module +port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse); + + +FrameWriter : entity work.FRAME_WRITER +port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse); + + +STATEOUT(0) <= '1' when state = Rst else '0'; +STATEOUT(1) <= '1' when state = Configure else '0'; +STATEOUT(2) <= '1' when state = IDLE else '0'; +STATEOUT(3) <= '1' when state = RefreshScreen else '0'; + + + +refreshPulse <= Refresh_RatePulse; + +Start <= '1'; + +process(reset,clk) +begin + if reset = '0' then + LCD_data <= (others=>'0'); + LCD_RS <= '0'; + LCD_RW <= '0'; + LCD_RET <= '0'; + LCD_CS1 <= '0'; + LCD_CS2 <= '0'; + LCD_E <= '0'; + state <= Rst; + CFGM_Enable <= '0'; + FRMW_Enable <= '0'; + elsif clk'event and clk ='1' then + case state is + when Rst => + LCD_data <= (others=>'0'); + LCD_RS <= '0'; + LCD_RW <= '0'; + LCD_E <= '0'; + CFGM_Enable <= '1'; + FRMW_Enable <= '0'; + if Refresh_RatePulse = '1' then + state <= Configure; + end if; + when Configure => + LCD_data <= CFGM_LCD_data; + LCD_RS <= CFGM_LCD_RS; + LCD_RW <= CFGM_LCD_RW; + LCD_E <= CFGM_LCD_E; + CFGM_Enable <= '0'; + if CFGM_completed = '1' then + state <= IDLE; + end if; + when IDLE => + if Refresh_RatePulse = '1' then + state <= RefreshScreen; + FRMW_Enable <= '1'; + end if; + LCD_RS <= '0'; + LCD_RW <= '0'; + LCD_E <= '0'; + LCD_data <= (others=>'0'); + when RefreshScreen => + LCD_data <= FRMW_LCD_data; + LCD_RS <= FRMW_LCD_RS; + LCD_RW <= FRMW_LCD_RW; + LCD_E <= FRMW_LCD_E; + FRMW_Enable <= '0'; + if FRMW_completed = '1' then + state <= IDLE; + end if; + end case; + end if; +end process; +end Behavioral; + + + + + diff --git a/LCD_16x2_DRIVER/With_AMBA/LCD_CLK_GENERATOR.vhd b/LCD_16x2_DRIVER/With_AMBA/LCD_CLK_GENERATOR.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/With_AMBA/LCD_CLK_GENERATOR.vhd @@ -0,0 +1,72 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 08:52:25 10/18/2010 +-- Design Name: +-- Module Name: LCD_CLK_GENERATOR - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + + +entity LCD_CLK_GENERATOR is + generic(OSC_freqKHz : integer := 50000); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + clk_1us : out STD_LOGIC); +end LCD_CLK_GENERATOR; + +architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is + +Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1; + + +signal cpt1 : integer; + +signal clk_1us_int : std_logic := '0'; + + +begin + +clk_1us <= clk_1us_int; + + +process(reset,clk) +begin + if reset = '0' then + cpt1 <= 0; + clk_1us_int <= '0'; + elsif clk'event and clk = '1' then + if cpt1 = clk_1usTRIGER then + clk_1us_int <= not clk_1us_int; + cpt1 <= 0; + else + cpt1 <= cpt1 + 1; + end if; + end if; +end process; + + +end ar_LCD_CLK_GENERATOR; + + + + + + + + + diff --git a/LCD_16x2_DRIVER/With_AMBA/Top_LCD.vhd b/LCD_16x2_DRIVER/With_AMBA/Top_LCD.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/With_AMBA/Top_LCD.vhd @@ -0,0 +1,102 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 08:44:41 10/14/2010 +-- Design Name: +-- Module Name: Top_LCD - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.LCD_16x2_CFG.all; + +entity Top_LCD is + Port ( reset : in STD_LOGIC; + clk : in STD_LOGIC; + Bp0 : in STD_LOGIC; + Bp1 : in STD_LOGIC; + Bp2 : in STD_LOGIC; + LCD_data : out STD_LOGIC_VECTOR (7 downto 0); + LCD_RS : out STD_LOGIC; + LCD_RW : out STD_LOGIC; + LCD_E : out STD_LOGIC; + LCD_RET : out STD_LOGIC; + LCD_CS1 : out STD_LOGIC; + LCD_CS2 : out STD_LOGIC; + SF_CE0 : out std_logic + ); +end Top_LCD; + +architecture Behavioral of Top_LCD is + +signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0); +signal CMD : std_logic_vector(10 downto 0); +signal Exec : std_logic; +signal Ready : std_logic; +signal rst : std_logic; +signal LCD_CTRL : LCD_DRVR_CTRL_BUSS; + +begin + +LCD_data <= LCD_CTRL.LCD_DATA; +LCD_RS <= LCD_CTRL.LCD_RS; +LCD_RW <= LCD_CTRL.LCD_RW; +LCD_E <= LCD_CTRL.LCD_E; + + +LCD_RET <= '0'; +LCD_CS1 <= '0'; +LCD_CS2 <= '0'; + +SF_CE0 <= '1'; + +rst <= not reset; + + + +Driver0 : entity work.LCD_16x2_ENGINE + generic map(50000) + Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL); + +FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else + X"42" when Bp1 = '1' else + X"43" when Bp2 = '1' else + X"44"; + +FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else + X"47" when Bp1 = '1' else + X"48" when Bp2 = '1' else + X"49"; + + +CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else + Duration_100us & CursorOFF; + + +Exec <= Bp1; + +FramBUFF(2*8+7 downto 2*8) <= X"23"; +FramBUFF(3*8+7 downto 3*8) <= X"66"; +FramBUFF(4*8+7 downto 4*8) <= X"67"; +FramBUFF(5*8+7 downto 5*8) <= X"68"; +FramBUFF(17*8+7 downto 17*8) <= X"69"; +--FramBUFF(16*2*8-1 downto 16) <= (others => '0'); + +end Behavioral; + + + + + + diff --git a/LCD_16x2_DRIVER/With_AMBA/Top_LCDcst.ucf b/LCD_16x2_DRIVER/With_AMBA/Top_LCDcst.ucf new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/With_AMBA/Top_LCDcst.ucf @@ -0,0 +1,37 @@ + +NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; + +NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; + +NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; + +NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; + +NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I; +NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I; +NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I; + +NET "LCD_data<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<4>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<5>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<6>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<7>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; + +NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN; +NET "Bp0" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN; +NET "Bp1" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN; +NET "Bp2" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN; + +net "clk" LOC = "C9" | IOSTANDARD = LVCMOS33; +net "clk" PERIOD = 20.0ns HIGH 40%; +#net "clkOUT" LOC = "N14" | IOSTANDARD = LVCMOS33; + +#net "STATEOUT<0>" LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; +#net "STATEOUT<1>" LOC = "V6" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; +#net "STATEOUT<2>" LOC = "N12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; +#net "STATEOUT<3>" LOC = "P12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; + +#net "refreshPulse" LOC = "N15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; \ No newline at end of file diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/FRAME_CLK.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/FRAME_CLK.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/Without_AMBA/VHD/FRAME_CLK.vhd @@ -0,0 +1,68 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:21:03 10/19/2010 +-- Design Name: +-- Module Name: FRAME_CLK_GEN - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + + +entity FRAME_CLK_GEN is + generic(OSC_freqKHz : integer := 50000); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + FRAME_CLK : out STD_LOGIC); +end FRAME_CLK_GEN; + +architecture Behavioral of FRAME_CLK_GEN is + +Constant Goal_FRAME_CLK_FREQ : integer := 20; + +Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1; + +signal CPT : integer := 0; +signal FRAME_CLK_reg : std_logic :='0'; + +begin + +FRAME_CLK <= FRAME_CLK_reg; + +process(reset,clk) +begin + if reset = '0' then + CPT <= 0; + FRAME_CLK_reg <= '0'; + elsif clk'event and clk = '1' then + if CPT = FRAME_CLK_TRIG then + CPT <= 0; + FRAME_CLK_reg <= not FRAME_CLK_reg; + else + CPT <= CPT + 1; + end if; + end if; +end process; +end Behavioral; + + + + + + + + + diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_CFG.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_CFG.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_CFG.vhd @@ -0,0 +1,57 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package LCD_16x2_CFG is + + type LCD_DRVR_CTRL_BUSS is + record + LCD_RW : std_logic; + LCD_RS : std_logic; + LCD_E : std_logic; + LCD_DATA : std_logic_vector(7 downto 0); + end record; + + type LCD_DRVR_SYNCH_BUSS is + record + DRVR_READY : std_logic; + LCD_INITIALISED : std_logic; + end record; + + + type LCD_DRVR_CMD_BUSS is + record + Word : std_logic_vector(7 downto 0); + CMD_Data : std_logic; --CMD = '0' and data = '1' + Exec : std_logic; + Duration : std_logic_vector(1 downto 0); + end record; + type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0); + + +constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01"; +constant FunctionSet : std_logic_vector(7 downto 0):= X"38"; +constant RetHome : std_logic_vector(7 downto 0):= X"02"; +constant SetEntryMode : std_logic_vector(7 downto 0):= X"06"; +constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0C"; + +constant CursorON : std_logic_vector(7 downto 0):= X"0E"; +constant CursorOFF : std_logic_vector(7 downto 0):= X"0C"; + +--===========================================================| +--======L C D D R I V E R T I M I N G C O D E=====| +--===========================================================| + +constant Duration_4us : std_logic_vector(1 downto 0) := "00"; +constant Duration_100us : std_logic_vector(1 downto 0) := "01"; +constant Duration_4ms : std_logic_vector(1 downto 0) := "10"; +constant Duration_20ms : std_logic_vector(1 downto 0) := "11"; + + +end LCD_16x2_CFG; + diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_ENGINE.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_ENGINE.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_ENGINE.vhd @@ -0,0 +1,206 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 08:32:21 10/19/2010 +-- Design Name: +-- Module Name: LCD_16x2_ENGINE - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use work.LCD_16x2_CFG.all; + +entity LCD_16x2_ENGINE is + generic(OSC_freqKHz : integer := 50000); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + DATA : in std_logic_vector(16*2*8-1 downto 0); + CMD : in std_logic_vector(10 downto 0); + Exec : in std_logic; + Ready : out std_logic; + LCD_CTRL : out LCD_DRVR_CTRL_BUSS + ); +end LCD_16x2_ENGINE; + +architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is + +constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome); + + + +signal SYNCH : LCD_DRVR_SYNCH_BUSS; +signal DRIVER_CMD : LCD_DRVR_CMD_BUSS; +signal FRAME_CLK : std_logic; + +signal FRAME_CLK_reg : std_logic; +signal RefreshFlag : std_logic; +signal CMD_Flag : std_logic; +signal Exec_Reg : std_logic; + +type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1); +signal state : state_t; +signal i : integer range 0 to 32 := 0; + + + +begin + +Driver0 : entity work.LCD_16x2_DRIVER + generic map(OSC_freqKHz) + Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD); + +FRAME_CLK_GEN0 : entity work.FRAME_CLK_GEN + generic map(OSC_freqKHz) + Port map( clk,reset,FRAME_CLK); + + + +process(reset,clk) +begin + if reset = '0' then + state <= INIT0; + Ready <= '0'; + RefreshFlag <= '0'; + i <= 0; + elsif clk'event and clk ='1' then + FRAME_CLK_reg <= FRAME_CLK; + Exec_Reg <= Exec; + + if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then + RefreshFlag <= '1'; + elsif state = Refresh or state = Refresh0 or state = Refresh1 then + RefreshFlag <= '0'; + end if; + + if Exec_Reg = '0' and Exec = '1' then + CMD_Flag <= '1'; + elsif state = ExecCMD0 or state = ExecCMD1 then + CMD_Flag <= '0'; + end if; + + case state is + when INIT0 => + if SYNCH.DRVR_READY = '1' then + DRIVER_CMD.Exec <= '1'; + DRIVER_CMD.Duration <= Duration_20ms; + DRIVER_CMD.CMD_Data <= '0'; + DRIVER_CMD.Word <= ConfigTbl(i); + i <= i + 1; + state <= INIT1; + else + DRIVER_CMD.Exec <= '0'; + end if; + when INIT1 => + state <= INIT2; + DRIVER_CMD.Exec <= '0'; + when INIT2 => + if SYNCH.DRVR_READY = '1' then + if i = 5 then + state <= Idle; + else + state <= INIT0; + end if; + end if; + when Idle=> + DRIVER_CMD.Exec <= '0'; + if RefreshFlag = '1' then + Ready <= '0'; + state <= Refresh; + elsif CMD_Flag = '1' then + Ready <= '0'; + state <= ExecCMD0; + else + Ready <= '1'; + end if; + i <= 0; + when Refresh=> + if SYNCH.DRVR_READY = '1' then + DRIVER_CMD.Exec <= '1'; + DRIVER_CMD.Duration <= Duration_100us; + DRIVER_CMD.CMD_Data <= '1'; + DRIVER_CMD.Word <= DATA(i*8+7 downto i*8); + i <= i + 1; + state <= Refresh0; + else + DRIVER_CMD.Exec <= '0'; + end if; + when Refresh0=> + state <= Refresh1; + DRIVER_CMD.Exec <= '0'; + when Refresh1=> + if SYNCH.DRVR_READY = '1' then + if i = 32 then + state <= ReturnHome; + elsif i = 16 then + state <= GoLine2; + else + state <= Refresh; + end if; + end if; + + when ExecCMD0=> + if SYNCH.DRVR_READY = '1' then + DRIVER_CMD.Exec <= '1'; + DRIVER_CMD.Duration <= CMD(9 downto 8); + DRIVER_CMD.CMD_Data <= '0'; + DRIVER_CMD.Word <= CMD(7 downto 0); + state <= ExecCMD1; + else + DRIVER_CMD.Exec <= '0'; + end if; + + when ExecCMD1=> + state <= Idle; + DRIVER_CMD.Exec <= '0'; + + when GoLine2=> + if SYNCH.DRVR_READY = '1' then + DRIVER_CMD.Exec <= '1'; + DRIVER_CMD.Duration <= Duration_100us; + DRIVER_CMD.CMD_Data <= '0'; + DRIVER_CMD.Word <= X"C0"; + state <= GoLine2_0; + else + DRIVER_CMD.Exec <= '0'; + end if; + when GoLine2_0=> + state <= Refresh; + DRIVER_CMD.Exec <= '0'; + when ReturnHome=> + if SYNCH.DRVR_READY = '1' then + DRIVER_CMD.Exec <= '1'; + DRIVER_CMD.Duration <= Duration_4ms; + DRIVER_CMD.CMD_Data <= '0'; + DRIVER_CMD.Word <= X"02"; + state <= Idle; + else + DRIVER_CMD.Exec <= '0'; + end if; + end case; + end if; +end process; + + +end ar_LCD_16x2_ENGINE; + + + + + + + + + + diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_2x16_DRIVER.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_2x16_DRIVER.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_2x16_DRIVER.vhd @@ -0,0 +1,156 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:09:57 10/13/2010 +-- Design Name: +-- Module Name: LCD_2x16_DRIVER - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; + + +entity LCD_2x16_DRIVER is + generic( + OSC_Freq_MHz : integer:=60; + Refresh_RateHz : integer:=5 + ); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0); + LCD_data : out STD_LOGIC_VECTOR (7 downto 0); + LCD_RS : out STD_LOGIC; + LCD_RW : out STD_LOGIC; + LCD_E : out STD_LOGIC; + LCD_RET : out STD_LOGIC; + LCD_CS1 : out STD_LOGIC; + LCD_CS2 : out STD_LOGIC; + STATEOUT: out std_logic_vector(3 downto 0); + refreshPulse : out std_logic + ); +end LCD_2x16_DRIVER; + +architecture Behavioral of LCD_2x16_DRIVER is + +type stateT is(Rst,Configure,IDLE,RefreshScreen); +signal state : stateT; + +signal ShortTimePulse : std_logic; +signal MidleTimePulse : std_logic; +signal Refresh_RatePulse : std_logic; +signal Start : STD_LOGIC; + +signal CFGM_LCD_RS : std_logic; +signal CFGM_LCD_RW : std_logic; +signal CFGM_LCD_E : std_logic; +signal CFGM_LCD_DATA : std_logic_vector(7 downto 0); +signal CFGM_Enable : std_logic; +signal CFGM_completed : std_logic; + + +signal FRMW_LCD_RS : std_logic; +signal FRMW_LCD_RW : std_logic; +signal FRMW_LCD_E : std_logic; +signal FRMW_LCD_DATA : std_logic_vector(7 downto 0); +signal FRMW_Enable : std_logic; +signal FRMW_completed : std_logic; + +begin + + +Counter : entity work.LCD_Counter +generic map(OSC_Freq_MHz,Refresh_RateHz) +port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start); + +ConfigModule : entity work.Config_Module +port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse); + + +FrameWriter : entity work.FRAME_WRITER +port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse); + + +STATEOUT(0) <= '1' when state = Rst else '0'; +STATEOUT(1) <= '1' when state = Configure else '0'; +STATEOUT(2) <= '1' when state = IDLE else '0'; +STATEOUT(3) <= '1' when state = RefreshScreen else '0'; + + + +refreshPulse <= Refresh_RatePulse; + +Start <= '1'; + +process(reset,clk) +begin + if reset = '0' then + LCD_data <= (others=>'0'); + LCD_RS <= '0'; + LCD_RW <= '0'; + LCD_RET <= '0'; + LCD_CS1 <= '0'; + LCD_CS2 <= '0'; + LCD_E <= '0'; + state <= Rst; + CFGM_Enable <= '0'; + FRMW_Enable <= '0'; + elsif clk'event and clk ='1' then + case state is + when Rst => + LCD_data <= (others=>'0'); + LCD_RS <= '0'; + LCD_RW <= '0'; + LCD_E <= '0'; + CFGM_Enable <= '1'; + FRMW_Enable <= '0'; + if Refresh_RatePulse = '1' then + state <= Configure; + end if; + when Configure => + LCD_data <= CFGM_LCD_data; + LCD_RS <= CFGM_LCD_RS; + LCD_RW <= CFGM_LCD_RW; + LCD_E <= CFGM_LCD_E; + CFGM_Enable <= '0'; + if CFGM_completed = '1' then + state <= IDLE; + end if; + when IDLE => + if Refresh_RatePulse = '1' then + state <= RefreshScreen; + FRMW_Enable <= '1'; + end if; + LCD_RS <= '0'; + LCD_RW <= '0'; + LCD_E <= '0'; + LCD_data <= (others=>'0'); + when RefreshScreen => + LCD_data <= FRMW_LCD_data; + LCD_RS <= FRMW_LCD_RS; + LCD_RW <= FRMW_LCD_RW; + LCD_E <= FRMW_LCD_E; + FRMW_Enable <= '0'; + if FRMW_completed = '1' then + state <= IDLE; + end if; + end case; + end if; +end process; +end Behavioral; + + + + + diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_CLK_GENERATOR.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_CLK_GENERATOR.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_CLK_GENERATOR.vhd @@ -0,0 +1,72 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 08:52:25 10/18/2010 +-- Design Name: +-- Module Name: LCD_CLK_GENERATOR - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + + +entity LCD_CLK_GENERATOR is + generic(OSC_freqKHz : integer := 50000); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + clk_1us : out STD_LOGIC); +end LCD_CLK_GENERATOR; + +architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is + +Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1; + + +signal cpt1 : integer; + +signal clk_1us_int : std_logic := '0'; + + +begin + +clk_1us <= clk_1us_int; + + +process(reset,clk) +begin + if reset = '0' then + cpt1 <= 0; + clk_1us_int <= '0'; + elsif clk'event and clk = '1' then + if cpt1 = clk_1usTRIGER then + clk_1us_int <= not clk_1us_int; + cpt1 <= 0; + else + cpt1 <= cpt1 + 1; + end if; + end if; +end process; + + +end ar_LCD_CLK_GENERATOR; + + + + + + + + + diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCD.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCD.vhd new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCD.vhd @@ -0,0 +1,102 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 08:44:41 10/14/2010 +-- Design Name: +-- Module Name: Top_LCD - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.LCD_16x2_CFG.all; + +entity Top_LCD is + Port ( reset : in STD_LOGIC; + clk : in STD_LOGIC; + Bp0 : in STD_LOGIC; + Bp1 : in STD_LOGIC; + Bp2 : in STD_LOGIC; + LCD_data : out STD_LOGIC_VECTOR (7 downto 0); + LCD_RS : out STD_LOGIC; + LCD_RW : out STD_LOGIC; + LCD_E : out STD_LOGIC; + LCD_RET : out STD_LOGIC; + LCD_CS1 : out STD_LOGIC; + LCD_CS2 : out STD_LOGIC; + SF_CE0 : out std_logic + ); +end Top_LCD; + +architecture Behavioral of Top_LCD is + +signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0); +signal CMD : std_logic_vector(10 downto 0); +signal Exec : std_logic; +signal Ready : std_logic; +signal rst : std_logic; +signal LCD_CTRL : LCD_DRVR_CTRL_BUSS; + +begin + +LCD_data <= LCD_CTRL.LCD_DATA; +LCD_RS <= LCD_CTRL.LCD_RS; +LCD_RW <= LCD_CTRL.LCD_RW; +LCD_E <= LCD_CTRL.LCD_E; + + +LCD_RET <= '0'; +LCD_CS1 <= '0'; +LCD_CS2 <= '0'; + +SF_CE0 <= '1'; + +rst <= not reset; + + + +Driver0 : entity work.LCD_16x2_ENGINE + generic map(50000) + Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL); + +FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else + X"42" when Bp1 = '1' else + X"43" when Bp2 = '1' else + X"44"; + +FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else + X"47" when Bp1 = '1' else + X"48" when Bp2 = '1' else + X"49"; + + +CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else + Duration_100us & CursorOFF; + + +Exec <= Bp1; + +FramBUFF(2*8+7 downto 2*8) <= X"23"; +FramBUFF(3*8+7 downto 3*8) <= X"66"; +FramBUFF(4*8+7 downto 4*8) <= X"67"; +FramBUFF(5*8+7 downto 5*8) <= X"68"; +FramBUFF(17*8+7 downto 17*8) <= X"69"; +--FramBUFF(16*2*8-1 downto 16) <= (others => '0'); + +end Behavioral; + + + + + + diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCDcst.ucf b/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCDcst.ucf new file mode 100755 --- /dev/null +++ b/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCDcst.ucf @@ -0,0 +1,37 @@ + +NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; + +NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; + +NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; + +NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; + +NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I; +NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I; +NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I; + +NET "LCD_data<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<4>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<5>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<6>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; +NET "LCD_data<7>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; + +NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN; +NET "Bp0" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN; +NET "Bp1" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN; +NET "Bp2" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN; + +net "clk" LOC = "C9" | IOSTANDARD = LVCMOS33; +net "clk" PERIOD = 20.0ns HIGH 40%; +#net "clkOUT" LOC = "N14" | IOSTANDARD = LVCMOS33; + +#net "STATEOUT<0>" LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; +#net "STATEOUT<1>" LOC = "V6" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; +#net "STATEOUT<2>" LOC = "N12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; +#net "STATEOUT<3>" LOC = "P12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; + +#net "refreshPulse" LOC = "N15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; \ No newline at end of file