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-- Company:
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-- Engineer:
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--
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-- Create Date: 08:44:41 10/14/2010
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-- Design Name:
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-- Module Name: Top_LCD - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.LCD_16x2_CFG.all;
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entity Top_LCD is
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Port ( reset : in STD_LOGIC;
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clk : in STD_LOGIC;
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Bp0 : in STD_LOGIC;
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Bp1 : in STD_LOGIC;
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Bp2 : in STD_LOGIC;
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LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
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LCD_RS : out STD_LOGIC;
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LCD_RW : out STD_LOGIC;
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LCD_E : out STD_LOGIC;
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LCD_RET : out STD_LOGIC;
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LCD_CS1 : out STD_LOGIC;
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LCD_CS2 : out STD_LOGIC;
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SF_CE0 : out std_logic
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);
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end Top_LCD;
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architecture Behavioral of Top_LCD is
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signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0);
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signal CMD : std_logic_vector(10 downto 0);
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signal Exec : std_logic;
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signal Ready : std_logic;
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signal rst : std_logic;
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signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
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begin
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LCD_data <= LCD_CTRL.LCD_DATA;
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LCD_RS <= LCD_CTRL.LCD_RS;
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LCD_RW <= LCD_CTRL.LCD_RW;
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LCD_E <= LCD_CTRL.LCD_E;
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LCD_RET <= '0';
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LCD_CS1 <= '0';
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LCD_CS2 <= '0';
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SF_CE0 <= '1';
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rst <= not reset;
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Driver0 : entity work.LCD_16x2_ENGINE
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generic map(50000)
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Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
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FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else
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X"42" when Bp1 = '1' else
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X"43" when Bp2 = '1' else
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X"44";
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FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else
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X"47" when Bp1 = '1' else
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X"48" when Bp2 = '1' else
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X"49";
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CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else
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Duration_100us & CursorOFF;
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Exec <= Bp1;
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FramBUFF(2*8+7 downto 2*8) <= X"23";
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FramBUFF(3*8+7 downto 3*8) <= X"66";
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FramBUFF(4*8+7 downto 4*8) <= X"67";
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FramBUFF(5*8+7 downto 5*8) <= X"68";
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FramBUFF(17*8+7 downto 17*8) <= X"69";
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--FramBUFF(16*2*8-1 downto 16) <= (others => '0');
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end Behavioral;
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