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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 LIBRARY lpp;
27 USE lpp.lpp_memory.ALL;
28 USE lpp.iir_filter.ALL;
29
30 LIBRARY techmap;
31 USE techmap.gencomp.ALL;
32
33 ENTITY lpp_fifo_4_shared IS
34 GENERIC(
35 tech : INTEGER := 0;
36 Mem_use : INTEGER := use_RAM;
37 EMPTY_THRESHOLD_LIMIT : INTEGER := 16;
38 FULL_THRESHOLD_LIMIT : INTEGER := 5;
39 DataSz : INTEGER RANGE 1 TO 32 := 8;
40 AddrSz : INTEGER RANGE 3 TO 12 := 8
41 );
42 PORT(
43 clk : IN STD_LOGIC;
44 rstn : IN STD_LOGIC;
45 ---------------------------------------------------------------------------
46 run : IN STD_LOGIC;
47
48 ---------------------------------------------------------------------------
49 empty_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
50 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
51 r_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
52 r_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53
54 ---------------------------------------------------------------------------
55 full_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
56 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
57 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
58 w_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
59 w_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
60 );
61 END ENTITY;
62
63
64 ARCHITECTURE beh OF lpp_fifo_4_shared IS
65
66 SIGNAL full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
67
68 TYPE LPP_TYPE_ADDR_FIFO_SHARED IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(AddrSz-3 DOWNTO 0);
69 SIGNAL mem_r_addr_v : LPP_TYPE_ADDR_FIFO_SHARED;
70 SIGNAL mem_w_addr_v : LPP_TYPE_ADDR_FIFO_SHARED;
71 SIGNAL mem_r_addr : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
72 SIGNAL mem_w_addr : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
73
74 SIGNAL fifo_r_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
75 SIGNAL fifo_w_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
76 SIGNAL mem_r_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
77 SIGNAL mem_w_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
78 SIGNAL mem_r_e : STD_LOGIC;
79 SIGNAL mem_w_e : STD_LOGIC;
80
81 SIGNAL NB_DATA_IN_FIFO : INTEGER;
82
83
84 CONSTANT length : INTEGER := 2**(AddrSz-2);
85 TYPE INTEGER_ARRAY_4 IS ARRAY (3 DOWNTO 0) OF INTEGER;
86 SIGNAL mem_r_addr_v_int : INTEGER_ARRAY_4;
87 SIGNAL mem_w_addr_v_int : INTEGER_ARRAY_4;
88 SIGNAL space_busy : INTEGER_ARRAY_4;
89 SIGNAL space_free : INTEGER_ARRAY_4;
90
91 BEGIN
92
93 -----------------------------------------------------------------------------
94 SRAM : syncram_2p
95 GENERIC MAP(tech, AddrSz, DataSz)
96 PORT MAP(clk, mem_r_e, mem_r_addr, r_data,
97 clk, mem_w_e, mem_w_addr, w_data);
98 -----------------------------------------------------------------------------
99
100 mem_r_addr <= "00" & mem_r_addr_v(0) WHEN fifo_r_en_v(0) = '0' ELSE
101 "01" & mem_r_addr_v(1) WHEN fifo_r_en_v(1) = '0' ELSE
102 "10" & mem_r_addr_v(2) WHEN fifo_r_en_v(2) = '0' ELSE
103 "11" & mem_r_addr_v(3); -- WHEN fifo_r_en(2) = '0' ELSE
104
105 mem_w_addr <= "00" & mem_w_addr_v(0) WHEN fifo_w_en_v(0) = '0' ELSE
106 "01" & mem_w_addr_v(1) WHEN fifo_w_en_v(1) = '0' ELSE
107 "10" & mem_w_addr_v(2) WHEN fifo_w_en_v(2) = '0' ELSE
108 "11" & mem_w_addr_v(3); -- WHEN fifo_r_en(2) = '0' ELSE
109
110 mem_r_e <= '0' WHEN mem_r_en_v = "1111" ELSE '1';
111 mem_w_e <= '0' WHEN mem_w_en_v = "1111" ELSE '1';
112
113 ----------------------------------------------------------------------------
114 all_fifo : FOR I IN 3 DOWNTO 0 GENERATE
115 fifo_r_en_v(I) <= r_en(I);
116 fifo_w_en_v(I) <= w_en(I);
117
118 lpp_fifo_control_1 : lpp_fifo_control
119 GENERIC MAP (
120 AddrSz => AddrSz-2,
121 EMPTY_THRESHOLD_LIMIT => EMPTY_THRESHOLD_LIMIT,
122 FULL_THRESHOLD_LIMIT => FULL_THRESHOLD_LIMIT)
123 PORT MAP (
124 clk => clk,
125 rstn => rstn,
126 reUse => '0',
127 run => run,
128 fifo_r_en => fifo_r_en_v(I),
129 fifo_w_en => fifo_w_en_v(I),
130 mem_r_en => mem_r_en_v(I),
131 mem_w_en => mem_w_en_v(I),
132 mem_r_addr => mem_r_addr_v(I),
133 mem_w_addr => mem_w_addr_v(I),
134 empty => empty(I),
135 full => full_s(I),
136 full_almost => full_almost(I),
137 empty_threshold => empty_threshold(I),
138 full_threshold => full_threshold(I)
139 );
140
141 --full(I) <= full_s(I);
142
143 --mem_w_addr_v_int(I) <= to_integer(UNSIGNED(mem_w_addr_v(I)));
144 --mem_r_addr_v_int(I) <= to_integer(UNSIGNED(mem_r_addr_v(I)));
145
146 --space_busy(I) <= length WHEN full_s(I) = '1' ELSE
147 -- length + mem_w_addr_v_int(I) - mem_r_addr_v_int(I) WHEN mem_w_addr_v_int(I) < mem_r_addr_v_int(I) ELSE
148 -- mem_w_addr_v_int(I) - mem_r_addr_v_int(I);
149
150 --space_free(I) <= length - space_busy(I);
151
152 --empty_threshold(I) <= '0' WHEN space_busy(I) > EMPTY_THRESHOLD_LIMIT ELSE '1';
153 --full_threshold(I) <= '0' WHEN space_free(I) > FULL_THRESHOLD_LIMIT ELSE '1';
154
155 END GENERATE all_fifo;
156
157
158
159 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28
29 ENTITY lpp_fifo_4_shared_headreg_latency_0 IS
30 PORT(
31 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33 ---------------------------------------------------------------------------
34 run : IN STD_LOGIC;
35 ---------------------------------------------------------------------------
36 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
37 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
38
39 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
40 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
41 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
42 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
43 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
44 ---------------------------------------------------------------------------
45 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
47 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
48 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
49 );
50 END ENTITY;
51
52
53 ARCHITECTURE beh OF lpp_fifo_4_shared_headreg_latency_0 IS
54
55 TYPE REG_HEAD_TYPE IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
56 SIGNAL reg_head_data : REG_HEAD_TYPE;
57
58
59 SIGNAL reg_head_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
60 SIGNAL i_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
61 SIGNAL o_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 SIGNAL i_data_ren_s_temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 SIGNAL i_data_ren_s : STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
64 SIGNAL i_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
65
66
67 BEGIN
68 --i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
69 i_data_ren <= i_data_ren_s;
70 o_empty_almost <= i_empty_almost; --TODO
71
72 o_rdata_0 <= i_rdata WHEN o_data_ren_pre(0) = '0' AND o_data_ren(0) = '0' ELSE reg_head_data(0) ;
73 o_rdata_1 <= i_rdata WHEN o_data_ren_pre(1) = '0' AND o_data_ren(1) = '0' ELSE reg_head_data(1) ;
74 o_rdata_2 <= i_rdata WHEN o_data_ren_pre(2) = '0' AND o_data_ren(2) = '0' ELSE reg_head_data(2) ;
75 o_rdata_3 <= i_rdata WHEN o_data_ren_pre(3) = '0' AND o_data_ren(3) = '0' ELSE reg_head_data(3) ;
76
77 i_data_ren_s(0) <= i_data_ren_s_temp(0);
78 i_data_ren_s(1) <= i_data_ren_s_temp(1) WHEN i_data_ren_s_temp(0) = '1' ELSE '1';
79 i_data_ren_s(2) <= i_data_ren_s_temp(2) WHEN i_data_ren_s_temp(1 DOWNTO 0) = "11" ELSE '1';
80 i_data_ren_s(3) <= i_data_ren_s_temp(3) WHEN i_data_ren_s_temp(2 DOWNTO 0) = "111" ELSE '1';
81
82 each_fifo: FOR I IN 3 DOWNTO 0 GENERATE
83 o_empty(I) <= NOT reg_head_full(I);
84
85 -- i_data_ren_pre(I) <= i_data_ren_s(I);
86
87 PROCESS (clk, rstn)
88 BEGIN
89 IF rstn = '0' THEN
90 reg_head_data(I) <= (OTHERS => '0');
91 i_data_ren_pre(I) <= '1';
92 reg_head_full(I) <= '0';
93 o_data_ren_pre(I) <= '1';
94 ELSIF clk'event AND clk = '1' THEN
95 o_data_ren_pre(I) <= o_data_ren(I) ;
96 IF i_data_ren_pre(I) = '0' THEN
97 reg_head_data(I) <= i_rdata;
98 END IF;
99 i_data_ren_pre(I) <= i_data_ren_s(I);
100
101 -- IF i_data_ren_pre(I) = '0' THEN
102 IF i_data_ren_s(I) = '0' THEN
103 reg_head_full(I) <= '1';
104 -- ELSIF o_data_ren_pre(I) = '0' THEN
105 ELSIF o_data_ren(I) = '0' THEN
106 reg_head_full(I) <= '0';
107 END IF;
108
109 END IF;
110 END PROCESS;
111
112 i_data_ren_s_temp(I) <= '1' WHEN i_empty_reg(I) = '1' ELSE
113 '0' WHEN o_data_ren(I) = '0' ELSE
114 '0' WHEN reg_head_full(I) = '0' ELSE
115 '1';
116
117
118 PROCESS (clk, rstn)
119 BEGIN
120 IF rstn = '0' THEN
121 i_empty_reg(I) <= '1';
122 ELSIF clk'event AND clk = '1' THEN
123 i_empty_reg(I) <= i_empty(I);
124 END IF;
125 END PROCESS;
126
127
128
129 END GENERATE each_fifo;
130
131
132 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28
29 ENTITY lpp_fifo_4_shared_headreg_latency_1 IS
30 PORT(
31 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33 ---------------------------------------------------------------------------
34 run : IN STD_LOGIC;
35 ---------------------------------------------------------------------------
36 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
37 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
38
39 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
40 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
41 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
42 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
43 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
44 ---------------------------------------------------------------------------
45 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
47 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
48 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
49 );
50 END ENTITY;
51
52
53 ARCHITECTURE beh OF lpp_fifo_4_shared_headreg_latency_1 IS
54
55 TYPE REG_HEAD_TYPE IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
56 SIGNAL reg_head_data : REG_HEAD_TYPE;
57
58
59 SIGNAL reg_head_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
60 SIGNAL i_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
61 SIGNAL o_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 SIGNAL i_data_ren_s_temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 SIGNAL i_data_ren_s : STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
64 SIGNAL i_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
65 SIGNAL o_rdata_0_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --
66 SIGNAL o_rdata_1_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --
67 SIGNAL o_rdata_2_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --
68 SIGNAL o_rdata_3_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --
69
70
71 BEGIN
72 --i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
73 i_data_ren <= i_data_ren_s;
74
75 o_rdata_0_s <= i_rdata WHEN o_data_ren_pre(0) = '0' AND o_data_ren(0) = '0' ELSE reg_head_data(0) ;
76 o_rdata_1_s <= i_rdata WHEN o_data_ren_pre(1) = '0' AND o_data_ren(1) = '0' ELSE reg_head_data(1) ;
77 o_rdata_2_s <= i_rdata WHEN o_data_ren_pre(2) = '0' AND o_data_ren(2) = '0' ELSE reg_head_data(2) ;
78 o_rdata_3_s <= i_rdata WHEN o_data_ren_pre(3) = '0' AND o_data_ren(3) = '0' ELSE reg_head_data(3) ;
79
80
81 PROCESS (clk, rstn)
82 BEGIN -- PROCESS
83 IF rstn = '0' THEN -- asynchronous reset (active low)
84 o_rdata_0 <= (OTHERS => '0');
85 o_rdata_1 <= (OTHERS => '0');
86 o_rdata_2 <= (OTHERS => '0');
87 o_rdata_3 <= (OTHERS => '0');
88 --o_empty_almost <= (OTHERS => '0');
89 --o_empty <= (OTHERS => '0');
90 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
91 o_rdata_0 <= o_rdata_0_s;
92 o_rdata_1 <= o_rdata_1_s;
93 o_rdata_2 <= o_rdata_2_s;
94 o_rdata_3 <= o_rdata_3_s;
95
96 --o_empty_almost <= i_empty_almost; --TODO
97 --o_empty <= NOT reg_head_full;
98 END IF;
99 END PROCESS;
100
101
102 o_empty_almost <= i_empty_almost; --TODO
103 o_empty <= NOT reg_head_full OR (i_empty AND o_data_ren);
104
105
106
107 i_data_ren_s(0) <= i_data_ren_s_temp(0);
108 i_data_ren_s(1) <= i_data_ren_s_temp(1) WHEN i_data_ren_s_temp(0) = '1' ELSE '1';
109 i_data_ren_s(2) <= i_data_ren_s_temp(2) WHEN i_data_ren_s_temp(1 DOWNTO 0) = "11" ELSE '1';
110 i_data_ren_s(3) <= i_data_ren_s_temp(3) WHEN i_data_ren_s_temp(2 DOWNTO 0) = "111" ELSE '1';
111
112 each_fifo: FOR I IN 3 DOWNTO 0 GENERATE
113
114 -- i_data_ren_pre(I) <= i_data_ren_s(I);
115
116 PROCESS (clk, rstn)
117 BEGIN
118 IF rstn = '0' THEN
119 reg_head_data(I) <= (OTHERS => '0');
120 i_data_ren_pre(I) <= '1';
121 reg_head_full(I) <= '0';
122 o_data_ren_pre(I) <= '1';
123 ELSIF clk'event AND clk = '1' THEN
124 o_data_ren_pre(I) <= o_data_ren(I) ;
125 IF i_data_ren_pre(I) = '0' THEN
126 reg_head_data(I) <= i_rdata;
127 END IF;
128 i_data_ren_pre(I) <= i_data_ren_s(I);
129 IF i_data_ren_s(I) = '0' THEN
130 reg_head_full(I) <= '1';
131 ELSIF o_data_ren(I) = '0' THEN
132 reg_head_full(I) <= '0';
133 END IF;
134
135 END IF;
136 END PROCESS;
137
138 i_data_ren_s_temp(I) <= '1' WHEN i_empty_reg(I) = '1' ELSE
139 '0' WHEN o_data_ren(I) = '0' ELSE
140 '0' WHEN reg_head_full(I) = '0' ELSE
141 '1';
142
143
144 PROCESS (clk, rstn)
145 BEGIN
146 IF rstn = '0' THEN
147 i_empty_reg(I) <= '1';
148 ELSIF clk'event AND clk = '1' THEN
149 i_empty_reg(I) <= i_empty(I);
150 END IF;
151 END PROCESS;
152
153
154
155 END GENERATE each_fifo;
156
157
158 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 ENTITY lpp_fifo_control IS
27 GENERIC(
28 AddrSz : INTEGER RANGE 2 TO 12 := 8;
29 EMPTY_THRESHOLD_LIMIT : INTEGER := 16;
30 FULL_THRESHOLD_LIMIT : INTEGER := 5
31 );
32 PORT(
33 clk : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
35 --
36 reUse : IN STD_LOGIC;
37 run : IN STD_LOGIC;
38
39 --IN
40 fifo_r_en : IN STD_LOGIC;
41 fifo_w_en : IN STD_LOGIC;
42
43 mem_r_en : OUT STD_LOGIC;
44 mem_w_en : OUT STD_LOGIC;
45 mem_r_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0);
46 mem_w_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0);
47
48 empty : OUT STD_LOGIC;
49 full : OUT STD_LOGIC;
50 full_almost : OUT STD_LOGIC;
51 empty_threshold : OUT STD_LOGIC;
52 full_threshold : OUT STD_LOGIC
53
54 );
55 END ENTITY;
56
57
58 ARCHITECTURE beh OF lpp_fifo_control IS
59
60 SIGNAL sFull : STD_LOGIC;
61 SIGNAL sFull_s : STD_LOGIC;
62 SIGNAL sEmpty_s : STD_LOGIC;
63
64 SIGNAL sEmpty : STD_LOGIC;
65 SIGNAL sREN : STD_LOGIC;
66 SIGNAL sWEN : STD_LOGIC;
67
68 SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
69 SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
70 SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
71 SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
72
73 SIGNAL almost_full_s : STD_LOGIC;
74 SIGNAL almost_full_r : STD_LOGIC;
75
76 SIGNAL mem_r_addr_int : INTEGER;
77 SIGNAL mem_w_addr_int : INTEGER;
78 SIGNAL space_busy : INTEGER;
79 SIGNAL space_free : INTEGER;
80
81 CONSTANT length : INTEGER := 2**(AddrSz);
82
83 BEGIN
84
85 mem_r_addr <= Raddr_vect;
86 mem_w_addr <= Waddr_vect;
87
88
89 mem_r_en <= sREN;
90 mem_w_en <= sWEN;
91 --=============================
92 -- Read section
93 --=============================
94 sREN <= FIFO_R_EN OR sEmpty;
95 --sRE <= NOT sREN;
96
97 sEmpty_s <= '0' WHEN ReUse = '1' ELSE
98 '1' WHEN sEmpty = '1' AND Fifo_W_En = '1' ELSE
99 '1' WHEN sEmpty = '0' AND (Fifo_W_En = '1' AND Fifo_R_en = '0' AND Raddr_vect_s = Waddr_vect) ELSE
100 '0';
101
102 Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
103
104 PROCESS (clk, rstn)
105 BEGIN
106 IF(rstn = '0')THEN
107 Raddr_vect <= (OTHERS => '0');
108 sempty <= '1';
109 ELSIF(clk'EVENT AND clk = '1')THEN
110
111 IF run = '0' THEN
112 Raddr_vect <= (OTHERS => '0');
113 sempty <= '1';
114 ELSE
115 sEmpty <= sempty_s;
116
117 IF(sREN = '0' AND sempty = '0')THEN
118 Raddr_vect <= Raddr_vect_s;
119 END IF;
120 END IF;
121
122 END IF;
123 END PROCESS;
124
125 --=============================
126 -- Write section
127 --=============================
128 sWEN <= FIFO_W_EN OR sFull;
129 -- sWE <= NOT sWEN;
130
131 sFull_s <= '1' WHEN ReUse = '1' ELSE
132 '1' WHEN Waddr_vect_s = Raddr_vect AND FIFO_R_EN = '1' AND FIFO_W_EN = '0' ELSE
133 '1' WHEN sFull = '1' AND FIFO_R_EN = '1' ELSE
134 '0';
135
136 almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND FIFO_R_EN = '1' AND FIFO_W_EN = '0' ELSE
137 '1' WHEN almost_full_r = '1' AND FIFO_W_EN = FIFO_R_EN ELSE
138 '0';
139
140 Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
141
142 PROCESS (clk, rstn)
143 BEGIN
144 IF(rstn = '0')THEN
145 Waddr_vect <= (OTHERS => '0');
146 sfull <= '0';
147 almost_full_r <= '0';
148 ELSIF(clk'EVENT AND clk = '1')THEN
149 IF run = '0' THEN
150 Waddr_vect <= (OTHERS => '0');
151 sfull <= '0';
152 almost_full_r <= '0';
153 ELSE
154 sfull <= sfull_s;
155 almost_full_r <= almost_full_s;
156
157 IF(sWEN = '0' AND sfull = '0')THEN
158 Waddr_vect <= Waddr_vect_s;
159 END IF;
160 END IF;
161 END IF;
162 END PROCESS;
163
164 full_almost <= almost_full_s;
165 full <= sFull_s;
166 empty <= sEmpty_s;
167
168 -----------------------------------------------------------------------------
169 mem_w_addr_int <= to_integer(UNSIGNED(Waddr_vect));
170 mem_r_addr_int <= to_integer(UNSIGNED(Raddr_vect));
171
172 space_busy <= length WHEN sFull = '1' ELSE
173 length + mem_w_addr_int - mem_r_addr_int WHEN mem_w_addr_int < mem_r_addr_int ELSE
174 mem_w_addr_int - mem_r_addr_int;
175
176 space_free <= length - space_busy;
177
178 empty_threshold <= '0' WHEN space_busy > EMPTY_THRESHOLD_LIMIT ELSE '1';
179 full_threshold <= '0' WHEN space_free > FULL_THRESHOLD_LIMIT ELSE '1';
180 -----------------------------------------------------------------------------
181
182
183 END ARCHITECTURE;
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Show file before | Show file after | Hide comments
@@ -428,7 +428,7 BEGIN -- beh
428 pirq_ms => 6,
428 pirq_ms => 6,
429 pirq_wfp => 14,
429 pirq_wfp => 14,
430 hindex => 2,
430 hindex => 2,
431 top_lfr_version => X"000118") -- aa.bb.cc version
431 top_lfr_version => X"00011B") -- aa.bb.cc version
432 PORT MAP (
432 PORT MAP (
433 clk => clk_25,
433 clk => clk_25,
434 rstn => reset,
434 rstn => reset,
Show file before | Show file after | Hide comments
@@ -13,7 +13,7 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=
15 VHDLSYNFILES=
16 VHDLSIMFILES= tb.vhd
16 VHDLSIMFILES= FIFO_Verif.vhd tb.vhd
17 SIMTOP=testbench
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
Show file before | Show file after | Hide comments
@@ -1,3 +1,5
1 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO_control.vhd
2 vcom -quiet -93 -work work FIFO_Verif.vhd
1 vcom -quiet -93 -work work tb.vhd
3 vcom -quiet -93 -work work tb.vhd
2
4
3 vsim work.testbench
5 vsim work.testbench
Show file before | Show file after | Hide comments
@@ -13,236 +13,135 ENTITY testbench IS
13 END;
13 END;
14
14
15 ARCHITECTURE behav OF testbench IS
15 ARCHITECTURE behav OF testbench IS
16
17 COMPONENT fifo_verif
18 PORT (
19 verif_clk : OUT STD_LOGIC;
20 verif_rstn : OUT STD_LOGIC;
21 verif_ren : OUT STD_LOGIC;
22 verif_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
23 verif_wen : OUT STD_LOGIC;
24 verif_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
25 verif_empty : IN STD_LOGIC;
26 verif_full : IN STD_LOGIC;
27 verif_almost_full : IN STD_LOGIC;
28 error_now : OUT STD_LOGIC;
29 error_new : OUT STD_LOGIC);
30 END COMPONENT;
16
31
17 -----------------------------------------------------------------------------
32 -----------------------------------------------------------------------------
18 -- Common signal
33 SIGNAL CEL_clk : STD_LOGIC := '0';
19 SIGNAL clk : STD_LOGIC := '0';
34 SIGNAL CEL_rstn : STD_LOGIC := '0';
20 SIGNAL rstn : STD_LOGIC := '0';
35 -----------------------------------------------------------------------------
21 SIGNAL run : STD_LOGIC := '0';
36 SIGNAL CEL_data_ren : STD_LOGIC;
22
37 SIGNAL CEL_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
38 SIGNAL CEL_data_wen : STD_LOGIC;
39 SIGNAL CEL_wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
40 SIGNAL CEL_full_almost : STD_LOGIC;
41 SIGNAL CEL_full : STD_LOGIC;
42 SIGNAL CEL_empty : STD_LOGIC;
43 -----------------------------------------------------------------------------
44 SIGNAL CEL_error_now : STD_LOGIC;
45 SIGNAL CEL_error_new : STD_LOGIC;
23 -----------------------------------------------------------------------------
46 -----------------------------------------------------------------------------
24
47
25 SIGNAL full_almost : STD_LOGIC;
48 -----------------------------------------------------------------------------
26 SIGNAL full : STD_LOGIC;
49 SIGNAL RAM_clk : STD_LOGIC := '0';
27 SIGNAL data_wen : STD_LOGIC;
50 SIGNAL RAM_rstn : STD_LOGIC := '0';
28 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
29
30 SIGNAL empty : STD_LOGIC;
31 SIGNAL data_ren : STD_LOGIC;
32 SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
33 SIGNAL data_out_obs : STD_LOGIC_VECTOR(31 DOWNTO 0);
34
35 SIGNAL empty_reg : STD_LOGIC;
36 SIGNAL full_reg : STD_LOGIC;
37
38 -----------------------------------------------------------------------------
51 -----------------------------------------------------------------------------
39 TYPE DATA_CHANNEL IS ARRAY (0 TO 128-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
52 SIGNAL RAM_data_ren : STD_LOGIC;
40 SIGNAL data_in : DATA_CHANNEL;
53 SIGNAL RAM_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
41
54 SIGNAL RAM_data_wen : STD_LOGIC;
55 SIGNAL RAM_wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
56 SIGNAL RAM_full_almost : STD_LOGIC;
57 SIGNAL RAM_full : STD_LOGIC;
58 SIGNAL RAM_empty : STD_LOGIC;
42 -----------------------------------------------------------------------------
59 -----------------------------------------------------------------------------
43 CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE
60 SIGNAL RAM_error_now : STD_LOGIC;
44 CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0;
61 SIGNAL RAM_error_new : STD_LOGIC;
45 SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
62 -----------------------------------------------------------------------------
46 --
63
47 SIGNAL rand_ren : STD_LOGIC;
48 SIGNAL rand_wen : STD_LOGIC;
49
50 SIGNAL pointer_read : INTEGER;
51 SIGNAL pointer_write : INTEGER := 0;
52
53 SIGNAL error_now : STD_LOGIC;
54 SIGNAL error_new : STD_LOGIC;
55
56 SIGNAL read_stop : STD_LOGIC;
57 BEGIN
64 BEGIN
58
65
59
66
60 all_J : FOR J IN 0 TO 127 GENERATE
61 data_in(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+1, 32));
62 END GENERATE all_J;
63
64
65 -----------------------------------------------------------------------------
67 -----------------------------------------------------------------------------
66 lpp_fifo_1 : lpp_fifo
68 lpp_fifo_CEL : lpp_fifo
67 GENERIC MAP (
69 GENERIC MAP (
68 tech => 0,
70 tech => 0,
69 Mem_use => use_CEL,
71 Mem_use => use_CEL,
72 EMPTY_THRESHOLD_LIMIT => 1,
73 FULL_THRESHOLD_LIMIT => 1,
70 DataSz => 32,
74 DataSz => 32,
71 AddrSz => 8)
75 AddrSz => 8)
72 PORT MAP (
76 PORT MAP (
73 clk => clk,
77 clk => CEL_clk,
74 rstn => rstn,
78 rstn => CEL_rstn,
75 reUse => '0',
79 reUse => '0',
76 ren => data_ren,
80 ren => CEL_data_ren,
77 rdata => data_out,
81 rdata => CEL_data_out,
78 wen => data_wen,
82 wen => CEL_data_wen,
79 wdata => wdata,
83 wdata => CEL_wdata,
80 empty => empty,
84 empty => CEL_empty,
81 full => full,
85 full => CEL_full,
82 almost_full => full_almost);
86 full_almost => CEL_full_almost,
83
87 empty_threshold => OPEN,
88 full_threshold => OPEN);
84 -----------------------------------------------------------------------------
89 -----------------------------------------------------------------------------
85
90 fifo_verif_CEL : fifo_verif
91 PORT MAP (
92 verif_clk => CEL_clk,
93 verif_rstn => CEL_rstn,
94 verif_ren => CEL_data_ren,
95 verif_rdata => CEL_data_out,
96 verif_wen => CEL_data_wen,
97 verif_wdata => CEL_wdata,
98 verif_empty => CEL_empty,
99 verif_full => CEL_full,
100 verif_almost_full => CEL_full_almost,
101 error_now => CEL_error_now,
102 error_new => CEL_error_new
103 );
104 -----------------------------------------------------------------------------
86
105
87
106
88 -----------------------------------------------------------------------------
107 -----------------------------------------------------------------------------
89 -- READ
108 lpp_fifo_RAM : lpp_fifo
109 GENERIC MAP (
110 tech => 0,
111 Mem_use => use_RAM,
112 EMPTY_THRESHOLD_LIMIT => 1,
113 FULL_THRESHOLD_LIMIT => 1,
114 DataSz => 32,
115 AddrSz => 8)
116 PORT MAP (
117 clk => RAM_clk,
118 rstn => RAM_rstn,
119 reUse => '0',
120 ren => RAM_data_ren,
121 rdata => RAM_data_out,
122 wen => RAM_data_wen,
123 wdata => RAM_wdata,
124 empty => RAM_empty,
125 full => RAM_full,
126 full_almost => RAM_full_almost,
127 empty_threshold => OPEN,
128 full_threshold => OPEN);
90 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
91 PROCESS (clk, rstn)
130 fifo_verif_RAM : fifo_verif
92 BEGIN -- PROCESS
131 PORT MAP (
93 IF rstn = '0' THEN -- asynchronous reset (active low)
132 verif_clk => RAM_clk,
94 empty_reg <= '1';
133 verif_rstn => RAM_rstn,
95 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
134 verif_ren => RAM_data_ren,
96 empty_reg <= empty;
135 verif_rdata => RAM_data_out,
97 END IF;
136 verif_wen => RAM_data_wen,
98 END PROCESS;
137 verif_wdata => RAM_wdata,
99
138 verif_empty => RAM_empty,
100 PROCESS (clk, rstn)
139 verif_full => RAM_full,
101 BEGIN -- PROCESS
140 verif_almost_full => RAM_full_almost,
102 IF rstn = '0' THEN -- asynchronous reset (active low)
141 error_now => RAM_error_now,
103 data_out_obs <= (OTHERS => '0');
142 error_new => RAM_error_new
104
143 );
105 pointer_read <= 0;
106 error_now <= '0';
107 error_new <= '0';
108
109 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
110 error_now <= '0';
111 IF empty_reg = '0' THEN
112 IF data_ren = '0' THEN
113 --IF data_ren_and_not_empty = '0' THEN
114 error_new <= '0';
115 data_out_obs <= data_out;
116
117 IF pointer_read < 127 THEN
118 pointer_read <= pointer_read + 1;
119 ELSE
120 pointer_read <= 0;
121 END IF;
122
123 IF data_out /= data_in(pointer_read) THEN
124 error_now <= '1';
125 error_new <= '1';
126 END IF;
127 END IF;
128
129 END IF;
130 END IF;
131 END PROCESS;
132 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
133
145
134
146
135
136
137 -----------------------------------------------------------------------------
138 -- WRITE
139 -----------------------------------------------------------------------------
140 PROCESS (clk, rstn)
141 BEGIN -- PROCESS
142 IF rstn = '0' THEN -- asynchronous reset (active low)
143 full_reg <= '0';
144 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
145 full_reg <= full;
146 END IF;
147 END PROCESS;
148
149 proc_verif : PROCESS (clk, rstn)
150 BEGIN -- PROCESS proc_verif
151 IF rstn = '0' THEN -- asynchronous reset (active low)
152 pointer_write <= 0;
153 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
154 IF data_wen = '0' THEN
155 IF full_reg = '0' THEN
156 IF pointer_write < 127 THEN
157 pointer_write <= pointer_write+1;
158 ELSE
159 pointer_write <= 0;
160 END IF;
161 END IF;
162 END IF;
163 END IF;
164 END PROCESS proc_verif;
165
166 wdata <= data_in(pointer_write) WHEN data_wen = '0' ELSE (OTHERS => 'X');
167 -----------------------------------------------------------------------------
168
169
170
171 -----------------------------------------------------------------------------
172 clk <= NOT clk AFTER 5 ns; -- 100 MHz
173 -----------------------------------------------------------------------------
174 WaveGen_Proc : PROCESS
175 BEGIN
176 -- insert signal assignments here
177 WAIT UNTIL clk = '1';
178 read_stop <= '0';
179 rstn <= '0';
180 run <= '0';
181 WAIT UNTIL clk = '1';
182 WAIT UNTIL clk = '1';
183 WAIT UNTIL clk = '1';
184 rstn <= '1';
185 WAIT UNTIL clk = '1';
186 WAIT UNTIL clk = '1';
187 WAIT UNTIL clk = '1';
188 WAIT UNTIL clk = '1';
189 WAIT UNTIL clk = '1';
190 run <= '1';
191 WAIT UNTIL clk = '1';
192 WAIT UNTIL clk = '1';
193 WAIT UNTIL clk = '1';
194 WAIT UNTIL clk = '1';
195 WAIT FOR 10 us;
196 read_stop <= '1';
197 WAIT FOR 10 us;
198 read_stop <= '0';
199 WAIT FOR 80 us;
200 REPORT "*** END simulation ***" SEVERITY failure;
201 WAIT;
202 END PROCESS WaveGen_Proc;
203 -----------------------------------------------------------------------------
204
205
206
207 -----------------------------------------------------------------------------
208 -- RANDOM GENERATOR
209 -----------------------------------------------------------------------------
210 PROCESS (clk, rstn)
211 VARIABLE seed1, seed2 : POSITIVE;
212 VARIABLE rand1 : REAL;
213 VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
214 BEGIN -- PROCESS
215 IF rstn = '0' THEN -- asynchronous reset (active low)
216 random_vector <= (OTHERS => '0');
217 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
218 UNIFORM(seed1, seed2, rand1);
219 RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR(
220 to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)),
221 RANDOM_VECTOR_VAR'LENGTH)
222 );
223 random_vector <= RANDOM_VECTOR_VAR;
224 END IF;
225 END PROCESS;
226 -----------------------------------------------------------------------------
227 rand_wen <= random_vector(1);
228 rand_ren <= random_vector(0);
229 -----------------------------------------------------------------------------
230 PROCESS (clk, rstn)
231 BEGIN -- PROCESS
232 IF rstn = '0' THEN -- asynchronous reset (active low)
233 data_wen <= '1';
234 data_ren <= '1';
235 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
236 data_wen <= rand_wen;
237 IF read_stop = '0' THEN
238 data_ren <= rand_ren;
239 ELSE
240 data_ren <= '1';
241 END IF;
242 END IF;
243 END PROCESS;
244 -----------------------------------------------------------------------------
245
246
247
248 END;
147 END;
Show file before | Show file after | Hide comments
@@ -1,23 +1,42
1 onerror {resume}
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group COMMON /testbench/clk
3 add wave -noupdate -expand -group FIFO_CEL -expand -group COMMON /testbench/cel_clk
4 add wave -noupdate -expand -group COMMON /testbench/rstn
4 add wave -noupdate -expand -group FIFO_CEL -expand -group COMMON /testbench/cel_rstn
5 add wave -noupdate -expand -group COMMON /testbench/run
5 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_READ /testbench/cel_data_out
6 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full_almost
6 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_READ /testbench/cel_data_ren
7 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full
7 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_READ /testbench/cel_empty
8 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/data_wen
8 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_data_wen
9 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/wdata
9 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_full
10 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/empty
10 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_full_almost
11 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_ren
11 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_wdata
12 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_out
12 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_ERROR /testbench/cel_error_new
13 add wave -noupdate -radix hexadecimal /testbench/data_out_obs
13 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_ERROR /testbench/cel_error_now
14 add wave -noupdate /testbench/pointer_read
14 add wave -noupdate -expand -group FIFO_RAM -group COMMON /testbench/ram_clk
15 add wave -noupdate /testbench/pointer_write
15 add wave -noupdate -expand -group FIFO_RAM -group COMMON /testbench/ram_rstn
16 add wave -noupdate /testbench/error_now
16 add wave -noupdate -expand -group FIFO_RAM -group FIFO_READ /testbench/ram_data_out
17 add wave -noupdate /testbench/error_new
17 add wave -noupdate -expand -group FIFO_RAM -group FIFO_READ /testbench/ram_data_ren
18 add wave -noupdate /testbench/read_stop
18 add wave -noupdate -expand -group FIFO_RAM -group FIFO_READ /testbench/ram_empty
19 add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_data_wen
20 add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_full
21 add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_full_almost
22 add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_wdata
23 add wave -noupdate -expand -group FIFO_RAM -expand -group FIFO_ERROR /testbench/ram_error_new
24 add wave -noupdate -expand -group FIFO_RAM -expand -group FIFO_ERROR /testbench/ram_error_now
25 add wave -noupdate -format Analog-Step -height 74 -max 256.0 /testbench/lpp_fifo_ram/lpp_fifo_control_1/space_busy
26 add wave -noupdate -format Analog-Step -height 74 -max 256.0 /testbench/lpp_fifo_ram/lpp_fifo_control_1/space_free
27 add wave -noupdate /testbench/fifo_verif_ram/read_stop
28 add wave -noupdate /testbench/fifo_verif_ram/write_stop
29 add wave -noupdate -expand -group EMPTY_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/empty
30 add wave -noupdate -expand -group EMPTY_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/empty_threshold
31 add wave -noupdate -expand -group FULL_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/full
32 add wave -noupdate -expand -group FULL_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/full_almost
33 add wave -noupdate -expand -group FULL_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/full_threshold
34 add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/waddr_vect
35 add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/raddr_vect
36 add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/waddr_vect_s
37 add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/raddr_vect_s
19 TreeUpdate [SetDefaultTree]
38 TreeUpdate [SetDefaultTree]
20 WaveRestoreCursors {{Cursor 1} {56085000 ps} 0}
39 WaveRestoreCursors {{Cursor 1} {4865000 ps} 0}
21 configure wave -namecolwidth 510
40 configure wave -namecolwidth 510
22 configure wave -valuecolwidth 172
41 configure wave -valuecolwidth 172
23 configure wave -justifyvalue left
42 configure wave -justifyvalue left
@@ -32,4 +51,4 configure wave -griddelta 40
32 configure wave -timeline 0
51 configure wave -timeline 0
33 configure wave -timelineunits ns
52 configure wave -timelineunits ns
34 update
53 update
35 WaveRestoreZoom {0 ps} {105131250 ps}
54 WaveRestoreZoom {0 ps} {127181250 ps}
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@@ -42,6 +42,8 ENTITY lppFIFOxN IS
42
42
43 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
43 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
44
44
45 run : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
46
45 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
47 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
46 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
48 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
47
49
@@ -64,19 +66,25 BEGIN
64 GENERIC MAP (
66 GENERIC MAP (
65 tech => tech,
67 tech => tech,
66 Mem_use => Mem_use,
68 Mem_use => Mem_use,
69 EMPTY_THRESHOLD_LIMIT => 1,
70 FULL_THRESHOLD_LIMIT => 1,
67 DataSz => Data_sz,
71 DataSz => Data_sz,
68 AddrSz => Addr_sz)
72 AddrSz => Addr_sz)
69 PORT MAP (
73 PORT MAP (
70 clk => clk,
74 clk => clk,
71 rstn => rstn,
75 rstn => rstn,
72 reUse => reUse(I),
76 reUse => reUse(I),
77 run => run(I),
73 ren => ren(I),
78 ren => ren(I),
74 rdata => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ),
79 rdata => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ),
75 wen => wen(I),
80 wen => wen(I),
76 wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)),
81 wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)),
77 empty => empty(I),
82 empty => empty(I),
78 full => full(I),
83 full => full(I),
79 almost_full => almost_full(I));
84 full_almost => almost_full(I),
85 empty_threshold => OPEN,
86 full_threshold => OPEN
87 );
80 END GENERATE;
88 END GENERATE;
81
89
82 END ARCHITECTURE;
90 END ARCHITECTURE;
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@@ -30,51 +30,47 USE techmap.gencomp.ALL;
30
30
31 ENTITY lpp_fifo IS
31 ENTITY lpp_fifo IS
32 GENERIC(
32 GENERIC(
33 tech : INTEGER := 0;
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
34 Mem_use : INTEGER := use_RAM;
35 DataSz : INTEGER RANGE 1 TO 32 := 8;
35 EMPTY_THRESHOLD_LIMIT : INTEGER := 16;
36 AddrSz : INTEGER RANGE 2 TO 12 := 8
36 FULL_THRESHOLD_LIMIT : INTEGER := 5;
37 DataSz : INTEGER RANGE 1 TO 32 := 8;
38 AddrSz : INTEGER RANGE 2 TO 12 := 8
37 );
39 );
38 PORT(
40 PORT(
39 clk : IN STD_LOGIC;
41 clk : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
41 --
43 --
42 reUse : IN STD_LOGIC;
44 reUse : IN STD_LOGIC;
43
45 run : IN STD_LOGIC;
46
44 --IN
47 --IN
45 ren : IN STD_LOGIC;
48 ren : IN STD_LOGIC;
46 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
49 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
47
50
48 --OUT
51 --OUT
49 wen : IN STD_LOGIC;
52 wen : IN STD_LOGIC;
50 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
53 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
51
54
52 empty : OUT STD_LOGIC;
55 empty : OUT STD_LOGIC;
53 full : OUT STD_LOGIC;
56 full : OUT STD_LOGIC;
54 almost_full : OUT STD_LOGIC
57 full_almost : OUT STD_LOGIC;
58 empty_threshold : OUT STD_LOGIC;
59 full_threshold : OUT STD_LOGIC
55 );
60 );
56 END ENTITY;
61 END ENTITY;
57
62
58
63
59 ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS
64 ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS
60
65
61 SIGNAL sFull : STD_LOGIC;
66 SIGNAL sREN : STD_LOGIC;
62 SIGNAL sFull_s : STD_LOGIC;
67 SIGNAL sWEN : STD_LOGIC;
63 SIGNAL sEmpty_s : STD_LOGIC;
68 SIGNAL sRE : STD_LOGIC;
69 SIGNAL sWE : STD_LOGIC;
64
70
65 SIGNAL sEmpty : STD_LOGIC;
71 SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
66 SIGNAL sREN : STD_LOGIC;
72 SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
67 SIGNAL sWEN : STD_LOGIC;
68 SIGNAL sRE : STD_LOGIC;
69 SIGNAL sWE : STD_LOGIC;
70
73
71 SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
72 SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
73 SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
74 SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
75
76 SIGNAL almost_full_s : STD_LOGIC;
77 SIGNAL almost_full_r : STD_LOGIC;
78 BEGIN
74 BEGIN
79
75
80 --==================================================================================
76 --==================================================================================
@@ -93,75 +89,33 BEGIN
93 PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn);
89 PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn);
94 END GENERATE;
90 END GENERATE;
95 --==================================================================================
91 --==================================================================================
96
92 sRE <= NOT sREN;
97 --=============================
93 sWE <= NOT sWEN;
98 -- Read section
99 --=============================
100 sREN <= REN OR sEmpty;
101 sRE <= NOT sREN;
102
103 sEmpty_s <= '0' WHEN ReUse = '1' else
104 '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
105 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
106 '0';
107
108 Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
109
110 PROCESS (clk, rstn)
111 BEGIN
112 IF(rstn = '0')then
113 Raddr_vect <= (OTHERS => '0');
114 sempty <= '1';
115 ELSIF(clk'EVENT AND clk = '1')then
116 sEmpty <= sempty_s;
117
118 IF(sREN = '0' and sempty = '0')then
119 Raddr_vect <= Raddr_vect_s;
120 END IF;
121
122 END IF;
123 END PROCESS;
124
125 --=============================
126 -- Write section
127 --=============================
128 sWEN <= WEN OR sFull;
129 sWE <= NOT sWEN;
130
131 sFull_s <= '1' WHEN ReUse = '1' else
132 '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
133 '1' WHEN sFull = '1' AND REN = '1' ELSE
134 '0';
135
136 almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
137 '1' WHEN almost_full_r = '1' AND WEN = REN ELSE
138 '0';
139
140 Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
141
142 PROCESS (clk, rstn)
143 BEGIN
144 IF(rstn = '0')then
145 Waddr_vect <= (OTHERS => '0');
146 sfull <= '0';
147 almost_full_r <= '0';
148 ELSIF(clk'EVENT AND clk = '1')then
149 sfull <= sfull_s;
150 almost_full_r <= almost_full_s;
151
152 IF(sWEN = '0' and sfull = '0')THEN
153 Waddr_vect <= Waddr_vect_s;
154 END IF;
155
156 END IF;
157 END PROCESS;
158
159 almost_full <= almost_full_s;
160 full <= sFull_s;
161 empty <= sEmpty_s;
162
94
163
95
164
96 lpp_fifo_control_1 : lpp_fifo_control
97 GENERIC MAP (
98 AddrSz => AddrSz,
99 EMPTY_THRESHOLD_LIMIT => EMPTY_THRESHOLD_LIMIT,
100 FULL_THRESHOLD_LIMIT => FULL_THRESHOLD_LIMIT)
101 PORT MAP (
102 clk => clk,
103 rstn => rstn,
104 run => run,
105 reUse => reUse,
106 fifo_r_en => ren,
107 fifo_w_en => wen,
108 mem_r_en => sREN,
109 mem_w_en => SWEN,
110 mem_r_addr => Raddr_vect,
111 mem_w_addr => Waddr_vect,
112 empty => empty,
113 full => full,
114 full_almost => full_almost,
115 empty_threshold => empty_threshold,
116 full_threshold => full_threshold);
117
118
165 END ARCHITECTURE;
119 END ARCHITECTURE;
166
120
167
121
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@@ -39,21 +39,108 PACKAGE lpp_memory IS
39
39
40 COMPONENT lpp_fifo
40 COMPONENT lpp_fifo
41 GENERIC (
41 GENERIC (
42 tech : INTEGER;
42 tech : INTEGER;
43 Mem_use : INTEGER;
43 Mem_use : INTEGER;
44 DataSz : INTEGER RANGE 1 TO 32;
44 EMPTY_THRESHOLD_LIMIT : INTEGER;
45 AddrSz : INTEGER RANGE 2 TO 12);
45 FULL_THRESHOLD_LIMIT : INTEGER;
46 DataSz : INTEGER RANGE 1 TO 32;
47 AddrSz : INTEGER RANGE 2 TO 12);
48 PORT (
49 clk : IN STD_LOGIC;
50 rstn : IN STD_LOGIC;
51 reUse : IN STD_LOGIC;
52 run : IN STD_LOGIC;
53 ren : IN STD_LOGIC;
54 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
55 wen : IN STD_LOGIC;
56 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
57 empty : OUT STD_LOGIC;
58 full : OUT STD_LOGIC;
59 full_almost : OUT STD_LOGIC;
60 empty_threshold : OUT STD_LOGIC;
61 full_threshold : OUT STD_LOGIC);
62 END COMPONENT;
63
64 COMPONENT lpp_fifo_4_shared
65 GENERIC (
66 tech : INTEGER;
67 Mem_use : INTEGER;
68 EMPTY_THRESHOLD_LIMIT : INTEGER;
69 FULL_THRESHOLD_LIMIT : INTEGER;
70 DataSz : INTEGER RANGE 1 TO 32;
71 AddrSz : INTEGER RANGE 3 TO 12);
72 PORT (
73 clk : IN STD_LOGIC;
74 rstn : IN STD_LOGIC;
75 run : IN STD_LOGIC;
76 empty_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
77 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
78 r_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
79 r_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 full_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
83 w_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
84 w_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
85 END COMPONENT;
86
87 COMPONENT lpp_fifo_4_shared_headreg_latency_0
46 PORT (
88 PORT (
47 clk : IN STD_LOGIC;
89 clk : IN STD_LOGIC;
48 rstn : IN STD_LOGIC;
90 rstn : IN STD_LOGIC;
49 reUse : IN STD_LOGIC;
91 run : IN STD_LOGIC;
50 ren : IN STD_LOGIC;
92 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
51 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
93 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
52 wen : IN STD_LOGIC;
94 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
53 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
95 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
54 empty : OUT STD_LOGIC;
96 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
55 full : OUT STD_LOGIC;
97 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 almost_full : OUT STD_LOGIC);
98 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
102 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
103 END COMPONENT;
104
105 COMPONENT lpp_fifo_4_shared_headreg_latency_1
106 PORT (
107 clk : IN STD_LOGIC;
108 rstn : IN STD_LOGIC;
109 run : IN STD_LOGIC;
110 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
111 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
112 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
113 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
118 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
119 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
120 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
121 END COMPONENT;
122
123 COMPONENT lpp_fifo_control
124 GENERIC (
125 AddrSz : INTEGER RANGE 2 TO 12;
126 EMPTY_THRESHOLD_LIMIT : INTEGER;
127 FULL_THRESHOLD_LIMIT : INTEGER);
128 PORT (
129 clk : IN STD_LOGIC;
130 rstn : IN STD_LOGIC;
131 reUse : IN STD_LOGIC;
132 run : IN STD_LOGIC;
133 fifo_r_en : IN STD_LOGIC;
134 fifo_w_en : IN STD_LOGIC;
135 mem_r_en : OUT STD_LOGIC;
136 mem_w_en : OUT STD_LOGIC;
137 mem_r_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0);
138 mem_w_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0);
139 empty : OUT STD_LOGIC;
140 full : OUT STD_LOGIC;
141 full_almost : OUT STD_LOGIC;
142 empty_threshold : OUT STD_LOGIC;
143 full_threshold : OUT STD_LOGIC);
57 END COMPONENT;
144 END COMPONENT;
58
145
59 COMPONENT lppFIFOxN
146 COMPONENT lppFIFOxN
@@ -67,6 +154,7 PACKAGE lpp_memory IS
67 clk : IN STD_LOGIC;
154 clk : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
155 rstn : IN STD_LOGIC;
69 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
156 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
157 run : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
70 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
158 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
71 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
159 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
72 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
160 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
@@ -138,56 +226,6 PACKAGE lpp_memory IS
138 );
226 );
139 END COMPONENT;
227 END COMPONENT;
140
228
141 --COMPONENT lpp_fifo IS
142 -- GENERIC(
143 -- tech : INTEGER := 0;
144 -- Mem_use : INTEGER := use_RAM;
145 -- Enable_ReUse : STD_LOGIC := '0';
146 -- DataSz : INTEGER RANGE 1 TO 32 := 8;
147 -- AddrSz : INTEGER RANGE 2 TO 12 := 8
148 -- );
149 -- PORT(
150 -- rstn : IN STD_LOGIC;
151 -- ReUse : IN STD_LOGIC; --27/01/12
152 -- rclk : IN STD_LOGIC;
153 -- ren : IN STD_LOGIC;
154 -- rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
155 -- empty : OUT STD_LOGIC;
156 -- raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
157 -- wclk : IN STD_LOGIC;
158 -- wen : IN STD_LOGIC;
159 -- wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
160 -- full : OUT STD_LOGIC;
161 -- almost_full : OUT STD_LOGIC;
162 -- waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
163 -- );
164 --END COMPONENT;
165
166
167 --COMPONENT lppFIFOxN IS
168 -- GENERIC(
169 -- tech : INTEGER := 0;
170 -- Mem_use : INTEGER := use_RAM;
171 -- Data_sz : INTEGER RANGE 1 TO 32 := 8;
172 -- Addr_sz : INTEGER RANGE 1 TO 32 := 8;
173 -- FifoCnt : INTEGER := 1;
174 -- Enable_ReUse : STD_LOGIC := '0'
175 -- );
176 -- PORT(
177 -- rstn : IN STD_LOGIC;
178 -- wclk : IN STD_LOGIC;
179 -- rclk : IN STD_LOGIC;
180 -- ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
181 -- wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
182 -- ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
183 -- wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
184 -- rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
185 -- full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
186 -- almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
187 -- empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
188 -- );
189 --END COMPONENT;
190
191 COMPONENT FillFifo IS
229 COMPONENT FillFifo IS
192 GENERIC(
230 GENERIC(
193 Data_sz : INTEGER RANGE 1 TO 32 := 16;
231 Data_sz : INTEGER RANGE 1 TO 32 := 16;
Show file before | Show file after | Hide comments
@@ -1,4 +1,9
1 lpp_memory.vhd
1 lpp_memory.vhd
2 lpp_FIFO.vhd
2 lpp_FIFO.vhd
3 lpp_FIFO_4_Shared.vhd
4 lpp_FIFO_control.vhd
5 lpp_FIFO_4_Shared_headreg_latency_0.vhd
6 lpp_FIFO_4_Shared_headreg_latency_1.vhd
3 lppFIFOxN.vhd
7 lppFIFOxN.vhd
4
8
9
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@@ -117,6 +117,7 ARCHITECTURE beh OF lpp_lfr IS
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
120 SIGNAL data_shaping_R2 : STD_LOGIC;
120 --
121 --
121 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -312,6 +313,7 BEGIN
312 data_shaping_SP1 => data_shaping_SP1,
313 data_shaping_SP1 => data_shaping_SP1,
313 data_shaping_R0 => data_shaping_R0,
314 data_shaping_R0 => data_shaping_R0,
314 data_shaping_R1 => data_shaping_R1,
315 data_shaping_R1 => data_shaping_R1,
316 data_shaping_R2 => data_shaping_R2,
315 sample_f0_val => sample_f0_val,
317 sample_f0_val => sample_f0_val,
316 sample_f1_val => sample_f1_val,
318 sample_f1_val => sample_f1_val,
317 sample_f2_val => sample_f2_val,
319 sample_f2_val => sample_f2_val,
@@ -380,6 +382,7 BEGIN
380 data_shaping_SP1 => data_shaping_SP1,
382 data_shaping_SP1 => data_shaping_SP1,
381 data_shaping_R0 => data_shaping_R0,
383 data_shaping_R0 => data_shaping_R0,
382 data_shaping_R1 => data_shaping_R1,
384 data_shaping_R1 => data_shaping_R1,
385 data_shaping_R2 => data_shaping_R2,
383 delta_snapshot => delta_snapshot,
386 delta_snapshot => delta_snapshot,
384 delta_f0 => delta_f0,
387 delta_f0 => delta_f0,
385 delta_f0_2 => delta_f0_2,
388 delta_f0_2 => delta_f0_2,
@@ -745,4 +748,4 BEGIN
745 debug_ms(11 DOWNTO 0) & -- 23 .. 12
748 debug_ms(11 DOWNTO 0) & -- 23 .. 12
746 debug_signal(11 DOWNTO 0); -- 11 .. 0
749 debug_signal(11 DOWNTO 0); -- 11 .. 0
747
750
748 END beh; No newline at end of file
751 END beh;
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@@ -102,6 +102,7 ENTITY lpp_lfr_apbreg IS
102 data_shaping_SP1 : OUT STD_LOGIC;
102 data_shaping_SP1 : OUT STD_LOGIC;
103 data_shaping_R0 : OUT STD_LOGIC;
103 data_shaping_R0 : OUT STD_LOGIC;
104 data_shaping_R1 : OUT STD_LOGIC;
104 data_shaping_R1 : OUT STD_LOGIC;
105 data_shaping_R2 : OUT STD_LOGIC;
105
106
106 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
107 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
107 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
108 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
@@ -182,6 +183,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS
182 data_shaping_SP1 : STD_LOGIC;
183 data_shaping_SP1 : STD_LOGIC;
183 data_shaping_R0 : STD_LOGIC;
184 data_shaping_R0 : STD_LOGIC;
184 data_shaping_R1 : STD_LOGIC;
185 data_shaping_R1 : STD_LOGIC;
186 data_shaping_R2 : STD_LOGIC;
185 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
187 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
186 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
188 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
187 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
189 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
@@ -267,6 +269,7 BEGIN -- beh
267 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
269 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
268 data_shaping_R0 <= reg_wp.data_shaping_R0;
270 data_shaping_R0 <= reg_wp.data_shaping_R0;
269 data_shaping_R1 <= reg_wp.data_shaping_R1;
271 data_shaping_R1 <= reg_wp.data_shaping_R1;
272 data_shaping_R2 <= reg_wp.data_shaping_R2;
270
273
271 delta_snapshot <= reg_wp.delta_snapshot;
274 delta_snapshot <= reg_wp.delta_snapshot;
272 delta_f0 <= reg_wp.delta_f0;
275 delta_f0 <= reg_wp.delta_f0;
@@ -342,6 +345,7 BEGIN -- beh
342 reg_wp.data_shaping_SP1 <= '0';
345 reg_wp.data_shaping_SP1 <= '0';
343 reg_wp.data_shaping_R0 <= '0';
346 reg_wp.data_shaping_R0 <= '0';
344 reg_wp.data_shaping_R1 <= '0';
347 reg_wp.data_shaping_R1 <= '0';
348 reg_wp.data_shaping_R2 <= '0';
345 reg_wp.enable_f0 <= '0';
349 reg_wp.enable_f0 <= '0';
346 reg_wp.enable_f1 <= '0';
350 reg_wp.enable_f1 <= '0';
347 reg_wp.enable_f2 <= '0';
351 reg_wp.enable_f2 <= '0';
@@ -458,6 +462,7 BEGIN -- beh
458 prdata(2) <= reg_wp.data_shaping_SP1;
462 prdata(2) <= reg_wp.data_shaping_SP1;
459 prdata(3) <= reg_wp.data_shaping_R0;
463 prdata(3) <= reg_wp.data_shaping_R0;
460 prdata(4) <= reg_wp.data_shaping_R1;
464 prdata(4) <= reg_wp.data_shaping_R1;
465 prdata(5) <= reg_wp.data_shaping_R2;
461 --21
466 --21
462 WHEN "010101" => prdata(0) <= reg_wp.enable_f0;
467 WHEN "010101" => prdata(0) <= reg_wp.enable_f0;
463 prdata(1) <= reg_wp.enable_f1;
468 prdata(1) <= reg_wp.enable_f1;
@@ -536,6 +541,7 BEGIN -- beh
536 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
541 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
537 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
542 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
538 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
543 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
544 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
539 WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0);
545 WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0);
540 reg_wp.enable_f1 <= apbi.pwdata(1);
546 reg_wp.enable_f1 <= apbi.pwdata(1);
541 reg_wp.enable_f2 <= apbi.pwdata(2);
547 reg_wp.enable_f2 <= apbi.pwdata(2);
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@@ -33,6 +33,7 ENTITY lpp_lfr_filter IS
33 data_shaping_SP1 : IN STD_LOGIC;
33 data_shaping_SP1 : IN STD_LOGIC;
34 data_shaping_R0 : IN STD_LOGIC;
34 data_shaping_R0 : IN STD_LOGIC;
35 data_shaping_R1 : IN STD_LOGIC;
35 data_shaping_R1 : IN STD_LOGIC;
36 data_shaping_R2 : IN STD_LOGIC;
36 --
37 --
37 sample_f0_val : OUT STD_LOGIC;
38 sample_f0_val : OUT STD_LOGIC;
38 sample_f1_val : OUT STD_LOGIC;
39 sample_f1_val : OUT STD_LOGIC;
@@ -274,7 +275,7 BEGIN
274 sample_out_val => sample_f1_val_s,
275 sample_out_val => sample_f1_val_s,
275 sample_out => sample_f1);
276 sample_out => sample_f1);
276
277
277 sample_f1_val <= sample_f1_val_s;
278 sample_f1_val <= sample_f1_val_s;
278
279
279 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
280 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
280 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
281 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
@@ -326,8 +327,8 BEGIN
326
327
327 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
328 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
328 sample_f2_wdata_s(I) <= sample_f2(0, I);
329 sample_f2_wdata_s(I) <= sample_f2(0, I);
329 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
330 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I) WHEN data_shaping_R2 = '1' ELSE sample_f1(3, I);;
330 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
331 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I) WHEN data_shaping_R2 = '1' ELSE sample_f1(4, I);;
331 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
332 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
332 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
333 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
333 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
334 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
@@ -382,4 +383,4 BEGIN
382 sample_f2_wdata <= sample_f2_wdata_s;
383 sample_f2_wdata <= sample_f2_wdata_s;
383 sample_f3_wdata <= sample_f3_wdata_s;
384 sample_f3_wdata <= sample_f3_wdata_s;
384
385
385 END tb; No newline at end of file
386 END tb;
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@@ -291,6 +291,8 BEGIN
291
291
292 ReUse => (OTHERS => '0'),
292 ReUse => (OTHERS => '0'),
293
293
294 run => (OTHERS => '1'),
295
294 wen => sample_f0_A_wen,
296 wen => sample_f0_A_wen,
295 wdata => sample_f0_wdata,
297 wdata => sample_f0_wdata,
296
298
@@ -313,6 +315,7 BEGIN
313 rstn => rstn,
315 rstn => rstn,
314
316
315 ReUse => (OTHERS => '0'),
317 ReUse => (OTHERS => '0'),
318 run => (OTHERS => '1'),
316
319
317 wen => sample_f0_B_wen,
320 wen => sample_f0_B_wen,
318 wdata => sample_f0_wdata,
321 wdata => sample_f0_wdata,
@@ -358,6 +361,7 BEGIN
358 rstn => rstn,
361 rstn => rstn,
359
362
360 ReUse => (OTHERS => '0'),
363 ReUse => (OTHERS => '0'),
364 run => (OTHERS => '1'),
361
365
362 wen => sample_f1_wen_head,
366 wen => sample_f1_wen_head,
363 wdata => sample_f1_wdata_head,
367 wdata => sample_f1_wdata_head,
@@ -400,6 +404,7 BEGIN
400 rstn => rstn,
404 rstn => rstn,
401
405
402 ReUse => (OTHERS => '0'),
406 ReUse => (OTHERS => '0'),
407 run => (OTHERS => '1'),
403
408
404 wen => sample_f2_wen,
409 wen => sample_f2_wen,
405 wdata => sample_f2_wdata,
410 wdata => sample_f2_wdata,
@@ -748,6 +753,7 BEGIN
748 rstn => rstn,
753 rstn => rstn,
749
754
750 ReUse => MEM_IN_SM_ReUse,
755 ReUse => MEM_IN_SM_ReUse,
756 run => (OTHERS => '1'),
751
757
752 wen => MEM_IN_SM_wen,
758 wen => MEM_IN_SM_wen,
753 wdata => MEM_IN_SM_wData,
759 wdata => MEM_IN_SM_wData,
@@ -887,6 +893,7 BEGIN
887 rstn => rstn,
893 rstn => rstn,
888
894
889 ReUse => (OTHERS => '0'),
895 ReUse => (OTHERS => '0'),
896 run => (OTHERS => '1'),
890
897
891 wen => MEM_OUT_SM_Write,
898 wen => MEM_OUT_SM_Write,
892 wdata => MEM_OUT_SM_Data_in,
899 wdata => MEM_OUT_SM_Data_in,
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@@ -204,6 +204,7 PACKAGE lpp_lfr_pkg IS
204 data_shaping_SP1 : IN STD_LOGIC;
204 data_shaping_SP1 : IN STD_LOGIC;
205 data_shaping_R0 : IN STD_LOGIC;
205 data_shaping_R0 : IN STD_LOGIC;
206 data_shaping_R1 : IN STD_LOGIC;
206 data_shaping_R1 : IN STD_LOGIC;
207 data_shaping_R2 : IN STD_LOGIC;
207 sample_f0_val : OUT STD_LOGIC;
208 sample_f0_val : OUT STD_LOGIC;
208 sample_f1_val : OUT STD_LOGIC;
209 sample_f1_val : OUT STD_LOGIC;
209 sample_f2_val : OUT STD_LOGIC;
210 sample_f2_val : OUT STD_LOGIC;
@@ -332,6 +333,7 PACKAGE lpp_lfr_pkg IS
332 data_shaping_SP1 : OUT STD_LOGIC;
333 data_shaping_SP1 : OUT STD_LOGIC;
333 data_shaping_R0 : OUT STD_LOGIC;
334 data_shaping_R0 : OUT STD_LOGIC;
334 data_shaping_R1 : OUT STD_LOGIC;
335 data_shaping_R1 : OUT STD_LOGIC;
336 data_shaping_R2 : OUT STD_LOGIC;
335 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
337 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
336 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
338 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
337 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
339 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
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@@ -32,6 +32,8 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35 USE lpp.iir_filter.ALL;
36 USE lpp.lpp_memory.ALL;
35
37
36 LIBRARY techmap;
38 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
@@ -212,15 +214,18 ARCHITECTURE beh OF lpp_waveform IS
212 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
214 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
213 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
218 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
216
219
217 --
220 --
218
221
219 SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
222 SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
223 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
224
221
225
222 BEGIN -- beh
226 BEGIN -- beh
223
227
228
224 -----------------------------------------------------------------------------
229 -----------------------------------------------------------------------------
225 -- DEBUG
230 -- DEBUG
226 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
@@ -454,49 +459,83 BEGIN -- beh
454 --debug_f3_data_fifo_in <= wdata;s
459 --debug_f3_data_fifo_in <= wdata;s
455 -----------------------------------------------------------------------------
460 -----------------------------------------------------------------------------
456
461
457 lpp_waveform_fifo_1 : lpp_waveform_fifo
462
458 GENERIC MAP (tech => tech)
463 -- lpp_fifo_4_shared_1: lpp_fifo_4_shared
459 PORT MAP (
464 -- GENERIC MAP (
460 clk => clk,
465 -- tech => tech,
461 rstn => rstn,
466 -- Mem_use => use_RAM,
462 run => run,
467 -- EMPTY_ALMOST_LIMIT => 16,
468 -- FULL_ALMOST_LIMIT => 5,
469 -- DataSz => 32,
470 -- AddrSz => 7
471 -- )
472 -- PORT MAP (
473 -- clk => clk,
474 -- rstn => rstn,
475 -- run => run,
476 -- empty_almost => s_empty_almost,
477 -- empty => s_empty,
478 -- r_en => s_data_ren,
479 -- r_data => s_rdata,
480 -- full_almost => full_almost,
481 -- full => full,
482 -- w_en => data_wen,
483 -- w_data => wdata);
463
484
464 empty => s_empty,
485 --lpp_waveform_fifo_headreg_1 : lpp_fifo_4_shared_headreg_latency_1
465 empty_almost => s_empty_almost,
486 -- PORT MAP (
466 data_ren => s_data_ren,
487 -- clk => clk,
467 rdata => s_rdata,
488 -- rstn => rstn,
489 -- run => run,
490 -- o_empty_almost => empty_almost,
491 -- o_empty => empty,
468
492
469
493 -- o_data_ren => data_ren,
470 full_almost => full_almost,
494 -- o_rdata_0 => data_f0_data_out,
471 full => full,
495 -- o_rdata_1 => data_f1_data_out,
472 data_wen => data_wen,
496 -- o_rdata_2 => data_f2_data_out,
473 wdata => wdata);
497 -- o_rdata_3 => data_f3_data_out,
474
498
475 lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg
499 -- i_empty_almost => s_empty_almost,
476 GENERIC MAP (tech => tech)
500 -- i_empty => s_empty,
477 PORT MAP (
501 -- i_data_ren => s_data_ren,
478 clk => clk,
502 -- i_rdata => s_rdata);
479 rstn => rstn,
480 run => run,
481 o_empty_almost => empty_almost,
482 o_empty => empty,
483
503
484 o_data_ren => data_ren,
504 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
485 o_rdata_0 => data_f0_data_out,
505 lpp_fifo_1: lpp_fifo
486 o_rdata_1 => data_f1_data_out,
506 GENERIC MAP (
487 o_rdata_2 => data_f2_data_out,
507 tech => tech,
488 o_rdata_3 => data_f3_data_out,
508 Mem_use => use_RAM,
509 EMPTY_THRESHOLD_LIMIT => 16,
510 FULL_THRESHOLD_LIMIT => 5,
511 DataSz => 32,
512 AddrSz => 7)
513 PORT MAP (
514 clk => clk,
515 rstn => rstn,
516 reUse => '0',
517 run => run,
518 ren => data_ren(I),
519 rdata => s_rdata_v((I+1)*32-1 downto I*32),
520 wen => data_wen(I),
521 wdata => wdata,
522 empty => empty(I),
523 full => full(I),
524 full_almost => OPEN,
525 empty_threshold => empty_almost(I),
526 full_threshold => full_almost(I) );
527
528 END GENERATE generate_all_fifo;
489
529
490 i_empty_almost => s_empty_almost,
530
491 i_empty => s_empty,
531 --empty <= s_empty;
492 i_data_ren => s_data_ren,
532 --empty_almost <= s_empty_almost;
493 i_rdata => s_rdata);
533 --s_data_ren <= data_ren;
494
534
495
535 data_f0_data_out <= s_rdata_v(31 downto 0);
496 --data_f0_data_out <= rdata;
536 data_f1_data_out <= s_rdata_v(31+32 downto 0+32);
497 --data_f1_data_out <= rdata;
537 data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2);
498 --data_f2_data_out <= rdata;
538 data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3);
499 --data_f3_data_out <= rdata;
500
539
501 data_ren <= data_f3_data_out_ren &
540 data_ren <= data_f3_data_out_ren &
502 data_f2_data_out_ren &
541 data_f2_data_out_ren &
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